diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,10 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+## 0.5.11 *September 14th 2015*
+* Support for clash-lib-0.5.12
+* Fixes bugs:
+  * Converting Bool to Unsigned generates broken VHDL [#77](https://github.com/clash-lang/clash-compiler/issues/77)
+
 ## 0.5.10 *September 8th 2015*
 * Fixes bugs:
   * Maybe (Index n) not translatable to VHDL [#75](https://github.com/clash-lang/clash-compiler/issues/75)
diff --git a/clash-vhdl.cabal b/clash-vhdl.cabal
--- a/clash-vhdl.cabal
+++ b/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.5.10
+Version:              0.5.11
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -93,7 +93,7 @@
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.8,
+                      clash-lib               >= 0.5.12,
                       clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -13,13 +13,13 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.high"
     , "type"      : "high :: Bit"
-    , "templateE" : "\"1\""
+    , "templateE" : "std_logic_vector'(\"1\")"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.low"
     , "type"      : "low :: Bit"
-    , "templateE" : "\"0\""
+    , "templateE" : "std_logic_vector'(\"0\")"
     }
   }
 , { "BlackBox" :
diff --git a/src/CLaSH/Backend/VHDL.hs b/src/CLaSH/Backend/VHDL.hs
--- a/src/CLaSH/Backend/VHDL.hs
+++ b/src/CLaSH/Backend/VHDL.hs
@@ -485,7 +485,15 @@
     end      = start - argSize + 1
 
 expr_ _ (Identifier id_ (Just (Indexed (ty@(Product _ _),_,fI)))) = text id_ <> dot <> tyName ty <> "_sel" <> int fI
-expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),_,fI)))) = text id_ <> parens (int fI)
+
+expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),1,1)))) = text id_ <> parens (int 0)
+expr_ _ (Identifier id_ (Just (Indexed ((Vector n _),1,2)))) = text id_ <> parens (int 1 <+> "to" <+> int (n-1))
+
+-- This is a HACK for CLaSH.Driver.TopWrapper.mkOutput
+-- Vector's don't have a 10'th constructor, this is just so that we can
+-- recognize the particular case
+expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),10,fI)))) = text id_ <> parens (int fI)
+
 expr_ _ (Identifier id_ (Just (DC (ty@(SP _ _),_)))) = text id_ <> parens (int start <+> "downto" <+> int end)
   where
     start = typeSize ty - 1