clash-vhdl 0.5.1 → 0.5.2

raw patch · 3 files changed

+11/−7 lines, 3 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

CHANGELOG.md +4/−0
clash-vhdl.cabal +1/−1
src/CLaSH/Backend/VHDL.hs +6/−6

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.2 *April 24th 2015*+* Fixes bugs:+  * Fix bug where not enough array type definitions were created+ ## 0.5.1 *April 20th 2015* * Update to clash-prelude 0.7.2

clash-vhdl.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.5.1+Version:              0.5.2 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

src/CLaSH/Backend/VHDL.hs view

@@ -92,10 +92,10 @@    "end" <> semi <> packageBodyDec   where     usedTys     = concatMap mkUsedTys hwtys-    needsDec    = nubBy eqReprTy $ (hwtys ++ usedTys)+    needsDec    = nubBy eqReprTy . map mkVecZ $ (hwtys ++ usedTys)     hwTysSorted = topSortHWTys needsDec     packageDec  = vcat $ mapM tyDec hwTysSorted-    (funDecs,funBodies) = unzip $ maxDec : (catMaybes $ map funDec (nubBy eqTypM needsDec))+    (funDecs,funBodies) = unzip $ maxDec : (catMaybes $ map funDec (nubBy eqTypM hwTysSorted))      packageBodyDec :: VHDLM Doc     packageBodyDec = case funBodies of@@ -106,13 +106,13 @@               "end" <> semi      eqReprTy :: HWType -> HWType -> Bool-    eqReprTy (Vector _ ty1) (Vector _ ty2) = eqReprTy ty1 ty2+    eqReprTy (Vector n ty1) (Vector m ty2) = n == m && eqReprTy ty1 ty2     eqReprTy ty1 ty2       | isUnsigned ty1 && isUnsigned ty2 ||         isSLV ty1 && isSLV ty2              = typeSize ty1 == typeSize ty2       | otherwise                           = ty1 == ty2 -    eqTypM (Vector _ ty1) (Vector _ ty2) = eqReprTy ty1 ty2+    eqTypM (Vector n ty1) (Vector m ty2) = n == m && eqReprTy ty1 ty2     eqTypM (Signed _) (Signed _) = True     eqTypM ty1 ty2 = isUnsigned ty1 && isUnsigned ty2 ||                      isSLV      ty1 && isSLV      ty2 ||@@ -338,7 +338,7 @@ -- | Convert a Netlist HWType to a VHDL type vhdlType :: HWType -> VHDLM Doc vhdlType hwty = do-  tyCache %= HashSet.insert (mkVecZ hwty)+  tyCache %= HashSet.insert hwty   vhdlType' hwty  vhdlType' :: HWType -> VHDLM Doc@@ -368,7 +368,7 @@ -- | Convert a Netlist HWType to the root of a VHDL type vhdlTypeMark :: HWType -> VHDLM Doc vhdlTypeMark hwty = do-  tyCache %= HashSet.insert (mkVecZ hwty)+  tyCache %= HashSet.insert hwty   vhdlTypeMark' hwty   where     vhdlTypeMark' Bool            = "boolean"