clash-verilog 0.7 → 0.7.1
raw patch · 9 files changed
+60/−27 lines, 9 files
Files
- CHANGELOG.md +5/−1
- clash-verilog.cabal +3/−1
- primitives/CLaSH.Prelude.BlockRam.json +15/−16
- primitives/CLaSH.XException.json +7/−0
- primitives/GHC.IO.Exception.json +12/−0
- primitives/GHC.Integer.Type.json +12/−0
- primitives/GHC.Prim.json +1/−1
- primitives/GHC.Types.json +0/−5
- src/CLaSH/Backend/Verilog.hs +5/−3
CHANGELOG.md view
@@ -1,6 +1,10 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package -## 0.7+## 0.7.1 *April 11th 2017*+* Fixes bugs:+ * Incorrect unsigned->signed wrap-around and conversion++## 0.7 *January 16th 2017* * New features: * Support `clash-prelude` 0.11
clash-verilog.cabal view
@@ -1,5 +1,5 @@ Name: clash-verilog-Version: 0.7+Version: 0.7.1 Synopsis: CAES Language for Synchronous Hardware - Verilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -63,12 +63,14 @@ primitives/CLaSH.Sized.RTree.json primitives/CLaSH.Sized.Vector.json primitives/CLaSH.Transformations.json+ primitives/CLaSH.XException.json primitives/Control.Exception.Base.json primitives/Debug.Trace.json primitives/GHC.Base.json primitives/GHC.Classes.json primitives/GHC.CString.json primitives/GHC.Err.json+ primitives/GHC.IO.Exception.json primitives/GHC.Int.json primitives/GHC.Integer.Logarithms.json primitives/GHC.Integer.Type.json
primitives/CLaSH.Prelude.BlockRam.json view
@@ -1,33 +1,32 @@ [ { "BlackBox" : { "name" : "CLaSH.Prelude.BlockRam.blockRam#" , "type" :-"blockRam# :: KnownNat n -- ARG[0]- => SClock clk -- clk, ARG[1]- -> Vec n a -- init, ARG[2]- -> Signal' clk Int -- rd, ARG[3]- -> Signal' clk Bool -- wren, ARG[4]- -> Signal' clk Int -- wr, ARG[5]- -> Signal' clk a -- din, ARG[6]+"blockRam# :: SClock clk -- clk, ARG[0]+ -> Vec n a -- init, ARG[1]+ -> Signal' clk Int -- rd, ARG[2]+ -> Signal' clk Bool -- wren, ARG[3]+ -> Signal' clk Int -- wr, ARG[4]+ -> Signal' clk a -- din, ARG[5] -> Signal' clk a" , "templateD" : "// blockRam begin-reg ~TYPO ~GENSYM[RAM][0] [0:~LIT[0]-1];+reg ~TYPO ~GENSYM[RAM][0] [0:~LENGTH[~TYP[1]]-1]; reg ~TYPO ~GENSYM[dout][1]; -reg ~TYP[2] ~GENSYM[ram_init][2];+reg ~TYP[1] ~GENSYM[ram_init][2]; integer ~GENSYM[i][3]; initial begin- ~SYM[2] = ~ARG[2];- for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin- ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];+ ~SYM[2] = ~ARG[1];+ for (~SYM[3]=0; ~SYM[3] < ~LENGTH[~TYP[1]]; ~SYM[3] = ~SYM[3] + 1) begin+ ~SYM[0][~LENGTH[~TYP[1]]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]]; end end -always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRam][4]- if (~ARG[4]) begin- ~SYM[0][~ARG[5]] <= ~ARG[6];+always @(posedge ~CLK[0]) begin : ~GENSYM[~COMPNAME_blockRam][4]+ if (~ARG[3]) begin+ ~SYM[0][~ARG[4]] <= ~ARG[5]; end- ~SYM[1] <= ~SYM[0][~ARG[3]];+ ~SYM[1] <= ~SYM[0][~ARG[2]]; end assign ~RESULT = ~SYM[1];
+ primitives/CLaSH.XException.json view
@@ -0,0 +1,7 @@+[ { "BlackBox" :+ { "name" : "CLaSH.XException.seqX"+ , "type" : "seqX :: a -> b -> b"+ , "templateE" : "~ARG[1]"+ }+ }+]
+ primitives/GHC.IO.Exception.json view
@@ -0,0 +1,12 @@+[ { "BlackBox" :+ { "name" : "GHC.IO.Exception.assertError"+ , "type" : "assertError :: HasCallStack => Bool -> a -> a"+ , "comment" : "It would be nice if we could use a HDL assertion, however,+ because in HDL, case alternatives are evaluated+ concurrently, we would end up with the assertion being+ triggered, even when the result of that branch is not+ chosen in the multiplexer"+ , "templateE" : "~ARG[2]"+ }+ }+]
primitives/GHC.Integer.Type.json view
@@ -176,4 +176,16 @@ , "templateE" : "~ARG[0] <<< ~ARG[1]" } }+, { "BlackBox" :+ { "name" : "GHC.Integer.Type.wordToInteger"+ , "type" : "wordToInteger :: Word# -> Integer"+ , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"+ }+ }+, { "BlackBox" :+ { "name" : "GHC.Integer.Type.integerToWord"+ , "type" : "integerToWord :: Integer -> Word#"+ , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"+ }+ } ]
primitives/GHC.Prim.json view
@@ -37,7 +37,7 @@ , { "BlackBox" : { "name" : "GHC.Prim.ord#" , "type" : "ord :: Char# -> Int#"- , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"+ , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);" } } , { "BlackBox" :
primitives/GHC.Types.json view
@@ -1,9 +1,4 @@ [ { "Primitive" :- { "name" : "GHC.Types.Eq#"- , "primType" : "Constructor"- }- }-, { "Primitive" : { "name" : "GHC.Types.MkCoercible" , "primType" : "Constructor" }
src/CLaSH/Backend/Verilog.hs view
@@ -28,6 +28,7 @@ import Text.Printf import Text.PrettyPrint.Leijen.Text.Monadic +import CLaSH.Annotations.Primitive (HDL (..)) import CLaSH.Backend import CLaSH.Driver.Types (SrcSpan, noSrcSpan) import CLaSH.Netlist.BlackBox.Types (HdlSyn)@@ -58,6 +59,7 @@ instance Backend VerilogState where initBackend = VerilogState 0 [] noSrcSpan []+ hdlKind = const Verilog #ifdef CABAL primDir = const (Paths_clash_verilog.getDataFileName "primitives") #else@@ -427,16 +429,16 @@ expr_ _ (DataTag Bool (Left id_)) = text id_ <> brackets (int 0) expr_ _ (DataTag Bool (Right id_)) = do iw <- use intWidth- "$signed" <> parens (listBraces (sequence [braces (int (iw-1) <+> braces "1'b0"),text id_]))+ "$unsigned" <> parens (listBraces (sequence [braces (int (iw-1) <+> braces "1'b0"),text id_])) expr_ _ (DataTag (Sum _ _) (Left id_)) = "$unsigned" <> parens (text id_)-expr_ _ (DataTag (Sum _ _) (Right id_)) = "$signed" <> parens (text id_)+expr_ _ (DataTag (Sum _ _) (Right id_)) = "$unsigned" <> parens (text id_) expr_ _ (DataTag (Product _ _) (Right _)) = do iw <- use intWidth int iw <> "'sd0" -expr_ _ (DataTag hty@(SP _ _) (Right id_)) = "$signed" <> parens+expr_ _ (DataTag hty@(SP _ _) (Right id_)) = "$unsigned" <> parens (text id_ <> brackets (int start <> colon <> int end)) where