clash-verilog 0.7.1 → 0.7.2

raw patch · 3 files changed

+6/−2 lines, 3 files

Files

CHANGELOG.md +4/−0
clash-verilog.cabal +1/−1
src/CLaSH/Backend/Verilog.hs +1/−1

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.7.2+* New features:+  * Sum-of-product types: unused bits now "don't-care" [#212](https://github.com/clash-lang/clash-compiler/commit/fabf745793491ce3baf84ef0066b4ccf0753d503)+ ## 0.7.1 *April 11th 2017* * Fixes bugs:   * Incorrect unsigned->signed wrap-around and conversion

clash-verilog.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-verilog-Version:              0.7.1+Version:              0.7.2 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

src/CLaSH/Backend/Verilog.hs view

@@ -383,7 +383,7 @@     argExprs   = map (expr_ False) es     extraArg   = case typeSize ty - dcSize of                    0 -> []-                   n -> [exprLit (Just (ty,n)) (NumLit 0)]+                   n -> [int n <> "'b" <> bits (replicate n U)]     assignExpr = braces (hcat $ punctuate comma $ sequence (dcExpr:argExprs ++ extraArg))  expr_ _ (DataCon ty@(Sum _ _) (DC (_,i)) []) = int (typeSize ty) <> "'d" <> int i