clash-verilog 0.6 → 0.6.1
raw patch · 6 files changed
+86/−18 lines, 6 filesdep ~clash-preludePVP: major bump suggested
API removals or changes: PVP suggests a major version bump
Dependency ranges changed: clash-prelude
API changes (from Hackage documentation)
- CLaSH.Backend.Verilog: instance Backend VerilogState
+ CLaSH.Backend.Verilog: instance CLaSH.Backend.Backend CLaSH.Backend.Verilog.VerilogState
Files
- CHANGELOG.md +4/−0
- clash-verilog.cabal +3/−2
- primitives/CLaSH.Promoted.Nat.Unsafe.json +7/−0
- primitives/CLaSH.Promoted.Nat.json +24/−0
- primitives/CLaSH.Sized.Vector.json +44/−12
- src/CLaSH/Backend/Verilog.hs +4/−4
CHANGELOG.md view
@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.6.1 *October 16th 2015*+* New features:+ * Support for `clash-prelude` 0.10.1+ ## 0.6 * New features: * Support `clash-prelude-0.10`
clash-verilog.cabal view
@@ -1,5 +1,5 @@ Name: clash-verilog-Version: 0.6+Version: 0.6.1 Synopsis: CAES Language for Synchronous Hardware - Verilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -51,6 +51,7 @@ primitives/CLaSH.Prelude.ROM.File.json primitives/CLaSH.Prelude.Testbench.json primitives/CLaSH.Promoted.Nat.json+ primitives/CLaSH.Promoted.Nat.Unsafe.json primitives/CLaSH.Promoted.Symbol.json primitives/CLaSH.Signal.Bundle.json primitives/CLaSH.Signal.Explicit.json@@ -94,7 +95,7 @@ Build-depends: base >= 4.6.0.1 && < 5, clash-lib >= 0.6,- clash-prelude >= 0.10,+ clash-prelude >= 0.10.1, fgl >= 5.4.2.4, lens >= 3.9.2, mtl >= 2.1.2,
+ primitives/CLaSH.Promoted.Nat.Unsafe.json view
@@ -0,0 +1,7 @@+[ { "BlackBox" :+ { "name" : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat"+ , "type" : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat :: Integer -> SNat k"+ , "templateE" : "~LIT[0]"+ }+ }+]
primitives/CLaSH.Promoted.Nat.json view
@@ -10,4 +10,28 @@ , "templateE" : "~LIT[0]" } }+, { "BlackBox" :+ { "name" : "CLaSH.Promoted.Nat.addSNat"+ , "type" : "CLaSH.Promoted.Nat.addSNat :: SNat a -> SNat b -> SNat (a + b)"+ , "templateE" : "~LIT[0] + ~LIT[1]"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Promoted.Nat.subSNat"+ , "type" : "CLaSH.Promoted.Nat.subSNat :: SNat a -> SNat b -> SNat (a - b)"+ , "templateE" : "~LIT[0] - ~LIT[1]"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Promoted.Nat.mulSNat"+ , "type" : "CLaSH.Promoted.Nat.mulSNat :: SNat a -> SNat b -> SNat (a * b)"+ , "templateE" : "~LIT[0] * ~LIT[1]"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Promoted.Nat.powSNat"+ , "type" : "CLaSH.Promoted.Nat.powSNat :: SNat a -> SNat b -> SNat (a ^ b)"+ , "templateE" : "~LIT[0] ** ~LIT[1]"+ }+ } ]
primitives/CLaSH.Sized.Vector.json view
@@ -1,16 +1,4 @@ [ { "BlackBox" :- { "name" : "CLaSH.Sized.Vector.eq#"- , "type" : "eq# :: Eq a => Vec n a -> Vec n a -> Bool"- , "templateE" : "~ARG[0] == ~ARG[1]"- }- }-, { "BlackBox" :- { "name" : "CLaSH.Sized.Vector.neq#"- , "type" : "neq# :: Eq a => Vec n a -> Vec n a -> Bool"- , "templateE" : "~ARG[0] != ~ARG[1]"- }- }-, { "BlackBox" : { "name" : "CLaSH.Sized.Vector.head" , "type" : "head :: Vec (n + 1) a -> a" , "templateD" :@@ -394,6 +382,50 @@ => BitVector (n * m) -- ARG[2] -> Vec n (BitVector m)" , "templateE" : "~ARG[2]"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Sized.Vector.rotateLeftS"+ , "type" : "rotateLeftS :: KnownNat n => Vec n a -> SNat d -> Vec n a"+ , "templateD" :+"// rotateLeftS begin+wire ~TYP[1] ~SYM[1];+localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];++assign ~SYM[1] = ~ARG[1];++~GENERATE+if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]+ assign ~RESULT = ~SYM[1];+end else begin : do_shift_~SYM[4]+ assign ~RESULT = {~SYM[1][((~LIT[0]-shift_amount_~SYM[2])*~SIZE[~TYPEL[~TYPO]])-1 : 0]+ ,~SYM[1][~SIZE[~TYPO]-1 : (~LIT[0]-shift_amount_~SYM[2])*~SIZE[~TYPEL[~TYPO]]]+ };+end+~ENDGENERATE+// rotateLeftS end"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Sized.Vector.rotateRightS"+ , "type" : "rotateRightS :: KnownNat n => Vec n a -> SNat d -> Vec n a"+ , "templateD" :+"// rotateRightS begin+wire ~TYP[1] ~SYM[1];+localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];++assign ~SYM[1] = ~ARG[1];++~GENERATE+if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]+ assign ~RESULT = ~SYM[1];+end else begin : do_shift_~SYM[4]+ assign ~RESULT = {~SYM[1][(shift_amount_~SYM[2]*~SIZE[~TYPEL[~TYPO]])-1 : 0]+ ,~SYM[1][~SIZE[~TYPO]-1 : shift_amount_~SYM[2]*~SIZE[~TYPEL[~TYPO]]]+ };+end+~ENDGENERATE+// rotateRightS end" } } ]
src/CLaSH/Backend/Verilog.hs view
@@ -137,7 +137,7 @@ inst_ (Assignment id_ e) = fmap Just $ "assign" <+> text id_ <+> equals <+> expr_ False e <> semi -inst_ (CondAssignment id_ ty scrut [(Just (Literal _ (BoolLit b)), l),(_,r)]) = fmap Just $+inst_ (CondAssignment id_ ty scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $ "reg" <+> verilogType ty <+> regId <> semi <$> "always @(*) begin" <$> indent 2 ("if" <> parens (expr_ True scrut) <$>@@ -151,7 +151,7 @@ regId = text id_ <> "_reg" -inst_ (CondAssignment id_ ty scrut es) = fmap Just $+inst_ (CondAssignment id_ ty scrut scrutTy es) = fmap Just $ "reg" <+> verilogType ty <+> regId <> semi <$> "always @(*) begin" <$> indent 2 ("case" <> parens (expr_ True scrut) <$>@@ -162,11 +162,11 @@ where regId = text id_ <> "_reg" - conds :: [(Maybe Expr,Expr)] -> VerilogM [Doc]+ conds :: [(Maybe Literal,Expr)] -> VerilogM [Doc] conds [] = return [] conds [(_,e)] = ("default" <+> colon <+> regId <+> equals <+> expr_ False e) <:> return [] conds ((Nothing,e):_) = ("default" <+> colon <+> regId <+> equals <+> expr_ False e) <:> return []- conds ((Just c ,e):es') = (expr_ True c <+> colon <+> regId <+> equals <+> expr_ False e) <:> conds es'+ conds ((Just c ,e):es') = (exprLit (Just (scrutTy,conSize scrutTy)) c <+> colon <+> regId <+> equals <+> expr_ False e) <:> conds es' inst_ (InstDecl nm lbl pms) = fmap Just $ text nm <+> text lbl <$$> pms' <> semi