diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.10 *October 17th 20168
+* Fixes bugs:
+  * CLaSH.Sized.Vector.imap primitive gets indices in reverse order
+
 ## 0.6.9 *August 18th 2016*
 * Fixes bugs:
   * Fix primitives for {Signed,Unsigned} rotateL# and rotateR# [#169](https://github.com/clash-lang/clash-compiler/issues/169)
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.9
+Version:              0.6.10
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -101,7 +101,7 @@
                       clash-lib               >= 0.6.18   && < 0.7,
                       clash-prelude           >= 0.10.1   && < 0.11,
                       fgl                     >= 5.4.2.4  && < 5.6,
-                      lens                    >= 3.9.2    && < 4.15,
+                      lens                    >= 3.9.2    && < 4.16,
                       mtl                     >= 2.1.2    && < 2.3,
                       text                    >= 0.11.3.1 && < 1.3,
                       unordered-containers    >= 0.2.3.3  && < 0.3,
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -145,7 +145,7 @@
   wire ~TYPEL[~TYP[2]] ~GENSYM[map_in][4];
   wire ~TYPEL[~TYPO] ~GENSYM[map_out][5];
 
-  assign ~SYM[3] = ~SYM[1];
+  assign ~SYM[3] = ~LENGTH[~TYPO] - 1 - ~SYM[1];
   assign ~SYM[4] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
   ~INST 1
     ~OUTPUT <= ~SYM[5]~ ~TYPEL[~TYPO]~