clash-verilog 0.6.7 → 0.6.8

raw patch · 4 files changed

+14/−10 lines, 4 files

Files

CHANGELOG.md +5/−1
clash-verilog.cabal +1/−1
primitives/CLaSH.Sized.Internal.Signed.json +4/−4
primitives/GHC.Integer.Type.json +4/−4

CHANGELOG.md view

@@ -1,6 +1,10 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package -## 0.6.7+## 0.6.8 *August 3rd 2016*+* Fixes bugs:+  * Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger [#164](https://github.com/clash-lang/clash-compiler/issues/164)++## 0.6.7 *July 15th 2016* * New features:   * Support clash-lib-0.6.18

clash-verilog.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-verilog-Version:              0.6.7+Version:              0.6.8 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

primitives/CLaSH.Sized.Internal.Signed.json view

@@ -159,16 +159,16 @@ wire ~SIGD[~GENSYM[rem_res][0]][0]; wire ~SIGD[~GENSYM[dividend][1]][0]; wire ~SIGD[~GENSYM[divider][2]][1];+assign ~SYM[1] = ~ARG[0];+assign ~SYM[2] = ~ARG[1];  // remainder-assign ~SYM[0] = ~ARG[0] % ~ARG[1];+assign ~SYM[0] = ~SYM[1] % ~SYM[2];  // modulo-assign ~SYM[1] = ~ARG[0];-assign ~SYM[2] = ~ARG[1]; assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?                  ~SYM[0] :-                 (~SYM[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~SYM[1]);+                 (~SYM[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~SYM[2]); // modSigned end"     }   }

primitives/GHC.Integer.Type.json view

@@ -67,16 +67,16 @@ wire ~SIGD[~GENSYM[rem_res][0]][0]; wire ~SIGD[~GENSYM[dividend][1]][0]; wire ~SIGD[~GENSYM[divider][2]][1];+assign ~SYM[1] = ~ARG[0];+assign ~SYM[2] = ~ARG[1];  // remainder-assign ~SYM[0] = ~ARG[0] % ~ARG[1];+assign ~SYM[0] = ~SYM[1] % ~SYM[2];  // modulo-assign ~SYM[1] = ~ARG[0];-assign ~SYM[2] = ~ARG[1]; assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?                  ~SYM[0] :-                 ((~ARG[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0) : ~SYM[0] + ~ARG[1]);+                 (~SYM[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~SYM[2]); // modInteger end"     }   }