diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.7
+* New features:
+  * Support clash-lib-0.6.18
+
 ## 0.6.6 *March 11th 2016*
 * Support `clash-lib` 0.6.11
 
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.6
+Version:              0.6.7
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -97,15 +97,15 @@
                       TupleSections
                       ViewPatterns
 
-  Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.6.11,
-                      clash-prelude           >= 0.10.1,
-                      fgl                     >= 5.4.2.4,
-                      lens                    >= 3.9.2,
-                      mtl                     >= 2.1.2,
-                      text                    >= 0.11.3.1,
-                      unordered-containers    >= 0.2.3.3,
-                      wl-pprint-text          >= 1.1.0.0
+  Build-depends:      base                    >= 4.6.0.1  && < 5,
+                      clash-lib               >= 0.6.18   && < 0.7,
+                      clash-prelude           >= 0.10.1   && < 0.11,
+                      fgl                     >= 5.4.2.4  && < 5.6,
+                      lens                    >= 3.9.2    && < 4.15,
+                      mtl                     >= 2.1.2    && < 2.3,
+                      text                    >= 0.11.3.1 && < 1.3,
+                      unordered-containers    >= 0.2.3.3  && < 0.3,
+                      wl-pprint-text          >= 1.1.0.0  && < 1.2
 
   Exposed-modules:    CLaSH.Backend.Verilog
 
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -27,6 +27,7 @@
 import           Text.PrettyPrint.Leijen.Text.Monadic
 
 import           CLaSH.Backend
+import           CLaSH.Driver.Types                   (SrcSpan, noSrcSpan)
 import           CLaSH.Netlist.BlackBox.Types         (HdlSyn)
 import           CLaSH.Netlist.BlackBox.Util          (extractLiterals, renderBlackBox)
 import           CLaSH.Netlist.Id                     (mkBasicId')
@@ -45,6 +46,7 @@
   VerilogState
     { _genDepth  :: Int -- ^ Depth of current generative block
     , _idSeen    :: [Identifier]
+    , _srcSpan   :: SrcSpan
     , _intWidth  :: Int -- ^ Int/Word/Integer bit-width
     , _hdlsyn    :: HdlSyn
     }
@@ -52,7 +54,7 @@
 makeLenses ''VerilogState
 
 instance Backend VerilogState where
-  initBackend     = VerilogState 0 []
+  initBackend     = VerilogState 0 [] noSrcSpan
 #ifdef CABAL
   primDir         = const (Paths_clash_verilog.getDataFileName "primitives")
 #else
@@ -86,6 +88,8 @@
   hdlSyn          = use hdlsyn
   mkBasicId       = return (filterReserved . mkBasicId' True)
   setModName _    = id
+  setSrcSpan      = (srcSpan .=)
+  getSrcSpan      = use srcSpan
 
 type VerilogM a = State VerilogState a
 
@@ -114,8 +118,10 @@
   else s
 
 -- | Generate VHDL for a Netlist component
-genVerilog :: Component -> VerilogM (String,Doc)
-genVerilog c = (unpack cName,) A.<$> verilog
+genVerilog :: SrcSpan -> Component -> VerilogM (String,Doc)
+genVerilog sp c = do
+    setSrcSpan sp
+    (unpack cName,) A.<$> verilog
   where
     cName   = componentName c
     verilog = "// Automatically generated Verilog-2001" <$$>