diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.6 *March 11th 2016*
+* Support `clash-lib` 0.6.11
+
 ## 0.6.5 *January 29th 2016*
 * New features:
   * Support clash-lib-0.6.9
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.5
+Version:              0.6.6
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -98,7 +98,7 @@
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.6,
+                      clash-lib               >= 0.6.11,
                       clash-prelude           >= 0.10.1,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
diff --git a/primitives/CLaSH.Driver.TestbenchGen.json b/primitives/CLaSH.Driver.TestbenchGen.json
--- a/primitives/CLaSH.Driver.TestbenchGen.json
+++ b/primitives/CLaSH.Driver.TestbenchGen.json
@@ -2,7 +2,7 @@
     { "name"      : "CLaSH.Driver.TestbenchGen.clockGen"
     , "templateD" :
 "// pragma translate_off
-reg ~TYPO ~SYM[0];
+reg ~TYPO ~GENSYM[clk][0];
 always begin
   ~SYM[0] = 0;
   #~LIT[0] forever begin
@@ -20,7 +20,7 @@
     { "name"      : "CLaSH.Driver.TestbenchGen.resetGen"
     , "templateD" :
 "// pragma translate_off
-reg ~TYPO ~SYM[0];
+reg ~TYPO ~GENSYM[rst_n][0];
 initial begin
   #1 ~SYM[0] = 0;
   #~LIT[0] ~SYM[0] = 1;
@@ -47,7 +47,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Driver.TestbenchGen.finishedGen"
     , "templateD" :
-"reg ~TYPO ~SYM[0];
+"reg ~TYPO ~GENSYM[done][0];
 always begin
 // pragma translate_off
   ~SYM[0] <= 1'b0;
diff --git a/primitives/CLaSH.Driver.TopWrapper.json b/primitives/CLaSH.Driver.TopWrapper.json
--- a/primitives/CLaSH.Driver.TopWrapper.json
+++ b/primitives/CLaSH.Driver.TopWrapper.json
@@ -2,8 +2,8 @@
     { "name"      : "CLaSH.TopWrapper.syncReset"
     , "templateD" :
 "// reset ~RESULT is asynchronously asserted, but synchronously de-asserted
-reg ~SIGD[~SYM[0]][0];
-reg ~SIGD[~SYM[1]][0];
+reg ~SIGD[~GENSYM[r1][0]][0];
+reg ~SIGD[~GENSYM[r2][1]][0];
 
 always @(posedge ~CLKO or negedge ~ARG[0])
 if (~ ~ARG[0]) begin
diff --git a/primitives/CLaSH.Prelude.BlockRam.File.json b/primitives/CLaSH.Prelude.BlockRam.File.json
--- a/primitives/CLaSH.Prelude.BlockRam.File.json
+++ b/primitives/CLaSH.Prelude.BlockRam.File.json
@@ -12,21 +12,21 @@
                -> Signal' clk (BitVector m)"
     , "templateD" :
 "// blockRamFile begin
-reg ~TYPO RAM_~SYM[0] [0:~LIT[2]-1];
-reg ~TYPO dout_~SYM[1];
+reg ~TYPO ~GENSYM[RAM][0] [0:~LIT[2]-1];
+reg ~TYPO ~GENSYM[dout][1];
 
 initial begin
-  $readmemb(~FILE[~LIT[3]],RAM_~SYM[0]);
+  $readmemb(~FILE[~LIT[3]],~SYM[0]);
 end
 
-always @(posedge ~CLK[1]) begin : blockRamFile_~COMPNAME_~SYM[2]
+always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRamFile][2]
   if (~ARG[6]) begin
-    RAM_~SYM[0][~ARG[4]] <= ~ARG[7];
+    ~SYM[0][~ARG[4]] <= ~ARG[7];
   end
-  dout_~SYM[1] <= RAM_~SYM[0][~ARG[5]];
+  ~SYM[1] <= ~SYM[0][~ARG[5]];
 end
 
-assign ~RESULT = dout_~SYM[1];
+assign ~RESULT = ~SYM[1];
 // blockRamFile end"
     }
   }
diff --git a/primitives/CLaSH.Prelude.BlockRam.json b/primitives/CLaSH.Prelude.BlockRam.json
--- a/primitives/CLaSH.Prelude.BlockRam.json
+++ b/primitives/CLaSH.Prelude.BlockRam.json
@@ -11,26 +11,26 @@
            -> Signal' clk a"
     , "templateD" :
 "// blockRam begin
-reg ~TYPO RAM_~SYM[0] [0:~LIT[0]-1];
-reg ~TYPO dout_~SYM[1];
+reg ~TYPO ~GENSYM[RAM][0] [0:~LIT[0]-1];
+reg ~TYPO ~GENSYM[dout][1];
 
-reg ~TYP[2] ram_init_~SYM[2];
-integer ~SYM[3];
+reg ~TYP[2] ~GENSYM[ram_init][2];
+integer ~GENSYM[i][3];
 initial begin
-  ram_init_~SYM[2] = ~ARG[2];
+  ~SYM[2] = ~ARG[2];
   for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
-    RAM_~SYM[0][~LIT[0]-1-~SYM[3]] = ram_init_~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
   end
 end
 
-always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[4]
+always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRam][4]
   if (~ARG[5]) begin
-    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
+    ~SYM[0][~ARG[3]] <= ~ARG[6];
   end
-  dout_~SYM[1] <= RAM_~SYM[0][~ARG[4]];
+  ~SYM[1] <= ~SYM[0][~ARG[4]];
 end
 
-assign ~RESULT = dout_~SYM[1];
+assign ~RESULT = ~SYM[1];
 // blockRam end"
     }
   }
diff --git a/primitives/CLaSH.Prelude.RAM.json b/primitives/CLaSH.Prelude.RAM.json
--- a/primitives/CLaSH.Prelude.RAM.json
+++ b/primitives/CLaSH.Prelude.RAM.json
@@ -11,15 +11,15 @@
            -> Signal' rclk a"
     , "templateD" :
 "// asyncRam begin
-reg ~TYPO RAM_~SYM[0] [0:~LIT[2]-1];
+reg ~TYPO ~GENSYM[RAM][0] [0:~LIT[2]-1];
 
-always @(posedge ~CLK[0]) begin : Ram_~COMPNAME_~SYM[4]
+always @(posedge ~CLK[0]) begin : ~GENSYM[~COMPNAME_Ram][1]
   if (~ARG[5]) begin
-    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
+    ~SYM[0][~ARG[3]] <= ~ARG[6];
   end
 end
 
-assign ~RESULT = RAM_~SYM[0][~ARG[4]];
+assign ~RESULT = ~SYM[0][~ARG[4]];
 // asyncRam end"
     }
   }
diff --git a/primitives/CLaSH.Prelude.ROM.File.json b/primitives/CLaSH.Prelude.ROM.File.json
--- a/primitives/CLaSH.Prelude.ROM.File.json
+++ b/primitives/CLaSH.Prelude.ROM.File.json
@@ -8,13 +8,13 @@
               -> BitVector m"
     , "templateD" :
 "// asyncRomFile begin
-reg ~TYPO ROM_~SYM[0] [0:~LIT[1]-1];
+reg ~TYPO ~GENSYM[ROM][0] [0:~LIT[1]-1];
 
 initial begin
-  $readmemb(~FILE[~LIT[2]],ROM_~SYM[0]);
+  $readmemb(~FILE[~LIT[2]],~SYM[0]);
 end
 
-assign ~RESULT = ROM_~SYM[0][~ARG[3]];
+assign ~RESULT = ~SYM[0][~ARG[3]];
 // asyncRomFile end"
     }
   }
@@ -29,18 +29,18 @@
           -> Signal' clk (BitVector m)"
     , "templateD" :
 "// romFile begin
-reg ~TYPO ROM_~SYM[0] [0:~LIT[2]-1];
+reg ~TYPO ~GENSYM[ROM][0] [0:~LIT[2]-1];
 
 initial begin
-  $readmemb(~FILE[~LIT[3]],ROM_~SYM[0]);
+  $readmemb(~FILE[~LIT[3]],~SYM[0]);
 end
 
-reg ~TYPO dout_~SYM[1];
-always @(posedge ~CLK[1]) begin : romFile_~COMPNAME_~SYM[2]
-  dout_~SYM[1] <= ROM_~SYM[0][~ARG[4]];
+reg ~TYPO ~GENSYM[dout][1];
+always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_romFile][2]
+  ~SYM[1] <= ~SYM[0][~ARG[4]];
 end
 
-assign ~RESULT = dout_~SYM[1];
+assign ~RESULT = ~SYM[1];
 // romFile end"
     }
   }
diff --git a/primitives/CLaSH.Prelude.ROM.json b/primitives/CLaSH.Prelude.ROM.json
--- a/primitives/CLaSH.Prelude.ROM.json
+++ b/primitives/CLaSH.Prelude.ROM.json
@@ -7,18 +7,18 @@
            -> a"
     , "templateD" :
 "// asyncRom begin
-wire ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];
+wire ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];
 
-wire ~TYP[1] romflat_~SYM[1];
-assign romflat_~SYM[1] = ~ARG[1];
-genvar ~SYM[2];
+wire ~TYP[1] ~GENSYM[romflat][1];
+assign ~SYM[1] = ~ARG[1];
+genvar ~GENSYM[i][2];
 ~GENERATE
-for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
-  assign ROM_~SYM[0][(~LIT[0]-1)-~SYM[2]] = romflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
+  assign ~SYM[0][(~LIT[0]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
 ~ENDGENERATE
 
-assign ~RESULT = ROM_~SYM[0][~ARG[2]];
+assign ~RESULT = ~SYM[0][~ARG[2]];
 // asyncRom end"
     }
   }
@@ -32,23 +32,23 @@
       -> Signal' clk a"
     , "templateD" :
 "// rom begin
-reg ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];
-reg ~TYPO dout_~SYM[1];
+reg ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];
+reg ~TYPO ~GENSYM[dout][1];
 
-reg ~TYP[2] rom_init_~SYM[2];
-integer ~SYM[3];
+reg ~TYP[2] ~GENSYM[rom_init][2];
+integer ~GENSYM[i][3];
 initial begin
-  rom_init_~SYM[2] = ~ARG[2];
+  ~SYM[2] = ~ARG[2];
   for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
-    ROM_~SYM[0][~LIT[0]-1-~SYM[3]] = rom_init_~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
   end
 end
 
-always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[4]
-  dout_~SYM[1] <= ROM_~SYM[0][~ARG[3]];
+always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_rom][4]
+  ~SYM[1] <= ~SYM[0][~ARG[3]];
 end
 
-assign ~RESULT = dout_~SYM[1];
+assign ~RESULT = ~SYM[1];
 // rom end"
     }
   }
diff --git a/primitives/CLaSH.Signal.Internal.json b/primitives/CLaSH.Signal.Internal.json
--- a/primitives/CLaSH.Signal.Internal.json
+++ b/primitives/CLaSH.Signal.Internal.json
@@ -7,9 +7,9 @@
            -> Signal' clk a"
     , "templateD" :
 "// register begin
-reg ~SIGD[~SYM[0]][2];
+reg ~SIGD[~GENSYM[dout][0]][2];
 
-always @(posedge ~CLK[0] or negedge ~RST[0]) begin : register_~COMPNAME_~SYM[1]
+always @(posedge ~CLK[0] or negedge ~RST[0]) begin : ~GENSYM[~COMPNAME_register][1]
   if (~ ~RST[0]) begin
     ~SYM[0] <= ~ARG[1];
   end else begin
@@ -31,9 +31,9 @@
         -> Signal' clk a"
     , "templateD" :
 "// regEn begin
-reg ~SIGD[~SYM[0]][3];
+reg ~SIGD[~GENSYM[dout][0]][3];
 
-always @(posedge ~CLK[0] or negedge ~RST[0]) begin : regEn_~COMPNAME_~SYM[1]
+always @(posedge ~CLK[0] or negedge ~RST[0]) begin : ~GENSYM[~COMPNAME_regEn][1]
   if (~ ~RST[0]) begin
     ~SYM[0] <= ~ARG[1];
   end else begin
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -55,10 +55,10 @@
         -> Bit"
     , "templateD" :
 "// indexBit begin
-wire ~TYP[1] vec_~SYM[0];
-assign vec_~SYM[0] = ~ARG[1];
+wire ~TYP[1] ~GENSYM[bv][0];
+assign ~SYM[0] = ~ARG[1];
 
-assign ~RESULT = vec_~SYM[0][~ARG[2]];
+assign ~RESULT = ~SYM[0][~ARG[2]];
 // indexBit end"
     }
   }
@@ -72,16 +72,16 @@
              -> BitVector n"
     , "templateD" :
 "// replaceBit start
-reg ~TYPO vec_~SYM[0];
-wire ~TYP[3] din_~SYM[1];
-assign din_~SYM[1] = ~ARG[3];
+reg ~TYPO ~GENSYM[bv][0];
+wire ~TYP[3] ~GENSYM[din][1];
+assign ~SYM[1] = ~ARG[3];
 
 always @(*) begin
-  vec_~SYM[0] = ~ARG[1];
-  vec_~SYM[0][~ARG[2]] = din_~SYM[1];
+  ~SYM[0] = ~ARG[1];
+  ~SYM[0][~ARG[2]] = ~SYM[1];
 end
 
-assign ~RESULT = vec_~SYM[0];
+assign ~RESULT = ~SYM[0];
 // replaceBit end"
     }
   }
@@ -95,13 +95,13 @@
            -> BitVector (m + 1 + i)"
     , "templateD" :
 "// setSlice begin
-reg ~SIGD[~SYM[0]][0];
-wire ~TYP[3] din_~SYM[1];
-assign din_~SYM[1] = ~ARG[3]
+reg ~SIGD[~GENSYM[bv][0]][0];
+wire ~TYP[3] ~GENSYM[din][1];
+assign ~SYM[1] = ~ARG[3]
 
 always @(*) begin
   ~SYM[0] = ~ARG[0];
-  ~SYM[0][~LIT[1] : ~LIT[2]] = din_~SYM[1];
+  ~SYM[0][~LIT[1] : ~LIT[2]] = ~SYM[1];
 end
 
 assign ~RESULT = ~SYM[0];
@@ -117,7 +117,7 @@
         -> BitVector (m + 1 - n)"
     , "templateD" :
 "// slice begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[bv][0]][0];
 assign ~SYM[0] = ~ARG[0];
 assign ~RESULT = ~SYM[0][~LIT[1] : ~LIT[2]];
 // slice end"
@@ -140,7 +140,7 @@
       -> Bit"
     , "templateD" :
 "// msb begin~IF ~LIT[0] ~THEN
-wire ~SIGD[~SYM[0]][1];
+wire ~SIGD[~GENSYM[bv][0]][1];
 assign ~SYM[0] = ~ARG[1];
 assign ~RESULT = ~SYM[0][~LIT[0]-1];
 ~ELSE
@@ -155,7 +155,7 @@
       -> Bit"
     , "templateD" :
 "// lsb begin~IF ~SIZE[~TYP[0]] ~THEN
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[bv][0]][0];
 assign ~SYM[0] = ~ARG[0];
 assign ~RESULT = ~SYM[0][0];
 ~ELSE
@@ -329,7 +329,7 @@
     , "type"      : "rotateR# :: KnownNat n => BitVector n -> Int -> BitVector n"
     , "templateD" :
 "// rotateR begin
-wire [2*~LIT[0]-1:0] ~SYM[0];
+wire [2*~LIT[0]-1:0] ~GENSYM[bv][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
 assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];
 // rotateR end"
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -137,9 +137,9 @@
     , "type"      : "div# :: Signed n -> Signed n -> Signed n"
     , "templateD" :
 "// divInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // divide (rounds towards zero)
 assign ~SYM[0] = ~ARG[0] / ~ARG[1];
@@ -156,9 +156,9 @@
     , "type"      : "mod# :: Signed n -> Signed n -> Signed n"
     , "templateD" :
 "// modSigned begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[rem_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // remainder
 assign ~SYM[0] = ~ARG[0] % ~ARG[1];
@@ -230,7 +230,7 @@
     , "type"      : "rotateR# :: KnownNat n => Signed n -> Int -> Signed n"
     , "templateD" :
 "// rotateR begin
-wire [2*~LIT[0]-1:0] ~SYM[0];
+wire [2*~LIT[0]-1:0] ~GENSYM[s][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
 assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
 // rotateR end"
@@ -245,7 +245,7 @@
 ~GENERATE
 if (~LIT[1] < ~LIT[0]) begin
   // truncate, sign preserving
-  wire ~SIGD[~SYM[0]][2];
+  wire ~SIGD[~GENSYM[s][0]][2];
   assign ~SYM[0] = ~ARG[2];
   assign ~RESULT = $signed({~SYM[0][~LIT[0]-1],~SYM[0][(~LIT[1]-2):0]});
 end else begin
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -171,7 +171,7 @@
     , "type"      : "rotateL# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
 "// rotateL begin
-wire [2*~LIT[0]-1:0] ~SYM[0];
+wire [2*~LIT[0]-1:0] ~GENSYM[u][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
 assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
 // rotateL end"
@@ -182,7 +182,7 @@
     , "type"      : "rotateR# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
 "// rotateR begin
-wire [2*~LIT[0]-1:0] ~SYM[0];
+wire [2*~LIT[0]-1:0] ~GENSYM[u][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
 assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
 // rotateR end"
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -3,7 +3,7 @@
     , "type"      : "head :: Vec (n + 1) a -> a"
     , "templateD" :
 "// head begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[vec][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 -: ~SIZE[~TYPO]];
@@ -15,7 +15,7 @@
     , "type"      : "tail :: Vec (n + 1) a -> Vec n a"
     , "templateD" :
 "// tail begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[vec][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1 : 0];
@@ -27,7 +27,7 @@
     , "type"      : "Vec (n + 1) a -> a"
     , "templateD" :
 "// last begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[vec][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1:0];
@@ -39,7 +39,7 @@
     , "type"      : "Vec (n + 1) a -> Vec n a"
     , "templateD" :
 "// init begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[vec][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 : ~SIZE[~TYPEL[~TYP[0]]]];
@@ -57,20 +57,20 @@
         -> Vec n a"
     , "templateD" :
 "// select begin
-wire ~SIGD[~SYM[0]][4];
+wire ~SIGD[~GENSYM[vec][0]][4];
 assign ~SYM[0] = ~ARG[4];
 
 wire ~TYPEL[~TYPO] ~SYM[1] [0:~LENGTH[~TYP[4]]-1];
-genvar ~SYM[2];
+genvar ~GENSYM[i][2];
 ~GENERATE
-for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[4]]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
+for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[4]]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
   assign ~SYM[1][(~LENGTH[~TYP[4]]-1)-~SYM[2]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
 end
 ~ENDGENERATE
 
-genvar ~SYM[4];
+genvar ~GENSYM[i][4];
 ~GENERATE
-for (~SYM[4]=0; ~SYM[4] < ~LIT[3]; ~SYM[4] = ~SYM[4] + 1) begin : select_~SYM[5]
+for (~SYM[4]=0; ~SYM[4] < ~LIT[3]; ~SYM[4] = ~SYM[4] + 1) begin : ~GENSYM[select][5]
   assign ~RESULT[(~LIT[3]-1-~SYM[4])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[1][~LIT[1] + (~LIT[2] * ~SYM[4])];
 end
 ~ENDGENERATE
@@ -110,14 +110,14 @@
     , "type"      : "map :: (a -> b) -> Vec n a -> Vec n b"
     , "templateD" :
 "// map begin
-wire ~SIGD[~SYM[0]][1];
+wire ~SIGD[~GENSYM[vec][0]][1];
 assign ~SYM[0] = ~ARG[1];
 
-genvar ~SYM[1];
+genvar ~GENSYM[i][1];
 ~GENERATE
-for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
-  wire ~TYPEL[~TYP[1]] ~SYM[3];
-  wire ~TYPEL[~TYPO] ~SYM[4];
+for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[map][2]
+  wire ~TYPEL[~TYP[1]] ~GENSYM[map_in][3];
+  wire ~TYPEL[~TYPO] ~GENSYM[map_out][4];
 
   assign ~SYM[3] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];
   ~INST 0
@@ -135,15 +135,15 @@
     , "type"      : "imap :: KnownNat n => (Index n -> a -> b) -> Vec n a -> Vec n b"
     , "templateD" :
 "// imap begin
-wire ~SIGD[~SYM[0]][2];
+wire ~SIGD[~GENSYM[vec][0]][2];
 assign ~SYM[0] = ~ARG[2];
 
-genvar ~SYM[1];
+genvar ~GENSYM[i][1];
 ~GENERATE
-for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
-  wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~SYM[3];
-  wire ~TYPEL[~TYP[2]] ~SYM[4];
-  wire ~TYPEL[~TYPO] ~SYM[5];
+for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[imap][2]
+  wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~GENSYM[map_index][3];
+  wire ~TYPEL[~TYP[2]] ~GENSYM[map_in][4];
+  wire ~TYPEL[~TYPO] ~GENSYM[map_out][5];
 
   assign ~SYM[3] = ~SYM[1];
   assign ~SYM[4] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
@@ -163,16 +163,16 @@
     , "type"      : "zipWith :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c"
     , "templateD" :
 "// zipWith start
-wire ~SIGD[~SYM[0]][1];
-wire ~SIGD[~SYM[1]][2];
+wire ~SIGD[~GENSYM[vec1][0]][1];
+wire ~SIGD[~GENSYM[vec2][1]][2];
 assign ~SYM[0] = ~ARG[1];
 assign ~SYM[1] = ~ARG[2];
 
-genvar ~SYM[2];
+genvar ~GENSYM[i][2];
 ~GENERATE
-for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : zipWith_~SYM[2]
-  wire ~TYPEL[~TYP[1]] ~SYM[3];
-  wire ~TYPEL[~TYP[2]] ~SYM[4];
+for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : ~GENSYM[zipWith][6]
+  wire ~TYPEL[~TYP[1]] ~GENSYM[zipWith_in1][3];
+  wire ~TYPEL[~TYP[2]] ~GENSYM[zipWith_in2][4];
   wire ~TYPEL[~TYPO] ~SYM[5];
 
   assign ~SYM[3] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];
@@ -193,31 +193,31 @@
     , "type"      : "foldr :: (a -> b -> b) -> b -> Vec n a -> b"
     , "templateD" :
 "// foldr start~IF ~LENGTH[~TYP[2]] ~THEN
-wire ~TYPO intermediate_~SYM[0] [0:~LENGTH[~TYP[2]]];
-assign intermediate_~SYM[0][~LENGTH[~TYP[2]]] = ~ARG[1];
+wire ~TYPO ~GENSYM[intermediate][0] [0:~LENGTH[~TYP[2]]];
+assign ~SYM[0][~LENGTH[~TYP[2]]] = ~ARG[1];
 
-wire ~TYP[2] xs_~SYM[2];
-assign xs_~SYM[2] = ~ARG[2];
+wire ~TYP[2] ~GENSYM[xs][2];
+assign ~SYM[2] = ~ARG[2];
 
-genvar i_~SYM[3];
+genvar ~GENSYM[i][3];
 ~GENERATE
-for (i_~SYM[3]=0; i_~SYM[3] < ~LENGTH[~TYP[2]]; i_~SYM[3]=i_~SYM[3]+1) begin : foldr_~SYM[4]
-  wire ~TYPEL[~TYP[2]] ~SYM[5];
-  wire ~TYPO ~SYM[6];
-  wire ~TYPO ~SYM[7];
+for (~SYM[3]=0; ~SYM[3] < ~LENGTH[~TYP[2]]; ~SYM[3]=~SYM[3]+1) begin : ~GENSYM[foldr][4]
+  wire ~TYPEL[~TYP[2]] ~GENSYM[foldr_in1][5];
+  wire ~TYPO ~GENSYM[foldr_in2][6];
+  wire ~TYPO ~GENSYM[foldr_out][7];
 
-  assign ~SYM[5] = xs_~SYM[2][(~LENGTH[~TYP[2]]-1-i_~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
-  assign ~SYM[6] = intermediate_~SYM[0][i_~SYM[3]+1];
+  assign ~SYM[5] = ~SYM[2][(~LENGTH[~TYP[2]]-1-~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
+  assign ~SYM[6] = ~SYM[0][~SYM[3]+1];
   ~INST 0
     ~OUTPUT <= ~SYM[7]~ ~TYP[1]~
     ~INPUT  <= ~SYM[5]~ ~TYPEL[~TYP[2]]~
     ~INPUT  <= ~SYM[6]~ ~TYP[1]~
   ~INST
-  assign intermediate_~SYM[0][i_~SYM[3]] = ~SYM[7];
+  assign ~SYM[0][~SYM[3]] = ~SYM[7];
 end
 ~ENDGENERATE
 
-assign ~RESULT = intermediate_~SYM[0][0];
+assign ~RESULT = ~SYM[0][0];
 ~ELSE
 assign ~RESULT = ~ARG[1];
 ~FI// foldr end"
@@ -230,63 +230,63 @@
     , "templateD" :
 "// fold begin
 // put flat input array into the first half of the intermediate array
-wire ~TYPO intermediate_~SYM[0] [0:(2*~LENGTH[~TYP[1]])-2];
-wire ~TYP[1] vecflat_~SYM[1];
-assign vecflat_~SYM[1] = ~ARG[1];
-genvar ~SYM[2];
+wire ~TYPO ~GENSYM[intermediate][0] [0:(2*~LENGTH[~TYP[1]])-2];
+wire ~TYP[1] ~GENSYM[vecflat][1];
+assign ~SYM[1] = ~ARG[1];
+genvar ~GENSYM[i][2];
 ~GENERATE
-for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[1]]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
-  assign intermediate_~SYM[0][(~LENGTH[~TYP[1]]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[1]]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
+  assign ~SYM[0][(~LENGTH[~TYP[1]]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
 ~ENDGENERATE
 
 // calculate the depth of the tree
-function integer log2_~SYM[9];
+function integer ~GENSYM[log2][14];
   input integer value;
   begin
     value = value-1;
-    for (log2_~SYM[9]=0; value>0; log2_~SYM[9]=log2_~SYM[9]+1)
+    for (~SYM[14]=0; value>0; ~SYM[14]=~SYM[14]+1)
       value = value>>1;
   end
 endfunction
 
-localparam levels_~SYM[4] = log2_~SYM[9](~LENGTH[~TYP[1]]);
+localparam ~GENSYM[levels][4] = ~SYM[14](~LENGTH[~TYP[1]]);
 
 // given a level and a depth, calculate the corresponding index into the
 // intermediate array
-function integer depth2Index_~SYM[8];
+function integer ~GENSYM[depth2Index][13];
   input integer levels;
   input integer depth;
 
-  depth2Index_~SYM[8] = (2 ** levels) - (2 ** depth);
+  ~SYM[13] = (2 ** levels) - (2 ** depth);
 endfunction
 
 // Create the tree of instantiated components
-genvar d_~SYM[5];
-genvar i_~SYM[6];
+genvar ~GENSYM[d][5];
+genvar ~GENSYM[i][6];
 ~GENERATE
-if (levels_~SYM[4] != 0) begin : make_tree_~SYM[7]
-  for (d_~SYM[5] = (levels_~SYM[4] - 1); d_~SYM[5] >= 0; d_~SYM[5]=d_~SYM[5]-1) begin : tree_depth
-    for (i_~SYM[6] = 0; i_~SYM[6] < (2**d_~SYM[5]); i_~SYM[6] = i_~SYM[6]+1) begin : tree_depth_loop
-      wire ~TYPO ~SYM[8];
-      wire ~TYPO ~SYM[9];
-      wire ~TYPO ~SYM[10];
+if (~SYM[4] != 0) begin : ~GENSYM[make_tree][7]
+  for (~SYM[5] = (~SYM[4] - 1); ~SYM[5] >= 0; ~SYM[5]=~SYM[5]-1) begin : ~GENSYM[tree_depth][11]
+    for (~SYM[6] = 0; ~SYM[6] < (2**~SYM[5]); ~SYM[6] = ~SYM[6]+1) begin : ~GENSYM[tree_depth_loop][12]
+      wire ~TYPO ~GENSYM[fold_in1][8];
+      wire ~TYPO ~GENSYM[fold_in2][9];
+      wire ~TYPO ~GENSYM[fold_out][10];
 
-      assign ~SYM[8] = intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])];
-      assign ~SYM[9] = intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])+1];
+      assign ~SYM[8] = ~SYM[0][~SYM[13](~SYM[4]+1,~SYM[5]+2)+(2*~SYM[6])];
+      assign ~SYM[9] = ~SYM[0][~SYM[13](~SYM[4]+1,~SYM[5]+2)+(2*~SYM[6])+1];
       ~INST 0
         ~OUTPUT <= ~SYM[10]~ ~TYPO~
         ~INPUT  <= ~SYM[8]~ ~TYPO~
         ~INPUT  <= ~SYM[9]~ ~TYPO~
       ~INST
-      assign intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+1)+i_~SYM[6]] = ~SYM[10];
+      assign ~SYM[0][~SYM[13](~SYM[4]+1,~SYM[5]+1)+~SYM[6]] = ~SYM[10];
     end
   end
 end
 ~ENDGENERATE
 
 // The last element of the intermediate array holds the result
-assign ~RESULT = intermediate_~SYM[0][(2*~LENGTH[~TYP[1]])-2];
+assign ~RESULT = ~SYM[0][(2*~LENGTH[~TYP[1]])-2];
 // fold end"
     }
   }
@@ -295,18 +295,18 @@
     , "type"      : "index_integer :: KnownNat n => Vec n a -> Int -> a"
     , "templateD" :
 "// indexVec begin
-wire ~TYPO vec_~SYM[0] [0:~LIT[0]-1];
+wire ~TYPO ~GENSYM[vec][0] [0:~LIT[0]-1];
 
-wire ~TYP[1] vecflat_~SYM[1];
-assign vecflat_~SYM[1] = ~ARG[1];
-genvar ~SYM[2];
+wire ~TYP[1] ~GENSYM[vecflat][1];
+assign ~SYM[1] = ~ARG[1];
+genvar ~GENSYM[i][2];
 ~GENERATE
-for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
-  assign vec_~SYM[0][(~LIT[0]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
+  assign ~SYM[0][(~LIT[0]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
 ~ENDGENERATE
 
-assign ~RESULT = vec_~SYM[0][~ARG[2]];
+assign ~RESULT = ~SYM[0][~ARG[2]];
 // indexVec end"
     }
   }
@@ -315,22 +315,22 @@
     , "type"      : "replace_int :: KnownNat n => Vec n a -> Int -> a -> Vec n a"
     , "templateD" :
 "// replaceVec start
-wire ~TYP[1] vecflat_~SYM[0];
-assign vecflat_~SYM[0] = ~ARG[1];
+wire ~TYP[1] ~GENSYM[vecflat][0];
+assign ~SYM[0] = ~ARG[1];
 
-reg ~TYP[3] vec_~SYM[1] [0:~LIT[0]-1];
-integer ~SYM[2];
+reg ~TYP[3] ~GENSYM[vec][1] [0:~LIT[0]-1];
+integer ~GENSYM[i][2];
 always @(*) begin
   for (~SYM[2]=0;~SYM[2]<~LIT[0];~SYM[2]=~SYM[2]+1) begin
-    vec_~SYM[1][~LIT[0]-1-~SYM[2]] = vecflat_~SYM[0][~SYM[2]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]];
+    ~SYM[1][~LIT[0]-1-~SYM[2]] = ~SYM[0][~SYM[2]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]];
   end
-  vec_~SYM[1][~ARG[2]] = ~ARG[3];
+  ~SYM[1][~ARG[2]] = ~ARG[3];
 end
 
-genvar ~SYM[3];
+genvar ~GENSYM[i][3];
 ~GENERATE
-for (~SYM[3]=0;~SYM[3]<~LIT[0];~SYM[3]=~SYM[3]+1) begin : vec_~SYM[4]
-  assign ~RESULT[~SYM[3]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = vec_~SYM[1][(~LIT[0]-1)-~SYM[3]];
+for (~SYM[3]=0;~SYM[3]<~LIT[0];~SYM[3]=~SYM[3]+1) begin : ~GENSYM[mk_vec][4]
+  assign ~RESULT[~SYM[3]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = ~SYM[1][(~LIT[0]-1)-~SYM[3]];
 end
 ~ENDGENERATE
 // replaceVec end"
@@ -359,14 +359,14 @@
     , "type"      : "transpose :: KnownNat n => Vec m (Vec n a) -> Vec n (Vec m a)"
     , "templateD" :
 "// transpose begin
-wire ~SIGD[~SYM[0]][1];
+wire ~SIGD[~GENSYM[matrix][0]][1];
 assign ~SYM[0] = ~ARG[1];
 
-genvar ~SYM[1];
-genvar ~SYM[2];
+genvar ~GENSYM[row_index][1];
+genvar ~GENSYM[col_index][2];
 ~GENERATE
-for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYP[1]]; ~SYM[1] = ~SYM[1] + 1) begin : transpose_outer_~SYM[3]
-  for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : transpose_inner_~SYM[4]
+for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYP[1]]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[transpose_outer][3]
+  for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : ~GENSYM[transpose_inner][4]
     assign ~RESULT[((~SYM[2]*~SIZE[~TYPEL[~TYPO]])+(~SYM[1]*~SIZE[~TYPEL[~TYPEL[~TYPO]]]))+:~SIZE[~TYPEL[~TYPEL[~TYPO]]]] = ~SYM[0][((~SYM[1]*~SIZE[~TYPEL[~TYP[1]]])+(~SYM[2]*~SIZE[~TYPEL[~TYPEL[~TYPO]]]))+:~SIZE[~TYPEL[~TYPEL[~TYPO]]]];
   end
 end
@@ -379,12 +379,12 @@
     , "type"      : "reverse :: Vec n a -> Vec n a"
     , "templateD" :
 "// reverse begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[vec][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-genvar ~SYM[1];
+genvar ~GENSYM[i][1];
 ~GENERATE
-for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2]
+for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[reverse][2]
   assign ~RESULT[(~LENGTH[~TYPO] - 1 - ~SYM[1])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
 end
 ~ENDGENERATE
@@ -420,17 +420,17 @@
     , "type"      : "rotateLeftS :: KnownNat n => Vec n a -> SNat d -> Vec n a"
     , "templateD" :
 "// rotateLeftS begin
-wire ~TYP[1] ~SYM[1];
-localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];
+wire ~TYP[1] ~GENSYM[vec][1];
+localparam ~GENSYM[shift_amount][2] = ~LIT[2] % ~LIT[0];
 
 assign ~SYM[1] = ~ARG[1];
 
 ~GENERATE
-if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]
+if (~SYM[2] == 0) begin : ~GENSYM[no_shift][3]
   assign ~RESULT = ~SYM[1];
-end else begin : do_shift_~SYM[4]
-  assign ~RESULT = {~SYM[1][((~LIT[0]-shift_amount_~SYM[2])*~SIZE[~TYPEL[~TYPO]])-1 : 0]
-                   ,~SYM[1][~SIZE[~TYPO]-1 : (~LIT[0]-shift_amount_~SYM[2])*~SIZE[~TYPEL[~TYPO]]]
+end else begin : ~GENSYM[do_shift][4]
+  assign ~RESULT = {~SYM[1][((~LIT[0]-~SYM[2])*~SIZE[~TYPEL[~TYPO]])-1 : 0]
+                   ,~SYM[1][~SIZE[~TYPO]-1 : (~LIT[0]-~SYM[2])*~SIZE[~TYPEL[~TYPO]]]
                    };
 end
 ~ENDGENERATE
@@ -442,17 +442,17 @@
     , "type"      : "rotateRightS :: KnownNat n => Vec n a -> SNat d -> Vec n a"
     , "templateD" :
 "// rotateRightS begin
-wire ~TYP[1] ~SYM[1];
-localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];
+wire ~TYP[1] ~GENSYM[vec][1];
+localparam ~GENSYM[shift_amount][2] = ~LIT[2] % ~LIT[0];
 
 assign ~SYM[1] = ~ARG[1];
 
 ~GENERATE
-if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]
+if (~SYM[2] == 0) begin : ~GENSYM[no_shift][3]
   assign ~RESULT = ~SYM[1];
-end else begin : do_shift_~SYM[4]
-  assign ~RESULT = {~SYM[1][(shift_amount_~SYM[2]*~SIZE[~TYPEL[~TYPO]])-1 : 0]
-                   ,~SYM[1][~SIZE[~TYPO]-1 : shift_amount_~SYM[2]*~SIZE[~TYPEL[~TYPO]]]
+end else begin : ~GENSYM[do_shift][4]
+  assign ~RESULT = {~SYM[1][(~SYM[2]*~SIZE[~TYPEL[~TYPO]])-1 : 0]
+                   ,~SYM[1][~SIZE[~TYPO]-1 : ~SYM[2]*~SIZE[~TYPEL[~TYPO]]]
                    };
 end
 ~ENDGENERATE
diff --git a/primitives/GHC.Base.json b/primitives/GHC.Base.json
--- a/primitives/GHC.Base.json
+++ b/primitives/GHC.Base.json
@@ -20,9 +20,9 @@
     , "type"      : "divInt :: Int -> Int -> Int"
     , "templateD" :
 "// divInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // divide (rounds towards zero)
 assign ~SYM[0] = ~ARG[0] / ~ARG[1];
@@ -39,9 +39,9 @@
     , "type"      : "modInt :: Int -> Int -> Int"
     , "templateD" :
 "// modInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[rem_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // remainder
 assign ~SYM[0] = ~ARG[0] % ~ARG[1];
diff --git a/primitives/GHC.Classes.json b/primitives/GHC.Classes.json
--- a/primitives/GHC.Classes.json
+++ b/primitives/GHC.Classes.json
@@ -57,9 +57,9 @@
     , "type"      : "divInt# :: Int# -> Int# -> Int#"
     , "templateD" :
 "// divInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // divide (rounds towards zero)
 assign ~SYM[0] = ~ARG[0] / ~ARG[1];
@@ -76,9 +76,9 @@
     , "type"      : "modInt# :: Int# -> Int# -> Int#"
     , "templateD" :
 "// modInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[rem_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // remainder
 assign ~SYM[0] = ~ARG[0] % ~ARG[1];
diff --git a/primitives/GHC.Integer.Type.json b/primitives/GHC.Integer.Type.json
--- a/primitives/GHC.Integer.Type.json
+++ b/primitives/GHC.Integer.Type.json
@@ -45,9 +45,9 @@
     , "type"      : "divInteger :: Integer -> Integer -> Integer"
     , "templateD" :
 "// divInteger begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // divide (rounds towards zero)
 assign ~SYM[0] = ~ARG[0] / ~ARG[1];
@@ -64,9 +64,9 @@
     , "type"      : "modInteger :: Integer -> Integer -> Integer"
     , "templateD" :
 "// modInteger begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-wire ~SIGD[~SYM[2]][1];
+wire ~SIGD[~GENSYM[rem_res][0]][0];
+wire ~SIGD[~GENSYM[dividend][1]][0];
+wire ~SIGD[~GENSYM[divider][2]][1];
 
 // remainder
 assign ~SYM[0] = ~ARG[0] % ~ARG[1];
diff --git a/primitives/GHC.Prim.json b/primitives/GHC.Prim.json
--- a/primitives/GHC.Prim.json
+++ b/primitives/GHC.Prim.json
@@ -75,1768 +75,1719 @@
     , "type"      : "quotRemInt# :: Int# -> Int# -> (#Int#, Int##)"
     , "templateD" :
 "// quotRemInt begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-assign ~SYM[0] = ~ARG[0] / ~ARG[1];
-assign ~SYM[1] = ~ARG[0] % ~ARG[1];
-
-assign ~RESULT = {~SYM[0],~SYM[1]};
-// quotRemInt end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.andI#"
-    , "type"      : "andI# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] & ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.orI#"
-    , "type"      : "orI# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] | ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.xorI#"
-    , "type"      : "xorI# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] ^ ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.notI#"
-    , "type"      : "notI# :: Int# -> Int#"
-    , "templateE" : "~ ~ARG[0]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.negateInt#"
-    , "type"      : "negateInt# :: Int# -> Int#"
-    , "templateE" : "-(~ARG[0])"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.>#"
-     , "type"     : "(>#) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.>=#"
-    , "type"      : "(>=#) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.==#"
-    , "type"      : "(==) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim./=#"
-    , "type"      : "(/=#) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.<#"
-    , "type"      : "(<#) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.<=#"
-    , "type"      : "(<=#) :: Int# -> Int# -> Int#"
-    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.chr#"
-    , "type"      : "ord :: Int# -> Char#"
-    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.int2Word#"
-    , "type"      : "int2Word# :: Int# -> Word#"
-    , "templateE" : "$unsigned(~ARG[0])"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftL#"
-    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] <<< ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
-    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] >>> ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
-    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] >> ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.plusWord#"
-    , "type"      : "plusWord# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] + ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.minusWord#"
-    , "type"      : "minusWord# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] - ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.timesWord#"
-    , "type"      : "timesWord# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] * ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.quotWord#"
-    , "type"      : "quotWord# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] / ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.remWord#"
-    , "type"      : "remWord# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] % ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.quotRemWord#"
-    , "type"      : "quotRemWord# :: Word# -> Word# -> (#Word#, Word##)"
-    , "templateD" :
-"// quotRemWord begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][0];
-assign ~SYM[0] = ~ARG[0] / ~ARG[1];
-assign ~SYM[1] = ~ARG[0] % ~ARG[1];
-
-assign ~RESULT = {~SYM[0],~SYM[1]};
-// quotRemWord end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.and#"
-    , "type"      : "and# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] & ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.or#"
-    , "type"      : "or# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] | ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.xor#"
-    , "type"      : "xor# :: Word# -> Word# -> Word#"
-    , "templateE" : "~ARG[0] ^ ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.not#"
-    , "type"      : "not# :: Word# -> Word#"
-    , "templateE" : "~ ~ARG[0]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedShiftL#"
-    , "type"      : "uncheckedShiftL# :: Word# -> Int# -> Word#"
-    , "templateE" : "~ARG[0] << ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftL#"
-    , "type"      : "uncheckedShiftRL# :: Word# -> Int# -> Word#"
-    , "templateE" : "~ARG[0] >> ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.word2Int#"
-    , "type"      : "int2Word# :: Word# -> Int#"
-    , "templateE" : "$signed(~ARG[0])"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.gtWord#"
-     , "type"     : "gtWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.geWord#"
-    , "type"      : "geWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.eqWord#"
-    , "type"      : "eqWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.neWord#"
-    , "type"      : "neWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ltWord#"
-    , "type"      : "ltWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.leWord#"
-    , "type"      : "leWord# :: Word# -> Word# -> Int#"
-    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.popCnt8#"
-    , "type"      : "popCnt8# :: Word# -> Word#"
-    , "templateD" :
-"// popCnt8 begin
-localparam width_~SYM[0] = 8;
-
-// ceiling of log2
-function integer log2_~SYM[1];
-  input integer value;
-  begin
-    value = value-1;
-    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
-      value = value>>1;
-  end
-endfunction
-
-// depth of the tree
-localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
-
-wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
-
-// put input into the first half of the intermediate array
-genvar i_~SYM[4];
-~GENERATE
-for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
-  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
-end
-~ENDGENERATE
-
-// given a level and a depth, calculate the corresponding index into the
-// intermediate array
-function integer depth2Index_~SYM[5];
-  input integer levels;
-  input integer depth;
-
-  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
-endfunction
-
-// Create the tree of instantiated components
-genvar d_~SYM[6];
-genvar i_~SYM[7];
-~GENERATE
-if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
-  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
-    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
-      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
-    end
-  end
-end
-~ENDGENERATE
-
-// The last element of the intermediate array holds the result
-assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
-// popCnt8 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.popCnt16#"
-    , "type"      : "popCnt16# :: Word# -> Word#"
-    , "templateD" :
-"// popCnt16 begin
-localparam width_~SYM[0] = 16;
-
-// ceiling of log2
-function integer log2_~SYM[1];
-  input integer value;
-  begin
-    value = value-1;
-    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
-      value = value>>1;
-  end
-endfunction
-
-// depth of the tree
-localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
-
-wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
-
-// put input into the first half of the intermediate array
-genvar i_~SYM[4];
-~GENERATE
-for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
-  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
-end
-~ENDGENERATE
-
-// given a level and a depth, calculate the corresponding index into the
-// intermediate array
-function integer depth2Index_~SYM[5];
-  input integer levels;
-  input integer depth;
-
-  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
-endfunction
-
-// Create the tree of instantiated components
-genvar d_~SYM[6];
-genvar i_~SYM[7];
-~GENERATE
-if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
-  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
-    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
-      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
-    end
-  end
-end
-~ENDGENERATE
-
-// The last element of the intermediate array holds the result
-assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
-// popCnt16 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.popCnt32#"
-    , "type"      : "popCnt32# :: Word# -> Word#"
-    , "templateD" :
-"// popCnt32 begin
-localparam width_~SYM[0] = 32;
-
-// ceiling of log2
-function integer log2_~SYM[1];
-  input integer value;
-  begin
-    value = value-1;
-    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
-      value = value>>1;
-  end
-endfunction
-
-// depth of the tree
-localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
-
-wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
-
-// put input into the first half of the intermediate array
-genvar i_~SYM[4];
-~GENERATE
-for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
-  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
-end
-~ENDGENERATE
-
-// given a level and a depth, calculate the corresponding index into the
-// intermediate array
-function integer depth2Index_~SYM[5];
-  input integer levels;
-  input integer depth;
-
-  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
-endfunction
-
-// Create the tree of instantiated components
-genvar d_~SYM[6];
-genvar i_~SYM[7];
-~GENERATE
-if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
-  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
-    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
-      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
-    end
-  end
-end
-~ENDGENERATE
-
-// The last element of the intermediate array holds the result
-assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
-// popCnt32 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.popCnt64#"
-    , "type"      : "popCnt64# :: Word# -> Word#"
-    , "templateD" :
-"// popCnt64 begin
-localparam width_~SYM[0] = 64;
-
-// ceiling of log2
-function integer log2_~SYM[1];
-  input integer value;
-  begin
-    value = value-1;
-    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
-      value = value>>1;
-  end
-endfunction
-
-// depth of the tree
-localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
-
-wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
-
-// put input into the first half of the intermediate array
-genvar i_~SYM[4];
-~GENERATE
-for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
-  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
-end
-~ENDGENERATE
-
-// given a level and a depth, calculate the corresponding index into the
-// intermediate array
-function integer depth2Index_~SYM[5];
-  input integer levels;
-  input integer depth;
-
-  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
-endfunction
-
-// Create the tree of instantiated components
-genvar d_~SYM[6];
-genvar i_~SYM[7];
-~GENERATE
-if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
-  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
-    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
-      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
-    end
-  end
-end
-~ENDGENERATE
-
-// The last element of the intermediate array holds the result
-assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
-// popCnt64 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.popCnt#"
-    , "type"      : "popCnt8# :: Word# -> Word#"
-    , "templateD" :
-"// popCnt begin
-localparam width_~SYM[0] = ~SIZE[~TYPO];
-
-// ceiling of log2
-function integer log2_~SYM[1];
-  input integer value;
-  begin
-    value = value-1;
-    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
-      value = value>>1;
-  end
-endfunction
-
-// depth of the tree
-localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
-
-wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
-
-// put input into the first half of the intermediate array
-genvar i_~SYM[4];
-~GENERATE
-for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
-  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
-end
-~ENDGENERATE
-
-// given a level and a depth, calculate the corresponding index into the
-// intermediate array
-function integer depth2Index_~SYM[5];
-  input integer levels;
-  input integer depth;
-
-  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
-endfunction
-
-// Create the tree of instantiated components
-genvar d_~SYM[6];
-genvar i_~SYM[7];
-~GENERATE
-if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
-  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
-    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
-      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
-             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
-    end
-  end
-end
-~ENDGENERATE
-
-// The last element of the intermediate array holds the result
-assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
-// popCnt end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.clz8#"
-    , "type"      : "clz8 :: Word# -> Word#"
-    , "templateD" :
-"// clz8 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:7] v;
-assign v = ~ARG[0][7:0];
-
-wire [0:7] e;
-genvar i;
-~GENERATE
-for (i=0;i<4;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:5] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<2;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:3] res;
-~GENERATE
-if (1) begin
-localparam n = 3;
-wire [5:0] i;
-assign i = a[0:5];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// clz8 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.clz16#"
-    , "type"      : "clz16 :: Word# -> Word#"
-    , "templateD" :
-"// clz16 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:15] v;
-assign v = ~ARG[0][15:0];
-
-wire [0:15] e;
-genvar i;
-~GENERATE
-for (i=0;i<8;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:11] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<4;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:7] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<2;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:4] res;
-~GENERATE
-if (1) begin
-localparam n = 4;
-wire [7:0] i;
-assign i = b[0:7];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// clz16 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.clz32#"
-    , "type"      : "clz32 :: Word# -> Word#"
-    , "templateD" :
-"// clz32 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:31] v;
-assign v = ~ARG[0][31:0];
-
-wire [0:31] e;
-genvar i;
-~GENERATE
-for (i=0;i<16;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:23] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:15] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:9] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:5] res;
-~GENERATE
-if (1) begin
-localparam n = 5;
-wire [9:0] i;
-assign i = c[0:9];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// clz32 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.clz64#"
-    , "type"      : "clz64 :: Word# -> Word#"
-    , "templateD" :
-"// clz64 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:63] v;
-assign v = ~ARG[0][63:0];
-
-wire [0:63] e;
-genvar i;
-~GENERATE
-for (i=0;i<32;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:47] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:31] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:19] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:11] d;
-genvar i4;
-~GENERATE
-for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
-  localparam n = 5;
-  wire [9:0] i;
-  assign i = c[i4*10:i4*10+9];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:6] res;
-~GENERATE
-if (1) begin
-localparam n = 6;
-wire [11:0] i;
-assign i = d[0:11];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// clz64 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.clz#"
-    , "type"      : "clz :: Word# -> Word#"
-    , "templateD" :
-"// clz begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-~IF ~IW64 ~THEN
-wire [0:63] v;
-assign v = ~ARG[0][63:0];
-
-wire [0:63] e;
-genvar i;
-~GENERATE
-for (i=0;i<32;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:47] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:31] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:19] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:11] d;
-genvar i4;
-~GENERATE
-for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
-  localparam n = 5;
-  wire [9:0] i;
-  assign i = c[i4*10:i4*10+9];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:6] res;
-~GENERATE
-if (1) begin
-localparam n = 6;
-wire [11:0] i;
-assign i = d[0:11];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-~ELSE
-wire [0:31] v;
-assign v = ~ARG[0][31:0];
-
-wire [0:31] e;
-genvar i;
-~GENERATE
-for (i=0;i<16;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:23] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:15] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:9] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:5] res;
-~GENERATE
-if (1) begin
-localparam n = 5;
-wire [9:0] i;
-assign i = c[0:9];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-~FI
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// clz end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ctz8#"
-    , "type"      : "ctz8 :: Word# -> Word#"
-    , "templateD" :
-"// ctz8 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:7] v;
-genvar k;
-~GENERATE
-for (k=0;k<8;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:7] e;
-genvar i;
-~GENERATE
-for (i=0;i<4;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:5] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<2;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:3] res;
-~GENERATE
-if (1) begin
-localparam n = 3;
-wire [5:0] i;
-assign i = a[0:5];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// ctz8 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ctz16#"
-    , "type"      : "ctz16 :: Word# -> Word#"
-    , "templateD" :
-"// ctz16 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:15] v;
-genvar k;
-~GENERATE
-for (k=0;k<16;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:15] e;
-genvar i;
-~GENERATE
-for (i=0;i<8;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:11] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<4;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:7] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<2;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:4] res;
-~GENERATE
-if (1) begin
-localparam n = 4;
-wire [7:0] i;
-assign i = b[0:7];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// ctz16 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ctz32#"
-    , "type"      : "ctz32 :: Word# -> Word#"
-    , "templateD" :
-"// ctz32 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:31] v;
-genvar k;
-~GENERATE
-for (k=0;k<32;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:31] e;
-genvar i;
-~GENERATE
-for (i=0;i<16;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:23] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:15] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:9] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:5] res;
-~GENERATE
-if (1) begin
-localparam n = 5;
-wire [9:0] i;
-assign i = c[0:9];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// ctz32 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ctz64#"
-    , "type"      : "ctz64 :: Word# -> Word#"
-    , "templateD" :
-"// ctz64 begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-
-wire [0:63] v;
-genvar k;
-~GENERATE
-for (k=0;k<64;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:63] e;
-genvar i;
-~GENERATE
-for (i=0;i<32;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:47] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:31] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:19] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:11] d;
-genvar i4;
-~GENERATE
-for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
-  localparam n = 5;
-  wire [9:0] i;
-  assign i = c[i4*10:i4*10+9];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:6] res;
-~GENERATE
-if (1) begin
-localparam n = 6;
-wire [11:0] i;
-assign i = d[0:11];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// ctz64 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.ctz#"
-    , "type"      : "ctz :: Word# -> Word#"
-    , "templateD" :
-"// ctz begin
-~GENERATE
-if (1) begin
-function [1:0] enc;
-  input [1:0] a;
-  case (a)
-    2'b00:   enc = 2'b10;
-    2'b01:   enc = 2'b01;
-    2'b10:   enc = 2'b00;
-    default: enc = 2'b00;
-  endcase
-endfunction
-~IF ~IW64 ~THEN
-wire [0:63] v;
-genvar k;
-~GENERATE
-for (k=0;k<64;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:63] e;
-genvar i;
-~GENERATE
-for (i=0;i<32;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:47] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:31] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:19] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:11] d;
-genvar i4;
-~GENERATE
-for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
-  localparam n = 5;
-  wire [9:0] i;
-  assign i = c[i4*10:i4*10+9];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:6] res;
-~GENERATE
-if (1) begin
-localparam n = 6;
-wire [11:0] i;
-assign i = d[0:11];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-~ELSE
-wire [0:31] v;
-genvar k;
-~GENERATE
-for (k=0;k<32;k=k+1) begin : reverse
-  assign v[k] = ~ARG[0][k];
-end
-~ENDGENERATE
-
-wire [0:31] e;
-genvar i;
-~GENERATE
-for (i=0;i<16;i=i+1) begin : enc_stage
-  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
-end
-~ENDGENERATE
-
-reg [0:23] a;
-genvar i1;
-~GENERATE
-for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
-  localparam n = 2;
-  wire [3:0] i;
-  assign i = e[i1*4:i1*4+3];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:15] b;
-genvar i2;
-~GENERATE
-for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
-  localparam n = 3;
-  wire [5:0] i;
-  assign i = a[i2*6:i2*6+5];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:9] c;
-genvar i3;
-~GENERATE
-for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
-  localparam n = 4;
-  wire [7:0] i;
-  assign i = b[i3*8:i3*8+7];
-  always @(*) begin
-    case (i[n-1+n])
-      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-    endcase
-  end
-end
-~ENDGENERATE
-
-reg [0:5] res;
-~GENERATE
-if (1) begin
-localparam n = 5;
-wire [9:0] i;
-assign i = c[0:9];
-always @(*) begin
-  case (i[n-1+n])
-    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
-    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
-  endcase
-end
-end
-~ENDGENERATE
-~FI
-assign ~RESULT = $unsigned(res);
-end
-~ENDGENERATE
-// ctz end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.byteSwap16#"
-    , "type"      : "byteSwap16# :: Word# -> Word#"
-    , "templateD" :
-"// byteSwap16 begin
-wire ~TYP[0] ~SYM[0];
-assign ~SYM[0] = ~ARG[0];
-~IF ~IW64 ~THEN
-assign ~RESULT = {~SYM[0][63:16],~SYM[0][7:0],~SYM[0][15:8]};
-~ELSE
-assign ~RESULT = {~SYM[0][31:16],~SYM[0][7:0],~SYM[0][15:8]};
-~FI
-// byteSwap16 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.byteSwap32#"
-    , "type"      : "byteSwap32# :: Word# -> Word#"
-    , "templateD" :
-"// byteSwap32 begin
-wire ~TYPO ~SYM[0];
-assign ~SYM[0] = ~ARG[0];
-~IF ~IW64 ~THEN
-assign ~RESULT = {~SYM[0][63:32],~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};
-~ELSE
-assign ~RESULT = {~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};
-~FI
-// byteSwap32 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.byteSwap64#"
-    , "type"      : "byteSwap64# :: Word# -> Word#"
-    , "templateD" :
-"// byteSwap64 begin
-wire ~TYP[0] ~SYM[1];
-assign ~SYM[1] = ~ARG[0];
-assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
-                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};
-// byteSwap64 end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.byteSwap#"
-    , "type"      : "byteSwap# :: Word# -> Word#"
-    , "templateD" :
-"// byteSwap begin
-wire ~TYP[0] ~SYM[1];
-assign ~SYM[1] = ~ARG[0];
-~IF ~IW64 ~THEN
-assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
-                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};
-~ELSE
-assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]};
-~FI
-// byteSwap end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow8Int#"
-    , "type"      : "narrow8Int# :: Int# -> Int#"
-    , "templateD" :
-"// narrow8Int begin
-wire ~SIGD[~SYM[0]][0];
-assign ~SYM[0] = ~ARG[0];
-
-assign ~RESULT = $signed(~SYM[0][7:0]);
-// narrow8Int end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow16Int#"
-    , "type"      : "narrow16Int# :: Int# -> Int#"
-    , "templateD" :
-"// narrow16Int begin
-wire ~SIGD[~SYM[0]][0];
-assign ~SYM[0] = ~ARG[0];
-
-assign ~RESULT = $signed(~SYM[0][15:0]);
-// narrow16Int end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow32Int#"
-    , "type"      : "narrow32Int# :: Int# -> Int#"
-    , "templateD" :
-"// narrow32Int begin
-wire ~SIGD[~SYM[0]][0];
-assign ~SYM[0] = ~ARG[0];
-
-assign ~RESULT = $signed(~SYM[0][31:0]);
-// narrow32Int end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow8Word#"
-    , "type"      : "narrow8Int# :: Word# -> Word#"
-    , "templateD" :
-"// narrow8Word begin
-wire ~SIGD[~SYM[0]][0];
-assign ~SYM[0] = ~ARG[0];
-
-assign ~RESULT = $unsigned(~SYM[0][7:0]);
-// narrow8Word end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow16Word#"
-    , "type"      : "narrow16Word# :: Word# -> Word#"
-    , "templateD" :
-"// narrow16Word begin
-wire ~SIGD[~SYM[0]][0];
-assign ~SYM[0] = ~ARG[0];
-
-assign ~RESULT = $unsigned(~SYM[0][15:0]);
-// narrow16Word end"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.narrow32Word#"
-    , "type"      : "narrow32Int# :: Word# -> Word#"
-    , "templateD" :
-"// narrow32Word begin
-wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[rem_res][1]][0];
+assign ~SYM[0] = ~ARG[0] / ~ARG[1];
+assign ~SYM[1] = ~ARG[0] % ~ARG[1];
+
+assign ~RESULT = {~SYM[0],~SYM[1]};
+// quotRemInt end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.andI#"
+    , "type"      : "andI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] & ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.orI#"
+    , "type"      : "orI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] | ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.xorI#"
+    , "type"      : "xorI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] ^ ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.notI#"
+    , "type"      : "notI# :: Int# -> Int#"
+    , "templateE" : "~ ~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.negateInt#"
+    , "type"      : "negateInt# :: Int# -> Int#"
+    , "templateE" : "-(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.>#"
+     , "type"     : "(>#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.>=#"
+    , "type"      : "(>=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.==#"
+    , "type"      : "(==) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim./=#"
+    , "type"      : "(/=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.<#"
+    , "type"      : "(<#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.<=#"
+    , "type"      : "(<=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.chr#"
+    , "type"      : "ord :: Int# -> Char#"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.int2Word#"
+    , "type"      : "int2Word# :: Int# -> Word#"
+    , "templateE" : "$unsigned(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] <<< ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
+    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >>> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
+    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.plusWord#"
+    , "type"      : "plusWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] + ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.minusWord#"
+    , "type"      : "minusWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] - ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.timesWord#"
+    , "type"      : "timesWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] * ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotWord#"
+    , "type"      : "quotWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.remWord#"
+    , "type"      : "remWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotRemWord#"
+    , "type"      : "quotRemWord# :: Word# -> Word# -> (#Word#, Word##)"
+    , "templateD" :
+"// quotRemWord begin
+wire ~SIGD[~GENSYM[quot_res][0]][0];
+wire ~SIGD[~GENSYM[rem_res][1]][0];
+assign ~SYM[0] = ~ARG[0] / ~ARG[1];
+assign ~SYM[1] = ~ARG[0] % ~ARG[1];
+
+assign ~RESULT = {~SYM[0],~SYM[1]};
+// quotRemWord end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.and#"
+    , "type"      : "and# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] & ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.or#"
+    , "type"      : "or# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] | ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.xor#"
+    , "type"      : "xor# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] ^ ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.not#"
+    , "type"      : "not# :: Word# -> Word#"
+    , "templateE" : "~ ~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedShiftL#"
+    , "type"      : "uncheckedShiftL# :: Word# -> Int# -> Word#"
+    , "templateE" : "~ARG[0] << ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedShiftRL# :: Word# -> Int# -> Word#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.word2Int#"
+    , "type"      : "int2Word# :: Word# -> Int#"
+    , "templateE" : "$signed(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.gtWord#"
+     , "type"     : "gtWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.geWord#"
+    , "type"      : "geWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.eqWord#"
+    , "type"      : "eqWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.neWord#"
+    , "type"      : "neWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ltWord#"
+    , "type"      : "ltWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.leWord#"
+    , "type"      : "leWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt8#"
+    , "type"      : "popCnt8# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt8 begin
+localparam ~GENSYM[width][0] = 8;
+
+// ceiling of log2
+function integer ~GENSYM[log2][1];
+  input integer value;
+  begin
+    value = value-1;
+    for (~SYM[1]=0; value>0; ~SYM[1]=~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam ~GENSYM[levels][2] = ~SYM[1](~SYM[0]);
+
+wire [~SYM[2]:0] ~GENSYM[intermediate][3] [0:(2*~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar ~GENSYM[i][4];
+~GENERATE
+for (~SYM[4] = 0; ~SYM[4] < ~SYM[0]; ~SYM[4]=~SYM[4]+1) begin : ~GENSYM[mk_array][11]
+  assign ~SYM[3][~SYM[4]] = $unsigned(~ARG[0][~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer ~GENSYM[depth2Index][5];
+  input integer levels;
+  input integer depth;
+
+  ~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar ~GENSYM[d][6];
+genvar ~GENSYM[i][7];
+~GENERATE
+if (~SYM[2] != 0) begin : ~GENSYM[make_tree][8]
+  for (~SYM[6] = (~SYM[2] - 1); ~SYM[6] >= 0; ~SYM[6]=~SYM[6]-1) begin : ~GENSYM[tree_depth][9]
+    for (~SYM[7] = 0; ~SYM[7] < (2**~SYM[6]); ~SYM[7] = ~SYM[7]+1) begin : ~GENSYM[tree_depth_loop][10]
+      assign ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+1)+~SYM[7]] =
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])] +
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(~SYM[3][(2*~SYM[0])-2]);
+// popCnt8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt16#"
+    , "type"      : "popCnt16# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt16 begin
+localparam ~GENSYM[width][0] = 16;
+
+// ceiling of log2
+function integer ~GENSYM[log2][1];
+  input integer value;
+  begin
+    value = value-1;
+    for (~SYM[1]=0; value>0; ~SYM[1]=~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam ~GENSYM[levels][2] = ~SYM[1](~SYM[0]);
+
+wire [~SYM[2]:0] ~GENSYM[intermediate][3] [0:(2*~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar ~GENSYM[i][4];
+~GENERATE
+for (~SYM[4] = 0; ~SYM[4] < ~SYM[0]; ~SYM[4]=~SYM[4]+1) begin : ~GENSYM[mk_array][11]
+  assign ~SYM[3][~SYM[4]] = $unsigned(~ARG[0][~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer ~GENSYM[depth2Index][5];
+  input integer levels;
+  input integer depth;
+
+  ~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar ~GENSYM[d][6];
+genvar ~GENSYM[i][7];
+~GENERATE
+if (~SYM[2] != 0) begin : ~GENSYM[make_tree][8]
+  for (~SYM[6] = (~SYM[2] - 1); ~SYM[6] >= 0; ~SYM[6]=~SYM[6]-1) begin : ~GENSYM[tree_depth][9]
+    for (~SYM[7] = 0; ~SYM[7] < (2**~SYM[6]); ~SYM[7] = ~SYM[7]+1) begin : ~GENSYM[tree_depth_loop][10]
+      assign ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+1)+~SYM[7]] =
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])] +
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(~SYM[3][(2*~SYM[0])-2]);
+// popCnt16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt32#"
+    , "type"      : "popCnt32# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt32 begin
+localparam ~GENSYM[width][0] = 32;
+
+// ceiling of log2
+function integer ~GENSYM[log2][1];
+  input integer value;
+  begin
+    value = value-1;
+    for (~SYM[1]=0; value>0; ~SYM[1]=~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam ~GENSYM[levels][2] = ~SYM[1](~SYM[0]);
+
+wire [~SYM[2]:0] ~GENSYM[intermediate][3] [0:(2*~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar ~GENSYM[i][4];
+~GENERATE
+for (~SYM[4] = 0; ~SYM[4] < ~SYM[0]; ~SYM[4]=~SYM[4]+1) begin : ~GENSYM[mk_array][11]
+  assign ~SYM[3][~SYM[4]] = $unsigned(~ARG[0][~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer ~GENSYM[depth2Index][5];
+  input integer levels;
+  input integer depth;
+
+  ~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar ~GENSYM[d][6];
+genvar ~GENSYM[i][7];
+~GENERATE
+if (~SYM[2] != 0) begin : ~GENSYM[make_tree][8]
+  for (~SYM[6] = (~SYM[2] - 1); ~SYM[6] >= 0; ~SYM[6]=~SYM[6]-1) begin : ~GENSYM[tree_depth][9]
+    for (~SYM[7] = 0; ~SYM[7] < (2**~SYM[6]); ~SYM[7] = ~SYM[7]+1) begin : ~GENSYM[tree_depth_loop][10]
+      assign ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+1)+~SYM[7]] =
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])] +
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(~SYM[3][(2*~SYM[0])-2]);
+// popCnt32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt64#"
+    , "type"      : "popCnt64# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt64 begin
+localparam ~GENSYM[width][0] = 64;
+
+// ceiling of log2
+function integer ~GENSYM[log2][1];
+  input integer value;
+  begin
+    value = value-1;
+    for (~SYM[1]=0; value>0; ~SYM[1]=~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam ~GENSYM[levels][2] = ~SYM[1](~SYM[0]);
+
+wire [~SYM[2]:0] ~GENSYM[intermediate][3] [0:(2*~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar ~GENSYM[i][4];
+~GENERATE
+for (~SYM[4] = 0; ~SYM[4] < ~SYM[0]; ~SYM[4]=~SYM[4]+1) begin : ~GENSYM[mk_array][11]
+  assign ~SYM[3][~SYM[4]] = $unsigned(~ARG[0][~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer ~GENSYM[depth2Index][5];
+  input integer levels;
+  input integer depth;
+
+  ~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar ~GENSYM[d][6];
+genvar ~GENSYM[i][7];
+~GENERATE
+if (~SYM[2] != 0) begin : ~GENSYM[make_tree][8]
+  for (~SYM[6] = (~SYM[2] - 1); ~SYM[6] >= 0; ~SYM[6]=~SYM[6]-1) begin : ~GENSYM[tree_depth][9]
+    for (~SYM[7] = 0; ~SYM[7] < (2**~SYM[6]); ~SYM[7] = ~SYM[7]+1) begin : ~GENSYM[tree_depth_loop][10]
+      assign ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+1)+~SYM[7]] =
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])] +
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(~SYM[3][(2*~SYM[0])-2]);
+// popCnt64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt#"
+    , "type"      : "popCnt8# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt begin
+localparam ~GENSYM[width][0] = ~SIZE[~TYPO];
+
+// ceiling of log2
+function integer ~GENSYM[log2][1];
+  input integer value;
+  begin
+    value = value-1;
+    for (~SYM[1]=0; value>0; ~SYM[1]=~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam ~GENSYM[levels][2] = ~SYM[1](~SYM[0]);
+
+wire [~SYM[2]:0] ~GENSYM[intermediate][3] [0:(2*~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar ~GENSYM[i][4];
+~GENERATE
+for (~SYM[4] = 0; ~SYM[4] < ~SYM[0]; ~SYM[4]=~SYM[4]+1) begin : ~GENSYM[mk_array][11]
+  assign ~SYM[3][~SYM[4]] = $unsigned(~ARG[0][~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer ~GENSYM[depth2Index][5];
+  input integer levels;
+  input integer depth;
+
+  ~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar ~GENSYM[d][6];
+genvar ~GENSYM[i][7];
+~GENERATE
+if (~SYM[2] != 0) begin : ~GENSYM[make_tree][8]
+  for (~SYM[6] = (~SYM[2] - 1); ~SYM[6] >= 0; ~SYM[6]=~SYM[6]-1) begin : ~GENSYM[tree_depth][9]
+    for (~SYM[7] = 0; ~SYM[7] < (2**~SYM[6]); ~SYM[7] = ~SYM[7]+1) begin : ~GENSYM[tree_depth_loop][10]
+      assign ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+1)+~SYM[7]] =
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])] +
+             ~SYM[3][~SYM[5](~SYM[2]+1,~SYM[6]+2)+(2*~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(~SYM[3][(2*~SYM[0])-2]);
+// popCnt end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz8#"
+    , "type"      : "clz8 :: Word# -> Word#"
+    , "templateD" :
+"// clz8 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:7] ~GENSYM[v][1];
+assign ~SYM[1] = ~ARG[0][7:0];
+
+wire [0:7] ~GENSYM[e][2];
+genvar ~GENSYM[n][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<4;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:5] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<2;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage1][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:3] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 3;
+wire [5:0] i;
+assign i = ~SYM[4][0:5];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// clz8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz16#"
+    , "type"      : "clz16 :: Word# -> Word#"
+    , "templateD" :
+"// clz16 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:15] ~GENSYM[v][1];
+assign ~SYM[1] = ~ARG[0][15:0];
+
+wire [0:15] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<8;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<4;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:7] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<2;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:4] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 4;
+wire [7:0] i;
+assign i = ~SYM[9][0:7];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// clz16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz32#"
+    , "type"      : "clz32 :: Word# -> Word#"
+    , "templateD" :
+"// clz32 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:31] ~GENSYM[v][1];
+assign ~SYM[1] = ~ARG[0][31:0];
+
+wire [0:31] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<16;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<8;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<4;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<2;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = ~SYM[12][0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// clz32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz64#"
+    , "type"      : "clz64 :: Word# -> Word#"
+    , "templateD" :
+"// clz64 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:63] ~GENSYM[v][1];
+assign ~SYM[1] = ~ARG[0][63:0];
+
+wire [0:63] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<32;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<16;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<8;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<4;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[d][15];
+genvar ~GENSYM[i4][16];
+~GENERATE
+for (~SYM[16]=0;~SYM[16]<2;~SYM[16]=~SYM[16]+1) begin : ~GENSYM[mux_stage4][17]
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = ~SYM[12][~SYM[16]*10:~SYM[16]*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = ~SYM[15][0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// clz64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz#"
+    , "type"      : "clz :: Word# -> Word#"
+    , "templateD" :
+"// clz begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+~IF ~IW64 ~THEN
+wire [0:63] ~GENSYM[v][1];
+assign ~SYM[1] = ~ARG[0][63:0];
+
+wire [0:63] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<32;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<16;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<8;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<4;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[d][15];
+genvar ~GENSYM[i4][16];
+~GENERATE
+for (~SYM[16]=0;~SYM[16]<2;~SYM[16]=~SYM[16]+1) begin : ~GENSYM[mux_stage4][17]
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = ~SYM[12][~SYM[16]*10:~SYM[16]*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = ~SYM[15][0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~ELSE
+wire [0:31] ~SYM[1];
+assign ~SYM[1] = ~ARG[0][31:0];
+
+wire [0:31] ~SYM[2];
+genvar ~SYM[3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<16;~SYM[3]=~SYM[3]+1) begin : ~SYM[8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] ~SYM[4];
+genvar ~SYM[5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<8;~SYM[5]=~SYM[5]+1) begin : ~SYM[6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] ~SYM[9];
+genvar ~SYM[10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<4;~SYM[10]=~SYM[10]+1) begin : ~SYM[11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] ~SYM[12];
+genvar ~SYM[13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<2;~SYM[13]=~SYM[13]+1) begin : ~SYM[14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] ~SYM[7];
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = ~SYM[12][0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~FI
+assign ~RESULT = $unsigned(~SYM[7]);
+// clz end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz8#"
+    , "type"      : "ctz8 :: Word# -> Word#"
+    , "templateD" :
+"// ctz8 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:7] ~GENSYM[v][1];
+genvar ~GENSYM[k][18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<8;~SYM[18]=~SYM[18]+1) begin : ~GENSYM[reverse][19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:7] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<4;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:5] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<2;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:3] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 3;
+wire [5:0] i;
+assign i = ~SYM[4][0:5];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// ctz8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz16#"
+    , "type"      : "ctz16 :: Word# -> Word#"
+    , "templateD" :
+"// ctz16 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:15] ~GENSYM[v][1];
+genvar ~GENSYM[k][18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<16;~SYM[18]=~SYM[18]+1) begin : ~GENSYM[reverse][19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:15] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<8;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<4;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:7] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<2;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:4] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 4;
+wire [7:0] i;
+assign i = ~SYM[9][0:7];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// ctz16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz32#"
+    , "type"      : "ctz32 :: Word# -> Word#"
+    , "templateD" :
+"// ctz32 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:31] ~GENSYM[v][1];
+genvar ~GENSYM[k][18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<32;~SYM[18]=~SYM[18]+1) begin : ~GENSYM[reverse][19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:31] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<16;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<8;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<4;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<2;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = ~SYM[12][0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// ctz32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz64#"
+    , "type"      : "ctz64 :: Word# -> Word#"
+    , "templateD" :
+"// ctz64 begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+
+wire [0:63] ~GENSYM[v][1];
+genvar ~GENSYM[k][18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<64;~SYM[18]=~SYM[18]+1) begin : ~GENSYM[reverse][19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:63] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<32;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] a;
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<16;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<8;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<4;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[d][15];
+genvar ~GENSYM[i4][16];
+~GENERATE
+for (~SYM[16]=0;~SYM[16]<2;~SYM[16]=~SYM[16]+1) begin : ~GENSYM[mux_stage4][17]
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = ~SYM[12][~SYM[16]*10:~SYM[16]*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = ~SYM[15][0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(~SYM[7]);
+// ctz64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz#"
+    , "type"      : "ctz :: Word# -> Word#"
+    , "templateD" :
+"// ctz begin
+function [1:0] ~GENSYM[enc][0];
+  input [1:0] a;
+  case (a)
+    2'b00:   ~SYM[0] = 2'b10;
+    2'b01:   ~SYM[0] = 2'b01;
+    2'b10:   ~SYM[0] = 2'b00;
+    default: ~SYM[0] = 2'b00;
+  endcase
+endfunction
+~IF ~IW64 ~THEN
+wire [0:63] ~GENSYM[v][1];
+genvar ~GENSYM[k][18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<64;~SYM[18]=~SYM[18]+1) begin : ~GENSYM[reverse][19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:63] ~GENSYM[e][2];
+genvar ~GENSYM[i][3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<32;~SYM[3]=~SYM[3]+1) begin : ~GENSYM[enc_stage][8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] ~GENSYM[a][4];
+genvar ~GENSYM[i1][5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<16;~SYM[5]=~SYM[5]+1) begin : ~GENSYM[mux_stage][6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] ~GENSYM[b][9];
+genvar ~GENSYM[i2][10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<8;~SYM[10]=~SYM[10]+1) begin : ~GENSYM[mux_stage2][11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] ~GENSYM[c][12];
+genvar ~GENSYM[i3][13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<4;~SYM[13]=~SYM[13]+1) begin : ~GENSYM[mux_stage3][14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] ~GENSYM[d][15];
+genvar ~GENSYM[i4][16];
+~GENERATE
+for (~SYM[16]=0;~SYM[16]<2;~SYM[16]=~SYM[16]+1) begin : ~GENSYM[mux_stage4][17]
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = ~SYM[12][~SYM[16]*10:~SYM[16]*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[15][~SYM[16]*6:~SYM[16]*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] ~GENSYM[res][7];
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = ~SYM[15][0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~ELSE
+wire [0:31] ~SYM[1];
+genvar ~SYM[18];
+~GENERATE
+for (~SYM[18]=0;~SYM[18]<32;~SYM[18]=~SYM[18]+1) begin : ~SYM[19]
+  assign ~SYM[1][~SYM[18]] = ~ARG[0][~SYM[18]];
+end
+~ENDGENERATE
+
+wire [0:31] ~SYM[2];
+genvar ~SYM[3];
+~GENERATE
+for (~SYM[3]=0;~SYM[3]<16;~SYM[3]=~SYM[3]+1) begin : ~SYM[8]
+  assign ~SYM[2][~SYM[3]*2:~SYM[3]*2+1] = ~SYM[0](~SYM[1][~SYM[3]*2:~SYM[3]*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] ~SYM[4];
+genvar ~SYM[5];
+~GENERATE
+for (~SYM[5]=0;~SYM[5]<8;~SYM[5]=~SYM[5]+1) begin : ~SYM[6]
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = ~SYM[2][~SYM[5]*4:~SYM[5]*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[4][~SYM[5]*3:~SYM[5]*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] ~SYM[9];
+genvar ~SYM[10];
+~GENERATE
+for (~SYM[10]=0;~SYM[10]<4;~SYM[10]=~SYM[10]+1) begin : ~SYM[11]
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = ~SYM[4][~SYM[10]*6:~SYM[10]*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[9][~SYM[10]*4:~SYM[10]*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] ~SYM[12];
+genvar ~SYM[13];
+~GENERATE
+for (~SYM[13]=0;~SYM[13]<2;~SYM[13]=~SYM[13]+1) begin : ~SYM[14]
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = ~SYM[9][~SYM[13]*8:~SYM[13]*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : ~SYM[12][~SYM[13]*5:~SYM[13]*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] ~SYM[7];
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = ~SYM[12][0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : ~SYM[7] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : ~SYM[7] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~FI
+assign ~RESULT = $unsigned(~SYM[7]);
+// ctz end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap16#"
+    , "type"      : "byteSwap16# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap16 begin
+wire ~TYP[0] ~GENSYM[w][0];
+assign ~SYM[0] = ~ARG[0];~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[0][63:16],~SYM[0][7:0],~SYM[0][15:8]};~ELSE
+assign ~RESULT = {~SYM[0][31:16],~SYM[0][7:0],~SYM[0][15:8]};~FI
+// byteSwap16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap32#"
+    , "type"      : "byteSwap32# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap32 begin
+wire ~TYPO ~GENSYM[w][0];
+assign ~SYM[0] = ~ARG[0];~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[0][63:32],~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};~ELSE
+assign ~RESULT = {~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};~FI
+// byteSwap32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap64#"
+    , "type"      : "byteSwap64# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap64 begin
+wire ~TYP[0] ~GENSYM[w][1];
+assign ~SYM[1] = ~ARG[0];
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
+                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};
+// byteSwap64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap#"
+    , "type"      : "byteSwap# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap begin
+wire ~TYP[0] ~GENSYM[w][1];
+assign ~SYM[1] = ~ARG[0];~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
+                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};~ELSE
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]};~FI
+// byteSwap end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow8Int#"
+    , "type"      : "narrow8Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow8Int begin
+wire ~SIGD[~GENSYM[s][0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][7:0]);
+// narrow8Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow16Int#"
+    , "type"      : "narrow16Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow16Int begin
+wire ~SIGD[~GENSYM[s][0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][15:0]);
+// narrow16Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow32Int#"
+    , "type"      : "narrow32Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow32Int begin
+wire ~SIGD[~GENSYM[s][0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][31:0]);
+// narrow32Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow8Word#"
+    , "type"      : "narrow8Int# :: Word# -> Word#"
+    , "templateD" :
+"// narrow8Word begin
+wire ~SIGD[~GENSYM[w][0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $unsigned(~SYM[0][7:0]);
+// narrow8Word end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow16Word#"
+    , "type"      : "narrow16Word# :: Word# -> Word#"
+    , "templateD" :
+"// narrow16Word begin
+wire ~SIGD[~GENSYM[w][0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $unsigned(~SYM[0][15:0]);
+// narrow16Word end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow32Word#"
+    , "type"      : "narrow32Int# :: Word# -> Word#"
+    , "templateD" :
+"// narrow32Word begin
+wire ~SIGD[~GENSYM[w][0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 assign ~RESULT = $unsigned(~SYM[0][31:0]);
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -7,6 +7,7 @@
 -}
 
 {-# LANGUAGE CPP               #-}
+{-# LANGUAGE LambdaCase        #-}
 {-# LANGUAGE OverloadedStrings #-}
 {-# LANGUAGE RecursiveDo       #-}
 {-# LANGUAGE TemplateHaskell   #-}
@@ -16,18 +17,21 @@
 module CLaSH.Backend.Verilog (VerilogState) where
 
 import qualified Control.Applicative                  as A
-import           Control.Lens                         ((+=),(-=), makeLenses, use)
+import           Control.Lens                         ((+=),(-=),(.=),(%=), makeLenses, use)
 import           Control.Monad.State                  (State)
 import qualified Data.HashSet                         as HashSet
-import           Data.Maybe                           (catMaybes)
+import           Data.Maybe                           (catMaybes,mapMaybe)
 import           Data.Text.Lazy                       (pack, unpack)
+import qualified Data.Text.Lazy                       as Text
 import           Prelude                              hiding ((<$>))
 import           Text.PrettyPrint.Leijen.Text.Monadic
 
 import           CLaSH.Backend
+import           CLaSH.Netlist.BlackBox.Types         (HdlSyn)
 import           CLaSH.Netlist.BlackBox.Util          (extractLiterals, renderBlackBox)
+import           CLaSH.Netlist.Id                     (mkBasicId')
 import           CLaSH.Netlist.Types                  hiding (_intWidth, intWidth)
-import           CLaSH.Netlist.Util
+import           CLaSH.Netlist.Util                   hiding (mkBasicId)
 import           CLaSH.Util                           (curLoc, (<:>))
 
 #ifdef CABAL
@@ -40,13 +44,15 @@
 data VerilogState =
   VerilogState
     { _genDepth  :: Int -- ^ Depth of current generative block
+    , _idSeen    :: [Identifier]
     , _intWidth  :: Int -- ^ Int/Word/Integer bit-width
+    , _hdlsyn    :: HdlSyn
     }
 
 makeLenses ''VerilogState
 
 instance Backend VerilogState where
-  initBackend     = VerilogState 0
+  initBackend     = VerilogState 0 []
 #ifdef CABAL
   primDir         = const (Paths_clash_verilog.getDataFileName "primitives")
 #else
@@ -77,9 +83,36 @@
   iwWidth         = use intWidth
   toBV _          = text
   fromBV _        = text
+  hdlSyn          = use hdlsyn
+  mkBasicId       = return (filterReserved . mkBasicId' True)
+  setModName _    = id
 
 type VerilogM a = State VerilogState a
 
+-- List of reserved Verilog-2005 keywords
+reservedWords :: [Identifier]
+reservedWords = ["always","and","assign","automatic","begin","buf","bufif0"
+  ,"bufif1","case","casex","casez","cell","cmos","config","deassign","default"
+  ,"defparam","design","disable","edge","else","end","endcase","endconfig"
+  ,"endfunction","endgenerate","endmodule","endprimitive","endspecify"
+  ,"endtable","endtask","event","for","force","forever","fork","function"
+  ,"generate","genvar","highz0","highz1","if","ifnone","incdir","include"
+  ,"initial","inout","input","instance","integer","join","large","liblist"
+  ,"library","localparam","macromodule","medium","module","nand","negedge"
+  ,"nmos","nor","noshowcancelled","not","notif0","notif1","or","output"
+  ,"parameter","pmos","posedge","primitive","pull0","pull1","pulldown","pullup"
+  ,"pulsestyle_onevent","pulsestyle_ondetect","rcmos","real","realtime","reg"
+  ,"release","repeat","rnmos","rpmos","rtran","rtranif0","rtranif1","scalared"
+  ,"showcancelled","signed","small","specify","specparam","strong0","strong1"
+  ,"supply0","supply1","table","task","time","tran","tranif0","tranif1","tri"
+  ,"tri0","tri1","triand","trior","trireg","unsigned","use","uwire","vectored"
+  ,"wait","wand","weak0","weak1","while","wire","wor","xnor","xor"]
+
+filterReserved :: Identifier -> Identifier
+filterReserved s = if s `elem` reservedWords
+  then s `Text.append` "_r"
+  else s
+
 -- | Generate VHDL for a Netlist component
 genVerilog :: Component -> VerilogM (String,Doc)
 genVerilog c = (unpack cName,) A.<$> verilog
@@ -89,10 +122,14 @@
               module_ c
 
 module_ :: Component -> VerilogM Doc
-module_ c =
-    "module" <+> text (componentName c) <> tupled ports <> semi <$>
-    indent 2 (inputPorts <$> outputPorts <$$> decls (declarations c)) <$$> insts (declarations c) <$>
-    "endmodule"
+module_ c = do
+    { addSeen c
+    ; m <- "module" <+> text (componentName c) <> tupled ports <> semi <$>
+           indent 2 (inputPorts <$> outputPorts <$$> decls (declarations c)) <$$> insts (declarations c) <$>
+           "endmodule"
+    ; idSeen .= []
+    ; return m
+    }
   where
     ports = sequence
           $ [ encodingNote hwty <$> text i | (i,hwty) <- inputs c ] ++
@@ -107,6 +144,33 @@
                    [] -> empty
                    p  -> vcat (punctuate semi (sequence [ "output" <+> sigDecl (text i) ty | (i,ty) <- p ])) <> semi
 
+addSeen :: Component -> VerilogM ()
+addSeen c = do
+  let iport = map fst $ inputs c
+      hport = map fst $ hiddenPorts c
+      oport = map fst $ outputs c
+      nets  = mapMaybe (\case {NetDecl i _ -> Just i; _ -> Nothing}) $ declarations c
+  idSeen .= concat [iport,hport,oport,nets]
+
+mkUniqueId :: Identifier -> VerilogM Identifier
+mkUniqueId i = do
+  mkId <- mkBasicId
+  seen <- use idSeen
+  let i' = mkId i
+  case i `elem` seen of
+    True  -> go mkId seen i' 0
+    False -> do idSeen %= (i':)
+                return i'
+  where
+    go :: (Identifier -> Identifier) -> [Identifier] -> Identifier
+       -> Int -> VerilogM Identifier
+    go mkId seen i' n = do
+      let i'' = mkId (Text.append i' (Text.pack ('_':show n)))
+      case i'' `elem` seen of
+        True  -> go mkId seen i' (n+1)
+        False -> do idSeen %= (i'':)
+                    return i''
+
 verilogType :: HWType -> VerilogM Doc
 verilogType t = case t of
   Signed n -> "signed" <+> brackets (int (n-1) <> colon <> int 0)
@@ -147,41 +211,42 @@
 inst_ (Assignment id_ e) = fmap Just $
   "assign" <+> text id_ <+> equals <+> expr_ False e <> semi
 
-inst_ (CondAssignment id_ ty scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $
-    "reg" <+> verilogType ty <+> regId <> semi <$>
-    "always @(*) begin" <$>
-    indent 2 ("if" <> parens (expr_ True scrut) <$>
-                (indent 2 $ regId <+> equals <+> expr_ False t <> semi) <$>
-             "else" <$>
-                (indent 2 $ regId <+> equals <+> expr_ False f <> semi)) <$>
-    "end" <$>
-    "assign" <+> text id_ <+> equals <+> regId <> semi
+inst_ (CondAssignment id_ ty scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $ do
+    { regId <- mkUniqueId (Text.append id_ "_reg")
+    ; "reg" <+> verilogType ty <+> text regId <> semi <$>
+      "always @(*) begin" <$>
+      indent 2 ("if" <> parens (expr_ True scrut) <$>
+                  (indent 2 $ text regId <+> equals <+> expr_ False t <> semi) <$>
+               "else" <$>
+                  (indent 2 $ text regId <+> equals <+> expr_ False f <> semi)) <$>
+      "end" <$>
+      "assign" <+> text id_ <+> equals <+> text regId <> semi
+    }
   where
     (t,f) = if b then (l,r) else (r,l)
-    regId = text id_ <> "_reg"
 
 
-inst_ (CondAssignment id_ ty scrut scrutTy es) = fmap Just $
-    "reg" <+> verilogType ty <+> regId <> semi <$>
-    "always @(*) begin" <$>
-    indent 2 ("case" <> parens (expr_ True scrut) <$>
-                (indent 2 $ vcat $ punctuate semi (conds es)) <> semi <$>
-              "endcase") <$>
-    "end" <$>
-    "assign" <+> text id_ <+> equals <+> regId <> semi
+inst_ (CondAssignment id_ ty scrut scrutTy es) = fmap Just $ do
+    { regId <- mkUniqueId (Text.append id_ "_reg")
+    ; "reg" <+> verilogType ty <+> text regId <> semi <$>
+      "always @(*) begin" <$>
+      indent 2 ("case" <> parens (expr_ True scrut) <$>
+                  (indent 2 $ vcat $ punctuate semi (conds regId es)) <> semi <$>
+                "endcase") <$>
+      "end" <$>
+      "assign" <+> text id_ <+> equals <+> text regId <> semi
+    }
   where
-    regId = text id_ <> "_reg"
-
-    conds :: [(Maybe Literal,Expr)] -> VerilogM [Doc]
-    conds []                = return []
-    conds [(_,e)]           = ("default" <+> colon <+> regId <+> equals <+> expr_ False e) <:> return []
-    conds ((Nothing,e):_)   = ("default" <+> colon <+> regId <+> equals <+> expr_ False e) <:> return []
-    conds ((Just c ,e):es') = (exprLit (Just (scrutTy,conSize scrutTy)) c <+> colon <+> regId <+> equals <+> expr_ False e) <:> conds es'
+    conds :: Identifier -> [(Maybe Literal,Expr)] -> VerilogM [Doc]
+    conds _ []                = return []
+    conds i [(_,e)]           = ("default" <+> colon <+> text i <+> equals <+> expr_ False e) <:> return []
+    conds i ((Nothing,e):_)   = ("default" <+> colon <+> text i <+> equals <+> expr_ False e) <:> return []
+    conds i ((Just c ,e):es') = (exprLit (Just (scrutTy,conSize scrutTy)) c <+> colon <+> text i <+> equals <+> expr_ False e) <:> conds i es'
 
 inst_ (InstDecl nm lbl pms) = fmap Just $
     text nm <+> text lbl <$$> pms' <> semi
   where
-    pms' = tupled $ sequence [dot <> text i <+> parens (expr_ False e) | (i,e) <- pms]
+    pms' = tupled $ sequence [dot <> text i <+> parens (expr_ False e) | (i,_,_,e) <- pms]
 
 inst_ (BlackBoxD _ bs bbCtx) = do
   t <- renderBlackBox bs bbCtx
@@ -245,6 +310,8 @@
     end   = typeSize ty - conSize ty
 
 expr_ _ (Identifier id_ (Just _))                      = text id_
+
+expr_ b (DataCon _ (DC (Void, -1)) [e]) = expr_ b e
 
 expr_ _ (DataCon (Vector 0 _) _ _) =
   error $ $(curLoc) ++ "Verilog: Trying to create a Nil vector."