diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,6 +1,11 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
-## 0.6.4 *January 13th 2015*
+## 0.6.5 *January 29th 2016*
+* New features:
+  * Support clash-lib-0.6.9
+  * Support for `Debug.Trace.trace`, thanks to @ggreif
+
+## 0.6.4 *January 13th 2016*
 * New features:
   * Support for Haskell's: `Char`, `Int8`, `Int16`, `Int32`, `Int64`, `Word`, `Word8`, `Word16`, `Word32`, `Word64`.
   * Int/Word/Integer bitwidth for generated Verilog is configurable using the `-clash-intwidth=N` flag, where `N` can be either 32 or 64.
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.4
+Version:              0.6.5
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -34,7 +34,7 @@
 License-file:         LICENSE
 Author:               Christiaan Baaij
 Maintainer:           Christiaan Baaij <christiaan.baaij@gmail.com>
-Copyright:            Copyright © 2015 University of Twente
+Copyright:            Copyright © 2015-2016 University of Twente
 Category:             Hardware
 Build-type:           Simple
 
@@ -61,7 +61,9 @@
                       primitives/CLaSH.Sized.Internal.Signed.json
                       primitives/CLaSH.Sized.Internal.Unsigned.json
                       primitives/CLaSH.Sized.Vector.json
+                      primitives/CLaSH.Transformations.json
                       primitives/Control.Exception.Base.json
+                      primitives/Debug.Trace.json
                       primitives/GHC.Base.json
                       primitives/GHC.Classes.json
                       primitives/GHC.CString.json
diff --git a/primitives/CLaSH.Transformations.json b/primitives/CLaSH.Transformations.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Transformations.json
@@ -0,0 +1,7 @@
+[ { "BlackBox" :
+    { "name"      : "CLaSH.Transformations.removedArg"
+    , "type"      : "removedArg :: a"
+    , "templateE" : "~ERRORO"
+    }
+  }
+]
diff --git a/primitives/Debug.Trace.json b/primitives/Debug.Trace.json
new file mode 100644
--- /dev/null
+++ b/primitives/Debug.Trace.json
@@ -0,0 +1,7 @@
+[ { "BlackBox" :
+    { "name"      : "Debug.Trace.trace"
+    , "type"      : "trace :: String -> a -> a"
+    , "templateE" : "~ARG[1]"
+    }
+  }
+]
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -1,3 +1,11 @@
+{-|
+  Copyright   :  (C) 2015-2016, University of Twente
+  License     :  BSD2 (see the file LICENSE)
+  Maintainer  :  Christiaan Baaij <christiaan.baaij@gmail.com>
+
+  Generate Verilog for assorted Netlist datatypes
+-}
+
 {-# LANGUAGE CPP               #-}
 {-# LANGUAGE OverloadedStrings #-}
 {-# LANGUAGE RecursiveDo       #-}
@@ -5,7 +13,6 @@
 {-# LANGUAGE TupleSections     #-}
 {-# LANGUAGE ViewPatterns      #-}
 
--- | Generate SystemVerilog for assorted Netlist datatypes
 module CLaSH.Backend.Verilog (VerilogState) where
 
 import qualified Control.Applicative                  as A
@@ -68,6 +75,8 @@
   inst            = inst_
   expr            = expr_
   iwWidth         = use intWidth
+  toBV _          = text
+  fromBV _        = text
 
 type VerilogM a = State VerilogState a