diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,10 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.4 *January 13th 2015*
+* New features:
+  * Support for Haskell's: `Char`, `Int8`, `Int16`, `Int32`, `Int64`, `Word`, `Word8`, `Word16`, `Word32`, `Word64`.
+  * Int/Word/Integer bitwidth for generated Verilog is configurable using the `-clash-intwidth=N` flag, where `N` can be either 32 or 64.
+
 ## 0.6.3 *November 17th 2015*
 * Fixes bugs:
   * Name collision in verilog code [#93](https://github.com/clash-lang/clash-compiler/issues/93)
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.3
+Version:              0.6.4
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -66,11 +66,13 @@
                       primitives/GHC.Classes.json
                       primitives/GHC.CString.json
                       primitives/GHC.Err.json
+                      primitives/GHC.Int.json
                       primitives/GHC.Integer.Type.json
                       primitives/GHC.Prim.json
                       primitives/GHC.Real.json
                       primitives/GHC.Typelits.json
                       primitives/GHC.Types.json
+                      primitives/GHC.Word.json
                       primitives/Unsafe.Coerce.json
 
 Cabal-version:        >=1.10
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -1,13 +1,13 @@
 [ { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.size#"
     , "type"      : "size# :: KnownNat n => BitVector n -> Int"
-    , "templateE" : "~LIT[0]"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.maxIndex#"
     , "type"      : "maxIndex# :: KnownNat n => BitVector n -> Int"
-    , "templateE" : "~LIT[0] - 1"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0] - ~SIZE[~TYPO]'sd1"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Index.json b/primitives/CLaSH.Sized.Internal.Index.json
--- a/primitives/CLaSH.Sized.Internal.Index.json
+++ b/primitives/CLaSH.Sized.Internal.Index.json
@@ -49,7 +49,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.maxBound#"
     , "type"      : "maxBound# :: KnownNat n => Index n"
-    , "templateE" : "~LIT[0]-1"
+    , "templateE" : "~ARG[0]-~SIZE[~TYPO]'d1"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -1,7 +1,7 @@
 [ { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.size#"
     , "type"      : "size# :: KnownNat n => Signed n -> Int"
-    , "templateE" : "~LIT[0]"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0]"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -1,7 +1,7 @@
 [ { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.size#"
     , "type"      : "size# :: KnownNat n => Unsigned n -> Int"
-    , "templateE" : "~LIT[0]"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0]"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -338,14 +338,14 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.maxIndex"
-    , "type"      : "maxIndex :: KnownNat n => Vec n a -> Integer"
-    , "templateE" : "~LIT[0] - 1"
+    , "type"      : "maxIndex :: KnownNat n => Vec n a -> Int"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0] - ~SIZE[~TYPO]'d1"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.length"
-    , "type"      : "length :: KnownNat n => Vec n a -> Integer"
-    , "templateE" : "~LIT[0]"
+    , "type"      : "length :: KnownNat n => Vec n a -> Int"
+    , "templateE" : "~SIZE[~TYPO]'sd~LIT[0]"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/GHC.Base.json b/primitives/GHC.Base.json
--- a/primitives/GHC.Base.json
+++ b/primitives/GHC.Base.json
@@ -30,7 +30,7 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
 // divInt end"
     }
   }
@@ -49,9 +49,9 @@
 // modulo
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+                 ((~ARG[1] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~ARG[1]);
 // modInt end"
     }
   }
diff --git a/primitives/GHC.Classes.json b/primitives/GHC.Classes.json
--- a/primitives/GHC.Classes.json
+++ b/primitives/GHC.Classes.json
@@ -67,7 +67,7 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
 // divInt end"
     }
   }
@@ -86,9 +86,9 @@
 // modulo
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+                 ((~ARG[1] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~ARG[1]);
 // modInt end"
     }
   }
diff --git a/primitives/GHC.Int.json b/primitives/GHC.Int.json
new file mode 100644
--- /dev/null
+++ b/primitives/GHC.Int.json
@@ -0,0 +1,25 @@
+[ { "BlackBox" :
+    { "name"      : "GHC.Int.I8#"
+    , "type"      : "I8# :: Int# -> Int8"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Int.I16#"
+    , "type"      : "I16# :: Int# -> Int16"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Int.I32#"
+    , "type"      : "I32# :: Int# -> Int32"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Int.I64#"
+    , "type"      : "I64# :: Int# -> Int64"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
+    }
+  }
+]
diff --git a/primitives/GHC.Integer.Type.json b/primitives/GHC.Integer.Type.json
--- a/primitives/GHC.Integer.Type.json
+++ b/primitives/GHC.Integer.Type.json
@@ -1,13 +1,13 @@
 [ { "BlackBox" :
     { "name"      : "GHC.Integer.Type.smallInteger"
     , "type"      : "smallInteger :: Int# -> Integer"
-    , "templateE" : "~ARG[0]"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.integerToInt"
     , "type"      : "integerToInt :: Integer -> Int#"
-    , "templateE" : "~ARG[0]"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
     }
   }
 , { "BlackBox" :
@@ -37,7 +37,7 @@
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.absInteger"
     , "type"      : "absInteger :: Integer -> Integer"
-    , "templateE" : "~ARG[0] < 32'sd0 ? -~ARG[0] : ~ARG[0]"
+    , "templateE" : "(~ARG[0] < ~SIZE[~TYPO]'sd0) ? -~ARG[0] : ~ARG[0]"
     }
   }
 , { "BlackBox" :
@@ -55,7 +55,7 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
 // divInteger end"
     }
   }
@@ -74,9 +74,9 @@
 // modulo
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+                 ((~ARG[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0) : ~SYM[0] + ~ARG[1]);
 // modInteger end"
     }
   }
@@ -130,38 +130,38 @@
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.eqInteger#"
-    , "type"      : "eqInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] == ~ARG[1]) ? 32'sd1 : 32'sd0"
+    , "type"      : "eqInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.neqInteger#"
-    , "type"      : "neqInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] != ~ARG[1]) ? 32'sd1 : 32'sd0"
+    , "type"      : "neqInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.leInteger#"
-    , "type"      : "leInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? 32'sd1 : 32'sd0"
+    , "type"      : "leInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.gtInteger#"
-    , "type"      : "gtInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] > ~ARG[1] ? 32'sd1 : 32'sd0"
+    , "type"      : "gtInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.ltInteger#"
-    , "type"      : "ltInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] < ~ARG[1]) ? 32'sd1 : 32'sd0"
+    , "type"      : "ltInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.geInteger#"
-    , "type"      : "geInteger :: Integer -> Integer -> Bool"
-    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? 32'sd1 : 32'sd0"
+    , "type"      : "geInteger :: Integer -> Integer -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/GHC.Prim.json b/primitives/GHC.Prim.json
--- a/primitives/GHC.Prim.json
+++ b/primitives/GHC.Prim.json
@@ -1,107 +1,1862 @@
 [ { "BlackBox" :
-    { "name"      : "GHC.Prim.+#"
-    , "type"      : "(+#) :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] + ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.-#"
-    , "type"      : "(-#) :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] - ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.*#"
-    , "type"      : "(*#) :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] * ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.quotInt#"
-    , "type"      : "quotInt# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] / ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.remInt#"
-    , "type"      : "remInt# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] % ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.negateInt#"
-    , "type"      : "negateInt# :: Int# -> Int#"
-    , "templateE" : "-~ARG[0]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.>#"
-     , "type"      : "(>#) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] > ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.>=#"
-    , "type"      : "(>=#) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.==#"
-    , "type"      : "(==) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] == ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim./=#"
-    , "type"      : "(/=#) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] != ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.<#"
-    , "type"      : "(<#) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] < ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.<=#"
-    , "type"      : "(<=#) :: Int# -> Int# -> Bool"
-    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? 32'sd1 : 32'sd0"
-    }
-  }
-, { "Primitive" :
-    { "name"     : "GHC.Prim.dataToTag#"
-    , "primType" : "Function"
-    }
-  }
-, { "Primitive" :
-    { "name"     : "GHC.Prim.tagToEnum#"
-    , "primType" : "Function"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.unsafeCoerce#"
-    , "type"      : "unsafeCoerce# :: a -> b"
-    , "templateE" : "~ARG[0]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
-    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] >>> ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
-    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] >> ~ARG[1]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "GHC.Prim.uncheckedIShiftL#"
-    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
-    , "templateE" : "~ARG[0] <<< ~ARG[1]"
+    { "name"      : "GHC.Prim.gtChar#"
+     , "type"     : "gtChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.geChar#"
+    , "type"      : "geChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.eqChar#"
+    , "type"      : "eqChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.neChar#"
+    , "type"      : "neChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ltChar#"
+    , "type"      : "ltChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.leChar#"
+    , "type"      : "leChar# :: Char# -> Char# -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ord#"
+    , "type"      : "ord :: Char# -> Int#"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.+#"
+    , "type"      : "(+#) :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] + ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.-#"
+    , "type"      : "(-#) :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] - ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.*#"
+    , "type"      : "(*#) :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] * ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotInt#"
+    , "type"      : "quotInt# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.remInt#"
+    , "type"      : "remInt# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotRemInt#"
+    , "type"      : "quotRemInt# :: Int# -> Int# -> (#Int#, Int##)"
+    , "templateD" :
+"// quotRemInt begin
+wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~SYM[1]][0];
+assign ~SYM[0] = ~ARG[0] / ~ARG[1];
+assign ~SYM[1] = ~ARG[0] % ~ARG[1];
+
+assign ~RESULT = {~SYM[0],~SYM[1]};
+// quotRemInt end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.andI#"
+    , "type"      : "andI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] & ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.orI#"
+    , "type"      : "orI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] | ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.xorI#"
+    , "type"      : "xorI# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] ^ ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.notI#"
+    , "type"      : "notI# :: Int# -> Int#"
+    , "templateE" : "~ ~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.negateInt#"
+    , "type"      : "negateInt# :: Int# -> Int#"
+    , "templateE" : "-(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.>#"
+     , "type"     : "(>#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.>=#"
+    , "type"      : "(>=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.==#"
+    , "type"      : "(==) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim./=#"
+    , "type"      : "(/=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.<#"
+    , "type"      : "(<#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.<=#"
+    , "type"      : "(<=#) :: Int# -> Int# -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.chr#"
+    , "type"      : "ord :: Int# -> Char#"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.int2Word#"
+    , "type"      : "int2Word# :: Int# -> Word#"
+    , "templateE" : "$unsigned(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] <<< ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
+    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >>> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
+    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.plusWord#"
+    , "type"      : "plusWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] + ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.minusWord#"
+    , "type"      : "minusWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] - ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.timesWord#"
+    , "type"      : "timesWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] * ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotWord#"
+    , "type"      : "quotWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.remWord#"
+    , "type"      : "remWord# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.quotRemWord#"
+    , "type"      : "quotRemWord# :: Word# -> Word# -> (#Word#, Word##)"
+    , "templateD" :
+"// quotRemWord begin
+wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~SYM[1]][0];
+assign ~SYM[0] = ~ARG[0] / ~ARG[1];
+assign ~SYM[1] = ~ARG[0] % ~ARG[1];
+
+assign ~RESULT = {~SYM[0],~SYM[1]};
+// quotRemWord end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.and#"
+    , "type"      : "and# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] & ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.or#"
+    , "type"      : "or# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] | ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.xor#"
+    , "type"      : "xor# :: Word# -> Word# -> Word#"
+    , "templateE" : "~ARG[0] ^ ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.not#"
+    , "type"      : "not# :: Word# -> Word#"
+    , "templateE" : "~ ~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedShiftL#"
+    , "type"      : "uncheckedShiftL# :: Word# -> Int# -> Word#"
+    , "templateE" : "~ARG[0] << ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedShiftRL# :: Word# -> Int# -> Word#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.word2Int#"
+    , "type"      : "int2Word# :: Word# -> Int#"
+    , "templateE" : "$signed(~ARG[0])"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.gtWord#"
+     , "type"     : "gtWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.geWord#"
+    , "type"      : "geWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.eqWord#"
+    , "type"      : "eqWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.neWord#"
+    , "type"      : "neWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ltWord#"
+    , "type"      : "ltWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.leWord#"
+    , "type"      : "leWord# :: Word# -> Word# -> Int#"
+    , "templateE" : "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt8#"
+    , "type"      : "popCnt8# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt8 begin
+localparam width_~SYM[0] = 8;
+
+// ceiling of log2
+function integer log2_~SYM[1];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
+
+wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar i_~SYM[4];
+~GENERATE
+for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
+  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[5];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[6];
+genvar i_~SYM[7];
+~GENERATE
+if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
+  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
+    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
+      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
+// popCnt8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt16#"
+    , "type"      : "popCnt16# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt16 begin
+localparam width_~SYM[0] = 16;
+
+// ceiling of log2
+function integer log2_~SYM[1];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
+
+wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar i_~SYM[4];
+~GENERATE
+for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
+  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[5];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[6];
+genvar i_~SYM[7];
+~GENERATE
+if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
+  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
+    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
+      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
+// popCnt16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt32#"
+    , "type"      : "popCnt32# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt32 begin
+localparam width_~SYM[0] = 32;
+
+// ceiling of log2
+function integer log2_~SYM[1];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
+
+wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar i_~SYM[4];
+~GENERATE
+for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
+  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[5];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[6];
+genvar i_~SYM[7];
+~GENERATE
+if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
+  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
+    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
+      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
+// popCnt32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt64#"
+    , "type"      : "popCnt64# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt64 begin
+localparam width_~SYM[0] = 64;
+
+// ceiling of log2
+function integer log2_~SYM[1];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
+
+wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar i_~SYM[4];
+~GENERATE
+for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
+  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[5];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[6];
+genvar i_~SYM[7];
+~GENERATE
+if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
+  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
+    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
+      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
+// popCnt64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.popCnt#"
+    , "type"      : "popCnt8# :: Word# -> Word#"
+    , "templateD" :
+"// popCnt begin
+localparam width_~SYM[0] = ~SIZE[~TYPO];
+
+// ceiling of log2
+function integer log2_~SYM[1];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[1]=0; value>0; log2_~SYM[1]=log2_~SYM[1]+1)
+      value = value>>1;
+  end
+endfunction
+
+// depth of the tree
+localparam levels_~SYM[2] = log2_~SYM[1](width_~SYM[0]);
+
+wire [levels_~SYM[2]:0] intermediate_~SYM[3] [0:(2*width_~SYM[0])-2];
+
+// put input into the first half of the intermediate array
+genvar i_~SYM[4];
+~GENERATE
+for (i_~SYM[4] = 0; i_~SYM[4] < width_~SYM[0]; i_~SYM[4]=i_~SYM[4]+1) begin : array_~SYM[5]
+  assign intermediate_~SYM[3][i_~SYM[4]] = $unsigned(~ARG[0][i_~SYM[4]]);
+end
+~ENDGENERATE
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[5];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[5] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[6];
+genvar i_~SYM[7];
+~GENERATE
+if (levels_~SYM[2] != 0) begin : make_tree_~SYM[8]
+  for (d_~SYM[6] = (levels_~SYM[2] - 1); d_~SYM[6] >= 0; d_~SYM[6]=d_~SYM[6]-1) begin : tree_depth
+    for (i_~SYM[7] = 0; i_~SYM[7] < (2**d_~SYM[6]); i_~SYM[7] = i_~SYM[7]+1) begin : tree_depth_loop
+      assign intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+1)+i_~SYM[7]] =
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])] +
+             intermediate_~SYM[3][depth2Index_~SYM[5](levels_~SYM[2]+1,d_~SYM[6]+2)+(2*i_~SYM[7])+1];
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = $unsigned(intermediate_~SYM[3][(2*width_~SYM[0])-2]);
+// popCnt end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz8#"
+    , "type"      : "clz8 :: Word# -> Word#"
+    , "templateD" :
+"// clz8 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:7] v;
+assign v = ~ARG[0][7:0];
+
+wire [0:7] e;
+genvar i;
+~GENERATE
+for (i=0;i<4;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:5] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<2;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:3] res;
+~GENERATE
+if (1) begin
+localparam n = 3;
+wire [5:0] i;
+assign i = a[0:5];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// clz8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz16#"
+    , "type"      : "clz16 :: Word# -> Word#"
+    , "templateD" :
+"// clz16 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:15] v;
+assign v = ~ARG[0][15:0];
+
+wire [0:15] e;
+genvar i;
+~GENERATE
+for (i=0;i<8;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:11] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<4;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:7] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<2;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:4] res;
+~GENERATE
+if (1) begin
+localparam n = 4;
+wire [7:0] i;
+assign i = b[0:7];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// clz16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz32#"
+    , "type"      : "clz32 :: Word# -> Word#"
+    , "templateD" :
+"// clz32 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:31] v;
+assign v = ~ARG[0][31:0];
+
+wire [0:31] e;
+genvar i;
+~GENERATE
+for (i=0;i<16;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] res;
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = c[0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// clz32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz64#"
+    , "type"      : "clz64 :: Word# -> Word#"
+    , "templateD" :
+"// clz64 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:63] v;
+assign v = ~ARG[0][63:0];
+
+wire [0:63] e;
+genvar i;
+~GENERATE
+for (i=0;i<32;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] d;
+genvar i4;
+~GENERATE
+for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = c[i4*10:i4*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] res;
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = d[0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// clz64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.clz#"
+    , "type"      : "clz :: Word# -> Word#"
+    , "templateD" :
+"// clz begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+~IF ~IW64 ~THEN
+wire [0:63] v;
+assign v = ~ARG[0][63:0];
+
+wire [0:63] e;
+genvar i;
+~GENERATE
+for (i=0;i<32;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] d;
+genvar i4;
+~GENERATE
+for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = c[i4*10:i4*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] res;
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = d[0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~ELSE
+wire [0:31] v;
+assign v = ~ARG[0][31:0];
+
+wire [0:31] e;
+genvar i;
+~GENERATE
+for (i=0;i<16;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] res;
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = c[0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~FI
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// clz end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz8#"
+    , "type"      : "ctz8 :: Word# -> Word#"
+    , "templateD" :
+"// ctz8 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:7] v;
+genvar k;
+~GENERATE
+for (k=0;k<8;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:7] e;
+genvar i;
+~GENERATE
+for (i=0;i<4;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:5] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<2;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:3] res;
+~GENERATE
+if (1) begin
+localparam n = 3;
+wire [5:0] i;
+assign i = a[0:5];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// ctz8 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz16#"
+    , "type"      : "ctz16 :: Word# -> Word#"
+    , "templateD" :
+"// ctz16 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:15] v;
+genvar k;
+~GENERATE
+for (k=0;k<16;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:15] e;
+genvar i;
+~GENERATE
+for (i=0;i<8;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:11] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<4;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:7] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<2;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:4] res;
+~GENERATE
+if (1) begin
+localparam n = 4;
+wire [7:0] i;
+assign i = b[0:7];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// ctz16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz32#"
+    , "type"      : "ctz32 :: Word# -> Word#"
+    , "templateD" :
+"// ctz32 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:31] v;
+genvar k;
+~GENERATE
+for (k=0;k<32;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:31] e;
+genvar i;
+~GENERATE
+for (i=0;i<16;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] res;
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = c[0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// ctz32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz64#"
+    , "type"      : "ctz64 :: Word# -> Word#"
+    , "templateD" :
+"// ctz64 begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+
+wire [0:63] v;
+genvar k;
+~GENERATE
+for (k=0;k<64;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:63] e;
+genvar i;
+~GENERATE
+for (i=0;i<32;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] d;
+genvar i4;
+~GENERATE
+for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = c[i4*10:i4*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] res;
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = d[0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// ctz64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.ctz#"
+    , "type"      : "ctz :: Word# -> Word#"
+    , "templateD" :
+"// ctz begin
+~GENERATE
+if (1) begin
+function [1:0] enc;
+  input [1:0] a;
+  case (a)
+    2'b00:   enc = 2'b10;
+    2'b01:   enc = 2'b01;
+    2'b10:   enc = 2'b00;
+    default: enc = 2'b00;
+  endcase
+endfunction
+~IF ~IW64 ~THEN
+wire [0:63] v;
+genvar k;
+~GENERATE
+for (k=0;k<64;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:63] e;
+genvar i;
+~GENERATE
+for (i=0;i<32;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:47] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<16;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:31] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<8;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:19] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<4;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:11] d;
+genvar i4;
+~GENERATE
+for (i4=0;i4<2;i4=i4+1) begin : mux_stage4
+  localparam n = 5;
+  wire [9:0] i;
+  assign i = c[i4*10:i4*10+9];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : d[i4*6:i4*6+5] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:6] res;
+~GENERATE
+if (1) begin
+localparam n = 6;
+wire [11:0] i;
+assign i = d[0:11];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~ELSE
+wire [0:31] v;
+genvar k;
+~GENERATE
+for (k=0;k<32;k=k+1) begin : reverse
+  assign v[k] = ~ARG[0][k];
+end
+~ENDGENERATE
+
+wire [0:31] e;
+genvar i;
+~GENERATE
+for (i=0;i<16;i=i+1) begin : enc_stage
+  assign e[i*2:i*2+1] = enc(v[i*2:i*2+1]);
+end
+~ENDGENERATE
+
+reg [0:23] a;
+genvar i1;
+~GENERATE
+for (i1=0;i1<8;i1=i1+1) begin : mux_stage1
+  localparam n = 2;
+  wire [3:0] i;
+  assign i = e[i1*4:i1*4+3];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : a[i1*3:i1*3+2] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:15] b;
+genvar i2;
+~GENERATE
+for (i2=0;i2<4;i2=i2+1) begin : mux_stage2
+  localparam n = 3;
+  wire [5:0] i;
+  assign i = a[i2*6:i2*6+5];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : b[i2*4:i2*4+3] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:9] c;
+genvar i3;
+~GENERATE
+for (i3=0;i3<2;i3=i3+1) begin : mux_stage3
+  localparam n = 4;
+  wire [7:0] i;
+  assign i = b[i3*8:i3*8+7];
+  always @(*) begin
+    case (i[n-1+n])
+      1'b0    : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+      default : c[i3*5:i3*5+4] = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+    endcase
+  end
+end
+~ENDGENERATE
+
+reg [0:5] res;
+~GENERATE
+if (1) begin
+localparam n = 5;
+wire [9:0] i;
+assign i = c[0:9];
+always @(*) begin
+  case (i[n-1+n])
+    1'b0    : res = {i[n-1+n] && i[n-1],1'b0,i[2*n-2:n]};
+    default : res = {i[n-1+n] && i[n-1],~ i[n-1],i[n-2:0]};
+  endcase
+end
+end
+~ENDGENERATE
+~FI
+assign ~RESULT = $unsigned(res);
+end
+~ENDGENERATE
+// ctz end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap16#"
+    , "type"      : "byteSwap16# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap16 begin
+wire ~TYP[0] ~SYM[0];
+assign ~SYM[0] = ~ARG[0];
+~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[0][63:16],~SYM[0][7:0],~SYM[0][15:8]};
+~ELSE
+assign ~RESULT = {~SYM[0][31:16],~SYM[0][7:0],~SYM[0][15:8]};
+~FI
+// byteSwap16 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap32#"
+    , "type"      : "byteSwap32# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap32 begin
+wire ~TYPO ~SYM[0];
+assign ~SYM[0] = ~ARG[0];
+~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[0][63:32],~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};
+~ELSE
+assign ~RESULT = {~SYM[0][7:0],~SYM[0][15:8],~SYM[0][23:16],~SYM[0][31:24]};
+~FI
+// byteSwap32 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap64#"
+    , "type"      : "byteSwap64# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap64 begin
+wire ~TYP[0] ~SYM[1];
+assign ~SYM[1] = ~ARG[0];
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
+                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};
+// byteSwap64 end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.byteSwap#"
+    , "type"      : "byteSwap# :: Word# -> Word#"
+    , "templateD" :
+"// byteSwap begin
+wire ~TYP[0] ~SYM[1];
+assign ~SYM[1] = ~ARG[0];
+~IF ~IW64 ~THEN
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]
+                 ,~SYM[1][39:32],~SYM[1][47:40],~SYM[1][55:48],~SYM[1][63:56]};
+~ELSE
+assign ~RESULT = {~SYM[1][7:0],~SYM[1][15:8],~SYM[1][23:16],~SYM[1][31:24]};
+~FI
+// byteSwap end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow8Int#"
+    , "type"      : "narrow8Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow8Int begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][7:0]);
+// narrow8Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow16Int#"
+    , "type"      : "narrow16Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow16Int begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][15:0]);
+// narrow16Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow32Int#"
+    , "type"      : "narrow32Int# :: Int# -> Int#"
+    , "templateD" :
+"// narrow32Int begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $signed(~SYM[0][31:0]);
+// narrow32Int end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow8Word#"
+    , "type"      : "narrow8Int# :: Word# -> Word#"
+    , "templateD" :
+"// narrow8Word begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $unsigned(~SYM[0][7:0]);
+// narrow8Word end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow16Word#"
+    , "type"      : "narrow16Word# :: Word# -> Word#"
+    , "templateD" :
+"// narrow16Word begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $unsigned(~SYM[0][15:0]);
+// narrow16Word end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.narrow32Word#"
+    , "type"      : "narrow32Int# :: Word# -> Word#"
+    , "templateD" :
+"// narrow32Word begin
+wire ~SIGD[~SYM[0]][0];
+assign ~SYM[0] = ~ARG[0];
+
+assign ~RESULT = $unsigned(~SYM[0][31:0]);
+// narrow32Word end"
+    }
+  }
+, { "Primitive" :
+    { "name"     : "GHC.Prim.dataToTag#"
+    , "primType" : "Function"
+    }
+  }
+, { "Primitive" :
+    { "name"     : "GHC.Prim.tagToEnum#"
+    , "primType" : "Function"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.unsafeCoerce#"
+    , "type"      : "unsafeCoerce# :: a -> b"
+    , "templateE" : "~ARG[0]"
     }
   }
 ]
diff --git a/primitives/GHC.Typelits.json b/primitives/GHC.Typelits.json
--- a/primitives/GHC.Typelits.json
+++ b/primitives/GHC.Typelits.json
@@ -1,7 +1,7 @@
 [ { "BlackBox" :
     { "name"      : "GHC.TypeLits.natVal"
     , "type"      : "natVal :: forall n proxy. KnownNat n => proxy n -> Integer"
-    , "templateE" : "~LIT[0]"
+    , "templateE" : "~ARG[0]"
     }
   }
 ]
diff --git a/primitives/GHC.Types.json b/primitives/GHC.Types.json
--- a/primitives/GHC.Types.json
+++ b/primitives/GHC.Types.json
@@ -8,4 +8,22 @@
     , "primType"  : "Constructor"
     }
   }
+, { "BlackBox" :
+    { "name"      : "GHC.Types.C#"
+    , "type"      : "I# :: Char# -> Char"
+    , "templateE" : "~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Types.I#"
+    , "type"      : "I# :: Int# -> Int"
+    , "templateE" : "~ARG[0]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Types.W#"
+    , "type"      : "W# :: Word# -> Word"
+    , "templateE" : "~ARG[0]"
+    }
+  }
 ]
diff --git a/primitives/GHC.Word.json b/primitives/GHC.Word.json
new file mode 100644
--- /dev/null
+++ b/primitives/GHC.Word.json
@@ -0,0 +1,25 @@
+[ { "BlackBox" :
+    { "name"      : "GHC.Word.W8#"
+    , "type"      : "W8# :: Word# -> Word8"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Word.W16#"
+    , "type"      : "W16# :: Word# -> Word16"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Word.W32#"
+    , "type"      : "W32# :: Word# -> Word32"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Word.W64#"
+    , "type"      : "W64# :: Word# -> Word64"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
+    }
+  }
+]
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -19,7 +19,7 @@
 
 import           CLaSH.Backend
 import           CLaSH.Netlist.BlackBox.Util          (extractLiterals, renderBlackBox)
-import           CLaSH.Netlist.Types
+import           CLaSH.Netlist.Types                  hiding (_intWidth, intWidth)
 import           CLaSH.Netlist.Util
 import           CLaSH.Util                           (curLoc, (<:>))
 
@@ -33,6 +33,7 @@
 data VerilogState =
   VerilogState
     { _genDepth  :: Int -- ^ Depth of current generative block
+    , _intWidth  :: Int -- ^ Int/Word/Integer bit-width
     }
 
 makeLenses ''VerilogState
@@ -66,6 +67,7 @@
                           else "endgenerate"
   inst            = inst_
   expr            = expr_
+  iwWidth         = use intWidth
 
 type VerilogM a = State VerilogState a
 
@@ -98,11 +100,10 @@
 
 verilogType :: HWType -> VerilogM Doc
 verilogType t = case t of
-    Integer       -> verilogType (Signed 32)
-    (Signed n)    -> "signed" <+> brackets (int (n-1) <> colon <> int 0)
-    (Clock _ _)   -> empty
-    (Reset _ _)   -> empty
-    _             -> brackets (int (typeSize t -1) <> colon <> int 0)
+  Signed n -> "signed" <+> brackets (int (n-1) <> colon <> int 0)
+  Clock {} -> empty
+  Reset {} -> empty
+  _        -> brackets (int (typeSize t -1) <> colon <> int 0)
 
 sigDecl :: VerilogM Doc -> HWType -> VerilogM Doc
 sigDecl d t = verilogType t <+> d
@@ -285,12 +286,16 @@
   parenIf (b || b') $ string t
 
 expr_ _ (DataTag Bool (Left id_))          = text id_ <> brackets (int 0)
-expr_ _ (DataTag Bool (Right id_))         = "$signed" <> parens (listBraces (sequence [braces (int 31 <+> braces "1'b0"),text id_]))
+expr_ _ (DataTag Bool (Right id_))         = do
+  iw <- use intWidth
+  "$signed" <> parens (listBraces (sequence [braces (int (iw-1) <+> braces "1'b0"),text id_]))
 
 expr_ _ (DataTag (Sum _ _) (Left id_))     = "$unsigned" <> parens (text id_)
 expr_ _ (DataTag (Sum _ _) (Right id_))    = "$signed" <> parens (text id_)
 
-expr_ _ (DataTag (Product _ _) (Right _))  = "32'sd0"
+expr_ _ (DataTag (Product _ _) (Right _))  = do
+  iw <- use intWidth
+  int iw <> "'sd0"
 
 expr_ _ (DataTag hty@(SP _ _) (Right id_)) = "$signed" <> parens
                                                (text id_ <> brackets
@@ -299,8 +304,12 @@
     start = typeSize hty - 1
     end   = typeSize hty - conSize hty
 
-expr_ _ (DataTag (Vector 0 _) (Right _)) = "32'sd0"
-expr_ _ (DataTag (Vector _ _) (Right _)) = "32'sd1"
+expr_ _ (DataTag (Vector 0 _) (Right _)) = do
+  iw <- use intWidth
+  int iw <> "'sd0"
+expr_ _ (DataTag (Vector _ _) (Right _)) = do
+  iw <- use intWidth
+  int iw <> "'sd1"
 
 expr_ _ e = error $ $(curLoc) ++ (show e) -- empty
 
@@ -324,17 +333,6 @@
   Signed _
    | i < 0     -> "-" <> int sz <> "'sd" <> integer (abs i)
    | otherwise -> int sz <> "'sd" <> integer i
-  Integer ->
-    let integerLow  = -2^(31 :: Integer) :: Integer
-        integerHigh = 2^(31 :: Integer) - 1 :: Integer
-        i' = if i < integerLow
-                then integerLow
-                else if i > integerHigh
-                     then integerHigh
-                     else i
-    in  if (i' < 0)
-           then "-" <> int 32 <> "'sd" <> integer (abs i')
-           else int 32 <> "'sd" <> integer i
   _ -> int sz <> "'b" <> blit
   where
     blit = bits (toBits sz i)