diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,11 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.3 *November 17th 2015*
+* Fixes bugs:
+  * Name collision in verilog code [#93](https://github.com/clash-lang/clash-compiler/issues/93)
+  * Integer literals missing "32'sd" prefix when used in assignments.
+  * HO-primitives incorrect for nested vectors.
+
 ## 0.6.2 *October 21st 2015*
 * New features:
   * Support `clash-prelude` 0.10.2
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.6.2
+Version:              0.6.3
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -116,10 +116,15 @@
 genvar ~SYM[1];
 ~GENERATE
 for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
+  wire ~TYPEL[~TYP[1]] ~SYM[3];
+  wire ~TYPEL[~TYPO] ~SYM[4];
+
+  assign ~SYM[3] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];
   ~INST 0
-    ~OUTPUT <= ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
-    ~INPUT  <= ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]]~ ~TYPEL[~TYP[1]]~
+    ~OUTPUT <= ~SYM[4]~ ~TYPEL[~TYPO]~
+    ~INPUT  <= ~SYM[3]~ ~TYPEL[~TYP[1]]~
   ~INST
+  assign ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[4];
 end
 ~ENDGENERATE
 // map end"
@@ -137,12 +142,17 @@
 ~GENERATE
 for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
   wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~SYM[3];
+  wire ~TYPEL[~TYP[2]] ~SYM[4];
+  wire ~TYPEL[~TYPO] ~SYM[5];
+
   assign ~SYM[3] = ~SYM[1];
+  assign ~SYM[4] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
   ~INST 1
-    ~OUTPUT <= ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
+    ~OUTPUT <= ~SYM[5]~ ~TYPEL[~TYPO]~
     ~INPUT  <= ~SYM[3]~ ~INDEXTYPE[~LIT[0]]~
-    ~INPUT  <= ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
+    ~INPUT  <= ~SYM[4]~ ~TYPEL[~TYP[2]]~
   ~INST
+  assign ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
 end
 ~ENDGENERATE
 // imap end"
@@ -161,11 +171,18 @@
 genvar ~SYM[2];
 ~GENERATE
 for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : zipWith_~SYM[2]
+  wire ~TYPEL[~TYP[1]] ~SYM[3];
+  wire ~TYPEL[~TYP[2]] ~SYM[4];
+  wire ~TYPEL[~TYPO] ~SYM[5];
+
+  assign ~SYM[3] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];
+  assign ~SYM[4] = ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
   ~INST 0
-    ~OUTPUT <= ~RESULT[~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
-    ~INPUT  <= ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]]~ ~TYPEL[~TYP[1]]~
-    ~INPUT  <= ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
+    ~OUTPUT <= ~SYM[5]~ ~TYPEL[~TYPO]~
+    ~INPUT  <= ~SYM[3]~ ~TYPEL[~TYP[1]]~
+    ~INPUT  <= ~SYM[4]~ ~TYPEL[~TYP[2]]~
   ~INST
+  assign ~RESULT[~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[5];
 end
 ~ENDGENERATE
 // zipWith end"
@@ -184,12 +201,19 @@
 
 genvar i_~SYM[3];
 ~GENERATE
-for (i_~SYM[3]=0; i_~SYM[3] < ~LENGTH[~TYP[2]]; i_~SYM[3]=i_~SYM[3]+1) begin : foldr_loop
+for (i_~SYM[3]=0; i_~SYM[3] < ~LENGTH[~TYP[2]]; i_~SYM[3]=i_~SYM[3]+1) begin : foldr_~SYM[4]
+  wire ~TYPEL[~TYP[2]] ~SYM[5];
+  wire ~TYPO ~SYM[6];
+  wire ~TYPO ~SYM[7];
+
+  assign ~SYM[5] = xs_~SYM[2][(~LENGTH[~TYP[2]]-1-i_~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];
+  assign ~SYM[6] = intermediate_~SYM[0][i_~SYM[3]+1];
   ~INST 0
-    ~OUTPUT <= intermediate_~SYM[0][i_~SYM[3]]~ ~TYP[1]~
-    ~INPUT <= xs_~SYM[2][(~LENGTH[~TYP[2]]-1-i_~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
-    ~INPUT <= intermediate_~SYM[0][i_~SYM[3]+1]~ ~TYP[1]~
+    ~OUTPUT <= ~SYM[7]~ ~TYP[1]~
+    ~INPUT  <= ~SYM[5]~ ~TYPEL[~TYP[2]]~
+    ~INPUT  <= ~SYM[6]~ ~TYP[1]~
   ~INST
+  assign intermediate_~SYM[0][i_~SYM[3]] = ~SYM[7];
 end
 ~ENDGENERATE
 
@@ -244,11 +268,18 @@
 if (levels_~SYM[4] != 0) begin : make_tree_~SYM[7]
   for (d_~SYM[5] = (levels_~SYM[4] - 1); d_~SYM[5] >= 0; d_~SYM[5]=d_~SYM[5]-1) begin : tree_depth
     for (i_~SYM[6] = 0; i_~SYM[6] < (2**d_~SYM[5]); i_~SYM[6] = i_~SYM[6]+1) begin : tree_depth_loop
-        ~INST 0
-          ~OUTPUT <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+1)+i_~SYM[6]]~ ~TYPO~
-          ~INPUT  <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])]~ ~TYPO~
-          ~INPUT  <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])+1]~ ~TYPO~
-        ~INST
+      wire ~TYPO ~SYM[8];
+      wire ~TYPO ~SYM[9];
+      wire ~TYPO ~SYM[10];
+
+      assign ~SYM[8] = intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])];
+      assign ~SYM[9] = intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])+1];
+      ~INST 0
+        ~OUTPUT <= ~SYM[10]~ ~TYPO~
+        ~INPUT  <= ~SYM[8]~ ~TYPO~
+        ~INPUT  <= ~SYM[9]~ ~TYPO~
+      ~INST
+      assign intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+1)+i_~SYM[6]] = ~SYM[10];
     end
   end
 end
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -316,26 +316,26 @@
 vectorChain _                                       = Nothing
 
 exprLit :: Maybe (HWType,Size) -> Literal -> VerilogM Doc
-exprLit Nothing (NumLit i) =
-  let integerLow  = -2^(31 :: Integer) :: Integer
-      integerHigh = 2^(31 :: Integer) - 1 :: Integer
-      i' = if i < integerLow
-              then integerLow
-              else if i > integerHigh
-                   then integerHigh
-                   else i
-  in  parenIf (i' < 0) (integer i')
-exprLit (Just (hty,sz)) (NumLit i) = case hty of
-                                       Unsigned _   -> int sz <> "'d" <> integer i
-                                       Index _      -> int (typeSize hty) <> "'d" <> integer i
-                                       Signed _
-                                        | i < 0     -> "-" <> int sz <> "'sd" <> integer (abs i)
-                                        | otherwise -> int sz <> "'sd" <> integer i
-                                       Integer
-                                        | i < 0     -> "-" <> int 32 <> "'sd" <> integer (abs i)
-                                        | otherwise -> int 32 <> "'sd" <> integer i
-                                       _            -> int sz <> "'b" <> blit
+exprLit Nothing (NumLit i) = integer i
 
+exprLit (Just (hty,sz)) (NumLit i) = case hty of
+  Unsigned _ -> int sz <> "'d" <> integer i
+  Index _ -> int (typeSize hty) <> "'d" <> integer i
+  Signed _
+   | i < 0     -> "-" <> int sz <> "'sd" <> integer (abs i)
+   | otherwise -> int sz <> "'sd" <> integer i
+  Integer ->
+    let integerLow  = -2^(31 :: Integer) :: Integer
+        integerHigh = 2^(31 :: Integer) - 1 :: Integer
+        i' = if i < integerLow
+                then integerLow
+                else if i > integerHigh
+                     then integerHigh
+                     else i
+    in  if (i' < 0)
+           then "-" <> int 32 <> "'sd" <> integer (abs i')
+           else int 32 <> "'sd" <> integer i
+  _ -> int sz <> "'b" <> blit
   where
     blit = bits (toBits sz i)
 exprLit _             (BoolLit t)   = if t then "1'b1" else "1'b0"