clash-verilog 0.5.9 → 0.5.10

raw patch · 4 files changed

+8/−4 lines, 4 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• clash-verilog.cabal +1/−1
• primitives/CLaSH.Driver.TestbenchGen.json +1/−1
• primitives/CLaSH.Prelude.Testbench.json +2/−2

@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.5.10 *September 21st 2015*+* New features:+  * Report simulation time in assert messages+ ## 0.5.9 *September 14th 2015* * Support for clash-lib-0.5.12 

@@ -1,5 +1,5 @@ Name:                 clash-verilog-Version:              0.5.9+Version:              0.5.10 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

@@ -22,7 +22,7 @@ "// pragma translate_off reg ~TYPO ~SYM[0]; initial begin-  ~SYM[0] = 0;+  #1 ~SYM[0] = 0;   #~LIT[0] ~SYM[0] = 1; end assign ~RESULT = ~SYM[0];

@@ -12,8 +12,8 @@ "// assert begin // pragma translate_off always @(posedge ~CLK[2] or posedge ~RST[2]) begin-  if (~ARG[4] != ~ARG[5]) begin-    $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~ARG[5], ~ARG[4]);+  if (~ARG[4] !== ~ARG[5]) begin+    $display(\"@%0tns: %s, expected: %b, actual: %b\", $time, ~LIT[3], ~ARG[5], ~ARG[4]);     $finish;   end end