clash-verilog 0.5.7 → 0.5.8
raw patch · 6 files changed
+72/−14 lines, 6 filesPVP: major bump suggested
API removals or changes: PVP suggests a major version bump
API changes (from Hackage documentation)
- CLaSH.Backend.Verilog: instance Backend VerilogState
+ CLaSH.Backend.Verilog: instance CLaSH.Backend.Backend CLaSH.Backend.Verilog.VerilogState
Files
- CHANGELOG.md +5/−0
- README.md +27/−3
- clash-verilog.cabal +28/−5
- primitives/CLaSH.Prelude.Testbench.json +1/−1
- primitives/CLaSH.Sized.Internal.Signed.json +5/−5
- src/CLaSH/Backend/Verilog.hs +6/−0
CHANGELOG.md view
@@ -1,5 +1,10 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.5.8 *September 7th 2015*+* Fixes bugs:+ * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)+ * rem and quot on Signed are broken [#73](https://github.com/clash-lang/clash-compiler/issues/73)+ ## 0.5.7 *June 26th 2015* * New features: * Generate Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
README.md view
@@ -1,5 +1,29 @@-# Support-For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)+# `clash-verilog` - Verilog backend for the CλaSH compiler -# `clash-verilog` * See the LICENSE file for license and copyright details++# CλaSH - A functional hardware description language+CλaSH (pronounced ‘clash’) is a functional hardware description language that+borrows both its syntax and semantics from the functional programming language+Haskell. The CλaSH compiler transforms these high-level descriptions to+low-level synthesizable VHDL, Verilog, or SystemVerilog.++Features of CλaSH:++ * Strongly typed (like VHDL), yet with a very high degree of type inference,+ which enables both safe and fast prototying using consise descriptions (like+ Verilog)++ * Interactive REPL: load your designs in an interpreter and easily test all+ your component without needing to setup a test bench.++ * Higher-order functions, with type inference, result in designs that are+ fully parametric by default.++ * Synchronous sequential circuit design based on streams of values, called+ `Signal`s.++ * Support for multiple clock domains, with type safe clock domain crossing.++# Support+For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)
clash-verilog.cabal view
@@ -1,14 +1,30 @@ Name: clash-verilog-Version: 0.5.7+Version: 0.5.8 Synopsis: CAES Language for Synchronous Hardware - Verilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language- Haskell. The merits of using a functional language to describe hardware comes- from the fact that combinational circuits can be directly modelled as- mathematical functions and that functional languages lend themselves very well- at describing and (de-)composing mathematical functions.+ Haskell. The CλaSH compiler transforms these high-level descriptions to+ low-level synthesizable VHDL, Verilog, or SystemVerilog. .+ Features of CλaSH:+ .+ * Strongly typed (like VHDL), yet with a very high degree of type inference,+ which enables both safe and fast prototying using consise descriptions (like+ Verilog)+ .+ * Interactive REPL: load your designs in an interpreter and easily test all+ your component without needing to setup a test bench.+ .+ * Higher-order functions, with type inference, result in designs that are+ fully parametric by default.+ .+ * Synchronous sequential circuit design based on streams of values, called+ @Signal@s.+ .+ * Support for multiple clock domains, with type safe clock domain crossing.+ .+ . This package provides: . * Verilog Backend@@ -68,6 +84,13 @@ default-language: Haskell2010 ghc-options: -Wall CPP-Options: -DCABAL++ other-extensions: CPP+ OverloadedStrings+ RecursiveDo+ TemplateHaskell+ TupleSections+ ViewPatterns Build-depends: base >= 4.6.0.1 && < 5, clash-lib >= 0.5.8,
primitives/CLaSH.Prelude.Testbench.json view
@@ -14,7 +14,7 @@ always @(posedge ~CLK[2] or posedge ~RST[2]) begin if (~ARG[4] != ~ARG[5]) begin $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~ARG[5], ~ARG[4]);- $stop;+ $finish; end end // pragma translate_on
primitives/CLaSH.Sized.Internal.Signed.json view
@@ -1,5 +1,5 @@ [ { "BlackBox" :- { "name" : "CLaSH.Sized.Internal.Internal.Signed.size#"+ { "name" : "CLaSH.Sized.Internal.Signed.size#" , "type" : "size# :: KnownNat n => Signed n -> Int" , "templateE" : "~LIT[0]" }@@ -122,14 +122,14 @@ } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Signed.quot#"- , "type" : "quot# :: KnownNat n => Signed n -> Signed n -> Signed n"- , "templateE" : "~ARG[1] / ~ARG[2]"+ , "type" : "quot# :: Signed n -> Signed n -> Signed n"+ , "templateE" : "~ARG[0] / ~ARG[1]" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Signed.rem#"- , "type" : "rem# :: KnownNat n => Signed n -> Signed n -> Signed n"- , "templateE" : "~ARG[1] % ~ARG[2]"+ , "type" : "rem# :: Signed n -> Signed n -> Signed n"+ , "templateE" : "~ARG[0] % ~ARG[1]" } } , { "BlackBox" :
src/CLaSH/Backend/Verilog.hs view
@@ -256,6 +256,11 @@ , [Literal _ (NumLit n), Literal _ i] <- extractLiterals bbCtx = exprLit (Just (BitVector (fromInteger n),fromInteger n)) i +expr_ _ (BlackBoxE pNm _ bbCtx _)+ | pNm == "CLaSH.Sized.Internal.Index.fromInteger#"+ , [Literal _ (NumLit n), Literal _ i] <- extractLiterals bbCtx+ = exprLit (Just (Index (fromInteger n),fromInteger n)) i+ expr_ b (BlackBoxE _ bs bbCtx b') = do t <- renderBlackBox bs bbCtx parenIf (b || b') $ string t@@ -295,6 +300,7 @@ exprLit Nothing (NumLit i) = integer i exprLit (Just (hty,sz)) (NumLit i) = case hty of Unsigned _ -> int sz <> "'d" <> integer i+ Index _ -> int (typeSize hty) <> "'d" <> integer i Signed _ | i < 0 -> "-" <> int sz <> "'sd" <> integer (abs i) | otherwise -> int sz <> "'sd" <> integer i