diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.7 *June 26th 2015*
+* New features:
+  * Generate Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
+
 ## 0.5.6 *June 25th 2015*
 * New features:
   * Support `clash-prelude-0.9`
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.5.6
+Version:              0.5.7
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -70,7 +70,7 @@
   CPP-Options:        -DCABAL
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.7,
+                      clash-lib               >= 0.5.8,
                       clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
diff --git a/primitives/CLaSH.Prelude.ROM.json b/primitives/CLaSH.Prelude.ROM.json
--- a/primitives/CLaSH.Prelude.ROM.json
+++ b/primitives/CLaSH.Prelude.ROM.json
@@ -12,9 +12,11 @@
 wire ~TYP[1] romflat_~SYM[1];
 assign romflat_~SYM[1] = ~ARG[1];
 genvar ~SYM[2];
+~GENERATE
 for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
   assign ROM_~SYM[0][(~LIT[0]-1)-~SYM[2]] = romflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
+~ENDGENERATE
 
 assign ~RESULT = ROM_~SYM[0][~ARG[2]];
 // asyncRom end"
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -242,6 +242,7 @@
     , "comment"   : "Back-end should only use this code when the result is smaller than the argument"
     , "templateD" :
 "// resize begin
+~GENERATE
 if (~LIT[1] < ~LIT[0]) begin
   // truncate, sign preserving
   wire ~SIGD[~SYM[0]][2];
@@ -251,6 +252,7 @@
   // sign-extend
   assign ~RESULT = $signed(~ARG[2]);
 end
+~ENDGENERATE
 // resize end"
     }
   }
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -74,14 +74,18 @@
 
 wire ~TYPEL[~TYPO] ~SYM[1] [0:~LENGTH[~TYP[4]]-1];
 genvar ~SYM[2];
+~GENERATE
 for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[4]]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
   assign ~SYM[1][(~LENGTH[~TYP[4]]-1)-~SYM[2]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
 end
+~ENDGENERATE
 
 genvar ~SYM[4];
+~GENERATE
 for (~SYM[4]=0; ~SYM[4] < ~LIT[3]; ~SYM[4] = ~SYM[4] + 1) begin : select_~SYM[5]
   assign ~RESULT[(~LIT[3]-1-~SYM[4])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[1][~LIT[1] + (~LIT[2] * ~SYM[4])];
 end
+~ENDGENERATE
 // select end"
     }
   }
@@ -124,10 +128,12 @@
 assign ~SYM[1] = ~ARG[1];
 
 genvar ~SYM[2];
+~GENERATE
 for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYP[0]]; ~SYM[2] = ~SYM[2] + 1) begin : merge_~SYM[3]
   assign ~RESULT[(2*~SYM[2]+1)*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
   assign ~RESULT[(2*~SYM[2])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]   = ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
 end
+~ENDGENERATE
 // merge end"
     }
   }
@@ -140,12 +146,14 @@
 assign ~SYM[0] = ~ARG[1];
 
 genvar ~SYM[1];
+~GENERATE
 for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
   ~INST 0
     ~OUTPUT <= ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
     ~INPUT  <= ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]]~ ~TYPEL[~TYP[1]]~
   ~INST
 end
+~ENDGENERATE
 // map end"
     }
   }
@@ -160,6 +168,7 @@
 assign ~SYM[1] = ~ARG[2];
 
 genvar ~SYM[2];
+~GENERATE
 for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : zipWith_~SYM[2]
   ~INST 0
     ~OUTPUT <= ~RESULT[~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
@@ -167,6 +176,7 @@
     ~INPUT  <= ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
   ~INST
 end
+~ENDGENERATE
 // zipWith end"
     }
   }
@@ -180,9 +190,11 @@
 wire ~TYP[1] vecflat_~SYM[1];
 assign vecflat_~SYM[1] = ~ARG[1];
 genvar ~SYM[2];
+~GENERATE
 for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
   assign vec_~SYM[0][(~LIT[0]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
+~ENDGENERATE
 
 assign ~RESULT = vec_~SYM[0][~ARG[2]];
 // indexVec end"
@@ -206,9 +218,11 @@
 end
 
 genvar ~SYM[3];
+~GENERATE
 for (~SYM[3]=0;~SYM[3]<~LIT[0];~SYM[3]=~SYM[3]+1) begin : vec_~SYM[4]
   assign ~RESULT[~SYM[3]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = vec_~SYM[1][(~LIT[0]-1)-~SYM[3]];
 end
+~ENDGENERATE
 // replaceVec end"
     }
   }
@@ -239,9 +253,11 @@
 assign ~SYM[0] = ~ARG[0];
 
 genvar ~SYM[1];
+~GENERATE
 for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2]
   assign ~RESULT[(~LENGTH[~TYPO] - 1 - ~SYM[1])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
 end
+~ENDGENERATE
 // reverse end"
     }
   }
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -9,6 +9,7 @@
 module CLaSH.Backend.Verilog (VerilogState) where
 
 import qualified Control.Applicative                  as A
+import           Control.Lens                         ((+=),(-=), makeLenses, use)
 import           Control.Monad.State                  (State)
 import qualified Data.HashSet                         as HashSet
 import           Data.Maybe                           (catMaybes)
@@ -29,10 +30,15 @@
 #endif
 
 -- | State for the 'CLaSH.Backend.Verilog.VerilogM' monad:
-data VerilogState = VerilogState
+data VerilogState =
+  VerilogState
+    { _genDepth  :: Int -- ^ Depth of current generative block
+    }
 
+makeLenses ''VerilogState
+
 instance Backend VerilogState where
-  initBackend     = VerilogState
+  initBackend     = VerilogState 0
 #ifdef CABAL
   primDir         = const (Paths_clash_verilog.getDataFileName "primitives")
 #else
@@ -48,6 +54,16 @@
   hdlTypeErrValue = verilogTypeErrValue
   hdlTypeMark     = verilogTypeMark
   hdlSig t ty     = sigDecl (text t) ty
+  genStmt True    = do cnt <- use genDepth
+                       genDepth += 1
+                       if cnt > 0
+                          then empty
+                          else "generate"
+  genStmt False   = do genDepth -= 1
+                       cnt <- use genDepth
+                       if cnt > 0
+                          then empty
+                          else "endgenerate"
   inst            = inst_
   expr            = expr_
 
@@ -58,7 +74,7 @@
 genVerilog c = (unpack cName,) A.<$> verilog
   where
     cName   = componentName c
-    verilog = "// Automatically generated Verilog-2005" <$$>
+    verilog = "// Automatically generated Verilog-2001" <$$>
               module_ c
 
 module_ :: Component -> VerilogM Doc