diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,12 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.6 *June 25th 2015*
+* New features:
+  * Support `clash-prelude-0.9`
+
+* Fixes bug:
+  * Can not operate "shiftR" on Int [#63](https://github.com/clash-lang/clash-compiler/issues/63)
+  * Fail to generate verilog when using "quot" and "div" on Index [#64](https://github.com/clash-lang/clash-compiler/issues/64)
+
 ## 0.5.5 *June 3rd 2015*
 * Initial release
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.5.5
+Version:              0.5.6
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -29,6 +29,10 @@
                       primitives/CLaSH.Driver.TopWrapper.json
                       primitives/CLaSH.GHC.GHC2Core.json
                       primitives/CLaSH.Prelude.BlockRam.json
+                      primitives/CLaSH.Prelude.BlockRam.File.json
+                      primitives/CLaSH.Prelude.RAM.json
+                      primitives/CLaSH.Prelude.ROM.json
+                      primitives/CLaSH.Prelude.ROM.File.json
                       primitives/CLaSH.Prelude.Testbench.json
                       primitives/CLaSH.Promoted.Nat.json
                       primitives/CLaSH.Promoted.Symbol.json
@@ -66,8 +70,8 @@
   CPP-Options:        -DCABAL
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.6,
-                      clash-prelude           >= 0.8,
+                      clash-lib               >= 0.5.7,
+                      clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
                       mtl                     >= 2.1.2,
diff --git a/primitives/CLaSH.Prelude.BlockRam.File.json b/primitives/CLaSH.Prelude.BlockRam.File.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.BlockRam.File.json
@@ -0,0 +1,33 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"
+    , "type" :
+"blockRamFile# :: KnownNat m                 -- ARG[0]
+               => SClock clk                 -- clk,  ARG[1]
+               -> SNat n                     -- sz,   ARG[2]
+               -> FilePath                   -- file, ARG[3]
+               -> Signal' clk Int            -- wr,   ARG[4]
+               -> Signal' clk Int            -- rd,   ARG[5]
+               -> Signal' clk Bool           -- wren, ARG[6]
+               -> Signal' clk (BitVector m)  -- din,  ARG[7]
+               -> Signal' clk (BitVector m)"
+    , "templateD" :
+"// blockRamFile begin
+reg ~TYPO RAM_~SYM[0] [0:~LIT[2]-1];
+reg ~TYPO dout_~SYM[1];
+
+initial begin
+  $readmemb(~FILE[~LIT[3]],RAM_~SYM[0]);
+end
+
+always @(posedge ~CLK[1]) begin : blockRamFile_~COMPNAME_~SYM[2]
+  if (~ARG[6]) begin
+    RAM_~SYM[0][~ARG[4]] <= ~ARG[7];
+  end
+  dout_~SYM[1] <= RAM_~SYM[0][~ARG[5]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// blockRamFile end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.BlockRam.json b/primitives/CLaSH.Prelude.BlockRam.json
--- a/primitives/CLaSH.Prelude.BlockRam.json
+++ b/primitives/CLaSH.Prelude.BlockRam.json
@@ -1,36 +1,37 @@
 [ { "BlackBox" :
-    { "name" : "CLaSH.Prelude.BlockRam.blockRam'"
+    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
     , "type" :
-"blockRam' :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])
-           => SClock clk               -- clk,  ARG[2]
-           -> Vec n a                  -- init, ARG[3]
-           -> Signal' clk (Unsigned m) -- wr,   ARG[4]
-           -> Signal' clk (Unsigned m) -- rd,   ARG[5]
-           -> Signal' clk Bool         -- wren, ARG[6]
-           -> Signal' clk a            -- din,  ARG[7]
+"blockRam# :: KnownNat n       -- ARG[0]
+           => SClock clk       -- clk,  ARG[1]
+           -> Vec n a          -- init, ARG[2]
+           -> Signal' clk Int  -- wr,   ARG[3]
+           -> Signal' clk Int  -- rd,   ARG[4]
+           -> Signal' clk Bool -- wren, ARG[5]
+           -> Signal' clk a    -- din,  ARG[6]
            -> Signal' clk a"
     , "templateD" :
-"// blockRam
-reg ~TYPO ~SYM[0] [0:~LIT[0]-1];
-reg ~SIGD[~SYM[1]][7];
+"// blockRam begin
+reg ~TYPO RAM_~SYM[0] [0:~LIT[0]-1];
+reg ~TYPO dout_~SYM[1];
 
-reg ~TYP[3] ~SYM[2];
+reg ~TYP[2] ram_init_~SYM[2];
 integer ~SYM[3];
 initial begin
-  ~SYM[2] = ~ARG[3];
+  ram_init_~SYM[2] = ~ARG[2];
   for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
-    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+    RAM_~SYM[0][~LIT[0]-1-~SYM[3]] = ram_init_~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
   end
 end
 
-always @(posedge ~CLK[2]) begin : blockRam_~COMPNAME_~SYM[4]
-  if (~ARG[6]) begin
-    ~SYM[0][~ARG[4]] <= ~ARG[7];
+always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[4]
+  if (~ARG[5]) begin
+    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
   end
-  ~SYM[1] <= ~SYM[0][~ARG[5]];
+  dout_~SYM[1] <= RAM_~SYM[0][~ARG[4]];
 end
 
-assign ~RESULT = ~SYM[1];"
+assign ~RESULT = dout_~SYM[1];
+// blockRam end"
     }
   }
 ]
diff --git a/primitives/CLaSH.Prelude.RAM.json b/primitives/CLaSH.Prelude.RAM.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.RAM.json
@@ -0,0 +1,26 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.RAM.asyncRam#"
+    , "type" :
+"asyncRam# :: SClock wclk       -- ^ wclk, ARG[0]
+           -> SClock rclk       -- ^ rclk, ARG[1]
+           -> SNat n            -- ^ sz,   ARG[2]
+           -> Signal' wclk Int  -- ^ wr,   ARG[3]
+           -> Signal' rclk Int  -- ^ rd,   ARG[4]
+           -> Signal' wclk Bool -- ^ en,   ARG[5]
+           -> Signal' wclk a    -- ^ din,  ARG[6]
+           -> Signal' rclk a"
+    , "templateD" :
+"// asyncRam begin
+reg ~TYPO RAM_~SYM[0] [0:~LIT[2]-1];
+
+always @(posedge ~CLK[0]) begin : Ram_~COMPNAME_~SYM[4]
+  if (~ARG[5]) begin
+    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
+  end
+end
+
+assign ~RESULT = RAM_~SYM[0][~ARG[4]];
+// asyncRam end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.ROM.File.json b/primitives/CLaSH.Prelude.ROM.File.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.ROM.File.json
@@ -0,0 +1,47 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.File.asyncRomFile#"
+    , "type" :
+"asyncRomFile :: KnownNat m -- ARG[0]
+              => SNat n     -- sz,   ARG[1]
+              -> FilePath   -- file, ARG[2]
+              -> Int        -- rd,   ARG[3]
+              -> BitVector m"
+    , "templateD" :
+"// asyncRomFile begin
+reg ~TYPO ROM_~SYM[0] [0:~LIT[1]-1];
+
+initial begin
+  $readmemb(~FILE[~LIT[2]],ROM_~SYM[0]);
+end
+
+assign ~RESULT = ROM_~SYM[0][~ARG[3]];
+// asyncRomFile end"
+    }
+  }
+, { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.File.romFile#"
+    , "type" :
+"romFile# :: KnownNat m      -- ARG[0]
+          => SClock clk      -- clk,  ARG[1]
+          -> SNat n          -- sz,   ARG[2]
+          -> FilePath        -- file, ARG[3]
+          -> Signal' clk Int -- rd,   ARG[4]
+          -> Signal' clk (BitVector m)"
+    , "templateD" :
+"// romFile begin
+reg ~TYPO ROM_~SYM[0] [0:~LIT[2]-1];
+
+initial begin
+  $readmemb(~FILE[~LIT[3]],ROM_~SYM[0]);
+end
+
+reg ~TYPO dout_~SYM[1];
+always @(posedge ~CLK[1]) begin : romFile_~COMPNAME_~SYM[2]
+  dout_~SYM[1] <= ROM_~SYM[0][~ARG[4]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// romFile end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.ROM.json b/primitives/CLaSH.Prelude.ROM.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.ROM.json
@@ -0,0 +1,53 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
+    , "type" :
+"asyncRom# :: KnownNat n -- ^ ARG[0]
+           => Vec n a    -- ^ ARG[1]
+           -> Int        -- ^ ARG[2]
+           -> a"
+    , "templateD" :
+"// asyncRom begin
+wire ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];
+
+wire ~TYP[1] romflat_~SYM[1];
+assign romflat_~SYM[1] = ~ARG[1];
+genvar ~SYM[2];
+for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
+  assign ROM_~SYM[0][(~LIT[0]-1)-~SYM[2]] = romflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+end
+
+assign ~RESULT = ROM_~SYM[0][~ARG[2]];
+// asyncRom end"
+    }
+  }
+, { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.rom#"
+    , "type" :
+"rom# :: KnownNat n      -- ARG[0]
+      => SClock clk      -- clk,  ARG[1]
+      -> Vec n a         -- init, ARG[2]
+      -> Signal' clk Int -- rd,   ARG[3]
+      -> Signal' clk a"
+    , "templateD" :
+"// rom begin
+reg ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];
+reg ~TYPO dout_~SYM[1];
+
+reg ~TYP[2] rom_init_~SYM[2];
+integer ~SYM[3];
+initial begin
+  rom_init_~SYM[2] = ~ARG[2];
+  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
+    ROM_~SYM[0][~LIT[0]-1-~SYM[3]] = rom_init_~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+  end
+end
+
+always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[4]
+  dout_~SYM[1] <= ROM_~SYM[0][~ARG[3]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// rom end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.Testbench.json b/primitives/CLaSH.Prelude.Testbench.json
--- a/primitives/CLaSH.Prelude.Testbench.json
+++ b/primitives/CLaSH.Prelude.Testbench.json
@@ -1,22 +1,25 @@
 [ { "BlackBox" :
-    { "name" : "CLaSH.Prelude.Testbench.assert"
+    { "name" : "CLaSH.Prelude.Testbench.assert'"
     , "type" :
 "assert :: (Eq a,Show a) -- (ARG[0],ARG[1])
-        => Signal' t a   -- ^ Checked value (ARG[2])
-        -> Signal' t a   -- ^ Expected value (ARG[3])
-        -> Signal' t b   -- ^ Return valued (ARG[4])
+        => SClock t      -- ^ ARG[2]
+        -> String        -- ^ ARG[3]
+        -> Signal' t a   -- ^ Checked value (ARG[4])
+        -> Signal' t a   -- ^ Expected value (ARG[5])
+        -> Signal' t b   -- ^ Return valued (ARG[6])
         -> Signal' t b"
     , "templateD" :
-"// assert
+"// assert begin
 // pragma translate_off
-always @(posedge ~CLK[2] or negedge ~RST[2]) begin
-  if (~ARG[2] != ~ARG[3]) begin
-    $display(\"expected: %b, actual: %b\", ~ARG[3], ~ARG[2]);
+always @(posedge ~CLK[2] or posedge ~RST[2]) begin
+  if (~ARG[4] != ~ARG[5]) begin
+    $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~ARG[5], ~ARG[4]);
     $stop;
   end
 end
 // pragma translate_on
-assign ~RESULT = ~ARG[4];"
+assign ~RESULT = ~ARG[6];
+// assert end"
     }
   }
 ]
diff --git a/primitives/CLaSH.Signal.Internal.json b/primitives/CLaSH.Signal.Internal.json
--- a/primitives/CLaSH.Signal.Internal.json
+++ b/primitives/CLaSH.Signal.Internal.json
@@ -6,7 +6,7 @@
            -> Signal' clk a  -- ARG[2]
            -> Signal' clk a"
     , "templateD" :
-"// register
+"// register begin
 reg ~SIGD[~SYM[0]][2];
 
 always @(posedge ~CLK[0] or negedge ~RST[0]) begin : register_~COMPNAME_~SYM[1]
@@ -17,7 +17,8 @@
   end
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// register end"
     }
   }
 , { "BlackBox" :
@@ -29,7 +30,7 @@
         -> Signal' clk a    -- ARG[3]
         -> Signal' clk a"
     , "templateD" :
-"// regEn
+"// regEn begin
 reg ~SIGD[~SYM[0]][3];
 
 always @(posedge ~CLK[0] or negedge ~RST[0]) begin : regEn_~COMPNAME_~SYM[1]
@@ -42,7 +43,8 @@
   end
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// regEn end"
     }
   }
 
@@ -68,6 +70,11 @@
   }
 , { "Primitive" :
     { "name"      : "CLaSH.Signal.Internal.traverse#"
+    , "primType"  : "Function"
+    }
+  }
+, { "Primitive" :
+    { "name"      : "CLaSH.Signal.Internal.joinSignal#"
     , "primType"  : "Function"
     }
   }
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -54,27 +54,12 @@
         -> Int         -- ARG[2]
         -> Bit"
     , "templateD" :
-"// index
-wire ~SIGD[~SYM[0]][1];
-wire ~SIGD[~SYM[1]][2];
-
-assign ~SYM[0] = ~ARG[1];
-assign ~SYM[1] = ~ARG[2];
+"// indexBit begin
+wire ~TYP[1] vec_~SYM[0];
+assign vec_~SYM[0] = ~ARG[1];
 
-reg ~TYPO ~SYM[2];
-// pragma translate_off
-always @(*) begin
-  if (~SYM[1] < $low(~SYM[0]) || ~SYM[1] > $high(~SYM[0])) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[1], 0, ~LIT[0]-1);
-    ~SYM[2] = ~ERRORO;
-  end else begin
-  // pragma translate_on
-    ~SYM[2] = ~SYM[0][~SYM[1]];
-  // pragma translate_off
-  end
-end
-assign ~RESULT = ~SYM[2];
-// pragma translate_on"
+assign ~RESULT = vec_~SYM[0][~ARG[2]];
+// indexBit end"
     }
   }
 , { "BlackBox" :
@@ -87,27 +72,16 @@
              -> BitVector n"
     , "templateD" :
 "// replaceBit start
-reg ~TYPO ~SYM[0];
-wire ~TYPO ~SYM[1];
-wire ~TYP[2] ~SYM[2];
-wire ~TYP[3] ~SYM[3];
-
-assign ~SYM[1] = ~ARG[1];
-assign ~SYM[2] = ~ARG[2];
-assign ~SYM[3] = ~ARG[3];
+reg ~TYPO vec_~SYM[0];
+wire ~TYP[3] din_~SYM[1];
+assign din_~SYM[1] = ~ARG[3];
 
-genvar ~SYM[4];
-for (~SYM[4]=0; ~SYM[4] < ~LIT[0]; ~SYM[4] = ~SYM[4] + 1) begin : replace_int_~SYM[5]
-  always @(*) begin
-    if (~SYM[2] == (~LIT[0] - 1 - ~SYM[4])) begin
-      ~SYM[0][~SYM[4]] = ~SYM[3];
-    end else begin
-      ~SYM[0][~SYM[4]] = ~SYM[1][~SYM[4]];
-    end
-  end
+always @(*) begin
+  vec_~SYM[0] = ~ARG[1];
+  vec_~SYM[0][~ARG[2]] = din_~SYM[1];
 end
 
-assign ~RESULT = ~SYM[0];
+assign ~RESULT = vec_~SYM[0];
 // replaceBit end"
     }
   }
@@ -120,15 +94,18 @@
            -> BitVector (m + 1 - n) -- ARG[3]
            -> BitVector (m + 1 + i)"
     , "templateD" :
-"// setSlice
-wire ~SIGD[~SYM[0]][0];
+"// setSlice begin
+reg ~SIGD[~SYM[0]][0];
+wire ~TYP[3] din_~SYM[1];
+assign din_~SYM[1] = ~ARG[3]
 
 always @(*) begin
   ~SYM[0] = ~ARG[0];
-  ~SYM[0][~LIT[1] : ~LIT[2]] = ~ARG[3];
+  ~SYM[0][~LIT[1] : ~LIT[2]] = din_~SYM[1];
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// setSlice end"
     }
   }
 , { "BlackBox" :
@@ -139,10 +116,11 @@
         -> SNat n                -- ARG[2]
         -> BitVector (m + 1 - n)"
     , "templateD" :
-"// slice
+"// slice begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
-assign ~RESULT = ~SYM[1][~LIT[1] : ~LIT[2]];"
+assign ~RESULT = ~SYM[0][~LIT[1] : ~LIT[2]];
+// slice end"
     }
   }
 , { "BlackBox" :
@@ -161,10 +139,11 @@
       => BitVector n -- ARG[1]
       -> Bit"
     , "templateD" :
-"// msb
+"// msb begin
 wire ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
-assign ~RESULT = ~SYM[0][~LIT[0]-1];"
+assign ~RESULT = ~SYM[0][~LIT[0]-1];
+// msb end"
     }
   }
 , { "BlackBox" :
@@ -173,10 +152,11 @@
 "lsb# :: BitVector n -- ARG[0]
       -> Bit"
     , "templateD" :
-"// lsb
+"// lsb begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
-assign ~RESULT = ~SYM[0][0];"
+assign ~RESULT = ~SYM[0][0];
+// msb end"
     }
   }
 , { "BlackBox" :
@@ -278,19 +258,13 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.quot#"
     , "type"      : "quot# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1]) / ~ARG[2]"
+    , "templateE" : "~ARG[0]) / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.rem#"
     , "type"      : "rem# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.BitVector.mod#"
-    , "type"      : "mod# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
@@ -339,20 +313,22 @@
     { "name"      : "CLaSH.Sized.Internal.BitVector.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => BitVector n -> Int -> BitVector n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = ~SYM[0][2*~LIT[0]-1 : ~LIT[0]];"
+assign ~RESULT = ~SYM[0][2*~LIT[0]-1 : ~LIT[0]];
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => BitVector n -> Int -> BitVector n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];
+// rotateR end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Index.json b/primitives/CLaSH.Sized.Internal.Index.json
--- a/primitives/CLaSH.Sized.Internal.Index.json
+++ b/primitives/CLaSH.Sized.Internal.Index.json
@@ -66,20 +66,14 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.quot#"
-    , "type"      : "quot# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] / ~ARG[2]"
+    , "type"      : "quot# :: Index n -> Index n -> Index n"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.rem#"
-    , "type"      : "rem# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.Index.mod#"
-    , "type"      : "mod# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "type"      : "rem# :: Index n -> Index n -> Index n"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -136,7 +136,7 @@
     { "name"      : "CLaSH.Sized.Internal.Signed.div#"
     , "type"      : "div# :: KnownNat n => Signed n -> Signed n -> Signed n"
     , "templateD" :
-"// divInt
+"// divInt begin
 wire ~SIGD[~SYM[0]][1];
 wire ~SIGD[~SYM[1]][1];
 wire ~SIGD[~SYM[2]][2];
@@ -147,14 +147,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[1];
 assign ~SYM[2] = ~ARG[2];
-assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ? ~SYM[0] : ~SYM[0] - ~LIT[0]'sd1;"
+assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ? ~SYM[0] : ~SYM[0] - ~LIT[0]'sd1;
+// divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.mod#"
     , "type"      : "mod# :: KnownNat n => Signed n -> Signed n -> Signed n"
     , "templateD" :
-"// modSigned
+"// modSigned begin
 wire ~SIGD[~SYM[0]][1];
 wire ~SIGD[~SYM[1]][1];
 wire ~SIGD[~SYM[2]][2];
@@ -167,7 +168,8 @@
 assign ~SYM[2] = ~ARG[2];
 assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == ~LIT[0]'sd0 ? ~LIT[0]'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == ~LIT[0]'sd0 ? ~LIT[0]'sd0 : ~SYM[0] + ~ARG[1]);
+// modSigned end"
     }
   }
 , { "BlackBox" :
@@ -216,20 +218,22 @@
     { "name"      : "CLaSH.Sized.Internal.Signed.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => Signed n -> Int -> Signed n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);"
+assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => Signed n -> Int -> Signed n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);"
+assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+// rotateR end"
     }
   }
 , { "BlackBox" :
@@ -237,7 +241,7 @@
     , "type"      : "resize# :: (KnownNat n, KnownNat m) => Signed n -> Signed m"
     , "comment"   : "Back-end should only use this code when the result is smaller than the argument"
     , "templateD" :
-"// resize
+"// resize begin
 if (~LIT[1] < ~LIT[0]) begin
   // truncate, sign preserving
   wire ~SIGD[~SYM[0]][2];
@@ -247,7 +251,7 @@
   // sign-extend
   assign ~RESULT = $signed(~ARG[2]);
 end
-"
+// resize end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -115,19 +115,13 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.quot#"
     , "type"      : "quot# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] / ~ARG[2]"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rem#"
     , "type"      : "rem# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.Unsigned.mod#"
-    , "type"      : "mod# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
@@ -176,20 +170,22 @@
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 wire [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+// rotateR end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -14,44 +14,48 @@
     { "name"      : "CLaSH.Sized.Vector.head"
     , "type"      : "head :: Vec (n + 1) a -> a"
     , "templateD" :
-"// head
+"// head begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1:~SIZE[~TYP[0]]-~SIZE[~TYPO]];"
+assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1:~SIZE[~TYP[0]]-~SIZE[~TYPO]];
+// head end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.tail"
     , "type"      : "tail :: Vec (n + 1) a -> Vec n a"
     , "templateD" :
-"// tail
+"// tail begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1 : 0];"
+assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1 : 0];
+// tail end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.last"
     , "type"      : "Vec (n + 1) a -> a"
     , "templateD" :
-"// last
+"// last begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1:0];"
+assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1:0];
+// last end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.init"
     , "type"      : "Vec (n + 1) a -> Vec n a"
     , "templateD" :
-"// init
+"// init begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 : ~SIZE[~TYPEL[~TYP[0]]]];"
+assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 : ~SIZE[~TYPEL[~TYP[0]]]];
+// init end"
     }
   }
 , { "BlackBox" :
@@ -90,7 +94,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.concat"
     , "type"      : "concat :: Vec n (Vec m a) -> Vec (n * m) a"
-    , "templateD" : "~ARG[0]"
+    , "templateE" : "~ARG[0]"
     }
   }
 , { "BlackBox" :
@@ -170,62 +174,42 @@
     { "name"      : "CLaSH.Sized.Vector.index_int"
     , "type"      : "index_integer :: KnownNat n => Vec n a -> Int -> a"
     , "templateD" :
-"// index_integer start
-wire ~TYPO ~SYM[0] [0:~LIT[0]-1];
-wire ~TYP[1] ~SYM[1];
-assign ~SYM[1] = ~ARG[1];
-genvar ~SYM[3];
-for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3]=~SYM[3]+1) begin : array_~SYM[4]
-  assign ~SYM[0][(~LIT[0]-1)-~SYM[3]] = ~SYM[1][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
-end
-
-wire ~TYP[2] ~SYM[2];
-assign ~SYM[2] = ~ARG[2];
+"// indexVec begin
+wire ~TYPO vec_~SYM[0] [0:~LIT[0]-1];
 
-reg ~TYPO ~SYM[5];
-always @(*) begin
-// pragma translate_off
-  if (~SYM[2] < 0 || ~SYM[2] >= ~LIT[0]) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[2], 0, ~LIT[0]-1);
-    ~SYM[5] = ~ERRORO;
-  end else begin
-  // pragma translate_on
-    ~SYM[5] = ~SYM[0][~SYM[2]];
-  // pragma translate_off
-  end
-// pragma translate_on
+wire ~TYP[1] vecflat_~SYM[1];
+assign vecflat_~SYM[1] = ~ARG[1];
+genvar ~SYM[2];
+for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
+  assign vec_~SYM[0][(~LIT[0]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
 end
-assign ~RESULT = ~SYM[5];
-// index_integer end"
+
+assign ~RESULT = vec_~SYM[0][~ARG[2]];
+// indexVec end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.replace_int"
     , "type"      : "replace_int :: KnownNat n => Vec n a -> Int -> a -> Vec n a"
     , "templateD" :
-"// replace_integer start
-reg ~TYPO ~SYM[0];
-wire ~TYPO ~SYM[1];
-wire ~TYP[2] ~SYM[2];
-wire ~TYP[3] ~SYM[3];
-
-assign ~SYM[1] = ~ARG[1];
-assign ~SYM[2] = ~ARG[2];
-assign ~SYM[3] = ~ARG[3];
+"// replaceVec start
+wire ~TYP[1] vecflat_~SYM[0];
+assign vecflat_~SYM[0] = ~ARG[1];
 
-genvar ~SYM[4];
-for (~SYM[4]=0; ~SYM[4] < ~LIT[0]; ~SYM[4] = ~SYM[4] + 1) begin : replace_int_~SYM[5]
-  always @(*) begin
-    if (~SYM[2] == (~LIT[0] - 1 - ~SYM[4])) begin
-      ~SYM[0][~SYM[4]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = ~SYM[3];
-    end else begin
-      ~SYM[0][~SYM[4]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = ~SYM[1][~SYM[4]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]];
-    end
+reg ~TYP[3] vec_~SYM[1] [0:~LIT[0]-1];
+integer ~SYM[2];
+always @(*) begin
+  for (~SYM[2]=0;~SYM[2]<~LIT[0];~SYM[2]=~SYM[2]+1) begin
+    vec_~SYM[1][~LIT[0]-1-~SYM[2]] = vecflat_~SYM[0][~SYM[2]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]];
   end
+  vec_~SYM[1][~ARG[2]] = ~ARG[3];
 end
 
-assign ~RESULT = ~SYM[0];
-// replace_integer end"
+genvar ~SYM[3];
+for (~SYM[3]=0;~SYM[3]<~LIT[0];~SYM[3]=~SYM[3]+1) begin : vec_~SYM[4]
+  assign ~RESULT[~SYM[3]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = vec_~SYM[1][(~LIT[0]-1)-~SYM[3]];
+end
+// replaceVec end"
     }
   }
 , { "BlackBox" :
@@ -250,14 +234,15 @@
     { "name"      : "CLaSH.Sized.Vector.reverse"
     , "type"      : "reverse :: Vec n a -> Vec n a"
     , "templateD" :
-"// reverse
+"// reverse begin
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
 genvar ~SYM[1];
 for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2]
   assign ~RESULT[(~LENGTH[~TYPO] - 1 - ~SYM[1])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
-end"
+end
+// reverse end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/GHC.Base.json b/primitives/GHC.Base.json
--- a/primitives/GHC.Base.json
+++ b/primitives/GHC.Base.json
@@ -19,7 +19,7 @@
     { "name"      : "GHC.Base.divInt"
     , "type"      : "divInt :: Int -> Int -> Int"
     , "templateD" :
-"// divInt
+"// divInt begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -30,14 +30,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Base.modInt"
     , "type"      : "modInt :: Int -> Int -> Int"
     , "templateD" :
-"// modInt
+"// modInt begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -50,7 +51,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInt end"
     }
   }
 ]
diff --git a/primitives/GHC.CString.json b/primitives/GHC.CString.json
--- a/primitives/GHC.CString.json
+++ b/primitives/GHC.CString.json
@@ -1,6 +1,6 @@
-[ { "Primitive" :
-    { "name"     : "GHC.CString.unpackCString#"
-    , "primType" : "Function"
+[ { "BlackBox" :
+    { "name"      : "GHC.CString.unpackCString#"
+    , "templateE" : "~LIT[0]"
     }
   }
 , { "Primitive" :
diff --git a/primitives/GHC.Classes.json b/primitives/GHC.Classes.json
--- a/primitives/GHC.Classes.json
+++ b/primitives/GHC.Classes.json
@@ -56,7 +56,7 @@
     { "name"      : "GHC.Classes.divInt#"
     , "type"      : "divInt# :: Int# -> Int# -> Int#"
     , "templateD" :
-"// divInt
+"// divInt begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -67,14 +67,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Classes.modInt#"
     , "type"      : "modInt# :: Int# -> Int# -> Int#"
     , "templateD" :
-"// modInt
+"// modInt begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -87,7 +88,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInt end"
     }
   }
 ]
diff --git a/primitives/GHC.Integer.Type.json b/primitives/GHC.Integer.Type.json
--- a/primitives/GHC.Integer.Type.json
+++ b/primitives/GHC.Integer.Type.json
@@ -44,7 +44,7 @@
     { "name"      : "GHC.Integer.Type.divInteger"
     , "type"      : "divInteger :: Integer -> Integer -> Integer"
     , "templateD" :
-"// divInteger
+"// divInteger begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -55,14 +55,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInteger end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.modInteger"
     , "type"      : "modInteger :: Integer -> Integer -> Integer"
     , "templateD" :
-"// modInteger
+"// modInteger begin
 wire ~SIGD[~SYM[0]][0];
 wire ~SIGD[~SYM[1]][0];
 wire ~SIGD[~SYM[2]][1];
@@ -75,7 +76,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInteger end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/GHC.Prim.json b/primitives/GHC.Prim.json
--- a/primitives/GHC.Prim.json
+++ b/primitives/GHC.Prim.json
@@ -86,4 +86,22 @@
     , "templateE" : "~ARG[0]"
     }
   }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
+    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >>> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
+    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] <<< ~ARG[1]"
+    }
+  }
 ]
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -12,7 +12,7 @@
 import           Control.Monad.State                  (State)
 import qualified Data.HashSet                         as HashSet
 import           Data.Maybe                           (catMaybes)
-import           Data.Text.Lazy                       (unpack)
+import           Data.Text.Lazy                       (pack, unpack)
 import           Prelude                              hiding ((<$>))
 import           Text.PrettyPrint.Leijen.Text.Monadic
 
@@ -289,9 +289,10 @@
 
   where
     blit = bits (toBits sz i)
-exprLit _             (BoolLit t)  = if t then "1'b1" else "1'b0"
-exprLit _             (BitLit b)   = "1'b" <> bit_char b
-exprLit _             l            = error $ $(curLoc) ++ "exprLit: " ++ show l
+exprLit _             (BoolLit t)   = if t then "1'b1" else "1'b0"
+exprLit _             (BitLit b)    = "1'b" <> bit_char b
+exprLit _             (StringLit s) = text . pack $ show s
+exprLit _             l             = error $ $(curLoc) ++ "exprLit: " ++ show l
 
 toBits :: Integral a => Int -> a -> [Bit]
 toBits size val = map (\x -> if odd x then H else L)