diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6
+* New features:
+  * Support `clash-prelude-0.10`
+
 ## 0.5.10 *September 21st 2015*
 * New features:
   * Report simulation time in assert messages
diff --git a/README.md b/README.md
--- a/README.md
+++ b/README.md
@@ -11,8 +11,8 @@
 Features of CλaSH:
 
   * Strongly typed (like VHDL), yet with a very high degree of type inference,
-    which enables both safe and fast prototying using consise descriptions (like
-    Verilog)
+    enabling both safe and fast prototying using consise descriptions (like
+    Verilog).
 
   * Interactive REPL: load your designs in an interpreter and easily test all
     your component without needing to setup a test bench.
@@ -21,7 +21,7 @@
     fully parametric by default.
 
   * Synchronous sequential circuit design based on streams of values, called
-    `Signal`s.
+    `Signal`s, lead to natural descriptions of feedback loops.
 
   * Support for multiple clock domains, with type safe clock domain crossing.
 
diff --git a/clash-verilog.cabal b/clash-verilog.cabal
--- a/clash-verilog.cabal
+++ b/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.5.10
+Version:              0.6
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -10,8 +10,8 @@
   Features of CλaSH:
   .
   * Strongly typed (like VHDL), yet with a very high degree of type inference,
-    which enables both safe and fast prototying using consise descriptions (like
-    Verilog)
+    enabling both safe and fast prototying using consise descriptions (like
+    Verilog).
   .
   * Interactive REPL: load your designs in an interpreter and easily test all
     your component without needing to setup a test bench.
@@ -20,7 +20,7 @@
     fully parametric by default.
   .
   * Synchronous sequential circuit design based on streams of values, called
-    @Signal@s.
+    @Signal@s, lead to natural descriptions of feedback loops.
   .
   * Support for multiple clock domains, with type safe clock domain crossing.
   .
@@ -93,8 +93,8 @@
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.12,
-                      clash-prelude           >= 0.9,
+                      clash-lib               >= 0.6,
+                      clash-prelude           >= 0.10,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
                       mtl                     >= 2.1.2,
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -139,11 +139,13 @@
       => BitVector n -- ARG[1]
       -> Bit"
     , "templateD" :
-"// msb begin
+"// msb begin~IF ~LIT[0] ~THEN
 wire ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
 assign ~RESULT = ~SYM[0][~LIT[0]-1];
-// msb end"
+~ELSE
+assign ~RESULT = 1'b0;
+~FI// msb end"
     }
   }
 , { "BlackBox" :
@@ -152,11 +154,13 @@
 "lsb# :: BitVector n -- ARG[0]
       -> Bit"
     , "templateD" :
-"// lsb begin
+"// lsb begin~IF ~SIZE[~TYP[0]] ~THEN
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 assign ~RESULT = ~SYM[0][0];
-// msb end"
+~ELSE
+assign ~RESULT = 1'b0;
+~FI// lsb end"
     }
   }
 , { "BlackBox" :
@@ -197,8 +201,8 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.minBound#"
-    , "type"      : "minBound# :: KnownNat n => BitVector n"
-    , "templateE" : "~LIT[0]'d0"
+    , "type"      : "minBound# :: BitVector n"
+    , "templateE" : "~SIZE[~TYPO]'d0"
     }
   }
 , { "BlackBox" :
@@ -270,7 +274,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.toInteger#"
     , "type"      : "toInteger# :: BitVector n -> Integer"
-    , "templateE" : "$unsigned(~ARG[0])"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
     }
   }
 , { "BlackBox" :
@@ -334,7 +338,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.resize#"
     , "type"      : "resize# :: KnownNat m => BitVector n -> BitVector m"
-    , "templateE" : "$unsigned(~ARG[1])"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[1]);"
     }
   }
 ]
diff --git a/primitives/CLaSH.Sized.Internal.Index.json b/primitives/CLaSH.Sized.Internal.Index.json
--- a/primitives/CLaSH.Sized.Internal.Index.json
+++ b/primitives/CLaSH.Sized.Internal.Index.json
@@ -79,7 +79,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.toInteger#"
     , "type"      : "toInteger# :: Index n -> Integer"
-    , "templateE" : "$unsigned(~ARG[0])"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
     }
   }
 ]
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -134,48 +134,48 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.div#"
-    , "type"      : "div# :: KnownNat n => Signed n -> Signed n -> Signed n"
+    , "type"      : "div# :: Signed n -> Signed n -> Signed n"
     , "templateD" :
 "// divInt begin
-wire ~SIGD[~SYM[0]][1];
-wire ~SIGD[~SYM[1]][1];
-wire ~SIGD[~SYM[2]][2];
+wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~SYM[1]][0];
+wire ~SIGD[~SYM[2]][1];
 
 // divide (rounds towards zero)
-assign ~SYM[0] = ~ARG[1] / ~ARG[2];
+assign ~SYM[0] = ~ARG[0] / ~ARG[1];
 
 // round toward minus infinity
-assign ~SYM[1] = ~ARG[1];
-assign ~SYM[2] = ~ARG[2];
-assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ? ~SYM[0] : ~SYM[0] - ~LIT[0]'sd1;
+assign ~SYM[1] = ~ARG[0];
+assign ~SYM[2] = ~ARG[1];
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;
 // divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.mod#"
-    , "type"      : "mod# :: KnownNat n => Signed n -> Signed n -> Signed n"
+    , "type"      : "mod# :: Signed n -> Signed n -> Signed n"
     , "templateD" :
 "// modSigned begin
-wire ~SIGD[~SYM[0]][1];
-wire ~SIGD[~SYM[1]][1];
-wire ~SIGD[~SYM[2]][2];
+wire ~SIGD[~SYM[0]][0];
+wire ~SIGD[~SYM[1]][0];
+wire ~SIGD[~SYM[2]][1];
 
 // remainder
-assign ~SYM[0] = ~ARG[1] % ~ARG[2];
+assign ~SYM[0] = ~ARG[0] % ~ARG[1];
 
 // modulo
-assign ~SYM[1] = ~ARG[1];
-assign ~SYM[2] = ~ARG[2];
-assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ?
+assign ~SYM[1] = ~ARG[0];
+assign ~SYM[2] = ~ARG[1];
+assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == ~LIT[0]'sd0 ? ~LIT[0]'sd0 : ~SYM[0] + ~ARG[1]);
+                 (~SYM[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~SYM[1]);
 // modSigned end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.toInteger#"
     , "type"      : "toInteger# :: Signed n -> Integer"
-    , "templateE" : "$signed(~ARG[0])"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[0]);"
     }
   }
 , { "BlackBox" :
@@ -259,7 +259,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.truncateB#"
     , "type"      : "truncateB# :: KnownNat m => Signed (n + m) -> Signed m"
-    , "templateE" : "$signed(~ARG[1])"
+    , "templateD" : "assign ~RESULT = $signed(~ARG[1]);"
     }
   }
 ]
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -54,8 +54,8 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.minBound#"
-    , "type"      : "minBound# :: KnownNat n => Unsigned n"
-    , "templateE" : "~LIT[0]'d0"
+    , "type"      : "minBound# :: Unsigned n"
+    , "templateE" : "~SIZE[~TYPO]'d0"
     }
   }
 , { "BlackBox" :
@@ -127,7 +127,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.toInteger#"
     , "type"      : "toInteger# :: Unsigned n -> Integer"
-    , "templateE" : "$unsigned(~ARG[0])"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[0]);"
     }
   }
 , { "BlackBox" :
@@ -191,7 +191,7 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.resize#"
     , "type"      : "resize# :: KnownNat m => Unsigned n -> Unsigned m"
-    , "templateE" : "$unsigned(~ARG[1])"
+    , "templateD" : "assign ~RESULT = $unsigned(~ARG[1]);"
     }
   }
 ]
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -18,7 +18,7 @@
 wire ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1:~SIZE[~TYP[0]]-~SIZE[~TYPO]];
+assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 -: ~SIZE[~TYPO]];
 // head end"
     }
   }
@@ -118,26 +118,6 @@
     }
   }
 , { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Vector.merge"
-    , "type"      : "merge :: Vec n a -> Vec n a -> Vec (n + n) a"
-    , "templateD" :
-"// merge begin
-wire ~SIGD[~SYM[0]][0];
-wire ~SIGD[~SYM[1]][1];
-assign ~SYM[0] = ~ARG[0];
-assign ~SYM[1] = ~ARG[1];
-
-genvar ~SYM[2];
-~GENERATE
-for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYP[0]]; ~SYM[2] = ~SYM[2] + 1) begin : merge_~SYM[3]
-  assign ~RESULT[(2*~SYM[2]+1)*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
-  assign ~RESULT[(2*~SYM[2])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]   = ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
-end
-~ENDGENERATE
-// merge end"
-    }
-  }
-, { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.map"
     , "type"      : "map :: (a -> b) -> Vec n a -> Vec n b"
     , "templateD" :
@@ -158,6 +138,29 @@
     }
   }
 , { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.imap"
+    , "type"      : "imap :: KnownNat n => (Index n -> a -> b) -> Vec n a -> Vec n b"
+    , "templateD" :
+"// imap begin
+wire ~SIGD[~SYM[0]][2];
+assign ~SYM[0] = ~ARG[2];
+
+genvar ~SYM[1];
+~GENERATE
+for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
+  wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~SYM[3];
+  assign ~SYM[3] = ~SYM[1];
+  ~INST 1
+    ~OUTPUT <= ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
+    ~INPUT  <= ~SYM[3]~ ~INDEXTYPE[~LIT[0]]~
+    ~INPUT  <= ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
+  ~INST
+end
+~ENDGENERATE
+// imap end"
+    }
+  }
+, { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.zipWith"
     , "type"      : "zipWith :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c"
     , "templateD" :
@@ -181,6 +184,94 @@
     }
   }
 , { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.foldr"
+    , "type"      : "foldr :: (a -> b -> b) -> b -> Vec n a -> b"
+    , "templateD" :
+"// foldr start~IF ~LENGTH[~TYP[2]] ~THEN
+wire ~TYPO intermediate_~SYM[0] [0:~LENGTH[~TYP[2]]];
+assign intermediate_~SYM[0][~LENGTH[~TYP[2]]] = ~ARG[1];
+
+wire ~TYP[2] xs_~SYM[2];
+assign xs_~SYM[2] = ~ARG[2];
+
+genvar i_~SYM[3];
+~GENERATE
+for (i_~SYM[3]=0; i_~SYM[3] < ~LENGTH[~TYP[2]]; i_~SYM[3]=i_~SYM[3]+1) begin : foldr_loop
+  ~INST 0
+    ~OUTPUT <= intermediate_~SYM[0][i_~SYM[3]]~ ~TYP[1]~
+    ~INPUT <= xs_~SYM[2][(~LENGTH[~TYP[2]]-1-i_~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
+    ~INPUT <= intermediate_~SYM[0][i_~SYM[3]+1]~ ~TYP[1]~
+  ~INST
+end
+~ENDGENERATE
+
+assign ~RESULT = intermediate_~SYM[0][0];
+~ELSE
+assign ~RESULT = ~ARG[1];
+~FI// foldr end"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.fold"
+    , "type"      : "fold :: (a -> a -> a) -> Vec (n+1) a -> a"
+    , "comment"   : "THIS ONLY WORKS FOR POWER OF TWO LENGTH VECTORS"
+    , "templateD" :
+"// fold begin
+// put flat input array into the first half of the intermediate array
+wire ~TYPO intermediate_~SYM[0] [0:(2*~LENGTH[~TYP[1]])-2];
+wire ~TYP[1] vecflat_~SYM[1];
+assign vecflat_~SYM[1] = ~ARG[1];
+genvar ~SYM[2];
+~GENERATE
+for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[1]]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
+  assign intermediate_~SYM[0][(~LENGTH[~TYP[1]]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
+end
+~ENDGENERATE
+
+// calculate the depth of the tree
+function integer log2_~SYM[9];
+  input integer value;
+  begin
+    value = value-1;
+    for (log2_~SYM[9]=0; value>0; log2_~SYM[9]=log2_~SYM[9]+1)
+      value = value>>1;
+  end
+endfunction
+
+localparam levels_~SYM[4] = log2_~SYM[9](~LENGTH[~TYP[1]]);
+
+// given a level and a depth, calculate the corresponding index into the
+// intermediate array
+function integer depth2Index_~SYM[8];
+  input integer levels;
+  input integer depth;
+
+  depth2Index_~SYM[8] = (2 ** levels) - (2 ** depth);
+endfunction
+
+// Create the tree of instantiated components
+genvar d_~SYM[5];
+genvar i_~SYM[6];
+~GENERATE
+if (levels_~SYM[4] != 0) begin : make_tree_~SYM[7]
+  for (d_~SYM[5] = (levels_~SYM[4] - 1); d_~SYM[5] >= 0; d_~SYM[5]=d_~SYM[5]-1) begin : tree_depth
+    for (i_~SYM[6] = 0; i_~SYM[6] < (2**d_~SYM[5]); i_~SYM[6] = i_~SYM[6]+1) begin : tree_depth_loop
+        ~INST 0
+          ~OUTPUT <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+1)+i_~SYM[6]]~ ~TYPO~
+          ~INPUT  <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])]~ ~TYPO~
+          ~INPUT  <= intermediate_~SYM[0][depth2Index_~SYM[8](levels_~SYM[4]+1,d_~SYM[5]+2)+(2*i_~SYM[6])+1]~ ~TYPO~
+        ~INST
+    end
+  end
+end
+~ENDGENERATE
+
+// The last element of the intermediate array holds the result
+assign ~RESULT = intermediate_~SYM[0][(2*~LENGTH[~TYP[1]])-2];
+// fold end"
+    }
+  }
+, { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.index_int"
     , "type"      : "index_integer :: KnownNat n => Vec n a -> Int -> a"
     , "templateD" :
@@ -242,6 +333,26 @@
     { "name"      : "CLaSH.Sized.Vector.replicate"
     , "type"      : "replicate :: SNat n -> a -> Vec n a"
     , "templateE" : "{~LIT[0] {~ARG[1]}}"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "CLaSH.Sized.Vector.transpose"
+    , "type"      : "transpose :: KnownNat n => Vec m (Vec n a) -> Vec n (Vec m a)"
+    , "templateD" :
+"// transpose begin
+wire ~SIGD[~SYM[0]][1];
+assign ~SYM[0] = ~ARG[1];
+
+genvar ~SYM[1];
+genvar ~SYM[2];
+~GENERATE
+for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYP[1]]; ~SYM[1] = ~SYM[1] + 1) begin : transpose_outer_~SYM[3]
+  for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : transpose_inner_~SYM[4]
+    assign ~RESULT[((~SYM[2]*~SIZE[~TYPEL[~TYPO]])+(~SYM[1]*~SIZE[~TYPEL[~TYPEL[~TYPO]]]))+:~SIZE[~TYPEL[~TYPEL[~TYPO]]]] = ~SYM[0][((~SYM[1]*~SIZE[~TYPEL[~TYP[1]]])+(~SYM[2]*~SIZE[~TYPEL[~TYPEL[~TYPO]]]))+:~SIZE[~TYPEL[~TYPEL[~TYPO]]]];
+  end
+end
+~ENDGENERATE
+// transpose end"
     }
   }
 , { "BlackBox" :
diff --git a/src/CLaSH/Backend/Verilog.hs b/src/CLaSH/Backend/Verilog.hs
--- a/src/CLaSH/Backend/Verilog.hs
+++ b/src/CLaSH/Backend/Verilog.hs
@@ -236,6 +236,9 @@
 
 expr_ _ (Identifier id_ (Just _))                      = text id_
 
+expr_ _ (DataCon (Vector 0 _) _ _) =
+  error $ $(curLoc) ++ "Verilog: Trying to create a Nil vector."
+
 expr_ _ (DataCon (Vector 1 _) _ [e]) = expr_ False e
 expr_ _ e@(DataCon (Vector _ _) _ es@[_,_]) =
   case vectorChain e of
@@ -313,7 +316,15 @@
 vectorChain _                                       = Nothing
 
 exprLit :: Maybe (HWType,Size) -> Literal -> VerilogM Doc
-exprLit Nothing         (NumLit i) = integer i
+exprLit Nothing (NumLit i) =
+  let integerLow  = -2^(31 :: Integer) :: Integer
+      integerHigh = 2^(31 :: Integer) - 1 :: Integer
+      i' = if i < integerLow
+              then integerLow
+              else if i > integerHigh
+                   then integerHigh
+                   else i
+  in  parenIf (i' < 0) (integer i')
 exprLit (Just (hty,sz)) (NumLit i) = case hty of
                                        Unsigned _   -> int sz <> "'d" <> integer i
                                        Index _      -> int (typeSize hty) <> "'d" <> integer i