clash-systemverilog 0.6 → 0.6.1

raw patch · 6 files changed

+85/−18 lines, 6 filesdep ~clash-preludePVP: major bump suggested

API removals or changes: PVP suggests a major version bump

Dependency ranges changed: clash-prelude

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• clash-systemverilog.cabal +3/−2
• primitives/CLaSH.Promoted.Nat.Unsafe.json +7/−0
• primitives/CLaSH.Promoted.Nat.json +24/−0
• primitives/CLaSH.Sized.Vector.json +42/−12
• src/CLaSH/Backend/SystemVerilog.hs +5/−4

@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.6.1 *October 16th 2015*+* New features:+  * Support for `clash-prelude` 0.10.1+ ## 0.6 *October 3rd 2015* * New features:   * Support `clash-prelude-0.10`

@@ -1,5 +1,5 @@ Name:                 clash-systemverilog-Version:              0.6+Version:              0.6.1 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -51,6 +51,7 @@                       primitives/CLaSH.Prelude.ROM.File.json                       primitives/CLaSH.Prelude.Testbench.json                       primitives/CLaSH.Promoted.Nat.json+                      primitives/CLaSH.Promoted.Nat.Unsafe.json                       primitives/CLaSH.Promoted.Symbol.json                       primitives/CLaSH.Signal.Bundle.json                       primitives/CLaSH.Signal.Explicit.json@@ -94,7 +95,7 @@    Build-depends:      base                    >= 4.6.0.1 && < 5,                       clash-lib               >= 0.6,-                      clash-prelude           >= 0.10,+                      clash-prelude           >= 0.10.1,                       fgl                     >= 5.4.2.4,                       lens                    >= 3.9.2,                       mtl                     >= 2.1.2,

@@ -0,0 +1,7 @@+[ { "BlackBox" :+    { "name"      : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat"+    , "type"      : "CLaSH.Promoted.Nat.Unsafe.unsafeSNat :: Integer -> SNat k"+    , "templateE" : "~LIT[0]"+    }+  }+]

@@ -10,4 +10,28 @@     , "templateE" : "~LIT[0]"     }   }+, { "BlackBox" :+    { "name"      : "CLaSH.Promoted.Nat.addSNat"+    , "type"      : "CLaSH.Promoted.Nat.addSNat :: SNat a -> SNat b -> SNat (a + b)"+    , "templateE" : "~LIT[0] + ~LIT[1]"+    }+  }+, { "BlackBox" :+    { "name"      : "CLaSH.Promoted.Nat.subSNat"+    , "type"      : "CLaSH.Promoted.Nat.subSNat :: SNat a -> SNat b -> SNat (a - b)"+    , "templateE" : "~LIT[0] - ~LIT[1]"+    }+  }+, { "BlackBox" :+    { "name"      : "CLaSH.Promoted.Nat.mulSNat"+    , "type"      : "CLaSH.Promoted.Nat.mulSNat :: SNat a -> SNat b -> SNat (a * b)"+    , "templateE" : "~LIT[0] * ~LIT[1]"+    }+  }+, { "BlackBox" :+    { "name"      : "CLaSH.Promoted.Nat.powSNat"+    , "type"      : "CLaSH.Promoted.Nat.powSNat :: SNat a -> SNat b -> SNat (a ^ b)"+    , "templateE" : "~LIT[0] ** ~LIT[1]"+    }+  } ]

@@ -1,16 +1,4 @@ [ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.eq#"-    , "type"      : "eq# :: Eq a => Vec n a -> Vec n a -> Bool"-    , "templateE" : "~ARG[0] == ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.neq#"-    , "type"      : "neq# :: Eq a => Vec n a -> Vec n a -> Bool"-    , "templateE" : "~ARG[0] != ~ARG[1]"-    }-  }-, { "BlackBox" :     { "name"      : "CLaSH.Sized.Vector.head"     , "type"      : "head :: Vec (n + 1) a -> a"     , "templateD" :@@ -424,6 +412,48 @@   end ~ENDGENERATE // unconcatBitVector end"+    }+  }+, { "BlackBox" :+    { "name"      : "CLaSH.Sized.Vector.rotateLeftS"+    , "type"      : "rotateLeftS :: KnownNat n => Vec n a -> SNat d -> Vec n a"+    , "templateD" :+"// rotateLeftS begin+~SIGD[~SYM[1]][1];+localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];++assign ~SYM[1] = ~ARG[1];++~GENERATE+if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]+  assign ~RESULT = ~SYM[1];+end else begin : do_shift_~SYM[4]+  assign ~RESULT[0:~LIT[0]-shift_amount_~SYM[2]-1] = ~SYM[1][shift_amount_~SYM[2]:~LIT[0]-1];+  assign ~RESULT[shift_amount_~SYM[2]:~LIT[0]-1] = ~SYM[1][0 to shift_amount_~SYM[2]-1];+end+~ENDGENERATE+// rotateLeftS end"+    }+  }+, { "BlackBox" :+    { "name"      : "CLaSH.Sized.Vector.rotateRightS"+    , "type"      : "rotateRightS :: KnownNat n => Vec n a -> SNat d -> Vec n a"+    , "templateD" :+"// rotateRightS begin+~SIGD[~SYM[1]][1];+localparam shift_amount_~SYM[2] = ~LIT[2] % ~LIT[0];++assign ~SYM[1] = ~ARG[1];++~GENERATE+if (shift_amount_~SYM[2] == 0) begin : no_shift_~SYM[3]+  assign ~RESULT = ~SYM[1];+end else begin : do_shift_~SYM[4]+  assign ~RESULT[0:shift_amount_~SYM[2]-1] = ~SYM[1][~LIT[0]-shift_amount_~SYM[2]:~LIT[0]-1];+  assign ~RESULT[shift_amount_~SYM[2]:~LIT[0]-1] = ~SYM[1][0:~LIT[0]-shift_amount_~SYM[2]-1];+end+~ENDGENERATE+// rotateRightS end"     }   } ]

@@ -205,6 +205,7 @@     (Signed n)    -> "logic signed" <+> brackets (int (n-1) <> colon <> int 0)     (Clock _ _)   -> "logic"     (Reset _ _)   -> "logic"+    String        -> "string"     _             -> "logic" <+> brackets (int (typeSize t -1) <> colon <> int 0)  sigDecl :: SystemVerilogM Doc -> HWType -> SystemVerilogM Doc@@ -270,7 +271,7 @@ inst_ (Assignment id_ e) = fmap Just $   "assign" <+> text id_ <+> equals <+> expr_ False e <> semi -inst_ (CondAssignment id_ _ scrut [(Just (Literal _ (BoolLit b)), l),(_,r)]) = fmap Just $+inst_ (CondAssignment id_ _ scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $     "always_comb begin" <$>     indent 2 ("if" <> parens (expr_ True scrut) <$>                 (indent 2 $ text id_ <+> equals <+> expr_ False t <> semi) <$>@@ -280,18 +281,18 @@   where     (t,f) = if b then (l,r) else (r,l) -inst_ (CondAssignment id_ _ scrut es) = fmap Just $+inst_ (CondAssignment id_ _ scrut scrutTy es) = fmap Just $     "always_comb begin" <$>     indent 2 ("case" <> parens (expr_ True scrut) <$>                 (indent 2 $ vcat $ punctuate semi (conds es)) <> semi <$>               "endcase") <$>     "end"   where-    conds :: [(Maybe Expr,Expr)] -> SystemVerilogM [Doc]+    conds :: [(Maybe Literal,Expr)] -> SystemVerilogM [Doc]     conds []                = return []     conds [(_,e)]           = ("default" <+> colon <+> text id_ <+> equals <+> expr_ False e) <:> return []     conds ((Nothing,e):_)   = ("default" <+> colon <+> text id_ <+> equals <+> expr_ False e) <:> return []-    conds ((Just c ,e):es') = (expr_ True c <+> colon <+> text id_ <+> equals <+> expr_ False e) <:> conds es'+    conds ((Just c ,e):es') = (exprLit (Just (scrutTy,conSize scrutTy)) c <+> colon <+> text id_ <+> equals <+> expr_ False e) <:> conds es'  inst_ (InstDecl nm lbl pms) = fmap Just $     text nm <+> text lbl <$$> pms' <> semi