diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.6.9 *August 18th 2016*
+* Fixes bugs:
+  * Fix primitives for {Signed,Unsigned} rotateL# and rotateR# [#169](https://github.com/clash-lang/clash-compiler/issues/169)
+
 ## 0.6.8 *August 3rd 2016*
 * Fixes bugs:
   * Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger [#164](https://github.com/clash-lang/clash-compiler/issues/164)
diff --git a/clash-systemverilog.cabal b/clash-systemverilog.cabal
--- a/clash-systemverilog.cabal
+++ b/clash-systemverilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-systemverilog
-Version:              0.6.8
+Version:              0.6.9
 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -221,7 +221,7 @@
 "// rotateL begin
 logic [2*~LIT[0]-1:0] ~GENSYM[s][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]);
 // rotateL end"
     }
   }
@@ -232,7 +232,7 @@
 "// rotateR begin
 logic [2*~LIT[0]-1:0] ~GENSYM[s][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]);
 // rotateR end"
     }
   }
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -173,7 +173,7 @@
 "// rotateL begin
 logic [2*~LIT[0]-1:0] ~GENSYM[u][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];
 // rotateL end"
     }
   }
@@ -184,7 +184,7 @@
 "// rotateR begin
 logic [2*~LIT[0]-1:0] ~GENSYM[u][0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];
 // rotateR end"
     }
   }