clash-systemverilog 0.6.4 → 0.6.5

raw patch · 6 files changed

+50/−9 lines, 6 files

Files

• CHANGELOG.md +8/−1
• clash-systemverilog.cabal +4/−2
• primitives/CLaSH.Prelude.BlockRam.json +14/−5
• primitives/CLaSH.Transformations.json +7/−0
• primitives/Debug.Trace.json +7/−0
• src/CLaSH/Backend/SystemVerilog.hs +10/−1

@@ -1,6 +1,13 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package -## 0.6.4 *January 13th 2015*+## 0.6.5 *January 29th 2016*+* New features:+  * Support clash-lib-0.6.9+  * Support for `Debug.Trace.trace`, thanks to @ggreif+* Fixes bugs:+  * BlockRAM elements must be bit vectors [#113](https://github.com/clash-lang/clash-compiler/issues/113)++## 0.6.4 *January 13th 2016* * New features:   * Support for Haskell's: `Char`, `Int8`, `Int16`, `Int32`, `Int64`, `Word`, `Word8`, `Word16`, `Word32`, `Word64`.   * Int/Word/Integer bitwidth for generated SystemVerilog is configurable using the `-clash-intwidth=N` flag, where `N` can be either 32 or 64.

@@ -1,5 +1,5 @@ Name:                 clash-systemverilog-Version:              0.6.4+Version:              0.6.5 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -34,7 +34,7 @@ License-file:         LICENSE Author:               Christiaan Baaij Maintainer:           Christiaan Baaij <christiaan.baaij@gmail.com>-Copyright:            Copyright © 2015 University of Twente+Copyright:            Copyright © 2015-2016 University of Twente Category:             Hardware Build-type:           Simple @@ -61,7 +61,9 @@                       primitives/CLaSH.Sized.Internal.Signed.json                       primitives/CLaSH.Sized.Internal.Unsigned.json                       primitives/CLaSH.Sized.Vector.json+                      primitives/CLaSH.Transformations.json                       primitives/Control.Exception.Base.json+                      primitives/Debug.Trace.json                       primitives/GHC.Base.json                       primitives/GHC.Classes.json                       primitives/GHC.CString.json

@@ -11,21 +11,30 @@            -> Signal' clk a"     , "templateD" : "// blockRam begin-~SIGD[RAM_~SYM[0]][2];-~SIGD[dout_~SYM[1]][6];+typedef logic [~SIZE[~TYPO]-1:0] RAM_array_~SYM[4] [0:~LENGTH[~TYP[2]]-1];+RAM_array_~SYM[4] RAM_~SYM[0];+logic [~SIZE[~TYPO]-1:0] dout_~SYM[1]; +function RAM_array_~SYM[4] init_to_bv_~SYM[2];+  input ~SIGD[value][2];+  begin+    for (int i_~SYM[3]=0; i_~SYM[3]<~LENGTH[~TYP[2]]; i_~SYM[3]=i_~SYM[3]+1)+      init_to_bv_~SYM[2][i_~SYM[3]] = ~TOBV[value[ i_~SYM[3] ]][6];+  end+endfunction+ initial begin-  ~SYM[0] = ~LIT[3];+  RAM_~SYM[0] = init_to_bv_~SYM[2](~LIT[2]); end  always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[3]   if (~ARG[5]) begin-    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];+    RAM_~SYM[0][~ARG[3]] <= ~TOBV[~ARG[6]][6];   end   dout_~SYM[1] <= RAM_~SYM[0][~ARG[4]]; end -assign ~RESULT = dout_~SYM[1];+assign ~RESULT = ~FROMBV[dout_~SYM[1]][6]; // blockRam end"     }   }

@@ -0,0 +1,7 @@+[ { "BlackBox" :+    { "name"      : "CLaSH.Transformations.removedArg"+    , "type"      : "removedArg :: a"+    , "templateE" : "~ERRORO"+    }+  }+]

@@ -0,0 +1,7 @@+[ { "BlackBox" :+    { "name"      : "Debug.Trace.trace"+    , "type"      : "trace :: String -> a -> a"+    , "templateE" : "~ARG[1]"+    }+  }+]

@@ -1,3 +1,11 @@+{-|+  Copyright   :  (C) 2015-2016, University of Twente+  License     :  BSD2 (see the file LICENSE)+  Maintainer  :  Christiaan Baaij <christiaan.baaij@gmail.com>++  Generate SystemVerilog for assorted Netlist datatypes+-}+ {-# LANGUAGE CPP               #-} {-# LANGUAGE OverloadedStrings #-} {-# LANGUAGE RecursiveDo       #-}@@ -5,7 +13,6 @@ {-# LANGUAGE TupleSections     #-} {-# LANGUAGE ViewPatterns      #-} --- | Generate SystemVerilog for assorted Netlist datatypes module CLaSH.Backend.SystemVerilog (SystemVerilogState) where  import qualified Control.Applicative                  as A@@ -77,6 +84,8 @@   inst            = inst_   expr            = expr_   iwWidth         = use intWidth+  toBV hty id_    = verilogTypeMark hty <> "_to_lv" <> parens (text id_)+  fromBV hty id_  = fromSLV hty id_ (typeSize hty - 1) 0  type SystemVerilogM a = State SystemVerilogState a