clash-systemverilog 0.6.2 → 0.6.3
raw patch · 3 files changed
+24/−19 lines, 3 filesPVP ok
version bump matches the API change (PVP)
API changes (from Hackage documentation)
Files
- CHANGELOG.md +4/−0
- clash-systemverilog.cabal +1/−1
- src/CLaSH/Backend/SystemVerilog.hs +19/−18
CHANGELOG.md view
@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.6.3 *November 17th 2015*+* Fixes bugs:+ * Integer literals missing "32'sd" prefix when used in assignments+ ## 0.6.2 *October 21st 2015* * New features: * Support `clash-prelude` 0.10.2
clash-systemverilog.cabal view
@@ -1,5 +1,5 @@ Name: clash-systemverilog-Version: 0.6.2+Version: 0.6.3 Synopsis: CAES Language for Synchronous Hardware - SystemVerilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that
src/CLaSH/Backend/SystemVerilog.hs view
@@ -411,25 +411,26 @@ vectorChain _ = Nothing exprLit :: Maybe (HWType,Size) -> Literal -> SystemVerilogM Doc-exprLit Nothing (NumLit i) =- let integerLow = -2^(31 :: Integer) :: Integer- integerHigh = 2^(31 :: Integer) - 1 :: Integer- i' = if i < integerLow- then integerLow- else if i > integerHigh- then integerHigh- else i- in parenIf (i' < 0) (integer i')-exprLit (Just (hty,sz)) (NumLit i) = case hty of- Unsigned _ -> int sz <> "'d" <> integer i- Signed _- | i < 0 -> "-" <> int sz <> "'sd" <> integer (abs i)- | otherwise -> int sz <> "'sd" <> integer i- Integer- | i < 0 -> "-" <> int 32 <> "'sd" <> integer (abs i)- | otherwise -> int 32 <> "'sd" <> integer i- _ -> int sz <> "'b" <> blit+exprLit Nothing (NumLit i) = integer i +exprLit (Just (hty,sz)) (NumLit i) = case hty of+ Unsigned _ -> int sz <> "'d" <> integer i+ Index _ -> int (typeSize hty) <> "'d" <> integer i+ Signed _+ | i < 0 -> "-" <> int sz <> "'sd" <> integer (abs i)+ | otherwise -> int sz <> "'sd" <> integer i+ Integer ->+ let integerLow = -2^(31 :: Integer) :: Integer+ integerHigh = 2^(31 :: Integer) - 1 :: Integer+ i' = if i < integerLow+ then integerLow+ else if i > integerHigh+ then integerHigh+ else i+ in if (i' < 0)+ then "-" <> int 32 <> "'sd" <> integer (abs i')+ else int 32 <> "'sd" <> integer i+ _ -> int sz <> "'b" <> blit where blit = bits (toBits sz i) exprLit _ (BoolLit t) = if t then "1'b1" else "1'b0"