diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,10 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.8 *September 7th 2015*
+* Fixes bugs:
+  * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)
+  * rem and quot on Signed are broken [#73](https://github.com/clash-lang/clash-compiler/issues/73)
+
 ## 0.5.7 *June 26th 2015*
 * Fixes bug:
   * Incorrect primitive for `CLaSH.Prelude.Testbench.assert'`
diff --git a/README.md b/README.md
--- a/README.md
+++ b/README.md
@@ -1,5 +1,29 @@
-# Support
-For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)
+# `clash-systemverilog` - SystemVerilog backend for the CλaSH compiler
 
-# `clash-systemverilog`
   * See the LICENSE file for license and copyright details
+
+# CλaSH - A functional hardware description language
+CλaSH (pronounced ‘clash’) is a functional hardware description language that
+borrows both its syntax and semantics from the functional programming language
+Haskell. The CλaSH compiler transforms these high-level descriptions to
+low-level synthesizable VHDL, Verilog, or SystemVerilog.
+
+Features of CλaSH:
+
+  * Strongly typed (like VHDL), yet with a very high degree of type inference,
+    which enables both safe and fast prototying using consise descriptions (like
+    Verilog)
+
+  * Interactive REPL: load your designs in an interpreter and easily test all
+    your component without needing to setup a test bench.
+
+  * Higher-order functions, with type inference, result in designs that are
+    fully parametric by default.
+
+  * Synchronous sequential circuit design based on streams of values, called
+    `Signal`s.
+
+  * Support for multiple clock domains, with type safe clock domain crossing.
+
+# Support
+For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)
diff --git a/clash-systemverilog.cabal b/clash-systemverilog.cabal
--- a/clash-systemverilog.cabal
+++ b/clash-systemverilog.cabal
@@ -1,14 +1,30 @@
 Name:                 clash-systemverilog
-Version:              0.5.7
+Version:              0.5.8
 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
   borrows both its syntax and semantics from the functional programming language
-  Haskell. The merits of using a functional language to describe hardware comes
-  from the fact that combinational circuits can be directly modelled as
-  mathematical functions and that functional languages lend themselves very well
-  at describing and (de-)composing mathematical functions.
+  Haskell. The CλaSH compiler transforms these high-level descriptions to
+  low-level synthesizable VHDL, Verilog, or SystemVerilog.
   .
+  Features of CλaSH:
+  .
+  * Strongly typed (like VHDL), yet with a very high degree of type inference,
+    which enables both safe and fast prototying using consise descriptions (like
+    Verilog)
+  .
+  * Interactive REPL: load your designs in an interpreter and easily test all
+    your component without needing to setup a test bench.
+  .
+  * Higher-order functions, with type inference, result in designs that are
+    fully parametric by default.
+  .
+  * Synchronous sequential circuit design based on streams of values, called
+    @Signal@s.
+  .
+  * Support for multiple clock domains, with type safe clock domain crossing.
+  .
+  .
   This package provides:
   .
   * SystemVerilog Backend
@@ -68,6 +84,13 @@
   default-language:   Haskell2010
   ghc-options:        -Wall
   CPP-Options:        -DCABAL
+
+  other-extensions:   CPP
+                      OverloadedStrings
+                      RecursiveDo
+                      TemplateHaskell
+                      TupleSections
+                      ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
                       clash-lib               >= 0.5.8,
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -1,5 +1,5 @@
 [ { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.Internal.Signed.size#"
+    { "name"      : "CLaSH.Sized.Internal.Signed.size#"
     , "type"      : "size# :: KnownNat n => Signed n -> Int"
     , "templateE" : "~LIT[0]"
     }
@@ -122,14 +122,14 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.quot#"
-    , "type"      : "quot# :: KnownNat n => Signed n -> Signed n -> Signed n"
-    , "templateE" : "~ARG[1] / ~ARG[2]"
+    , "type"      : "quot# :: Signed n -> Signed n -> Signed n"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.rem#"
-    , "type"      : "rem# :: KnownNat n => Signed n -> Signed n -> Signed n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "type"      : "rem# :: Signed n -> Signed n -> Signed n"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :