diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,11 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.5.7 *June 26th 2015* +* Fixes bug: + * Incorrect primitive for `CLaSH.Prelude.Testbench.assert'` + * Incorrect primitive for `CLaSH.Sized.Vec.index_int` + * Sometimes created incorrect nested `generate` statements + ## 0.5.6 *June 25th 2015* * New features: * Support `clash-prelude-0.9` diff --git a/clash-systemverilog.cabal b/clash-systemverilog.cabal --- a/clash-systemverilog.cabal +++ b/clash-systemverilog.cabal @@ -1,5 +1,5 @@ Name: clash-systemverilog -Version: 0.5.6 +Version: 0.5.7 Synopsis: CAES Language for Synchronous Hardware - SystemVerilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that @@ -70,7 +70,7 @@ CPP-Options: -DCABAL Build-depends: base >= 4.6.0.1 && < 5, - clash-lib >= 0.5.7, + clash-lib >= 0.5.8, clash-prelude >= 0.9, fgl >= 5.4.2.4, lens >= 3.9.2, diff --git a/primitives/CLaSH.Prelude.Testbench.json b/primitives/CLaSH.Prelude.Testbench.json --- a/primitives/CLaSH.Prelude.Testbench.json +++ b/primitives/CLaSH.Prelude.Testbench.json @@ -1,5 +1,5 @@ [ { "BlackBox" : - { "name" : "CLaSH.Prelude.Testbench.assert" + { "name" : "CLaSH.Prelude.Testbench.assert'" , "type" : "assert :: (Eq a,Show a) -- (ARG[0],ARG[1]) => SClock t -- ^ ARG[2] @@ -13,7 +13,7 @@ // pragma translate_off always @(posedge ~CLK[2] or posedge ~RST[2]) begin if (~ARG[4] != ~ARG[5]) begin - $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~TYPM[3]_to_lv(~ARG[5]), ~TYPM[2]_to_lv(~ARG[4])); + $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~TYPM[5]_to_lv(~ARG[5]), ~TYPM[4]_to_lv(~ARG[4])); $stop; end end diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json --- a/primitives/CLaSH.Sized.Internal.Signed.json +++ b/primitives/CLaSH.Sized.Internal.Signed.json @@ -242,7 +242,7 @@ , "comment" : "Back-end should only use this code when the result is smaller than the argument" , "templateD" : "// resize begin -generate +~GENERATE if (~LIT[1] < ~LIT[0]) begin // truncate, sign preserving ~SIGD[~SYM[0]][2]; @@ -252,7 +252,7 @@ // sign-extend assign ~RESULT = $signed(~ARG[2]); end -endgenerate +~ENDGENERATE // resize end" } } diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json --- a/primitives/CLaSH.Sized.Vector.json +++ b/primitives/CLaSH.Sized.Vector.json @@ -73,11 +73,11 @@ assign ~SYM[0] = ~ARG[4]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1]=0; ~SYM[1] < ~LIT[3]; ~SYM[1] = ~SYM[1] + 1) begin : select_~SYM[2] assign ~RESULT[~SYM[1]] = ~SYM[0][~LIT[1] + (~LIT[2] * ~SYM[1])]; end -endgenerate +~ENDGENERATE // select end" } } @@ -93,7 +93,7 @@ assign ~SYM[1] = ~ARG[1]; genvar ~SYM[2]; -generate +~GENERATE for (~SYM[2]=0; ~SYM[2] < $size(~RESULT); ~SYM[2] = ~SYM[2] + 1) begin : append_~SYM[3] if (~SYM[2] < $size(~SYM[0])) begin assign ~RESULT[~SYM[2]] = ~SYM[0][~SYM[2]]; @@ -101,7 +101,7 @@ assign ~RESULT[~SYM[2]] = ~SYM[1][~SYM[2]-$size(~SYM[0])]; end end -endgenerate +~ENDGENERATE // (++) end" } } @@ -114,11 +114,11 @@ assign ~SYM[0] = ~ARG[0]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1]=0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : concat_~SYM[2] assign ~RESULT[(~SYM[5] * $size(~SYM[0][0])) : ((~SYM[5] * $size(~SYM[0][0])) + $high(~SYM[0][0]))] = ~SYM[0][~SYM[1]]; end -endgenerate +~ENDGENERATE // concat end" } } @@ -149,11 +149,11 @@ assign ~SYM[0] = ~ARG[2]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1] = 0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : unconcat_~SYM[2] assign ~RESULT[~SYM[1]] = ~SYM[0][(~SYM[1] * ~LIT[1]) : ((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1)]; end -endgenerate +~ENDGENERATE // unconcat end" } } @@ -168,12 +168,12 @@ assign ~SYM[1] = ~ARG[1]; genvar ~SYM[2]; -generate +~GENERATE for (~SYM[2] = 0; ~SYM[2] < $size(~SYM[0]); ~SYM[2] = ~SYM[2] + 1) begin : merge_~SYM[3] assign ~RESULT[2*~SYM[2]] = ~SYM[0][~SYM[2]]; assign ~RESULT[2*~SYM[2]+1] = ~SYM[1][~SYM[2]]; end -endgenerate +~ENDGENERATE // merge end" } } @@ -186,14 +186,14 @@ assign ~SYM[0] = ~ARG[1]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1]=0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2] ~INST 0 ~OUTPUT <= ~RESULT[~SYM[1]]~ ~TYPEL[~TYPO]~ ~INPUT <= ~SYM[0][~SYM[1]]~ ~TYPEL[~TYP[1]]~ ~INST end -endgenerate +~ENDGENERATE // map end" } } @@ -208,7 +208,7 @@ assign ~SYM[1] = ~ARG[2]; genvar ~SYM[2]; -generate +~GENERATE for (~SYM[2] = 0; ~SYM[2] < $size(~RESULT); ~SYM[2] = ~SYM[2] + 1) begin : zipWith_~SYM[2] ~INST 0 ~OUTPUT <= ~RESULT[~SYM[2]]~ ~TYPEL[~TYPO]~ @@ -216,7 +216,7 @@ ~INPUT <= ~SYM[1][~SYM[2]]~ ~TYPEL[~TYP[2]]~ ~INST end -endgenerate +~ENDGENERATE // zipWith end" } } @@ -226,7 +226,7 @@ , "templateD" : "// indexVec begin ~SIGD[vec_~SYM[0]][1]; -assign vec_SYM[0] = ~ARG[1]; +assign vec_~SYM[0] = ~ARG[1]; assign ~RESULT = vec_~SYM[0][~ARG[2]]; // indexVec end" @@ -277,11 +277,11 @@ assign ~SYM[0] = ~ARG[0]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1] = 0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2] assign ~RESULT[$high(~SYM[0]) - ~SYM[1]] = ~SYM[0][~SYM[1]]; end -endgenerate +~ENDGENERATE // reverse end" } } @@ -303,11 +303,11 @@ assign ~SYM[0] = ~ARG[1]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1] = 0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : concatBitVector_~SYM[2] assign ~RESULT[((~SYM[1] * ~LIT[0]) + ~LIT[0] - 1) : (~SYM[1] * ~LIT[0])] = ~SYM[0][$high(~SYM[0]) - ~SYM[1]]; end -endgenerate +~ENDGENERATE // concatBitVector end" } } @@ -323,11 +323,11 @@ assign ~SYM[0] = ~ARG[2]; genvar ~SYM[1]; -generate +~GENERATE for (~SYM[1] = 0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : unconcatBitVector_~SYM[2] assign ~RESULT[$high(~RESULT) - ~SYM[1]] = ~SYM[0][((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1) : (~SYM[1] * ~LIT[1])]; end -endgenerate +~ENDGENERATE // unconcatBitVector end" } } diff --git a/src/CLaSH/Backend/SystemVerilog.hs b/src/CLaSH/Backend/SystemVerilog.hs --- a/src/CLaSH/Backend/SystemVerilog.hs +++ b/src/CLaSH/Backend/SystemVerilog.hs @@ -41,12 +41,13 @@ { _tyCache :: HashSet HWType -- ^ Previously encountered HWTypes , _tyCount :: Int -- ^ Product type counter , _nameCache :: HashMap HWType Doc -- ^ Cache for previously generated product type names + , _genDepth :: Int -- ^ Depth of current generative block } makeLenses ''SystemVerilogState instance Backend SystemVerilogState where - initBackend = SystemVerilogState HashSet.empty 0 HashMap.empty + initBackend = SystemVerilogState HashSet.empty 0 HashMap.empty 0 #ifdef CABAL primDir = const (Paths_clash_systemverilog.getDataFileName "primitives") #else @@ -62,6 +63,16 @@ hdlTypeErrValue = verilogTypeErrValue hdlTypeMark = verilogTypeMark hdlSig t ty = sigDecl (text t) ty + genStmt True = do cnt <- use genDepth + genDepth += 1 + if cnt > 0 + then empty + else "generate" + genStmt False = do genDepth -= 1 + cnt <- use genDepth + if cnt > 0 + then empty + else "endgenerate" inst = inst_ expr = expr_ @@ -72,7 +83,7 @@ genVerilog modName c = (unpack cName,) A.<$> verilog where cName = componentName c - verilog = "// Automatically generated SystemVerilog" <$$> + verilog = "// Automatically generated SystemVerilog-2005" <$$> tyImports modName <$$> module_ c @@ -309,7 +320,7 @@ end = start - argSize + 1 expr_ _ (Identifier id_ (Just (Indexed (ty@(Product _ _),_,fI)))) = text id_ <> dot <> verilogTypeMark ty <> "_sel" <> int fI -expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),_,fI)))) = text id_ <> parens (int fI) +expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),_,fI)))) = text id_ <> brackets (int fI) expr_ _ (Identifier id_ (Just (DC (ty@(SP _ _),_)))) = text id_ <> brackets (int start <> colon <> int end) where start = typeSize ty - 1