diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,13 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.6 *June 25th 2015*
+* New features:
+  * Support `clash-prelude-0.9`
+
+* Fixes bug:
+  * Can not operate "shiftR" on Int [#63](https://github.com/clash-lang/clash-compiler/issues/63)
+  * Fail to generate verilog when using "quot" and "div" on Index [#64](https://github.com/clash-lang/clash-compiler/issues/64)
+
 ## 0.5.5 *June 3rd 2015*
 * New features:
   * Compile against `clash-lib-0.5.6`
diff --git a/clash-systemverilog.cabal b/clash-systemverilog.cabal
--- a/clash-systemverilog.cabal
+++ b/clash-systemverilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-systemverilog
-Version:              0.5.5
+Version:              0.5.6
 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -29,6 +29,10 @@
                       primitives/CLaSH.Driver.TopWrapper.json
                       primitives/CLaSH.GHC.GHC2Core.json
                       primitives/CLaSH.Prelude.BlockRam.json
+                      primitives/CLaSH.Prelude.BlockRam.File.json
+                      primitives/CLaSH.Prelude.RAM.json
+                      primitives/CLaSH.Prelude.ROM.json
+                      primitives/CLaSH.Prelude.ROM.File.json
                       primitives/CLaSH.Prelude.Testbench.json
                       primitives/CLaSH.Promoted.Nat.json
                       primitives/CLaSH.Promoted.Symbol.json
@@ -66,8 +70,8 @@
   CPP-Options:        -DCABAL
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.6,
-                      clash-prelude           >= 0.8,
+                      clash-lib               >= 0.5.7,
+                      clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
                       mtl                     >= 2.1.2,
diff --git a/primitives/CLaSH.Prelude.BlockRam.File.json b/primitives/CLaSH.Prelude.BlockRam.File.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.BlockRam.File.json
@@ -0,0 +1,33 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"
+    , "type" :
+"blockRamFile# :: KnownNat m                 -- ARG[0]
+               => SClock clk                 -- clk,  ARG[1]
+               -> SNat n                     -- sz,   ARG[2]
+               -> FilePath                   -- file, ARG[3]
+               -> Signal' clk Int            -- wr,   ARG[4]
+               -> Signal' clk Int            -- rd,   ARG[5]
+               -> Signal' clk Bool           -- wren, ARG[6]
+               -> Signal' clk (BitVector m)  -- din,  ARG[7]
+               -> Signal' clk (BitVector m)"
+    , "templateD" :
+"// blockRamFile begin
+~TYPO RAM_~SYM[0] [0:~LIT[2]-1];
+~SIGD[dout_~SYM[1]][7];
+
+initial begin
+  $readmemb(~FILE[~LIT[3]],RAM_~SYM[0]);
+end
+
+always @(posedge ~CLK[1]) begin : blockRamFile_~COMPNAME_~SYM[2]
+  if (~ARG[7]) begin
+    RAM_~SYM[0][~ARG[4]] <= ~ARG[7];
+  end
+  dout_~SYM[1] <= RAM_~SYM[0][~ARG[6]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// blockRamFile end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.BlockRam.json b/primitives/CLaSH.Prelude.BlockRam.json
--- a/primitives/CLaSH.Prelude.BlockRam.json
+++ b/primitives/CLaSH.Prelude.BlockRam.json
@@ -1,31 +1,32 @@
 [ { "BlackBox" :
-    { "name" : "CLaSH.Prelude.BlockRam.blockRam'"
+    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
     , "type" :
-"blockRam' :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])
-           => SClock clk               -- clk,  ARG[2]
-           -> Vec n a                  -- init, ARG[3]
-           -> Signal' clk (Unsigned m) -- wr,   ARG[4]
-           -> Signal' clk (Unsigned m) -- rd,   ARG[5]
-           -> Signal' clk Bool         -- wren, ARG[6]
-           -> Signal' clk a            -- din,  ARG[7]
+"blockRam# :: KnownNat n       -- ARG[0]
+           => SClock clk       -- clk,  ARG[1]
+           -> Vec n a          -- init, ARG[2]
+           -> Signal' clk Int  -- wr,   ARG[3]
+           -> Signal' clk Int  -- rd,   ARG[4]
+           -> Signal' clk Bool -- wren, ARG[5]
+           -> Signal' clk a    -- din,  ARG[6]
            -> Signal' clk a"
     , "templateD" :
-"// blockRam
-~SIGD[~SYM[0]][3];
-~SIGD[~SYM[1]][7];
+"// blockRam begin
+~SIGD[RAM_~SYM[0]][2];
+~SIGD[dout_~SYM[1]][6];
 
 initial begin
   ~SYM[0] = ~LIT[3];
 end
 
-always @(posedge ~CLK[2]) begin : blockRam_~COMPNAME_~SYM[3]
-  if (~ARG[6]) begin
-    ~SYM[0][~ARG[4]] <= ~ARG[7];
+always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[3]
+  if (~ARG[5]) begin
+    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
   end
-  ~SYM[1] <= ~SYM[0][~ARG[5]];
+  dout_~SYM[1] <= RAM_~SYM[0][~ARG[4]];
 end
 
-assign ~RESULT = ~SYM[1];"
+assign ~RESULT = dout_~SYM[1];
+// blockRam end"
     }
   }
 ]
diff --git a/primitives/CLaSH.Prelude.RAM.json b/primitives/CLaSH.Prelude.RAM.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.RAM.json
@@ -0,0 +1,26 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.RAM.asyncRam#"
+    , "type" :
+"asyncRam# :: SClock wclk       -- ^ wclk, ARG[0]
+           -> SClock rclk       -- ^ rclk, ARG[1]
+           -> SNat n            -- ^ sz,   ARG[2]
+           -> Signal' wclk Int  -- ^ wr,   ARG[3]
+           -> Signal' rclk Int  -- ^ rd,   ARG[4]
+           -> Signal' wclk Bool -- ^ en,   ARG[5]
+           -> Signal' wclk a    -- ^ din,  ARG[6]
+           -> Signal' rclk a"
+    , "templateD" :
+"// asyncRam begin
+~SIGD[RAM_~SYM[0]][6] [0:~LIT[2]-1];
+
+always @(posedge ~CLK[0]) begin : Ram_~COMPNAME_~SYM[4]
+  if (~ARG[5]) begin
+    RAM_~SYM[0][~ARG[3]] <= ~ARG[6];
+  end
+end
+
+assign ~RESULT = RAM_~SYM[0][~ARG[4]];
+// asyncRam end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.ROM.File.json b/primitives/CLaSH.Prelude.ROM.File.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.ROM.File.json
@@ -0,0 +1,47 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.File.asyncRomFile#"
+    , "type" :
+"asyncRomFile :: KnownNat m -- ARG[0]
+              => SNat n     -- sz,   ARG[1]
+              -> FilePath   -- file, ARG[2]
+              -> Int        -- rd,   ARG[3]
+              -> BitVector m"
+    , "templateD" :
+"// asyncRomFile begin
+~TYPO ROM_~SYM[0] [0:~LIT[1]-1];
+
+initial begin
+  $readmemb(~FILE[~LIT[2]],ROM_~SYM[0]);
+end
+
+assign ~RESULT = ROM_~SYM[0][~ARG[3]];
+// asyncRomFile end"
+    }
+  }
+, { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.File.romFile#"
+    , "type" :
+"romFile# :: KnownNat m      -- ARG[0]
+          => SClock clk      -- clk,  ARG[1]
+          -> SNat n          -- sz,   ARG[2]
+          -> FilePath        -- file, ARG[3]
+          -> Signal' clk Int -- rd,   ARG[4]
+          -> Signal' clk (BitVector m)"
+    , "templateD" :
+"// romFile begin
+~TYPO ROM_~SYM[0] [0:~LIT[2]-1];
+
+initial begin
+  $readmemb(~FILE[~LIT[3]],ROM_~SYM[0]);
+end
+
+~SIGDO[dout_~SYM[1]];
+always @(posedge ~CLK[1]) begin : romFile_~COMPNAME_~SYM[2]
+  dout_~SYM[1] <= ROM_~SYM[0][~ARG[4]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// romFile end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.ROM.json b/primitives/CLaSH.Prelude.ROM.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Prelude.ROM.json
@@ -0,0 +1,39 @@
+[ { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
+    , "type" :
+"asyncRom# :: KnownNat n -- ^ ARG[0]
+           => Vec n a    -- ^ ARG[1]
+           -> Int        -- ^ ARG[2]
+           -> a"
+    , "templateD" :
+"// asyncRom begin
+~SIGD[ROM_~SYM[0]][1];
+assign ROM_SYM[0] = ~ARG[1];
+
+assign ~RESULT = ROM_~SYM[0][~ARG[2]];
+// asyncRom end"
+    }
+  }
+, { "BlackBox" :
+    { "name" : "CLaSH.Prelude.ROM.rom#"
+    , "type" :
+"rom# :: KnownNat n      -- ARG[0]
+      => SClock clk      -- clk,  ARG[1]
+      -> Vec n a         -- init, ARG[2]
+      -> Signal' clk Int -- rd,   ARG[3]
+      -> Signal' clk a"
+    , "templateD" :
+"// rom begin
+~SIGD[ROM_~SYM[0]][2];
+assign ROM_~SYM[0] = ~ARG[2];
+
+~SIGDO[dout_~SYM[1]];
+always @(posedge ~CLK[1]) begin : rom_~COMPNAME_~SYM[2]
+  dout_~SYM[1] <= ROM_~SYM[0][~ARG[3]];
+end
+
+assign ~RESULT = dout_~SYM[1];
+// rom end"
+    }
+  }
+]
diff --git a/primitives/CLaSH.Prelude.Testbench.json b/primitives/CLaSH.Prelude.Testbench.json
--- a/primitives/CLaSH.Prelude.Testbench.json
+++ b/primitives/CLaSH.Prelude.Testbench.json
@@ -2,21 +2,24 @@
     { "name" : "CLaSH.Prelude.Testbench.assert"
     , "type" :
 "assert :: (Eq a,Show a) -- (ARG[0],ARG[1])
-        => Signal' t a   -- ^ Checked value (ARG[2])
-        -> Signal' t a   -- ^ Expected value (ARG[3])
-        -> Signal' t b   -- ^ Return valued (ARG[4])
+        => SClock t      -- ^ ARG[2]
+        -> String        -- ^ ARG[3]
+        -> Signal' t a   -- ^ Checked value (ARG[4])
+        -> Signal' t a   -- ^ Expected value (ARG[5])
+        -> Signal' t b   -- ^ Return valued (ARG[6])
         -> Signal' t b"
     , "templateD" :
-"// assert
+"// assert begin
 // pragma translate_off
-always @(posedge ~CLK[2] or negedge ~RST[2]) begin
-  if (~ARG[2] != ~ARG[3]) begin
-    $display(\"expected: %b, actual: %b\", ~TYPM[3]_to_lv(~ARG[3]), ~TYPM[2]_to_lv(~ARG[2]));
+always @(posedge ~CLK[2] or posedge ~RST[2]) begin
+  if (~ARG[4] != ~ARG[5]) begin
+    $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~TYPM[3]_to_lv(~ARG[5]), ~TYPM[2]_to_lv(~ARG[4]));
     $stop;
   end
 end
 // pragma translate_on
-assign ~RESULT = ~ARG[4];"
+assign ~RESULT = ~ARG[6];
+// assert end"
     }
   }
 ]
diff --git a/primitives/CLaSH.Signal.Internal.json b/primitives/CLaSH.Signal.Internal.json
--- a/primitives/CLaSH.Signal.Internal.json
+++ b/primitives/CLaSH.Signal.Internal.json
@@ -6,7 +6,8 @@
            -> Signal' clk a  -- ARG[2]
            -> Signal' clk a"
     , "templateD" :
-"~SIGD[~SYM[0]][2];
+"// register begin
+~SIGD[~SYM[0]][2];
 
 always_ff @(posedge ~CLK[0] or negedge ~RST[0]) begin : register_~COMPNAME_~SYM[1]
   if (~ ~RST[0]) begin
@@ -16,7 +17,8 @@
   end
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// register end"
     }
   }
 , { "BlackBox" :
@@ -28,7 +30,8 @@
         -> Signal' clk a    -- ARG[3]
         -> Signal' clk a"
     , "templateD" :
-"~SIGD[~SYM[0]][3];
+"// regEn begin
+~SIGD[~SYM[0]][3];
 
 always_ff @(posedge ~CLK[0] or negedge ~RST[0]) begin : regEn_~COMPNAME_~SYM[1]
   if (~ ~RST[0]) begin
@@ -40,7 +43,8 @@
   end
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// regEn end"
     }
   }
 
@@ -66,6 +70,11 @@
   }
 , { "Primitive" :
     { "name"      : "CLaSH.Signal.Internal.traverse#"
+    , "primType"  : "Function"
+    }
+  }
+, { "Primitive" :
+    { "name"      : "CLaSH.Signal.Internal.joinSignal#"
     , "primType"  : "Function"
     }
   }
diff --git a/primitives/CLaSH.Sized.Internal.BitVector.json b/primitives/CLaSH.Sized.Internal.BitVector.json
--- a/primitives/CLaSH.Sized.Internal.BitVector.json
+++ b/primitives/CLaSH.Sized.Internal.BitVector.json
@@ -54,25 +54,12 @@
         -> Int         -- ARG[2]
         -> Bit"
     , "templateD" :
-"// index
-~SIGD[~SYM[0]][1];
-~SIGD[~SYM[1]][2];
-
-assign ~SYM[0] = ~ARG[1];
-assign ~SYM[1] = ~ARG[2];
+"// indexBit begin
+~SIGD[vec_~SYM[0]][1];
+assign vec_~SYM[0] = ~ARG[1];
 
-// pragma translate_off
-always_comb begin
-  if (~SYM[1] < $low(~SYM[0]) || ~SYM[1] > $high(~SYM[0])) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[1], $low(~SYM[0]), $high(~SYM[0]));
-    ~RESULT = ~ERRORO;
-  end else begin
-  // pragma translate_on
-    ~RESULT = ~SYM[0][~SYM[1]];
-  // pragma translate_off
-  end
-end
-// pragma translate_on"
+assign ~RESULT = vec_~SYM[0][~ARG[2]];
+// indexBit end"
     }
   }
 , { "BlackBox" :
@@ -84,26 +71,18 @@
              -> Bit         -- ARG[3]
              -> BitVector n"
     , "templateD" :
-"// replaceBit
-~SIGD[~SYM[0]][2];
-assign ~SYM[0] = ~ARG[2];
+"// replaceBit start
+~SIGD[vec_~SYM[0]][1];
+~SIGD[din_~SYM[1]][3];
+assign din_~SYM[1] = ~ARG[3];
 
-~SIGD[~SYM[1]][1];
 always_comb begin
-  ~SYM[1] = ~ARG[1];
-  // pragma translate_off
-  if (~SYM[0] < $low(~SYM[1]) || ~SYM[0] > $high(~SYM[1])) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[0], $low(~SYM[1]), $high(~SYM[1]));
-    ~SYM[1] = ~ERROR[1];
-  end else begin
-    // pragma translate_on
-    ~SYM[1][~SYM[0]] = ~ARG[3];
-    // pragma translate_off
-  end
-  // pragma translate_on
+  vec_~SYM[0] = ~ARG[1];
+  vec_~SYM[0][~ARG[2]] = din_~SYM[1];
 end
 
-assign ~RESULT = ~SYM[1];"
+assign ~RESULT = vec_~SYM[0];
+// replaceBit end"
     }
   }
 , { "BlackBox" :
@@ -115,7 +94,7 @@
            -> BitVector (m + 1 - n) -- ARG[3]
            -> BitVector (m + 1 + i)"
     , "templateD" :
-"// setSlice
+"// setSlice begin
 ~SIGD[~SYM[0]][0];
 
 always_comb begin
@@ -123,7 +102,8 @@
   ~SYM[0][~LIT[1] : ~LIT[2]] = ~ARG[3];
 end
 
-assign ~RESULT = ~SYM[0];"
+assign ~RESULT = ~SYM[0];
+// setSlice end"
     }
   }
 , { "BlackBox" :
@@ -134,10 +114,11 @@
         -> SNat n                -- ARG[2]
         -> BitVector (m + 1 - n)"
     , "templateD" :
-"// slice
+"// slice begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
-assign ~RESULT = ~SYM[1][~LIT[1] : ~LIT[2]];"
+assign ~RESULT = ~SYM[0][~LIT[1] : ~LIT[2]];
+// slice end"
     }
   }
 , { "BlackBox" :
@@ -147,12 +128,13 @@
         => BitVector (m + n) -- ARG[1]
         -> (BitVector m, BitVector n)"
     , "templateD" :
-"// split
+"// split begin
 ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
 assign ~RESULT = '{ ~SYM[0][$high(~SYM[0]) : ~LIT[0]]
                   , ~SYM[0][(~LIT[0]-1) : 0]
-                  };"
+                  };
+// split end"
     }
   }
 , { "BlackBox" :
@@ -162,10 +144,11 @@
       => BitVector n -- ARG[1]
       -> Bit"
     , "templateD" :
-"// msb
+"// msb begin
 ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
-assign ~RESULT = ~SYM[0][~LIT[0]-1];"
+assign ~RESULT = ~SYM[0][~LIT[0]-1];
+// msb end"
     }
   }
 , { "BlackBox" :
@@ -174,10 +157,11 @@
 "lsb# :: BitVector n -- ARG[0]
       -> Bit"
     , "templateD" :
-"// lsb
+"// lsb begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
-assign ~RESULT = ~SYM[0][0];"
+assign ~RESULT = ~SYM[0][0];
+// lsb end"
     }
   }
 , { "BlackBox" :
@@ -279,19 +263,13 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.quot#"
     , "type"      : "quot# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1]) / ~ARG[2]"
+    , "templateE" : "~ARG[0]) / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.rem#"
     , "type"      : "rem# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.BitVector.mod#"
-    , "type"      : "mod# :: BitVector n -> BitVector n -> BitVector n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
@@ -340,20 +318,22 @@
     { "name"      : "CLaSH.Sized.Internal.BitVector.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => BitVector n -> Int -> BitVector n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = ~SYM[0][2*~LIT[0]-1 : ~LIT[0]];"
+assign ~RESULT = ~SYM[0][2*~LIT[0]-1 : ~LIT[0]];
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.BitVector.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => BitVector n -> Int -> BitVector n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];
+// rotateR end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Index.json b/primitives/CLaSH.Sized.Internal.Index.json
--- a/primitives/CLaSH.Sized.Internal.Index.json
+++ b/primitives/CLaSH.Sized.Internal.Index.json
@@ -66,20 +66,14 @@
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.quot#"
-    , "type"      : "quot# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] / ~ARG[2]"
+    , "type"      : "quot# :: Index n -> Index n -> Index n"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Index.rem#"
-    , "type"      : "rem# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.Index.mod#"
-    , "type"      : "mod# :: KnownNat n => Index n -> Index n -> Index n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "type"      : "rem# :: Index n -> Index n -> Index n"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Signed.json b/primitives/CLaSH.Sized.Internal.Signed.json
--- a/primitives/CLaSH.Sized.Internal.Signed.json
+++ b/primitives/CLaSH.Sized.Internal.Signed.json
@@ -136,7 +136,7 @@
     { "name"      : "CLaSH.Sized.Internal.Signed.div#"
     , "type"      : "div# :: KnownNat n => Signed n -> Signed n -> Signed n"
     , "templateD" :
-"// divInt
+"// divSigned begin
 ~SIGD[~SYM[0]][1];
 ~SIGD[~SYM[1]][1];
 ~SIGD[~SYM[2]][2];
@@ -147,14 +147,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[1];
 assign ~SYM[2] = ~ARG[2];
-assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ? ~SYM[0] : ~SYM[0] - ~LIT[0]'sd1;"
+assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ? ~SYM[0] : ~SYM[0] - ~LIT[0]'sd1;
+// divSigned end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.mod#"
     , "type"      : "mod# :: KnownNat n => Signed n -> Signed n -> Signed n"
     , "templateD" :
-"// modSigned
+"// modSigned begin
 ~SIGD[~SYM[0]][1];
 ~SIGD[~SYM[1]][1];
 ~SIGD[~SYM[2]][2];
@@ -167,7 +168,8 @@
 assign ~SYM[2] = ~ARG[2];
 assign ~RESULT = (~SYM[1][~LIT[0]-1] == ~SYM[2][~LIT[0]-1]) ?
                  ~SYM[0] :
-                 (~ARG[1] == ~LIT[0]'sd0 ? ~LIT[0]'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == ~LIT[0]'sd0 ? ~LIT[0]'sd0 : ~SYM[0] + ~ARG[1]);
+// modSigned end"
     }
   }
 , { "BlackBox" :
@@ -216,20 +218,22 @@
     { "name"      : "CLaSH.Sized.Internal.Signed.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => Signed n -> Int -> Signed n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);"
+assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Signed.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => Signed n -> Int -> Signed n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);"
+assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]);
+// rotateR end"
     }
   }
 , { "BlackBox" :
@@ -237,7 +241,7 @@
     , "type"      : "resize# :: (KnownNat n, KnownNat m) => Signed n -> Signed m"
     , "comment"   : "Back-end should only use this code when the result is smaller than the argument"
     , "templateD" :
-"// resize
+"// resize begin
 generate
   if (~LIT[1] < ~LIT[0]) begin
     // truncate, sign preserving
@@ -248,7 +252,8 @@
     // sign-extend
     assign ~RESULT = $signed(~ARG[2]);
   end
-endgenerate"
+endgenerate
+// resize end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -115,19 +115,13 @@
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.quot#"
     , "type"      : "quot# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] / ~ARG[2]"
+    , "templateE" : "~ARG[0] / ~ARG[1]"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rem#"
     , "type"      : "rem# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "CLaSH.Sized.Internal.Unsigned.mod#"
-    , "type"      : "mod# :: Unsigned n -> Unsigned n -> Unsigned n"
-    , "templateE" : "~ARG[1] % ~ARG[2]"
+    , "templateE" : "~ARG[0] % ~ARG[1]"
     }
   }
 , { "BlackBox" :
@@ -176,20 +170,22 @@
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateL#"
     , "type"      : "rotateL# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
-"// rotateL
+"// rotateL begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+// rotateL end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateR#"
     , "type"      : "rotateR# :: KnownNat n => Unsigned n -> Int -> Unsigned n"
     , "templateD" :
-"// rotateR
+"// rotateR begin
 logic [2*~LIT[0]-1:0] ~SYM[0];
 assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];
-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"
+assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];
+// rotateR end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/CLaSH.Sized.Vector.json b/primitives/CLaSH.Sized.Vector.json
--- a/primitives/CLaSH.Sized.Vector.json
+++ b/primitives/CLaSH.Sized.Vector.json
@@ -14,44 +14,48 @@
     { "name"      : "CLaSH.Sized.Vector.head"
     , "type"      : "head :: Vec (n + 1) a -> a"
     , "templateD" :
-"// head
+"// head begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][0];"
+assign ~RESULT = ~SYM[0][0];
+// head end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.tail"
     , "type"      : "tail :: Vec (n + 1) a -> Vec n a"
     , "templateD" :
-"// tail
+"// tail begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][1 : $high(~SYM[0])];"
+assign ~RESULT = ~SYM[0][1 : $high(~SYM[0])];
+// tail end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.last"
     , "type"      : "Vec (n + 1) a -> a"
     , "templateD" :
-"// last
+"// last begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][$high(~SYM[0])];"
+assign ~RESULT = ~SYM[0][$high(~SYM[0])];
+// last end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.init"
     , "type"      : "Vec (n + 1) a -> Vec n a"
     , "templateD" :
-"// init
+"// init begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
-assign ~RESULT = ~SYM[0][0 : $high(~SYM[0]) - 1];"
+assign ~RESULT = ~SYM[0][0 : $high(~SYM[0]) - 1];
+// init end"
     }
   }
 , { "BlackBox" :
@@ -64,7 +68,7 @@
         -> Vec i a                       -- ARG[4]
         -> Vec n a"
     , "templateD" :
-"// select
+"// select begin
 ~SIGD[~SYM[0]][4];
 assign ~SYM[0] = ~ARG[4];
 
@@ -73,14 +77,15 @@
   for (~SYM[1]=0; ~SYM[1] < ~LIT[3]; ~SYM[1] = ~SYM[1] + 1) begin : select_~SYM[2]
     assign ~RESULT[~SYM[1]] = ~SYM[0][~LIT[1] + (~LIT[2] * ~SYM[1])];
   end
-endgenerate"
+endgenerate
+// select end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.++"
     , "type"      : "(++) :: Vec n a -> Vec m a -> Vec (n + m) a"
     , "templateD" :
-"// (++)
+"// (++) begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][1];
 
@@ -96,14 +101,15 @@
       assign ~RESULT[~SYM[2]] = ~SYM[1][~SYM[2]-$size(~SYM[0])];
     end
   end
-endgenerate"
+endgenerate
+// (++) end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.concat"
     , "type"      : "concat :: Vec n (Vec m a) -> Vec (n * m) a"
     , "templateD" :
-"// concat
+"// concat begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
@@ -112,20 +118,22 @@
   for (~SYM[1]=0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : concat_~SYM[2]
     assign ~RESULT[(~SYM[5] * $size(~SYM[0][0])) : ((~SYM[5] * $size(~SYM[0][0])) + $high(~SYM[0][0]))] = ~SYM[0][~SYM[1]];
   end
-endgenerate"
+endgenerate
+// concat end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.splitAt"
     , "type"      : "splitAt :: SNat m -> Vec (m + n) a -> (Vec m a, Vec n a)"
     , "templateD" :
-"// splitAt
+"// splitAt begin
 ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
 
 assign ~RESULT = '{~SYM[0][$left(~RESULT.~TYPMO_sel0) : $right(~RESULT.~TYPMO_sel0)]
                   ,~SYM[0][($left(~RESULT.~TYPMO_sel1) + $size(~RESULT.~TYPMO_sel0)) : ($right(~RESULT.~TYPMO_sel1) + $size(~RESULT.~TYPMO_sel0))]
-                  };"
+                  };
+// splitAt end"
     }
   }
 , { "BlackBox" :
@@ -136,7 +144,7 @@
            -> Vec (n * m) a  -- ARG[2]
            -> Vec n (Vec m a)"
     , "templateD" :
-"// unconcat
+"// unconcat begin
 ~SIGD[~SYM[0]][2];
 assign ~SYM[0] = ~ARG[2];
 
@@ -145,14 +153,15 @@
   for (~SYM[1] = 0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : unconcat_~SYM[2]
     assign ~RESULT[~SYM[1]] = ~SYM[0][(~SYM[1] * ~LIT[1]) : ((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1)];
   end
-endgenerate"
+endgenerate
+// unconcat end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.merge"
     , "type"      : "merge :: Vec n a -> Vec n a -> Vec (n + n) a"
     , "templateD" :
-"// merge
+"// merge begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][1];
 assign ~SYM[0] = ~ARG[0];
@@ -164,14 +173,15 @@
     assign ~RESULT[2*~SYM[2]]   = ~SYM[0][~SYM[2]];
     assign ~RESULT[2*~SYM[2]+1] = ~SYM[1][~SYM[2]];
   end
-endgenerate"
+endgenerate
+// merge end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.map"
     , "type"      : "map :: (a -> b) -> Vec n a -> Vec n b"
     , "templateD" :
-"// map
+"// map begin
 ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
 
@@ -183,14 +193,15 @@
       ~INPUT  <= ~SYM[0][~SYM[1]]~ ~TYPEL[~TYP[1]]~
     ~INST
   end
-endgenerate"
+endgenerate
+// map end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.zipWith"
     , "type"      : "zipWith :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c"
     , "templateD" :
-"// zipWith
+"// zipWith begin
 ~SIGD[~SYM[0]][1];
 ~SIGD[~SYM[1]][2];
 assign ~SYM[0] = ~ARG[1];
@@ -205,59 +216,38 @@
       ~INPUT  <= ~SYM[1][~SYM[2]]~ ~TYPEL[~TYP[2]]~
     ~INST
   end
-endgenerate"
+endgenerate
+// zipWith end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.index_int"
     , "type"      : "index_integer :: KnownNat n => Vec n a -> Int -> a"
     , "templateD" :
-"// index_integer
-~SIGD[~SYM[0]][1];
-~SIGD[~SYM[1]][2];
-
-assign ~SYM[0] = ~ARG[1];
-assign ~SYM[1] = ~ARG[2];
-
+"// indexVec begin
+~SIGD[vec_~SYM[0]][1];
+assign vec_SYM[0] = ~ARG[1];
 
-always_comb begin
-// pragma translate_off
-  if (~SYM[1] < $low(~SYM[0]) || ~SYM[1] > $high(~SYM[0])) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[1], $low(~SYM[0]), $high(~SYM[0]));
-    ~RESULT = ~ERRORO;
-  end else begin
-  // pragma translate_on
-    ~RESULT = ~SYM[0][~SYM[1]];
-  // pragma translate_off
-  end
-// pragma translate_on
-end"
+assign ~RESULT = vec_~SYM[0][~ARG[2]];
+// indexVec end"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Vector.replace_int"
     , "type"      : "replace_int :: KnownNat n => Vec n a -> Int -> a -> Vec n a"
     , "templateD" :
-"// replace_integer
-~SIGD[~SYM[0]][2];
-assign ~SYM[0] = ~ARG[2];
+"// replaceVec start
+~SIGD[vec_~SYM[0]][1];
+~SIGD[din_~SYM[1]][3];
+assign din_~SYM[1] = ~ARG[3];
 
-~SIGD[~SYM[1]][1];
 always_comb begin
-  ~SYM[1] = ~ARG[1];
-  // pragma translate_off
-  if (~SYM[0] < $low(~SYM[1]) || ~SYM[0] > $high(~SYM[1])) begin
-    $display(\"Index: %d, is out of bounds: %d to %d\", ~SYM[0], $low(~SYM[1]), $high(~SYM[1]));
-    ~SYM[1] = ~ERROR[1];
-  end else begin
-    // pragma translate_on
-    ~SYM[1][~SYM[0]] = ~ARG[3];
-    // pragma translate_off
-  end
-  // pragma translate_on
+  vec_~SYM[0] = ~ARG[1];
+  vec_~SYM[0][~ARG[2]] = din_~SYM[1];
 end
 
-assign ~RESULT = ~SYM[1];"
+assign ~RESULT = vec_~SYM[0];
+// replaceVec end"
     }
   }
 , { "BlackBox" :
@@ -282,7 +272,7 @@
     { "name"      : "CLaSH.Sized.Vector.reverse"
     , "type"      : "reverse :: Vec n a -> Vec n a"
     , "templateD" :
-"// reverse
+"// reverse begin
 ~SIGD[~SYM[0]][0];
 assign ~SYM[0] = ~ARG[0];
 
@@ -291,7 +281,8 @@
   for (~SYM[1] = 0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2]
     assign ~RESULT[$high(~SYM[0]) - ~SYM[1]] = ~SYM[0][~SYM[1]];
   end
-endgenerate"
+endgenerate
+// reverse end"
     }
   }
 , { "BlackBox" :
@@ -307,7 +298,7 @@
                   => Vec n (BitVector m)  -- ARG[1]
                   -> BitVector (n * m)"
     , "templateD" :
-"// concatBitVector
+"// concatBitVector begin
 ~SIGD[~SYM[0]][1];
 assign ~SYM[0] = ~ARG[1];
 
@@ -316,7 +307,8 @@
   for (~SYM[1] = 0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : concatBitVector_~SYM[2]
     assign ~RESULT[((~SYM[1] * ~LIT[0]) + ~LIT[0] - 1) : (~SYM[1] * ~LIT[0])] = ~SYM[0][$high(~SYM[0]) - ~SYM[1]];
   end
-endgenerate"
+endgenerate
+// concatBitVector end"
     }
   }
 , { "BlackBox" :
@@ -326,7 +318,7 @@
                     => BitVector (n * m)        -- ARG[2]
                     -> Vec n (BitVector m)"
     , "templateD" :
-"// unconcatBitVector
+"// unconcatBitVector begin
 ~SIGD[~SYM[0]][2];
 assign ~SYM[0] = ~ARG[2];
 
@@ -335,7 +327,8 @@
   for (~SYM[1] = 0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : unconcatBitVector_~SYM[2]
     assign ~RESULT[$high(~RESULT) - ~SYM[1]] = ~SYM[0][((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1) : (~SYM[1] * ~LIT[1])];
   end
-endgenerate"
+endgenerate
+// unconcatBitVector end"
     }
   }
 ]
diff --git a/primitives/GHC.Base.json b/primitives/GHC.Base.json
--- a/primitives/GHC.Base.json
+++ b/primitives/GHC.Base.json
@@ -19,7 +19,7 @@
     { "name"      : "GHC.Base.divInt"
     , "type"      : "divInt :: Int -> Int -> Int"
     , "templateD" :
-"// divInt
+"// divInt begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -30,14 +30,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Base.modInt"
     , "type"      : "modInt :: Int -> Int -> Int"
     , "templateD" :
-"// modInt
+"// modInt begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -50,7 +51,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInt end"
     }
   }
 ]
diff --git a/primitives/GHC.CString.json b/primitives/GHC.CString.json
--- a/primitives/GHC.CString.json
+++ b/primitives/GHC.CString.json
@@ -1,6 +1,6 @@
-[ { "Primitive" :
-    { "name"     : "GHC.CString.unpackCString#"
-    , "primType" : "Function"
+[ { "BlackBox" :
+    { "name"      : "GHC.CString.unpackCString#"
+    , "templateE" : "~LIT[0]"
     }
   }
 , { "Primitive" :
diff --git a/primitives/GHC.Classes.json b/primitives/GHC.Classes.json
--- a/primitives/GHC.Classes.json
+++ b/primitives/GHC.Classes.json
@@ -56,7 +56,7 @@
     { "name"      : "GHC.Classes.divInt#"
     , "type"      : "divInt# :: Int# -> Int# -> Int#"
     , "templateD" :
-"// divInt
+"// divInt begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -67,14 +67,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInt end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Classes.modInt#"
     , "type"      : "modInt# :: Int# -> Int# -> Int#"
     , "templateD" :
-"// modInt
+"// modInt begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -87,7 +88,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInt end"
     }
   }
 ]
diff --git a/primitives/GHC.Integer.Type.json b/primitives/GHC.Integer.Type.json
--- a/primitives/GHC.Integer.Type.json
+++ b/primitives/GHC.Integer.Type.json
@@ -44,7 +44,7 @@
     { "name"      : "GHC.Integer.Type.divInteger"
     , "type"      : "divInteger :: Integer -> Integer -> Integer"
     , "templateD" :
-"// divInteger
+"// divInteger begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -55,14 +55,15 @@
 // round toward minus infinity
 assign ~SYM[1] = ~ARG[0];
 assign ~SYM[2] = ~ARG[1];
-assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;"
+assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ? ~SYM[0] : ~SYM[0] - 32'sd1;
+// divInteger end"
     }
   }
 , { "BlackBox" :
     { "name"      : "GHC.Integer.Type.modInteger"
     , "type"      : "modInteger :: Integer -> Integer -> Integer"
     , "templateD" :
-"// modInteger
+"// modInteger begin
 ~SIGD[~SYM[0]][0];
 ~SIGD[~SYM[1]][0];
 ~SIGD[~SYM[2]][1];
@@ -75,7 +76,8 @@
 assign ~SYM[2] = ~ARG[1];
 assign ~RESULT = (~SYM[1][31] == ~SYM[2][31]) ?
                  ~SYM[0] :
-                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);"
+                 (~ARG[1] == 32'sd0 ? 32'sd0 : ~SYM[0] + ~ARG[1]);
+// modInteger end"
     }
   }
 , { "BlackBox" :
diff --git a/primitives/GHC.Prim.json b/primitives/GHC.Prim.json
--- a/primitives/GHC.Prim.json
+++ b/primitives/GHC.Prim.json
@@ -86,4 +86,22 @@
     , "templateE" : "~ARG[0]"
     }
   }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRA#"
+    , "type"      : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >>> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftRL#"
+    , "type"      : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] >> ~ARG[1]"
+    }
+  }
+, { "BlackBox" :
+    { "name"      : "GHC.Prim.uncheckedIShiftL#"
+    , "type"      : "uncheckedIShiftL# :: Int# -> Int# -> Int#"
+    , "templateE" : "~ARG[0] <<< ~ARG[1]"
+    }
+  }
 ]
diff --git a/src/CLaSH/Backend/SystemVerilog.hs b/src/CLaSH/Backend/SystemVerilog.hs
--- a/src/CLaSH/Backend/SystemVerilog.hs
+++ b/src/CLaSH/Backend/SystemVerilog.hs
@@ -81,7 +81,7 @@
              -> [HWType]
              -> SystemVerilogM [(String,Doc)]
 mkTyPackage_ modName hwtys = (:[]) A.<$> (modName ++ "_types",) A.<$>
-    "package" <+> modNameD <> "_types" <+> semi <$>
+    "package" <+> modNameD <> "_types" <> semi <$>
       indent 2 packageDec <$>
       indent 2 funDecs <$>
     "endpackage" <+> colon <+> modNameD <> "_types"
@@ -401,9 +401,10 @@
 
   where
     blit = bits (toBits sz i)
-exprLit _             (BoolLit t)  = if t then "1'b1" else "1'b0"
-exprLit _             (BitLit b)   = "1'b" <> bit_char b
-exprLit _             l            = error $ $(curLoc) ++ "exprLit: " ++ show l
+exprLit _             (BoolLit t)   = if t then "1'b1" else "1'b0"
+exprLit _             (BitLit b)    = "1'b" <> bit_char b
+exprLit _             (StringLit s) = text . pack $ show s
+exprLit _             l             = error $ $(curLoc) ++ "exprLit: " ++ show l
 
 toBits :: Integral a => Int -> a -> [Bit]
 toBits size val = map (\x -> if odd x then H else L)