clash-systemverilog 0.5.4 → 0.5.5
raw patch · 4 files changed
+40/−20 lines, 4 filesdep ~clash-libdep ~clash-preludePVP ok
version bump matches the API change (PVP)
Dependency ranges changed: clash-lib, clash-prelude
API changes (from Hackage documentation)
Files
- CHANGELOG.md +6/−1
- clash-systemverilog.cabal +3/−3
- primitives/CLaSH.Sized.Vector.json +2/−2
- src/CLaSH/Backend/SystemVerilog.hs +29/−14
CHANGELOG.md view
@@ -1,6 +1,11 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package -## 0.5.4+## 0.5.5 *June 3rd 2015*+* New features:+ * Compile against `clash-lib-0.5.6`+ * Generated component names are prefixed by the name of the module containing the `topEntity`++## 0.5.4 *May 10th 2015* * New features: * Generate smarter labels for `register` and `blockRam` blackboxes to make finding longest paths easier
clash-systemverilog.cabal view
@@ -1,5 +1,5 @@ Name: clash-systemverilog-Version: 0.5.4+Version: 0.5.5 Synopsis: CAES Language for Synchronous Hardware - SystemVerilog backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -66,8 +66,8 @@ CPP-Options: -DCABAL Build-depends: base >= 4.6.0.1 && < 5,- clash-lib >= 0.5.4,- clash-prelude >= 0.7.2,+ clash-lib >= 0.5.6,+ clash-prelude >= 0.8, fgl >= 5.4.2.4, lens >= 3.9.2, mtl >= 2.1.2,
primitives/CLaSH.Sized.Vector.json view
@@ -314,7 +314,7 @@ genvar ~SYM[1]; generate for (~SYM[1] = 0; ~SYM[1] < $size(~SYM[0]); ~SYM[1] = ~SYM[1] + 1) begin : concatBitVector_~SYM[2]- assign ~RESULT[((~SYM[1] * ~LIT[0]) + ~LIT[0] - 1) : (~SYM[1] * ~LIT[0])] = ~SYM[0][~SYM[1]];+ assign ~RESULT[((~SYM[1] * ~LIT[0]) + ~LIT[0] - 1) : (~SYM[1] * ~LIT[0])] = ~SYM[0][$high(~SYM[0]) - ~SYM[1]]; end endgenerate" }@@ -333,7 +333,7 @@ genvar ~SYM[1]; generate for (~SYM[1] = 0; ~SYM[1] < $size(~RESULT); ~SYM[1] = ~SYM[1] + 1) begin : unconcatBitVector_~SYM[2]- assign ~RESULT[~SYM[1]] = ~SYM[0][((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1) : (~SYM[1] * ~LIT[1])];+ assign ~RESULT[$high(~RESULT) - ~SYM[1]] = ~SYM[0][((~SYM[1] * ~LIT[1]) + ~LIT[1] - 1) : (~SYM[1] * ~LIT[1])]; end endgenerate" }
src/CLaSH/Backend/SystemVerilog.hs view
@@ -19,7 +19,7 @@ import qualified Data.HashSet as HashSet import Data.List (mapAccumL,nubBy) import Data.Maybe (catMaybes,mapMaybe)-import Data.Text.Lazy (unpack)+import Data.Text.Lazy (pack,unpack) import Prelude hiding ((<$>)) import Text.PrettyPrint.Leijen.Text.Monadic @@ -68,23 +68,25 @@ type SystemVerilogM a = State SystemVerilogState a -- | Generate VHDL for a Netlist component-genVerilog :: Component -> SystemVerilogM (String,Doc)-genVerilog c = (unpack cName,) A.<$> verilog+genVerilog :: String -> Component -> SystemVerilogM (String,Doc)+genVerilog modName c = (unpack cName,) A.<$> verilog where cName = componentName c verilog = "// Automatically generated SystemVerilog" <$$>- tyImports <$$>+ tyImports modName <$$> module_ c -- | Generate a SystemVerilog package containing type definitions for the given HWTypes-mkTyPackage_ :: [HWType]- -> SystemVerilogM Doc-mkTyPackage_ hwtys =- "package types ;" <$>+mkTyPackage_ :: String+ -> [HWType]+ -> SystemVerilogM [(String,Doc)]+mkTyPackage_ modName hwtys = (:[]) A.<$> (modName ++ "_types",) A.<$>+ "package" <+> modNameD <> "_types" <+> semi <$> indent 2 packageDec <$> indent 2 funDecs <$>- "endpackage : types"+ "endpackage" <+> colon <+> modNameD <> "_types" where+ modNameD = text (pack modName) usedTys = concatMap mkUsedTys hwtys needsDec = nubBy eqReprTy $ (hwtys ++ usedTys) hwTysSorted = topSortHWTys needsDec@@ -160,8 +162,8 @@ <> semi) <$> "endfunction" -tyImports :: SystemVerilogM Doc-tyImports = "import types:: * ;"+tyImports :: String -> SystemVerilogM Doc+tyImports modName = "import" <+> text (pack modName) <> "_types::*;" module_ :: Component -> SystemVerilogM Doc module_ c =@@ -257,8 +259,18 @@ inst_ (Assignment id_ e) = fmap Just $ "assign" <+> text id_ <+> equals <+> expr_ False e <> semi -inst_ (CondAssignment id_ scrut es) = fmap Just $+inst_ (CondAssignment id_ _ scrut [(Just (Literal _ (BoolLit b)), l),(_,r)]) = fmap Just $ "always_comb begin" <$>+ indent 2 ("if" <> parens (expr_ True scrut) <$>+ (indent 2 $ text id_ <+> equals <+> expr_ False t <> semi) <$>+ "else" <$>+ (indent 2 $ text id_ <+> equals <+> expr_ False f <> semi)) <$>+ "end"+ where+ (t,f) = if b then (l,r) else (r,l)++inst_ (CondAssignment id_ _ scrut es) = fmap Just $+ "always_comb begin" <$> indent 2 ("case" <> parens (expr_ True scrut) <$> (indent 2 $ vcat $ punctuate semi (conds es)) <> semi <$> "endcase") <$>@@ -382,6 +394,9 @@ Signed _ | i < 0 -> "-" <> int sz <> "'sd" <> integer (abs i) | otherwise -> int sz <> "'sd" <> integer i+ Integer+ | i < 0 -> "-" <> int 32 <> "'sd" <> integer (abs i)+ | otherwise -> int 32 <> "'sd" <> integer i _ -> int sz <> "'b" <> blit where@@ -403,8 +418,8 @@ bit_char :: Bit -> SystemVerilogM Doc bit_char H = char '1' bit_char L = char '0'-bit_char U = char 'U'-bit_char Z = char 'Z'+bit_char U = char 'x'+bit_char Z = char 'z' toSLV :: HWType -> Expr -> SystemVerilogM Doc toSLV t@(Product _ tys) (Identifier id_ Nothing) = do