clash-systemverilog 0.5.3 → 0.5.4

raw patch · 4 files changed

+21/−15 lines, 4 filesdep ~clash-libPVP ok

version bump matches the API change (PVP)

Dependency ranges changed: clash-lib

API changes (from Hackage documentation)

Files

• CHANGELOG.md +4/−0
• clash-systemverilog.cabal +2/−2
• primitives/CLaSH.Prelude.BlockRam.json +1/−1
• primitives/CLaSH.Signal.Internal.json +14/−12

@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.5.4+* New features:+  * Generate smarter labels for `register` and `blockRam` blackboxes to make finding longest paths easier+ ## 0.5.3 *May 5th 2015* * Fixes bugs:   * Incorrect implementation of rotateL and rotateR blackbox for BitVector

@@ -1,5 +1,5 @@ Name:                 clash-systemverilog-Version:              0.5.3+Version:              0.5.4 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -66,7 +66,7 @@   CPP-Options:        -DCABAL    Build-depends:      base                    >= 4.6.0.1 && < 5,-                      clash-lib               >= 0.5,+                      clash-lib               >= 0.5.4,                       clash-prelude           >= 0.7.2,                       fgl                     >= 5.4.2.4,                       lens                    >= 3.9.2,

@@ -18,7 +18,7 @@   ~SYM[0] = ~LIT[3]; end -always @(posedge ~CLK[2]) begin+always @(posedge ~CLK[2]) begin : blockRam_~COMPNAME_~SYM[3]   if (~ARG[6]) begin     ~SYM[0][~ARG[4]] <= ~ARG[7];   end

@@ -8,11 +8,12 @@     , "templateD" : "~SIGD[~SYM[0]][2]; -always_ff @(posedge ~CLK[0] or negedge ~RST[0])-if (~ ~RST[0]) begin-  ~SYM[0] <= ~ARG[1];-end else begin-  ~SYM[0] <= ~ARG[2];+always_ff @(posedge ~CLK[0] or negedge ~RST[0]) begin : register_~COMPNAME_~SYM[1]+  if (~ ~RST[0]) begin+    ~SYM[0] <= ~ARG[1];+  end else begin+    ~SYM[0] <= ~ARG[2];+  end end  assign ~RESULT = ~SYM[0];"@@ -29,16 +30,17 @@     , "templateD" : "~SIGD[~SYM[0]][3]; -always_ff @(posedge ~CLK[0] or negedge ~RST[0])-if (~ ~RST[0]) begin-  ~SYM[1] <= ~ARG[1];-end else begin-  if (~ARG[2]) begin-    ~SYM[1] <= ~ARG[3];+always_ff @(posedge ~CLK[0] or negedge ~RST[0]) begin : regEn_~COMPNAME_~SYM[1]+  if (~ ~RST[0]) begin+    ~SYM[0] <= ~ARG[1];+  end else begin+    if (~ARG[2]) begin+      ~SYM[0] <= ~ARG[3];+    end   end end -assign ~RESULT = ~SYM[1];"+assign ~RESULT = ~SYM[0];"     }   }