clash-systemverilog 0.5.2 → 0.5.3

raw patch · 3 files changed

+7/−3 lines, 3 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

CHANGELOG.md +4/−0
clash-systemverilog.cabal +1/−1
primitives/CLaSH.Sized.Internal.BitVector.json +2/−2

CHANGELOG.md view

@@ -1,5 +1,9 @@ # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package +## 0.5.3 *May 5th 2015*+* Fixes bugs:+  * Incorrect implementation of rotateL and rotateR blackbox for BitVector+ ## 0.5.2 *May 1st 2015* * New features:   * Support wrapper generation

clash-systemverilog.cabal view

@@ -1,5 +1,5 @@ Name:                 clash-systemverilog-Version:              0.5.2+Version:              0.5.3 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

primitives/CLaSH.Sized.Internal.BitVector.json view

@@ -343,7 +343,7 @@ "// rotateL logic [2*~LIT[0]-1:0] ~SYM[0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2];-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"+assign ~RESULT = ~SYM[0][2*~LIT[0]-1 : ~LIT[0]];"     }   } , { "BlackBox" :@@ -353,7 +353,7 @@ "// rotateR logic [2*~LIT[0]-1:0] ~SYM[0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2];-assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0];"+assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0];"     }   } , { "BlackBox" :