diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.2 *May 1st 2015*
+* New features:
+  * Support wrapper generation
+
 ## 0.5.1 *April 20th 2015*
 * Update to clash-prelude 0.7.2
 
diff --git a/clash-systemverilog.cabal b/clash-systemverilog.cabal
--- a/clash-systemverilog.cabal
+++ b/clash-systemverilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-systemverilog
-Version:              0.5.1
+Version:              0.5.2
 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -26,6 +26,7 @@
                       CHANGELOG.md
 
 Data-files:           primitives/CLaSH.Driver.TestbenchGen.json
+                      primitives/CLaSH.Driver.TopWrapper.json
                       primitives/CLaSH.GHC.GHC2Core.json
                       primitives/CLaSH.Prelude.BlockRam.json
                       primitives/CLaSH.Prelude.Testbench.json
diff --git a/primitives/CLaSH.Driver.TopWrapper.json b/primitives/CLaSH.Driver.TopWrapper.json
new file mode 100644
--- /dev/null
+++ b/primitives/CLaSH.Driver.TopWrapper.json
@@ -0,0 +1,20 @@
+[ { "BlackBox" :
+    { "name"      : "CLaSH.TopWrapper.syncReset"
+    , "templateD" :
+"// reset ~RESULT is asynchronously asserted, but synchronously de-asserted
+~SIGD[~SYM[0]][0];
+~SIGD[~SYM[1]][0];
+
+always_ff @(posedge ~CLKO or negedge ~ARG[0])
+if (~ ~ARG[0]) begin
+  ~SYM[0] <= 1'b0;
+  ~SYM[1] <= 1'b0;
+end else begin
+  ~SYM[0] <= 1'b1;
+  ~SYM[1] <= ~SYM[0];
+end
+
+assign ~RESULT = ~SYM[1];"
+    }
+  }
+]
diff --git a/src/CLaSH/Backend/SystemVerilog.hs b/src/CLaSH/Backend/SystemVerilog.hs
--- a/src/CLaSH/Backend/SystemVerilog.hs
+++ b/src/CLaSH/Backend/SystemVerilog.hs
@@ -148,8 +148,8 @@
 tyDec _ = empty
 
 funDec :: HWType -> SystemVerilogM Doc
-funDec (Clock _) = empty
-funDec (Reset _) = empty
+funDec (Clock _ _) = empty
+funDec (Reset _ _) = empty
 funDec t =
   "function logic" <+> brackets (int (typeSize t - 1) <> colon <> int 0)  <+> verilogTypeMark t <> "_to_lv" <> parens (sigDecl "i" t) <> semi <$>
   indent 2 (verilogTypeMark t <> "_to_lv" <+> "=" <+>
@@ -166,19 +166,21 @@
 module_ :: Component -> SystemVerilogM Doc
 module_ c =
     "module" <+> text (componentName c) <> tupled ports <> semi <$>
-    indent 2 (inputPorts <$> outputPort <$$> decls (declarations c)) <$$> insts (declarations c) <$>
+    indent 2 (inputPorts <$> outputPorts <$$> decls (declarations c)) <$$> insts (declarations c) <$>
     "endmodule"
   where
     ports = sequence
-          $ [ text i | (i,_) <- inputs c ] ++
-            [ text i | (i,_) <- hiddenPorts c] ++
-            [ text (fst $ output c) ]
+          $ [ encodingNote hwty <$> text i | (i,hwty) <- inputs c ] ++
+            [ encodingNote hwty <$> text i | (i,hwty) <- hiddenPorts c] ++
+            [ encodingNote hwty <$> text i | (i,hwty) <- outputs c]
 
     inputPorts = case (inputs c ++ hiddenPorts c) of
                    [] -> empty
                    p  -> vcat (punctuate semi (sequence [ "input" <+> sigDecl (text i) ty | (i,ty) <- p ])) <> semi
 
-    outputPort = "output" <+> sigDecl (text (fst $ output c)) (snd $ output c) <> semi
+    outputPorts = case (outputs c) of
+                   [] -> empty
+                   p  -> vcat (punctuate semi (sequence [ "output" <+> sigDecl (text i) ty | (i,ty) <- p ])) <> semi
 
 verilogType :: HWType -> SystemVerilogM Doc
 verilogType t = do
@@ -188,8 +190,8 @@
     (Product _ _) -> tyName t
     Integer       -> verilogType (Signed 32)
     (Signed n)    -> "logic signed" <+> brackets (int (n-1) <> colon <> int 0)
-    (Clock _)     -> "logic"
-    (Reset _)     -> "logic"
+    (Clock _ _)   -> "logic"
+    (Reset _ _)   -> "logic"
     _             -> "logic" <+> brackets (int (typeSize t -1) <> colon <> int 0)
 
 sigDecl :: SystemVerilogM Doc -> HWType -> SystemVerilogM Doc
@@ -215,8 +217,8 @@
     prodName = do i <- tyCount <<%= (+1)
                   "product" <> int i
 tyName t@(SP _ _)        = "logic_vector_" <> int (typeSize t)
-tyName (Clock _) = "logic"
-tyName (Reset _) = "logic"
+tyName (Clock _ _) = "logic"
+tyName (Reset _ _) = "logic"
 tyName t =  error $ $(curLoc) ++ "tyName: " ++ show t
 
 -- | Convert a Netlist HWType to an error VHDL value for that type
@@ -295,6 +297,7 @@
     end      = start - argSize + 1
 
 expr_ _ (Identifier id_ (Just (Indexed (ty@(Product _ _),_,fI)))) = text id_ <> dot <> verilogTypeMark ty <> "_sel" <> int fI
+expr_ _ (Identifier id_ (Just (Indexed ((Vector _ _),_,fI)))) = text id_ <> parens (int fI)
 expr_ _ (Identifier id_ (Just (DC (ty@(SP _ _),_)))) = text id_ <> brackets (int start <> colon <> int end)
   where
     start = typeSize ty - 1
@@ -457,3 +460,8 @@
 
 punctuate' :: Monad m => m Doc -> m [Doc] -> m Doc
 punctuate' s d = vcat (punctuate s d) <> s
+
+encodingNote :: HWType -> SystemVerilogM Doc
+encodingNote (Clock _ _) = "// clock"
+encodingNote (Reset _ _) = "// asynchronous reset: active low"
+encodingNote _           = empty