clash-shake 0.2.2 → 0.3.0
raw patch · 3 files changed
+41/−11 lines, 3 filesPVP ok
version bump matches the API change (PVP)
API changes (from Hackage documentation)
- Clash.Shake: [clash] :: ClashKit -> [String] -> Action ()
+ Clash.Shake: instance GHC.Base.Monoid Clash.Shake.ClashKit
+ Clash.Shake: instance GHC.Base.Semigroup Clash.Shake.ClashKit
+ Clash.Shake: type RunClash = [String] -> Action ()
+ Clash.Shake.Intel: arrowDeca :: Target
- Clash.Shake: ClashKit :: ([String] -> Action ()) -> Action [FilePath] -> ClashKit
+ Clash.Shake: ClashKit :: Action [FilePath] -> ClashKit
- Clash.Shake: clashRules :: FilePath -> HDL -> [FilePath] -> FilePath -> [String] -> Action () -> Rules ClashKit
+ Clash.Shake: clashRules :: FilePath -> HDL -> [FilePath] -> FilePath -> [String] -> Action () -> Rules (RunClash, ClashKit)
Files
- clash-shake.cabal +1/−1
- src/Clash/Shake.hs +16/−5
- src/Clash/Shake/Intel.hs +24/−5
clash-shake.cabal view
@@ -5,7 +5,7 @@ -- see: https://github.com/sol/hpack name: clash-shake-version: 0.2.2+version: 0.3.0 synopsis: Shake rules for building Clash programs description: Shake rules for building Clash programs and synthesizing FPGA configuration. Contains build rules for Xilinx ISE, Xilinx Vivado,
src/Clash/Shake.hs view
@@ -5,7 +5,7 @@ , (|>) , useConfig- , ClashKit(..)+ , RunClash(..), ClashKit(..) , clashRules , SynthKit(..) @@ -60,17 +60,28 @@ hdlClashFlag Verilog = "--verilog" hdlClashFlag SystemVerilog = "--systemverilog" +type RunClash = [String] -> Action ()+ data ClashKit = ClashKit- { clash :: [String] -> Action ()- , manifestSrcs :: Action [FilePath]+ { manifestSrcs :: Action [FilePath] } +instance Semigroup ClashKit where+ kit <> kit' = ClashKit+ { manifestSrcs = (<>) <$> manifestSrcs kit <*> manifestSrcs kit'+ }++instance Monoid ClashKit where+ mempty = ClashKit+ { manifestSrcs = pure mempty+ }+ withWorkingDirectory :: FilePath -> IO a -> IO a withWorkingDirectory dir act = bracket Dir.getCurrentDirectory Dir.setCurrentDirectory $ \_ -> Dir.setCurrentDirectory dir >> act -clashRules :: FilePath -> HDL -> [FilePath] -> FilePath -> [String] -> Action () -> Rules ClashKit+clashRules :: FilePath -> HDL -> [FilePath] -> FilePath -> [String] -> Action () -> Rules (RunClash, ClashKit) clashRules outDir hdl srcDirs src clashFlags extraGenerated = do let clash args = liftIO $ do let srcFlags = ["-i" <> srcDir | srcDir <- srcDirs]@@ -122,7 +133,7 @@ extraGenerated clash [hdlClashFlag hdl, src] - return ClashKit{..}+ return (clash, ClashKit{..}) data SynthKit = SynthKit { bitfile :: FilePath
src/Clash/Shake/Intel.hs view
@@ -1,6 +1,8 @@ {-# LANGUAGE OverloadedStrings, RecordWildCards, TemplateHaskell #-} module Clash.Shake.Intel- ( Target(..), de0Nano+ ( Target(..)+ , de0Nano, arrowDeca+ , quartus ) where @@ -32,6 +34,9 @@ de0Nano :: Target de0Nano = Target "Cyclone IV E" "EP4CE22F17C6" +arrowDeca :: Target+arrowDeca = Target "MAX 10" "10M50DAF484C6GES"+ quartus :: Target -> ClashKit -> FilePath -> FilePath -> String -> Rules SynthKit quartus fpga kit@ClashKit{..} outDir srcDir topName = do let projectName = topName@@ -72,7 +77,9 @@ let src = srcDir </> makeRelative outDir out copyFileChanged src out - outDir </> topName <.> "sof" %> \_out -> do+ let bitfile = outDir </> topName <.> "sof"++ bitfile %> \_out -> do srcs1 <- manifestSrcs srcs2 <- hdlSrcs cores <- ipCores@@ -84,11 +91,23 @@ ] quartus "quartus_sh" ["-t", projectName <.> "tcl"] + outDir </> topName <.> "rbf" %> \out -> do+ let sof = out -<.> "sof"+ need [sof]+ quartus "quartus_cpf"+ [ "--option=bitstream_compression=off"+ , "-c", makeRelative outDir sof+ , makeRelative outDir out+ ]+ return $ SynthKit- { bitfile = outDir </> topName <.> "sof"+ { bitfile = bitfile , phonies = [ "quartus" |> do- need [outDir </> projectName <.> "tcl"]- quartus "quartus_sh" ["-t", outDir </> projectName <.> "tcl"]+ need [outDir </> projectName <.> "tcl"]+ quartus "quartus_sh" ["-t", projectName <.> "tcl"]+ , "upload" |> do+ need [bitfile]+ quartus "quartus_pgm" ["-m", "jtag", "-o", "p;" <> makeRelative outDir bitfile] ] }