clash-prelude 0.9.1 → 0.9.2

raw patch · 8 files changed

+37/−24 lines, 8 filesPVP: major bump suggested

API removals or changes: PVP suggests a major version bump

API changes (from Hackage documentation)

Files

• CHANGELOG.md +3/−0
• clash-prelude.cabal +1/−1
• src/CLaSH/Examples.hs +3/−3
• src/CLaSH/Prelude/BlockRam.hs +6/−6
• src/CLaSH/Prelude/RAM.hs +2/−2
• src/CLaSH/Signal/Internal.hs +6/−0
• src/CLaSH/Sized/Vector.hs +5/−5
• src/CLaSH/Tutorial.hs +11/−7

@@ -1,5 +1,8 @@ # Changelog for [`clash-prelude` package](http://hackage.haskell.org/package/clash-prelude) +## 0.9.2 *August 2nd 2015*+* Disable strictness analysis in `CLaSH.Signal.Internal`, this allows turning on strictness analysis in the GHC front-end of the CLaSH compiler.+ ## 0.9.1 *June 26th 2015* * Updated documentation on data-file support on Altera/Quartus 

@@ -1,5 +1,5 @@ Name:                 clash-prelude-Version:              0.9.1+Version:              0.9.2 Synopsis:             CAES Language for Synchronous Hardware - Prelude library Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that

@@ -350,7 +350,7 @@  The following property holds: -prop> decoderShift enable binaryIn === decoderCase enable binaryIn+prop> \enable binaryIn -> decoderShift enable binaryIn === decoderCase enable binaryIn  = Encoder @@ -381,7 +381,7 @@  The following property holds: -prop> en ==> (encoderCase en (decoderCase en decIn) === decIn)+prop> \en decIn -> en ==> (encoderCase en (decoderCase en decIn) === decIn) -}  {- $counters@@ -424,7 +424,7 @@  The following property holds: -prop> en ==> testFor 1000 (upCounter (signal en) .==. upDownCounter (signal en))+prop> \en -> en ==> testFor 1000 (upCounter (signal en) .==. upDownCounter (signal en))  = LFSR 

@@ -84,7 +84,7 @@     -> ( Vec 7 Value        , (MemAddr,MemAddr,Bool,Value,InstrAddr)        )-cpu regbank (memOut,instr) = ((regbank',(rdAddr,wrAddr,wrEn,aluOut,fromIntegral ipntr))+cpu regbank (memOut,instr) = (regbank',(rdAddr,wrAddr,wrEn,aluOut,fromIntegral ipntr))   where     -- Current instruction pointer     ipntr = regbank '!!' PC@@ -146,7 +146,7 @@ system instrs = memOut   where     memOut = dataMem wrAddr rdAddr wrEn aluOut-    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'CLaSH.Prelude.Mealy.mealyB' cpu (('replicate' d7 0),Zero) (memOut,instr)+    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'CLaSH.Prelude.Mealy.mealyB' cpu ('replicate' d7 0) (memOut,instr)     instr  = 'CLaSH.Prelude.ROM.asyncRom' instrs '<$>' ipntr @ @@ -207,7 +207,7 @@ system2 instrs = memOut   where     memOut = 'CLaSH.Prelude.RAM.asyncRam' d32 wrAddr rdAddr wrEn aluOut-    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'mealyB' cpu (('replicate' d7 0),Zero) (memOut,instr)+    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'mealyB' cpu ('replicate' d7 0) (memOut,instr)     instr  = 'CLaSH.Prelude.ROM.asyncRom' instrs '<$>' ipntr @ @@ -247,7 +247,7 @@      -> ( (Vec 7 Value,Reg)         , (MemAddr,MemAddr,Bool,Value,InstrAddr)         )-cpu2 (regbank,ldRegD) (memOut,instr) = (((regbank',ldRegD'),(rdAddr,wrAddr,wrEn,aluOut,fromIntegral ipntr))+cpu2 (regbank,ldRegD) (memOut,instr) = ((regbank',ldRegD'),(rdAddr,wrAddr,wrEn,aluOut,fromIntegral ipntr))   where     -- Current instruction pointer     ipntr = regbank '!!' PC@@ -287,7 +287,7 @@ system3 instrs = memOut   where     memOut = 'blockRam' (replicate d32 0) wrAddr rdAddr wrEn aluOut-    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'mealyB' cpu (('replicate' d7 0),Zero) (memOut,instr)+    (rdAddr,wrAddr,wrEn,aluOut,ipntr) = 'mealyB' cpu2 (('replicate' d7 0),Zero) (memOut,instr)     instr  = 'CLaSH.Prelude.ROM.asyncRom' instrs '<$>' ipntr @ @@ -336,7 +336,7 @@ also 'undefined'.  @-__>>> L.take 33 $ L.tail $ sample $ system3 prog2__+__>>> L.take 32 $ L.tail $ sample $ system3 prog2__ [4,4,4,4,4,4,4,4,4,6,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,2] @ 

@@ -49,7 +49,7 @@ -- -- * See "CLaSH.Prelude.BlockRam#usingrams" for more information on how to use a -- RAM.-asyncRam :: (KnownNat n, Enum addr)+asyncRam :: Enum addr          => SNat n      -- ^ Size @n@ of the RAM          -> Signal addr -- ^ Write address @w@          -> Signal addr -- ^ Read address @r@@@ -108,7 +108,7 @@ -- -- * See "CLaSH.Prelude.BlockRam#usingrams" for more information on how to use a -- RAM.-asyncRam' :: (KnownNat n, Enum addr)+asyncRam' :: Enum addr           => SClock wclk       -- ^ 'Clock' to which to synchronise the write                                -- port of the RAM           -> SClock rclk       -- ^ 'Clock' to which the read address signal,

@@ -10,6 +10,12 @@  {-# LANGUAGE Unsafe #-} +-- Until we have a -fcpr-off DynFlag (it currently exists only as a StaticFlag),+-- we just disable strictness analysis for this module completely. See+-- https://github.com/clash-lang/clash-compiler/commit/721fcfa9198925661cd836668705f817bddaae3c+-- for more details+{-# OPTIONS_GHC -fno-strictness #-}+ {-# OPTIONS_HADDOCK show-extensions #-}  {-|

@@ -1140,12 +1140,12 @@ -- >>> let append' xs ys = foldr (:>) ys xs -- <BLANKLINE> -- <interactive>:...---     Occurs check: cannot construct the infinite type: n1 ~ n1 + 1---     Expected type: a -> Vec n1 a -> Vec n1 a---       Actual type: a -> Vec n1 a -> Vec (n1 + 1) a+--     Occurs check: cannot construct the infinite type: ... ~ ... + 1+--     Expected type: a -> Vec ... a -> Vec ... a+--       Actual type: a -> Vec ... a -> Vec (... + 1) a --     Relevant bindings include---       ys :: Vec n1 a (bound at ...)---       append' :: Vec n a -> Vec n1 a -> Vec n1 a+--       ys :: Vec ... a (bound at ...)+--       append' :: Vec n a -> Vec ... a -> Vec ... a --         (bound at ...) --     In the first argument of ‘foldr’, namely ‘(:>)’ --     In the expression: foldr (:>) ys xs

@@ -39,7 +39,7 @@   -- * Composition of sequential circuits   -- $composition_sequential -  -- * TopEntity annotations: controlling the VHDL\/Verilog\/SystemVerilog generation.+  -- * TopEntity annotations: controlling the VHDL\/(System)Verilog generation.   -- $annotations    -- * Multiple clock domains@@ -167,7 +167,7 @@        * Make sure that the @bin@ directory of __GHC__ is in your @PATH@. -    The following are alternative options, if the cannot find what you are looking for on <http://www.haskell.org/ghc/download>+    The following are alternative options, if you cannot find what you are looking for on <http://www.haskell.org/ghc/download>        * Ubuntu: @@ -180,7 +180,7 @@        * OS X: -          * Follow the instructions on: <https://ghcformacosx.github.io/ Haskell for Max OS X>+          * Follow the instructions on: <https://ghcformacosx.github.io/ Haskell for Mac OS X>           * Run: @cabal update@           * Skip step 2. @@ -212,7 +212,11 @@    (2) Install __CλaSH__ -      * Run @cabal install clash-ghc --enable-documentation@+      * Run:++          * /i386/ Linux: @cabal install clash-ghc --enable-documentation --enable-executable-dynamic@+          * Other: @cabal install clash-ghc --enable-documentation@+       * /This is going to take awhile, so have a refreshment/    (4) Verify that everything is working by:@@ -239,7 +243,7 @@ @  For those familiar with Haskell/GHC, this is indeed just @GHCi@, with three-added command (@:vhdl@, @:verilog@, and @:systemverilog@). You can load files+added commands (@:vhdl@, @:verilog@, and @:systemverilog@). You can load files into the interpreter using the @:l \<FILENAME\>@ command. Now, depending on your choice in editor, the following @edit-load-run@ cycle probably work best for you: @@ -783,7 +787,7 @@  We can exert some control how the top level function is created by the CλaSH compiler by annotating the @topEntity@ function with a 'TopEntity' annotation.-You apply these annotation using the @ANN@ pragma like so:+You apply these annotations using the @ANN@ pragma like so:  @ {\-\# ANN topEntity (TopEntity {t_name = ..., ...  }) \#-\}@@ -858,7 +862,7 @@     , t_extraIn  = [ (\"CLOCK_50\", 1)                    , (\"KEY0\"    , 1)                    ]-    , t_clocks   = [ 'defClkAltera' "altpll50" "CLOCK_50(0)" "not KEY0(0)" ]+    , t_clocks   = [ 'altpll' "altpll50" "CLOCK_50(0)" "not KEY0(0)" ]     }) \#-\} @