diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,8 +1,30 @@ # Changelog for the Clash project -## 1.2.2 *June 12th 2020* +## 1.2.3 *July 11th 2020* +* Changed: + * Upgrade to nixos 20.03. Nix and snap users will now use packages present in 20.03. +* Added: + * `instance Monoid a => Monoid (Vec n a)` + * `instance Text.Printf(Index)` + * `instance Text.Printf(Signed)` + * `instance Text.Printf(Unsigned)` +* Fixed: + * Clash renders incorrect VHDL when GHCs Worker/Wrapper transformation is enabled [#1402](https://github.com/clash-lang/clash-compiler/issues/14020) + * Minor faults in generated HDL when using annotations from `Clash.Annotations.SynthesisAttributes` + * Cabal installed through Snap (`clash.cabal`) can now access the internet to fetch pacakges. [#1411]https://github.com/clash-lang/clash-compiler/issues/1411 + * Generated QSys file for `altpll` incompatible with Quartus CLI (did work in Quartus GUI) + * Clash no longer uses component names that clash with identifiers imported + from: + * IEEE.STD_LOGIC_1164.all + * IEEE.NUMERIC_STD.all + * IEEE.MATH_REAL.all + * std.textio.all + when generating VHDL. + See https://github.com/clash-lang/clash-compiler/issues/1439. + +## 1.2.2 *June 12th 2020* * Changed: * The hardwired functions to unroll primitive definitions for 'zipWith', 'map', 'foldr', and 'init' have been changed to only unroll a single step, whereas they would previously unroll the whole definition in one step. This allows Clash to take advantage of the lazy nature of these functions, in turn speeding up compilation speeds significantly in some cases. Part of [PR 1354](https://github.com/clash-lang/clash-compiler/pull/1354). diff --git a/clash-lib.cabal b/clash-lib.cabal --- a/clash-lib.cabal +++ b/clash-lib.cabal @@ -1,6 +1,6 @@ Cabal-version: 2.2 Name: clash-lib -Version: 1.2.2 +Version: 1.2.3 Synopsis: CAES Language for Synchronous Hardware - As a Library Description: Clash is a functional hardware description language that borrows both its @@ -141,7 +141,7 @@ base >= 4.11 && < 5, binary >= 0.8.5 && < 0.11, bytestring >= 0.10.0.2 && < 0.11, - clash-prelude == 1.2.2, + clash-prelude == 1.2.3, concurrent-supply >= 0.1.7 && < 0.2, containers >= 0.5.0.0 && < 0.7, data-binary-ieee754 >= 0.4.4 && < 0.6, diff --git a/src/Clash/Backend/VHDL.hs b/src/Clash/Backend/VHDL.hs --- a/src/Clash/Backend/VHDL.hs +++ b/src/Clash/Backend/VHDL.hs @@ -227,6 +227,45 @@ timeUnits :: [Identifier] timeUnits = ["fs", "ps", "ns", "us", "ms", "sec", "min", "hr"] +-- | Identifiers which are imported from the following: +-- +-- use IEEE.STD_LOGIC_1164.ALL; +-- use IEEE.NUMERIC_STD.ALL; +-- use IEEE.MATH_REAL.ALL; +-- use std.textio.all; +-- +-- Clash should not use these identifiers, as it can lead to errors when +-- interfacing with an EDA tool. +-- +-- See https://github.com/clash-lang/clash-compiler/issues/1439. +-- +importedNames :: [Identifier] +importedNames = + [ -- ieee.std_logic_1164.all + "std_ulogic", "std_ulogic_vector", "resolved", "std_logic", "std_logic_vector" + , "x01", "x01z", "ux01", "ux01z", "to_bit", "to_bitvector", "to_stdulogic" + , "to_stdlogicvector", "to_stdulogicvector", "to_01", "to_x01", "to_x01z" + , "to_ux01", "rising_edge", "falling_edge", "is_x" + -- ieee.numeric_std.all + , "unresolved_unsigned", "unresolved_signed", "u_unsigned", "u_signed" + , "unsigned", "signed", "find_leftmost", "find_rightmost", "minimum" + , "maximum", "shift_left", "shift_right", "rotate_left", "rotate_right" + , "resize", "to_integer", "to_unsigned", "to_signed", "std_match" + -- ieee.math_real.all + , "math_e", "math_1_over_e", "math_pi", "math_2_pi", "math_1_over_pi" + , "math_pi_over_2", "math_pi_over_3", "path_pi_over_4", "path_3_pi_over_2" + , "math_log_of_2", "math_log_of_10", "math_log10_of_e", "math_sqrt_2" + , "math_1_over_sqrt_2", "math_sqrt_pi", "math_deg_to_rad", "math_rad_to_deg" + , "sign", "ceil", "floor", "round", "trunc", "realmax", "realmin", "uniform" + , "sqrt", "cbrt", "exp", "log", "log2", "log10", "sin", "cos", "tan", "arcsin" + , "arccos", "arctan", "sinh", "cosh", "tanh", "arcsinh", "arccosh", "arctanh" + -- std.textio.all + , "line", "text", "side", "width", "justify", "input", "output", "readline" + , "read", "sread", "string_read", "bread", "binary_read", "oread", "octal_read" + , "hread", "hex_read", "writeline", "tee", "write", "swrite", "string_write" + , "bwrite", "binary_write", "owrite", "octal_write", "hwrite", "hex_write" + ] + -- List of reserved VHDL-2008 keywords -- + used internal names: toslv, fromslv, tagtoenum, datatotag -- + used IEEE library names: integer, boolean, std_logic, std_logic_vector, @@ -247,7 +286,7 @@ ,"unaffected","units","until","use","variable","vmode","vprop","vunit","wait" ,"when","while","with","xnor","xor","toslv","fromslv","tagtoenum","datatotag" ,"integer", "boolean", "std_logic", "std_logic_vector", "signed", "unsigned" - ,"to_integer", "to_signed", "to_unsigned", "string","log"] ++ timeUnits + ,"to_integer", "to_signed", "to_unsigned", "string","log"] ++ timeUnits ++ importedNames filterReserved :: Identifier -> Identifier filterReserved s = if s `elem` reservedWords @@ -959,7 +998,7 @@ -- | Convert single attribute to VHDL syntax renderAttr :: Attr' -> T.Text -renderAttr (StringAttr' _key value) = T.pack $ show value +renderAttr (StringAttr' _key value) = T.replace "\\\"" "\"\"" $ T.pack $ show value renderAttr (IntegerAttr' _key value) = T.pack $ show value renderAttr (BoolAttr' _key True ) = T.pack $ "true" renderAttr (BoolAttr' _key False) = T.pack $ "false" @@ -976,6 +1015,7 @@ Unsigned n -> baseType <> parens (int (n-1) <+> "downto 0") Vector n _ -> baseType <> parens ("0 to" <+> int (n-1)) RTree d _ -> baseType <> parens ("0 to" <+> int ((2^d)-1)) + Annotated _ elTy -> appendSize baseType elTy _ -> baseType -- | Same as @qualTyName@, but instantiate generic types with their size. @@ -1846,6 +1886,7 @@ encodingNote :: HWType -> VHDLM Doc encodingNote (Clock _) = "-- clock" <> line encodingNote (Reset _ ) = "-- reset" <> line +encodingNote (Annotated _ t) = encodingNote t encodingNote _ = emptyDoc tupledSemi :: Applicative f => f [Doc] -> f Doc @@ -2193,7 +2234,7 @@ -- These mask projections always come last, so it's safe not to return a -- modified name, but an expression instead. traceIf True ($(curLoc) ++ "WARNING: rendering bitvector mask as dontcare") $ - sizedQualTyNameErrValue (Signed iw) + sizedQualTyNameErrValue (Unsigned iw) renderModifier (Range r,t) doc = do nm <- Mon (use modNm) let doc1 = case r of diff --git a/src/Clash/Backend/Verilog.hs b/src/Clash/Backend/Verilog.hs --- a/src/Clash/Backend/Verilog.hs +++ b/src/Clash/Backend/Verilog.hs @@ -333,6 +333,7 @@ Bit -> emptyDoc Bool -> emptyDoc FileType -> emptyDoc + Annotated _ ty -> verilogType ty _ -> brackets (int (typeSize t -1) <> colon <> int 0) sigDecl :: VerilogM Doc -> HWType -> VerilogM Doc @@ -1211,4 +1212,5 @@ encodingNote :: Applicative m => HWType -> m Doc encodingNote (Clock _) = string " // clock" encodingNote (Reset _) = string " // reset" +encodingNote (Annotated _ t) = encodingNote t encodingNote _ = emptyDoc diff --git a/src/Clash/Netlist.hs b/src/Clash/Netlist.hs --- a/src/Clash/Netlist.hs +++ b/src/Clash/Netlist.hs @@ -691,7 +691,7 @@ toSimpleVar :: Identifier -> (Expr,Type) -> NetlistMonad (Expr,[Declaration]) -toSimpleVar _ (e@(Identifier _ _),_) = return (e,[]) +toSimpleVar _ (e@(Identifier _ Nothing),_) = return (e,[]) toSimpleVar dstId (e,ty) = do argNm <- extendIdentifier Extended dstId diff --git a/src/Clash/Primitives/Intel/ClockGen.hs b/src/Clash/Primitives/Intel/ClockGen.hs --- a/src/Clash/Primitives/Intel/ClockGen.hs +++ b/src/Clash/Primitives/Intel/ClockGen.hs @@ -185,7 +185,54 @@ - PT#EFF_OUTPUT_FREQ_VALUE0 #{clkOutFreq} + + CT#PORT_clk0 PORT_USED + CT#CLK0_MULTIPLY_BY #{clkmult} + CT#WIDTH_CLOCK 5 + CT#LPM_TYPE altpll + CT#PLL_TYPE AUTO + CT#CLK0_PHASE_SHIFT 0 + CT#OPERATION_MODE NORMAL + CT#COMPENSATE_CLOCK CLK0 + CT#INCLK0_INPUT_FREQUENCY #{clkInPeriod} + CT#PORT_INCLK0 PORT_USED + CT#PORT_ARESET PORT_USED + CT#BANDWIDTH_TYPE AUTO + CT#CLK0_DUTY_CYCLE 50 + CT#CLK0_DIVIDE_BY #{clkdiv} + CT#PORT_LOCKED PORT_USED + + IF#phasecounterselect {input 4} + IF#locked {output 0} + IF#reset {input 0} + IF#clk {input 0} + IF#phaseupdown {input 0} + IF#scandone {output 0} + IF#readdata {output 32} + IF#write {input 0} + IF#scanclk {input 0} + IF#phasedone {output 0} + IF#address {input 2} + IF#c0 {output 0} + IF#writedata {input 32} + IF#read {input 0} + IF#areset {input 0} + IF#scanclkena {input 0} + IF#scandataout {output 0} + IF#configupdate {input 0} + IF#phasestep {input 0} + IF#scandata {input 0} + + MF#areset 1 + MF#clk 1 + MF#locked 1 + MF#inclk 1 + + PT#PHASE_SHIFT0 0.00000000 + PT#DIV_FACTOR0 #{clkdiv} + PT#EFF_OUTPUT_FREQ_VALUE0 #{clkOutFreq} + PT#MULT_FACTOR0 #{clkmult} + PT#DUTY_CYCLE0 50.00000000 |]