diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,9 @@ # Changelog for the [`clash-lib`](http://hackage.haskell.org/package/clash-lib) package +## 0.99.1 *May 12th 2018* +* Allow `~NAME[N]` tag inside `~GENSYM[X]` +* Support HDL record selector generation [#313](https://github.com/clash-lang/clash-compiler/pull/313) + ## 0.99 *March 31st 2018* * New features: * Support for `clash-prelude-0.99`: diff --git a/clash-lib.cabal b/clash-lib.cabal --- a/clash-lib.cabal +++ b/clash-lib.cabal @@ -1,5 +1,5 @@ Name: clash-lib -Version: 0.99 +Version: 0.99.1 Synopsis: CAES Language for Synchronous Hardware - As a Library Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that @@ -96,7 +96,7 @@ TupleSections ViewPatterns - Build-depends: aeson >= 0.6.2.0 && < 1.3, + Build-depends: aeson >= 0.6.2.0 && < 1.4, ansi-wl-pprint >= 0.6.8.2 && < 1.0, attoparsec >= 0.10.4.0 && < 0.14, base >= 4.8 && < 5, @@ -107,7 +107,7 @@ data-binary-ieee754 >= 0.4.4 && < 0.6, deepseq >= 1.3.0.2 && < 1.5, directory >= 1.2.0.1 && < 1.4, - errors >= 1.4.2 && < 2.3, + errors >= 1.4.2 && < 2.4, fgl >= 5.4.2.4 && < 5.7, filepath >= 1.3.0.1 && < 1.5, ghc >= 8.0.2 && < 8.6, diff --git a/src/Clash/Backend.hs b/src/Clash/Backend.hs --- a/src/Clash/Backend.hs +++ b/src/Clash/Backend.hs @@ -65,6 +65,8 @@ hdlTypeErrValue :: HWType -> Mon (State state) Doc -- | Convert a Netlist HWType to the root of a target HDL type hdlTypeMark :: HWType -> Mon (State state) Doc + -- | Create a record selector + hdlRecSel :: HWType -> Int -> Mon (State state) Doc -- | Create a signal declaration from an identifier (Text) and Netlist HWType hdlSig :: Text -> HWType -> Mon (State state) Doc -- | Create a generative block statement marker diff --git a/src/Clash/Backend/SystemVerilog.hs b/src/Clash/Backend/SystemVerilog.hs --- a/src/Clash/Backend/SystemVerilog.hs +++ b/src/Clash/Backend/SystemVerilog.hs @@ -99,6 +99,7 @@ hdlType _ = verilogType hdlTypeErrValue = verilogTypeErrValue hdlTypeMark = verilogTypeMark + hdlRecSel = verilogRecSel hdlSig t ty = sigDecl (string t) ty genStmt True = do cnt <- use genDepth genDepth += 1 @@ -630,6 +631,12 @@ _ -> char '\'' <> braces (int (2^n) <+> braces (verilogTypeErrValue elTy)) verilogTypeErrValue String = "\"ERROR\"" verilogTypeErrValue ty = braces (int (typeSize ty) <+> braces "1'bx") + +verilogRecSel + :: HWType + -> Int + -> SystemVerilogM Doc +verilogRecSel ty i = tyName ty <> "_sel" <> int i decls :: [Declaration] -> SystemVerilogM Doc decls [] = emptyDoc diff --git a/src/Clash/Backend/VHDL.hs b/src/Clash/Backend/VHDL.hs --- a/src/Clash/Backend/VHDL.hs +++ b/src/Clash/Backend/VHDL.hs @@ -97,6 +97,7 @@ _ -> vhdlType ty hdlTypeErrValue = vhdlTypeErrValue hdlTypeMark = vhdlTypeMark + hdlRecSel = vhdlRecSel hdlSig t ty = sigDecl (pretty t) ty genStmt = const emptyDoc inst = inst_ @@ -705,6 +706,12 @@ vhdlTypeErrValue (Void {}) = "std_logic_vector'(0 downto 1 => '-')" vhdlTypeErrValue String = "\"ERROR\"" vhdlTypeErrValue t = vhdlTypeMark t <> "'" <> parens (int 0 <+> "to" <+> int (typeSize t - 1) <+> rarrow <+> "'-'") + +vhdlRecSel + :: HWType + -> Int + -> VHDLM Doc +vhdlRecSel ty i = tyName ty <> "_sel" <> int i decls :: [Declaration] -> VHDLM Doc decls [] = emptyDoc diff --git a/src/Clash/Backend/Verilog.hs b/src/Clash/Backend/Verilog.hs --- a/src/Clash/Backend/Verilog.hs +++ b/src/Clash/Backend/Verilog.hs @@ -90,6 +90,7 @@ hdlType _ = verilogType hdlTypeErrValue = verilogTypeErrValue hdlTypeMark = verilogTypeMark + hdlRecSel = verilogRecSel hdlSig t ty = sigDecl (string t) ty genStmt True = do cnt <- use genDepth genDepth += 1 @@ -295,6 +296,14 @@ -- | Convert a Netlist HWType to an error VHDL value for that type verilogTypeErrValue :: HWType -> VerilogM Doc verilogTypeErrValue ty = braces (int (typeSize ty) <+> braces "1'bx") + +verilogRecSel + :: HWType + -> Int + -> VerilogM Doc +verilogRecSel ty i = case modifier 0 (Indexed (ty,0,i)) of + Just (start,end) -> brackets (int start <> colon <> int end) + _ -> error "Can't make a record selector" decls :: [Declaration] -> VerilogM Doc decls [] = emptyDoc diff --git a/src/Clash/Netlist/BlackBox/Parser.hs b/src/Clash/Netlist/BlackBox/Parser.hs --- a/src/Clash/Netlist/BlackBox/Parser.hs +++ b/src/Clash/Netlist/BlackBox/Parser.hs @@ -98,6 +98,7 @@ <|> (HdlSyn Other) <$ string "~OTHERSYN" <|> (BV True) <$> (string "~TOBV" *> brackets' pSigD) <*> brackets' pTagE <|> (BV False) <$> (string "~FROMBV" *> brackets' pSigD) <*> brackets' pTagE + <|> Sel <$> (string "~SEL" *> brackets' pTagE) <*> brackets' natural' <|> IsLit <$> (string "~ISLIT" *> brackets' natural') <|> IsVar <$> (string "~ISVAR" *> brackets' natural') <|> IsGated <$> (string "~ISGATED" *> brackets' natural') diff --git a/src/Clash/Netlist/BlackBox/Types.hs b/src/Clash/Netlist/BlackBox/Types.hs --- a/src/Clash/Netlist/BlackBox/Types.hs +++ b/src/Clash/Netlist/BlackBox/Types.hs @@ -47,6 +47,7 @@ | HdlSyn HdlSyn -- ^ Hole indicating which synthesis tool we're -- generating HDL for | BV !Bool [Element] !Element -- ^ Convert to (True)/from(False) a bit-vector + | Sel !Element !Int -- ^ Record selector of a type | IsLit !Int | IsVar !Int | IsGated !Int diff --git a/src/Clash/Netlist/BlackBox/Util.hs b/src/Clash/Netlist/BlackBox/Util.hs --- a/src/Clash/Netlist/BlackBox/Util.hs +++ b/src/Clash/Netlist/BlackBox/Util.hs @@ -139,6 +139,9 @@ . map (\case { C t -> t ; O _ | Identifier t _ <- fst (bbResult bbCtx) -> t + ; N n | let (e,_,_) = bbInputs bbCtx !! n + , Just t <- exprToText e + -> t ; _ -> error "unexpected element in GENSYM"}) setCompName :: Identifier -> BlackBoxTemplate -> BlackBoxTemplate @@ -427,6 +430,10 @@ let ty = lineToType b [e] renderOneLine <$> getMon (fromBV ty e') +renderTag b (Sel e n) = + let ty = lineToType b [e] + in renderOneLine <$> getMon (hdlRecSel ty n) + renderTag b (Typ Nothing) = fmap renderOneLine . getMon . hdlType Internal . snd $ bbResult b renderTag b (Typ (Just n)) = let (_,ty,_) = bbInputs b !! n in renderOneLine <$> getMon (hdlType Internal ty) @@ -574,6 +581,9 @@ if b then string "~TOBV" <> brackets (string es') <> brackets (string e') else string "~FROMBV" <> brackets (string es') <> brackets (string e') +prettyElem (Sel e i) = do + e' <- prettyElem e + renderOneLine <$> (string "~SEL" <> brackets (string e') <> brackets (int i)) prettyElem (IsLit i) = renderOneLine <$> (string "~ISLIT" <> brackets (int i)) prettyElem (IsVar i) = renderOneLine <$> (string "~ISVAR" <> brackets (int i)) prettyElem (IsGated i) = renderOneLine <$> (string "~ISGATED" <> brackets (int i)) @@ -609,4 +619,5 @@ SigD es _ -> usedArguments es BV _ es _ -> usedArguments es StrCmp _ i -> [i] + GenSym es _ -> usedArguments es _ -> [] diff --git a/src/Clash/Primitives/Types.hs b/src/Clash/Primitives/Types.hs --- a/src/Clash/Primitives/Types.hs +++ b/src/Clash/Primitives/Types.hs @@ -38,7 +38,8 @@ , imports :: [a] -- ^ VHDL only: add /use/ declarations for the given names , include :: Maybe ((S.Text,S.Text),a) - -- ^ Intel/Quartus only: create a /.qsys/ file from the given template. + -- ^ Create a file to be included with the generated primitive. The fields + -- are ((name, extension), content), where content is a template of the file -- Defaults to @Nothing@ when not specified in the /.json/ file , template :: !(Either a a) -- ^ Either a /declaration/ or an /expression/ template. }