diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,11 @@
 # Changelog for the [`clash-lib`](http://hackage.haskell.org/package/clash-lib) package
 
+## 0.6.14 *March 21st 2016*
+* New features:
+  * Also generate testbench for circuits without input ports [#135](https://github.com/clash-lang/clash-compiler/issues/135)
+* Fixes bugs:
+  * `clockWizard` broken [#49](https://github.com/clash-lang/clash-prelude/issues/49)
+
 ## 0.6.13 *March 14th 2016*
 * Fixes bugs:
   * Not all lambda's in a function position removed
diff --git a/clash-lib.cabal b/clash-lib.cabal
--- a/clash-lib.cabal
+++ b/clash-lib.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-lib
-Version:              0.6.13
+Version:              0.6.14
 Synopsis:             CAES Language for Synchronous Hardware - As a Library
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
diff --git a/src/CLaSH/Driver/TestbenchGen.hs b/src/CLaSH/Driver/TestbenchGen.hs
--- a/src/CLaSH/Driver/TestbenchGen.hs
+++ b/src/CLaSH/Driver/TestbenchGen.hs
@@ -20,7 +20,8 @@
 import qualified Data.HashMap.Lazy                as HashMap
 import           Data.IntMap.Strict               (IntMap)
 import           Data.List                        (find,nub)
-import           Data.Maybe                       (catMaybes,mapMaybe)
+import           Data.Maybe                       (catMaybes,listToMaybe,
+                                                   mapMaybe)
 import           Data.Text.Lazy                   (append,pack)
 import           Unbound.Generics.LocallyNameless (name2String)
 
@@ -60,16 +61,21 @@
              -> Component                    -- ^ Component to generate TB for
              -> IO ([Component],[(String,FilePath)])
 genTestBench opts supply primMap typeTrans tcm tupTcm eval mkId seen globals stimuliNmM expectedNmM modName dfiles
-  (Component cName hidden [inp] [outp] _) = do
-  let iw      = opt_intWidth opts
-      ioDecl  = [ uncurry NetDecl inp
-                , uncurry NetDecl outp
-                ]
-      inpExpr = Assignment (fst inp) (BlackBoxE "" [Err Nothing] (emptyBBContext {bbResult = (undefined,snd inp)}) False)
-  (inpInst,inpComps,seen',hidden',dfiles') <- maybe (return (inpExpr,[],seen,hidden,dfiles))
-      (genStimuli seen primMap globals typeTrans mkId tcm normalizeSignal hidden inp modName dfiles iw)
-      stimuliNmM
+  c@(Component cName hidden inps [outp] _) = do
+  let inpM    = listToMaybe inps
+      iw      = opt_intWidth opts
+      ioDecl  = maybe [] ((:[]) . uncurry NetDecl) inpM ++
+                [uncurry NetDecl outp]
 
+  (inpInstM,inpComps,seen',hidden',dfiles') <- case inpM of
+    Just inp -> case stimuliNmM of
+      Just stimuliNm
+              -> (\(v,w,x,y,z) -> (Just v,w,x,y,z)) <$>
+                 genStimuli seen primMap globals typeTrans mkId tcm normalizeSignal hidden inp modName dfiles iw stimuliNm
+      Nothing -> let inpExpr = Assignment (fst inp) (BlackBoxE "" [Err Nothing] (emptyBBContext {bbResult = (undefined,snd inp)}) False)
+                 in  return (Just inpExpr,[],seen,hidden,dfiles)
+    Nothing   -> return (Nothing,[],seen,hidden,dfiles)
+
   ((finDecl,finExpr),s) <- runNetlistMonad globals primMap tcm typeTrans modName dfiles' iw mkId ("finished":"done":seen') $ do
       done    <- genDone primMap
       let finDecl' = [ NetDecl "finished" Bool
@@ -93,7 +99,7 @@
 
   let instDecl = InstDecl cName "totest"
                    (map (\(i,t) -> (i,In,t,Identifier i Nothing))
-                        (concat [ clkNms, rstNms, [inp] ])
+                        (concat [ clkNms, rstNms, maybe [] (:[]) inpM ])
                    ++
                    [(\(i,t) -> (i,Out,t,Identifier i Nothing)) outp])
 
@@ -102,10 +108,12 @@
                           , concat clks
                           , concat rsts
                           , ioDecl
-                          , [instDecl,inpInst,expInst]
+                          , catMaybes [Just instDecl,inpInstM,Just expInst]
                           ])
 
-  return (tbComp:(inpComps++expComps),dfiles'')
+  case inps of
+    (_:_:_) -> traceIf (opt_dbgLevel opts > DebugNone) ("Can't make testbench for: " ++ show c) $ return ([],dfiles)
+    _ -> return (tbComp:(inpComps++expComps),dfiles'')
   where
     normalizeSignal :: HashMap TmName (Type,Term)
                     -> TmName
diff --git a/src/CLaSH/Driver/TopWrapper.hs b/src/CLaSH/Driver/TopWrapper.hs
--- a/src/CLaSH/Driver/TopWrapper.hs
+++ b/src/CLaSH/Driver/TopWrapper.hs
@@ -249,7 +249,7 @@
 clockPorts inp outp = (inPorts ++ outPorts,clks)
   where
     inPorts  = map (\(i,e) -> (pack i,In,Clock "" 0,stringToVar e)) inp
-    outPorts = map (\(i,e) -> (pack i,Out,Clock "" 0,stringToVar e)) inp
+    outPorts = map (\(i,e) -> (pack i,Out,Clock "" 0,stringToVar e)) outp
     clks  = map snd outp
 
 -- | Generate resets