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clash-lib 0.5.7 → 0.5.8

raw patch · 6 files changed

+26/−8 lines, 6 filesPVP: major bump suggested

API removals or changes: PVP suggests a major version bump

API changes (from Hackage documentation)

+ CLaSH.Backend: genStmt :: Backend state => Bool -> State state Doc
+ CLaSH.Netlist.BlackBox.Types: [Gen] :: Bool -> Element
- CLaSH.Netlist.BlackBox.Types: [SigD] :: Element -> (Maybe Int) -> Element
+ CLaSH.Netlist.BlackBox.Types: [SigD] :: [Element] -> (Maybe Int) -> Element

Files

CHANGELOG.md view
@@ -1,5 +1,9 @@ # Changelog for the [`clash-lib`](http://hackage.haskell.org/package/clash-lib) package +## 0.5.8 *June 26th 2015*+* Fixes bugs:+  * Allow text and tags in ~SIGD black box construct+ ## 0.5.7 *June 25th 2015* * New features:   * Support for copying string literals from Haskell to generated code
clash-lib.cabal view
@@ -1,5 +1,5 @@ Name:                 clash-lib-Version:              0.5.7+Version:              0.5.8 Synopsis:             CAES Language for Synchronous Hardware - As a Library Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that
src/CLaSH/Backend.hs view
@@ -36,6 +36,8 @@   hdlTypeMark      :: HWType       -> State state Doc   -- | Create a signal declaration from an identifier (Text) and Netlist HWType   hdlSig           :: Text -> HWType -> State state Doc+  -- | Create a generative block statement marker+  genStmt          :: Bool -> State state Doc   -- | Turn a Netlist Declaration to a HDL concurrent block   inst             :: Declaration  -> State state (Maybe Doc)   -- | Turn a Netlist expression into a HDL expression
src/CLaSH/Netlist/BlackBox/Parser.hs view
@@ -73,8 +73,10 @@      <|> Size              <$> (pToken "~SIZE" *> pBrackets pTagE)      <|> Length            <$> (pToken "~LENGTH" *> pBrackets pTagE)      <|> FilePath          <$> (pToken "~FILE" *> pBrackets pTagE)-     <|> SigD              <$> (pToken "~SIGD" *> pBrackets pTagE) <*> (Just <$> (pBrackets pNatural))-     <|> (`SigD` Nothing)  <$> (pToken "~SIGDO" *> pBrackets pTagE)+     <|> Gen               <$> (True <$ pToken "~GENERATE")+     <|> Gen               <$> (False <$ pToken "~ENDGENERATE")+     <|> SigD              <$> (pToken "~SIGD" *> pBrackets pSigD) <*> (Just <$> (pBrackets pNatural))+     <|> (`SigD` Nothing)  <$> (pToken "~SIGDO" *> pBrackets pSigD)  -- | Parse a bracketed text pBrackets :: Parser a -> Parser a@@ -92,3 +94,11 @@ pElemE :: Parser Element pElemE = pTagE       <|> C <$> pText++-- | Parse SigD+pSigD :: Parser [Element]+pSigD = pSome (pTagE <|> pLimitedText)++-- | Text excluding square brackets and tilde+pLimitedText :: Parser Element+pLimitedText = C <$> (pack <$> pList1 (pSatisfy (`notElem` "[]~") (Insertion (show "notElem \"[]~\"") '_' 5)))
src/CLaSH/Netlist/BlackBox/Types.hs view
@@ -25,7 +25,9 @@              | Size Element      -- ^ Size of a type hole              | Length Element    -- ^ Length of a vector hole              | FilePath Element  -- ^ Hole containing a filepath for a data file-             | SigD Element (Maybe Int)+             | Gen Bool          -- ^ Hole marking beginning (True) or end (False)+                                 -- of a generative construct+             | SigD [Element] (Maybe Int)   deriving Show  -- | Component instantiation hole. First argument indicates which function argument
src/CLaSH/Netlist/BlackBox/Util.hs view
@@ -79,7 +79,7 @@                                                           return (Sym k)                                             Just k  -> return (Sym k)                       D (Decl n l') -> D <$> (Decl n <$> mapM (combineM setSym' setSym') l')-                      SigD e' m     -> SigD <$> (head <$> setSym' [e']) <*> pure m+                      SigD e' m     -> SigD <$> (setSym' e') <*> pure m                       _             -> pure e               ) @@ -98,7 +98,7 @@ setClocks bc bt = mapM setClocks' bt   where     setClocks' (D (Decl n l)) = D <$> (Decl n <$> mapM (combineM (setClocks bc) (setClocks bc)) l)-    setClocks' (SigD e m)     = SigD <$> (head <$> setClocks bc [e]) <*> pure m+    setClocks' (SigD e m)     = SigD <$> (setClocks bc e) <*> pure m      setClocks' (Clk Nothing)  = let (clk,rate) = clkSyncId $ fst $ bbResult bc                                     clkName    = Text.append clk (Text.pack (show rate))@@ -178,7 +178,7 @@       else error $ $(curLoc) ++ "\nCan't match context:\n" ++ show b' ++ "\nwith template:\n" ++ show templ  renderElem b (SigD e m) = do-  e' <- renderElem b e+  e' <- Text.concat <$> mapM (renderElem b) e   let ty = case m of              Nothing -> snd $ bbResult b              Just n  -> let (_,ty',_) = bbInputs b !! n@@ -251,7 +251,7 @@     vecLen _            = error $ $(curLoc) ++ "vecLen of a non-vector type" renderTag b e@(TypElem _)   = let ty = lineToType b [e]                               in  (displayT . renderOneLine) <$> hdlType ty-+renderTag _ (Gen b)         = displayT . renderOneLine <$> genStmt b renderTag _ (D _)           = error $ $(curLoc) ++ "Unexpected component declaration" renderTag _ (SigD _ _)      = error $ $(curLoc) ++ "Unexpected signal declaration" renderTag _ (Clk _)         = error $ $(curLoc) ++ "Unexpected clock"