diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,13 @@
 # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package
 
+## 0.6.5 *November 17th 2015*
+* Fixes bugs:
+  * Integer literals used as arguments not always properly annotated with their type.
+  * Verilog: Name collision in verilog code [#93](https://github.com/clash-lang/clash-compiler/issues/93)
+  * (System)Verilog: Integer literals missing "32'sd" prefix when used in assignments.
+  * VHDL: Integer literals should only be capped to 32-bit when used in assignments.
+  * Verilog: HO-primitives incorrect for nested vectors.
+
 ## 0.6.4 *November 12th 2015*
 * Fixes bugs:
   * Reversing alternatives is not meaning preserving for literal patterns [#91](https://github.com/clash-lang/clash-compiler/issues/91)
diff --git a/clash-ghc.cabal b/clash-ghc.cabal
--- a/clash-ghc.cabal
+++ b/clash-ghc.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-ghc
-Version:              0.6.4
+Version:              0.6.5
 Synopsis:             CAES Language for Synchronous Hardware
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -94,10 +94,10 @@
                       unbound-generics          >= 0.1 && < 0.3,
                       unordered-containers      >= 0.2.1.0,
 
-                      clash-lib                 >= 0.6.4 && < 0.7,
-                      clash-systemverilog       >= 0.6.2,
-                      clash-vhdl                >= 0.6.3,
-                      clash-verilog             >= 0.6.2,
+                      clash-lib                 >= 0.6.5 && < 0.7,
+                      clash-systemverilog       >= 0.6.3,
+                      clash-vhdl                >= 0.6.4,
+                      clash-verilog             >= 0.6.3,
                       clash-prelude             >= 0.10.3 && < 0.11,
                       ghc-typelits-extra        >= 0.1,
                       ghc-typelits-natnormalise >= 0.3