diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,15 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package -## 0.6.10 +## 0.6.11 *March 11th 2016* +* New features: + * Add support for HDL synthesis tool specific HDL generation: + * New `-clash-hdlsyn Vivado` flag to generate HDL tweaked for Xilinx Vivado + * Preserve more Haskell names in generated HDL [#128](https://github.com/clash-lang/clash-compiler/issues/128) +* Fixes bugs: + * VHDL: Vivado fails to infer block ram [#127](https://github.com/clash-lang/clash-compiler/issues/127) + * Users must use the `-clash-hdlsyn Vivado` flag in order to generate Xilinx Vivado specific HDL for which Vivado can infer block RAM. + +## 0.6.10 *February 10th 2016* * New features: * hdl files can be written to a directory (set by the `-clash-hdldir` flag) other than the current working directory [#125](https://github.com/clash-lang/clash-compiler/issues/125). Also respects the `-outputdir` directory, _unless_: diff --git a/clash-ghc.cabal b/clash-ghc.cabal --- a/clash-ghc.cabal +++ b/clash-ghc.cabal @@ -1,5 +1,5 @@ Name: clash-ghc -Version: 0.6.10 +Version: 0.6.11 Synopsis: CAES Language for Synchronous Hardware Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that @@ -94,10 +94,10 @@ unbound-generics >= 0.1 && < 0.4, unordered-containers >= 0.2.1.0, - clash-lib >= 0.6.10 && < 0.7, - clash-systemverilog >= 0.6.5, - clash-vhdl >= 0.6.7, - clash-verilog >= 0.6.5, + clash-lib >= 0.6.11 && < 0.7, + clash-systemverilog >= 0.6.6, + clash-vhdl >= 0.6.8, + clash-verilog >= 0.6.6, clash-prelude >= 0.10.6 && < 0.11, ghc-typelits-extra >= 0.1, ghc-typelits-natnormalise >= 0.3 diff --git a/src-bin/InteractiveUI.hs b/src-bin/InteractiveUI.hs --- a/src-bin/InteractiveUI.hs +++ b/src-bin/InteractiveUI.hs @@ -114,6 +114,7 @@ import CLaSH.GHC.Evaluator import CLaSH.GHC.GenerateBindings import CLaSH.GHC.NetlistTypes +import CLaSH.Netlist.BlackBox.Types (HdlSyn) import qualified CLaSH.Primitives.Util import CLaSH.Util (clashLibVersion) import qualified Data.Version as Data.Version @@ -1555,7 +1556,7 @@ liftIO $ putStrLn $ showSDocForUser dflags unqual msg makeHDL' :: CLaSH.Backend.Backend backend - => (Int -> backend) + => (Int -> HdlSyn -> backend) -> IORef CLaSHOpts -> [FilePath] -> InputT GHCi () @@ -1570,7 +1571,7 @@ makeHDL :: GHC.GhcMonad m => CLaSH.Backend.Backend backend - => (Int -> backend) + => (Int -> HdlSyn -> backend) -> IORef CLaSHOpts -> [FilePath] -> m () @@ -1578,6 +1579,7 @@ dflags <- GHC.getSessionDynFlags liftIO $ do opts <- readIORef optsRef let iw = opt_intWidth opts + syn = opt_hdlSyn opts -- determine whether `-outputdir` was used outputDir = do odir <- objectDir dflags hidir <- hiDir dflags @@ -1587,21 +1589,21 @@ then Just odir else Nothing opts' = opts {opt_hdlDir = maybe outputDir Just (opt_hdlDir opts)} - primDir <- CLaSH.Backend.primDir (backend iw) + primDir <- CLaSH.Backend.primDir (backend iw syn) primMap <- CLaSH.Primitives.Util.generatePrimMap [primDir,"."] forM_ srcs $ \src -> do (bindingsMap,tcm,tupTcm,topEnt,testInpM,expOutM) <- generateBindings primMap src (Just dflags) - CLaSH.Driver.generateHDL bindingsMap (Just (backend iw)) primMap tcm + CLaSH.Driver.generateHDL bindingsMap (Just (backend iw syn)) primMap tcm tupTcm (ghcTypeToHWType iw) reduceConstant topEnt testInpM expOutM opts' makeVHDL :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () -makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: Int -> VHDLState) +makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> VHDLState) makeVerilog :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () -makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> VerilogState) +makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> VerilogState) makeSystemVerilog :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () -makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> SystemVerilogState) +makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> SystemVerilogState) ----------------------------------------------------------------------------- -- :type diff --git a/src-bin/Main.hs b/src-bin/Main.hs --- a/src-bin/Main.hs +++ b/src-bin/Main.hs @@ -79,6 +79,7 @@ import CLaSH.Backend.Verilog (VerilogState) import CLaSH.Driver.Types (CLaSHOpts (..)) import CLaSH.GHC.CLaSHFlags +import CLaSH.Netlist.BlackBox.Types (HdlSyn (..)) import CLaSH.Rewrite.Types (DebugLevel (..)) import CLaSH.Util (clashLibVersion) import CLaSH.GHC.LoadModules (ghcLibDir) @@ -125,6 +126,7 @@ , opt_cleanhdl = True , opt_intWidth = WORD_SIZE_IN_BITS , opt_hdlDir = Nothing + , opt_hdlSyn = Other }) (argv3, clashFlagWarnings) <- parseCLaSHFlags r argv2 @@ -945,18 +947,18 @@ -- ----------------------------------------------------------------------------- -- VHDL Generation -makeHDL' :: CLaSH.Backend.Backend backend => (Int -> backend) -> IORef CLaSHOpts -> [(String,Maybe Phase)] -> Ghc () +makeHDL' :: CLaSH.Backend.Backend backend => (Int -> HdlSyn -> backend) -> IORef CLaSHOpts -> [(String,Maybe Phase)] -> Ghc () makeHDL' _ _ [] = throwGhcException (CmdLineError "No input files") makeHDL' backend r srcs = makeHDL backend r $ fmap fst srcs makeVHDL :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () -makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: Int -> VHDLState) +makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> VHDLState) makeVerilog :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () -makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> VerilogState) +makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> VerilogState) makeSystemVerilog :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () -makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> SystemVerilogState) +makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: Int -> HdlSyn -> SystemVerilogState) -- ----------------------------------------------------------------------------- -- Util diff --git a/src-ghc/CLaSH/GHC/CLaSHFlags.hs b/src-ghc/CLaSH/GHC/CLaSHFlags.hs --- a/src-ghc/CLaSH/GHC/CLaSHFlags.hs +++ b/src-ghc/CLaSH/GHC/CLaSHFlags.hs @@ -43,6 +43,7 @@ , defFlag "clash-noclean" (NoArg (liftEwM (setNoClean r))) , defFlag "clash-intwidth" (IntSuffix (setIntWidth r)) , defFlag "clash-hdldir" (SepArg (setHdlDir r)) + , defFlag "clash-hdlsyn" (SepArg (setHdlSyn r)) ] setInlineLimit :: IORef CLaSHOpts @@ -82,3 +83,10 @@ -> String -> EwM IO () setHdlDir r s = liftEwM $ modifyIORef r (\c -> c {opt_hdlDir = Just s}) + +setHdlSyn :: IORef CLaSHOpts + -> String + -> EwM IO () +setHdlSyn r s = case readMaybe s of + Just hdlSyn -> liftEwM $ modifyIORef r (\c -> c {opt_hdlSyn = hdlSyn}) + Nothing -> addWarn (s ++ " is an invalid debug level")