clash-ghc 0.5.9 → 0.5.10

raw patch · 3 files changed

+19/−5 lines, 3 filesdep ~clash-libdep ~clash-vhdl

Dependency ranges changed: clash-lib, clash-vhdl

Files

• CHANGELOG.md +7/−0
• clash-ghc.cabal +3/−3
• src-ghc/CLaSH/GHC/LoadInterfaceFiles.hs +9/−2

@@ -1,5 +1,12 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package +## 0.5.10 *July 9th 2015*+* New features:+  * Use new VHDL backend which outputs VHDL-93 instead of VHDL-2002: generated VHDL is now accepted by a larger number of tools.+  * Treat all so-called bottom values (`error "FOO"`, `let x = x in x`, etc.) occuring in installed libraries as `undefined`.+    Before, there were (very) rare situations where we couldn't find the expressions belonging to a function and demanded a BlackBox, even though we knew the expression would be a bottom value.+    Now, we stop demanding a BlackBox for such a function and simply treat it as `undefined`, thus allowing a greater range of circuit descriptions that we can compile.+ ## 0.5.9 *June 26th 2015* * New features:   * Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus

@@ -1,5 +1,5 @@ Name:                 clash-ghc-Version:              0.5.9+Version:              0.5.10 Synopsis:             CAES Language for Synchronous Hardware Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -70,9 +70,9 @@                       unbound-generics          >= 0.1,                       unordered-containers      >= 0.2.1.0, -                      clash-lib                 >= 0.5.8,+                      clash-lib                 >= 0.5.9,                       clash-systemverilog       >= 0.5.7,-                      clash-vhdl                >= 0.5.7.1,+                      clash-vhdl                >= 0.5.8,                       clash-verilog             >= 0.5.7,                       clash-prelude             >= 0.9,                       ghc-typelits-natnormalise >= 0.3

@@ -16,6 +16,7 @@ import qualified Class import qualified CoreFVs import qualified CoreSyn+import qualified Demand import           DynFlags    (unsafeGlobalDynFlags) import qualified GHC import qualified Id@@ -139,8 +140,9 @@                          CoreSyn.CoreBndr                     -- unlocatable Var loadExprFromTyThing bndr tyThing = case tyThing of   GHC.AnId _id | Var.isId _id ->-    let unfolding  = IdInfo.unfoldingInfo $ Var.idInfo _id-        inlineInfo = IdInfo.inlinePragInfo $ Var.idInfo _id+    let _idInfo    = Var.idInfo _id+        unfolding  = IdInfo.unfoldingInfo _idInfo+        inlineInfo = IdInfo.inlinePragInfo _idInfo     in case unfolding of       (CoreSyn.CoreUnfolding {}) ->         case (BasicTypes.inl_inline inlineInfo,BasicTypes.inl_act inlineInfo) of@@ -152,5 +154,10 @@         let dcApp  = MkCore.mkCoreConApps dc es             dfExpr = MkCore.mkCoreLams dfbndrs dcApp         in Left (bndr,dfExpr)+      CoreSyn.NoUnfolding+        | Demand.isBottomingSig $ IdInfo.strictnessInfo _idInfo+        -> Left (bndr,CoreSyn.mkTyApps (CoreSyn.Var MkCore.uNDEFINED_ID)+                                       [Var.varType _id]+                )       _ -> Right bndr   _ -> Right bndr