clash-ghc 0.5.8 → 0.5.9
raw patch · 3 files changed
+13/−6 lines, 3 filesdep ~clash-libdep ~clash-systemverilogdep ~clash-verilog
Dependency ranges changed: clash-lib, clash-systemverilog, clash-verilog, clash-vhdl
Files
- CHANGELOG.md +7/−0
- clash-ghc.cabal +5/−5
- src-bin/Main.hs +1/−1
CHANGELOG.md view
@@ -1,5 +1,12 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package +## 0.5.9 *June 26th 2015*+* New features:+ * Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus++* Fixes bugs:+ * `--systemverilog` switch incorrectly generates verilog code instead of systemverilog code+ ## 0.5.8 *June 25th 2015* * New features: * Support for copying string literals from Haskell to generated code
clash-ghc.cabal view
@@ -1,5 +1,5 @@ Name: clash-ghc-Version: 0.5.8+Version: 0.5.9 Synopsis: CAES Language for Synchronous Hardware Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -70,10 +70,10 @@ unbound-generics >= 0.1, unordered-containers >= 0.2.1.0, - clash-lib >= 0.5.7,- clash-systemverilog >= 0.5.6,- clash-vhdl >= 0.5.7,- clash-verilog >= 0.5.6,+ clash-lib >= 0.5.8,+ clash-systemverilog >= 0.5.7,+ clash-vhdl >= 0.5.7.1,+ clash-verilog >= 0.5.7, clash-prelude >= 0.9, ghc-typelits-natnormalise >= 0.3
src-bin/Main.hs view
@@ -520,7 +520,7 @@ showPackagesMode = mkPostLoadMode ShowPackages doVHDLMode = mkPostLoadMode DoVHDL doVerilogMode = mkPostLoadMode DoVerilog-doSystemVerilogMode = mkPostLoadMode DoVerilog+doSystemVerilogMode = mkPostLoadMode DoSystemVerilog showInterfaceMode :: FilePath -> Mode showInterfaceMode fp = mkPostLoadMode (ShowInterface fp)