diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,10 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package +## 0.5.7 *June 3rd 2015* +* New features: + * New Verilog backend, run `:verilog` in interactive mode, or `--verilog` for batch mode + * Generated component names are prefixed by the name of the module containing the `topEntity` + ## 0.5.6 *May 18th 2015* * New features: * Inlining limit is configurable, run with `-clash-inline-limit=N` to set the inlining limit to `N` diff --git a/clash-ghc.cabal b/clash-ghc.cabal --- a/clash-ghc.cabal +++ b/clash-ghc.cabal @@ -1,5 +1,5 @@ Name: clash-ghc -Version: 0.5.6 +Version: 0.5.7 Synopsis: CAES Language for Synchronous Hardware Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that @@ -70,11 +70,12 @@ unbound-generics >= 0.1, unordered-containers >= 0.2.1.0, - clash-lib >= 0.5.5, - clash-vhdl >= 0.5.4, - clash-systemverilog >= 0.5.4, - clash-prelude >= 0.7.5, - ghc-typelits-natnormalise >= 0.2.1 + clash-lib >= 0.5.6, + clash-systemverilog >= 0.5.5, + clash-vhdl >= 0.5.5, + clash-verilog >= 0.5.5, + clash-prelude >= 0.8, + ghc-typelits-natnormalise >= 0.3 if os(windows) Build-Depends: Win32 diff --git a/src-bin/InteractiveUI.hs b/src-bin/InteractiveUI.hs --- a/src-bin/InteractiveUI.hs +++ b/src-bin/InteractiveUI.hs @@ -110,8 +110,9 @@ import GHC.TopHandler ( topHandler ) import qualified CLaSH.Backend -import CLaSH.Backend.VHDL (VHDLState) import CLaSH.Backend.SystemVerilog (SystemVerilogState) +import CLaSH.Backend.VHDL (VHDLState) +import CLaSH.Backend.Verilog (VerilogState) import qualified CLaSH.Driver import CLaSH.Driver.Types (CLaSHOpts) import CLaSH.GHC.Evaluator @@ -205,6 +206,7 @@ ("undef", keepGoing undefineMacro, completeMacro), ("unset", keepGoing unsetOptions, completeSetOptions), ("vhdl", keepGoingPaths (makeVHDL opts), completeHomeModuleOrFile), + ("verilog", keepGoingPaths (makeVerilog opts), completeHomeModuleOrFile), ("systemverilog", keepGoingPaths (makeSystemVerilog opts), completeHomeModuleOrFile) ] @@ -281,6 +283,8 @@ " :! run the shell command \n" ++ " :vhdl synthesize currently loaded module to vhdl\n" ++ " :vhdl [] synthesize specified modules/files to vhdl\n" ++ + " :verilog synthesize currently loaded module to verilog\n" ++ + " :verilog [] synthesize specified modules/files to verilog\n" ++ " :systemverilog synthesize currently loaded module to systemverilog\n" ++ " :systemverilog [] synthesize specified modules/files to systemverilog\n" ++ "\n" ++ @@ -1586,6 +1590,9 @@ makeVHDL :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: VHDLState) + +makeVerilog :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () +makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: VerilogState) makeSystemVerilog :: IORef CLaSHOpts -> [FilePath] -> InputT GHCi () makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: SystemVerilogState) diff --git a/src-bin/Main.hs b/src-bin/Main.hs --- a/src-bin/Main.hs +++ b/src-bin/Main.hs @@ -73,8 +73,9 @@ import Control.Exception (ErrorCall (..)) import qualified CLaSH.Backend -import CLaSH.Backend.VHDL (VHDLState) import CLaSH.Backend.SystemVerilog (SystemVerilogState) +import CLaSH.Backend.VHDL (VHDLState) +import CLaSH.Backend.Verilog (VerilogState) import CLaSH.Driver.Types (CLaSHOpts (..)) import CLaSH.GHC.CLaSHFlags import CLaSH.Rewrite.Types (DebugLevel (..)) @@ -204,6 +205,7 @@ DoMkDependHS -> (MkDepend, dflt_target, LinkBinary) DoAbiHash -> (OneShot, dflt_target, LinkBinary) DoVHDL -> (CompManager, dflt_target, LinkInMemory) + DoVerilog -> (CompManager, dflt_target, LinkInMemory) DoSystemVerilog -> (CompManager, dflt_target, LinkInMemory) _ -> (OneShot, dflt_target, LinkBinary) @@ -302,6 +304,7 @@ DoAbiHash -> abiHash (map fst srcs) ShowPackages -> liftIO $ showPackages dflags6 DoVHDL -> clash makeVHDL + DoVerilog -> clash makeVerilog DoSystemVerilog -> clash makeSystemVerilog liftIO $ dumpFinalStats dflags6 @@ -503,17 +506,20 @@ | DoAbiHash -- ghc --abi-hash | ShowPackages -- ghc --show-packages | DoVHDL -- ghc --vhdl + | DoVerilog -- ghc --verilog | DoSystemVerilog -- ghc --systemverilog doMkDependHSMode, doMakeMode, doInteractiveMode, - doAbiHashMode, showPackagesMode, doVHDLMode, doSystemVerilogMode :: Mode + doAbiHashMode, showPackagesMode, doVHDLMode, doVerilogMode, + doSystemVerilogMode :: Mode doMkDependHSMode = mkPostLoadMode DoMkDependHS doMakeMode = mkPostLoadMode DoMake doInteractiveMode = mkPostLoadMode DoInteractive doAbiHashMode = mkPostLoadMode DoAbiHash showPackagesMode = mkPostLoadMode ShowPackages doVHDLMode = mkPostLoadMode DoVHDL -doSystemVerilogMode = mkPostLoadMode DoSystemVerilog +doVerilogMode = mkPostLoadMode DoVerilog +doSystemVerilogMode = mkPostLoadMode DoVerilog showInterfaceMode :: FilePath -> Mode showInterfaceMode fp = mkPostLoadMode (ShowInterface fp) @@ -556,6 +562,7 @@ needsInputsMode (StopBefore _) = True needsInputsMode DoMake = True needsInputsMode DoVHDL = True +needsInputsMode DoVerilog = True needsInputsMode DoSystemVerilog = True needsInputsMode _ = False @@ -567,6 +574,7 @@ isLinkMode DoInteractive = True isLinkMode (DoEval _) = True isLinkMode DoVHDL = True +isLinkMode DoVerilog = True isLinkMode DoSystemVerilog = True isLinkMode _ = False @@ -574,7 +582,8 @@ isCompManagerMode DoMake = True isCompManagerMode DoInteractive = True isCompManagerMode (DoEval _) = True -isCompManagerMode DoVHDL = True +isCompManagerMode DoVHDL = True +isCompManagerMode DoVerilog = True isCompManagerMode DoSystemVerilog = True isCompManagerMode _ = False @@ -658,7 +667,8 @@ , defFlag "-interactive" (PassFlag (setMode doInteractiveMode)) , defFlag "-abi-hash" (PassFlag (setMode doAbiHashMode)) , defFlag "e" (SepArg (\s -> setMode (doEvalMode s) "-e")) - , defFlag "-vhdl" (PassFlag (setMode doVHDLMode)) + , defFlag "-vhdl" (PassFlag (setMode doVHDLMode)) + , defFlag "-verilog" (PassFlag (setMode doVerilogMode)) , defFlag "-systemverilog" (PassFlag (setMode doSystemVerilogMode)) ] @@ -938,6 +948,9 @@ makeVHDL :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: VHDLState) + +makeVerilog :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () +makeVerilog = makeHDL' (CLaSH.Backend.initBackend :: VerilogState) makeSystemVerilog :: IORef CLaSHOpts -> [(String, Maybe Phase)] -> Ghc () makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: SystemVerilogState) diff --git a/src-ghc/CLaSH/GHC/GenerateBindings.hs b/src-ghc/CLaSH/GHC/GenerateBindings.hs --- a/src-ghc/CLaSH/GHC/GenerateBindings.hs +++ b/src-ghc/CLaSH/GHC/GenerateBindings.hs @@ -45,12 +45,41 @@ allTcCache = tysPrimMap `HashMap.union` tcCache clsMap = HashMap.map (\(ty,i) -> (ty,mkClassSelector allTcCache ty i)) clsVMap allBindings = bindingsMap `HashMap.union` clsMap - topEntities = HashMap.filterWithKey (\var _ -> isSuffixOf "topEntity" $ name2String var) allBindings - retypedBindings = case HashMap.toList topEntities of - [topEntity] -> let droppedBindings = lambdaDropPrep allBindings (fst topEntity) - in snd $ retype allTcCache ([],droppedBindings) (fst topEntity) - _ -> allBindings - return (retypedBindings,allTcCache,topEntM) + droppedAndRetypedBindings = dropAndRetypeBindings allTcCache allBindings + return (droppedAndRetypedBindings,allTcCache,topEntM) + +dropAndRetypeBindings :: HashMap TyConName TyCon -> BindingMap -> BindingMap +dropAndRetypeBindings allTcCache allBindings = oBindings + where + topEntities = HashMap.toList + $ HashMap.filterWithKey + (\var _ -> isSuffixOf ".topEntity" $ name2String var) + allBindings + testInputs = HashMap.toList + $ HashMap.filterWithKey + (\var _ -> isSuffixOf ".testInput" $ name2String var) + allBindings + expectedOutputs = HashMap.toList + $ HashMap.filterWithKey + (\var _ -> isSuffixOf ".expectedOutput" $ name2String var) + allBindings + + dropAndRetype d (t,_) = snd + $ retype allTcCache + ([],lambdaDropPrep d t) + t + + tBindings = case topEntities of + (topEntity:_) -> dropAndRetype allBindings topEntity + _ -> allBindings + + iBindings = case testInputs of + (testInput:_) -> dropAndRetype tBindings testInput + _ -> tBindings + + oBindings = case expectedOutputs of + (expectedOutput:_) -> dropAndRetype iBindings expectedOutput + _ -> iBindings -- | clean up cast-removal mess retype :: HashMap TyConName TyCon