clash-ghc 0.5.15 → 0.6

raw patch · 4 files changed

+27/−12 lines, 4 filesdep ~clash-libdep ~clash-preludedep ~clash-systemverilog

Dependency ranges changed: clash-lib, clash-prelude, clash-systemverilog, clash-verilog, clash-vhdl

Files

• CHANGELOG.md +6/−0
• README.md +3/−3
• clash-ghc.cabal +9/−9
• src-ghc/CLaSH/GHC/Evaluator.hs +9/−0

@@ -1,5 +1,11 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package +## 0.6 *October 3rd 2015*+* New features:+  * Support `clash-prelude-0.10`+  * Pattern matching on `CLaSH.Sized.Vector`'s `:>` is now supported+  * Unroll "definitions" of the following primitives: `fold`, `dfold`, `foldr`+ ## 0.5.15 *September 21st 2015* * New features:   * Report simulation time in (System)Verilog assert messages

@@ -13,8 +13,8 @@ Features of CλaSH:    * Strongly typed (like VHDL), yet with a very high degree of type inference,-    which enables both safe and fast prototying using consise descriptions (like-    Verilog)+    enabling both safe and fast prototying using consise descriptions (like+    Verilog).    * Interactive REPL: load your designs in an interpreter and easily test all     your component without needing to setup a test bench.@@ -23,7 +23,7 @@     fully parametric by default.    * Synchronous sequential circuit design based on streams of values, called-    `Signal`s.+    `Signal`s, lead to natural descriptions of feedback loops.    * Support for multiple clock domains, with type safe clock domain crossing. 

@@ -1,5 +1,5 @@ Name:                 clash-ghc-Version:              0.5.15+Version:              0.6 Synopsis:             CAES Language for Synchronous Hardware Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -10,8 +10,8 @@   Features of CλaSH:   .   * Strongly typed (like VHDL), yet with a very high degree of type inference,-    which enables both safe and fast prototying using consise descriptions (like-    Verilog)+    enabling both safe and fast prototying using consise descriptions (like+    Verilog).   .   * Interactive REPL: load your designs in an interpreter and easily test all     your component without needing to setup a test bench.@@ -20,7 +20,7 @@     fully parametric by default.   .   * Synchronous sequential circuit design based on streams of values, called-    @Signal@s.+    @Signal@s, lead to natural descriptions of feedback loops.   .   * Support for multiple clock domains, with type safe clock domain crossing.   .@@ -94,11 +94,11 @@                       unbound-generics          >= 0.1 && < 0.3,                       unordered-containers      >= 0.2.1.0, -                      clash-lib                 >= 0.5.13 && < 0.6,-                      clash-systemverilog       >= 0.5.10,-                      clash-vhdl                >= 0.5.12,-                      clash-verilog             >= 0.5.10,-                      clash-prelude             >= 0.9.3,+                      clash-lib                 >= 0.6 && < 0.7,+                      clash-systemverilog       >= 0.6,+                      clash-vhdl                >= 0.6,+                      clash-verilog             >= 0.6,+                      clash-prelude             >= 0.10,                       ghc-typelits-natnormalise >= 0.3    if os(windows)

@@ -169,6 +169,15 @@                   [nilCon,consCon] = tyConDataCons vecTc               in  mkVec nilCon consCon argTy len (replicate len (last $ Either.lefts args))           _ -> e+  | isSubj && nm == "CLaSH.Sized.Vector.maxIndex"+  = case Either.rights args of+      [LitTy (NumTy n), _] ->+        let ty' = runFreshM (termType tcm e)+            (TyConApp intTcNm _) = tyView ty'+            (Just intTc) = HashMap.lookup intTcNm tcm+            [intCon] = tyConDataCons intTc+        in  mkApps (Data intCon) [Left (Literal (IntegerLiteral (toInteger (n - 1))))]+      _ -> e  reduceConstant _ _ e = e