diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,16 @@
 # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package
 
+## 0.5.12 *September 7th 2015*
+* New features:
+  * Modest compilation time speed-up. Compilation time of the [I2C](https://github.com/clash-lang/clash-compiler/tree/master/examples/i2c) module on my machine went down from 43s to 24s, and maximum memory usage went down from 840 MB to 700 MB.
+
+* Fixes bugs:
+  * Bug in VHDL ROM generation [#69](https://github.com/clash-lang/clash-compiler/issues/69)
+  * Clash running out of memory on Simple-ish project [#70](https://github.com/clash-lang/clash-compiler/issues/70)
+  * Fix asyncRom VHDL primitive [#71](https://github.com/clash-lang/clash-compiler/pull/71)
+  * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)
+  * rem and quot on Signed are broken [#73](https://github.com/clash-lang/clash-compiler/issues/73)
+
 ## 0.5.11 *August 2nd 2015*
 * New features:
   * Re-enable GHC's strictness analysis pass, which improves dead-code removal, which hopefully leads to smaller circuits.
diff --git a/README.md b/README.md
--- a/README.md
+++ b/README.md
@@ -1,7 +1,31 @@
-# Support
-For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)
+# `clash-ghc` - Haskell/GHC front-end for the CλaSH compiler
 
-# `clash-ghc`
   * See the LICENSE file for license and copyright details
   * Contains code from the [GHC compiler](http://haskell.org/ghc), see the
     LICENSE_GHC file for license and copyright details pertaining to that code.
+
+# CλaSH - A functional hardware description language
+CλaSH (pronounced ‘clash’) is a functional hardware description language that
+borrows both its syntax and semantics from the functional programming language
+Haskell. The CλaSH compiler transforms these high-level descriptions to
+low-level synthesizable VHDL, Verilog, or SystemVerilog.
+
+Features of CλaSH:
+
+  * Strongly typed (like VHDL), yet with a very high degree of type inference,
+    which enables both safe and fast prototying using consise descriptions (like
+    Verilog)
+
+  * Interactive REPL: load your designs in an interpreter and easily test all
+    your component without needing to setup a test bench.
+
+  * Higher-order functions, with type inference, result in designs that are
+    fully parametric by default.
+
+  * Synchronous sequential circuit design based on streams of values, called
+    `Signal`s.
+
+  * Support for multiple clock domains, with type safe clock domain crossing.
+
+# Support
+For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language)
diff --git a/clash-ghc.cabal b/clash-ghc.cabal
--- a/clash-ghc.cabal
+++ b/clash-ghc.cabal
@@ -1,14 +1,30 @@
 Name:                 clash-ghc
-Version:              0.5.11
+Version:              0.5.12
 Synopsis:             CAES Language for Synchronous Hardware
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
   borrows both its syntax and semantics from the functional programming language
-  Haskell. The merits of using a functional language to describe hardware comes
-  from the fact that combinational circuits can be directly modelled as
-  mathematical functions and that functional languages lend themselves very well
-  at describing and (de-)composing mathematical functions.
+  Haskell. The CλaSH compiler transforms these high-level descriptions to
+  low-level synthesizable VHDL, Verilog, or SystemVerilog.
   .
+  Features of CλaSH:
+  .
+  * Strongly typed (like VHDL), yet with a very high degree of type inference,
+    which enables both safe and fast prototying using consise descriptions (like
+    Verilog)
+  .
+  * Interactive REPL: load your designs in an interpreter and easily test all
+    your component without needing to setup a test bench.
+  .
+  * Higher-order functions, with type inference, result in designs that are
+    fully parametric by default.
+  .
+  * Synchronous sequential circuit design based on streams of values, called
+    @Signal@s.
+  .
+  * Support for multiple clock domains, with type safe clock domain crossing.
+  .
+  .
   This package provides:
   .
   * CλaSH Compiler binary using GHC/Haskell as a frontend
@@ -52,6 +68,14 @@
                       PatternGuards
                       NondecreasingIndentation
 
+  other-extensions:   FlexibleContexts
+                      OverloadedStrings
+                      RecordWildCards
+                      ScopedTypeVariables
+                      TemplateHaskell
+                      TupleSections
+                      ViewPatterns
+
   Build-Depends:      array                     >= 0.4,
                       base                      >= 4.3.1.0 && < 5,
                       bifunctors                >= 4.1.1,
@@ -70,10 +94,10 @@
                       unbound-generics          >= 0.1 && < 0.3,
                       unordered-containers      >= 0.2.1.0,
 
-                      clash-lib                 >= 0.5.10 && < 0.6,
-                      clash-systemverilog       >= 0.5.7,
-                      clash-vhdl                >= 0.5.8,
-                      clash-verilog             >= 0.5.7,
+                      clash-lib                 >= 0.5.11 && < 0.6,
+                      clash-systemverilog       >= 0.5.8,
+                      clash-vhdl                >= 0.5.9,
+                      clash-verilog             >= 0.5.8,
                       clash-prelude             >= 0.9.2,
                       ghc-typelits-natnormalise >= 0.3