packages feed

clash-ghc 0.4.1 → 0.5

raw patch · 35 files changed

+154/−1985 lines, 35 filesdep +clash-systemverilogdep +clash-vhdldep +unbound-genericsdep −ghc-pathsdep −unbounddep ~clash-libdep ~clash-preludedep ~ghc

Dependencies added: clash-systemverilog, clash-vhdl, unbound-generics

Dependencies removed: ghc-paths, unbound

Dependency ranges changed: clash-lib, clash-prelude, ghc

Files

CHANGELOG.md view
@@ -1,5 +1,9 @@ # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package +## 0.5 *March 11th 2015*+* New features:+  * SystemVerilog backend. [#45](https://github.com/clash-lang/clash-compiler/issues/45)+ ## 0.4.1 *February 4th 2015* * Include bug fixes from clash-lib 0.4.1 
LICENSE view
@@ -1,4 +1,4 @@-Copyright (c) 2012-2014, University of Twente+Copyright (c) 2012-2015, University of Twente All rights reserved.  Redistribution and use in source and binary forms, with or without
README.md view
@@ -1,9 +1,6 @@ # Support For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the [forum](https://groups.google.com/d/forum/clash-language) -# `clash-lib`-  * See the LICENSE file for license and copyright details- # `clash-ghc`   * See the LICENSE file for license and copyright details   * Contains code from the [GHC compiler](http://haskell.org/ghc), see the
clash-ghc.cabal view
@@ -1,5 +1,5 @@ Name:                 clash-ghc-Version:              0.4.1+Version:              0.5 Synopsis:             CAES Language for Synchronous Hardware Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -15,13 +15,13 @@   .   .   Prelude library: <http://hackage.haskell.org/package/clash-prelude>-Homepage:             http://christiaanb.github.io/clash2-bug-reports:          http://github.com/christiaanb/clash2/issues-License:              OtherLicense+Homepage:             http://www.clash-lang.org/+bug-reports:          http://github.com/clash-lang/clash-compiler/issues+License:              BSD2 License-file:         LICENSE Author:               Christiaan Baaij Maintainer:           Christiaan Baaij <christiaan.baaij@gmail.com>-Copyright:            Copyright © 2012-2014 University of Twente+Copyright:            Copyright © 2012-2015 University of Twente Category:             Hardware Build-type:           Simple @@ -31,40 +31,11 @@                       src-bin/HsVersions.h,                       src-bin/PosixSource.h -Data-files:           primitives/CLaSH.GHC.GHC2Core.json,-                      primitives/CLaSH.Prelude.BlockRam.json,-                      primitives/CLaSH.Prelude.Testbench.json,-                      primitives/CLaSH.Promoted.Nat.json,-                      primitives/CLaSH.Promoted.Symbol.json,-                      primitives/CLaSH.Signal.Bundle.json,-                      primitives/CLaSH.Signal.Explicit.json,-                      primitives/CLaSH.Signal.Internal.json,-                      primitives/CLaSH.Sized.Internal.BitVector.json,-                      primitives/CLaSH.Sized.Internal.Index.json,-                      primitives/CLaSH.Sized.Internal.Signed.json,-                      primitives/CLaSH.Sized.Internal.Unsigned.json,-                      primitives/CLaSH.Sized.Vector.json,-                      primitives/Control.Exception.Base.json,-                      primitives/GHC.Base.json,-                      primitives/GHC.Classes.json,-                      primitives/GHC.CString.json,-                      primitives/GHC.Err.json,-                      primitives/GHC.Integer.Type.json,-                      primitives/GHC.Prim.json,-                      primitives/GHC.Real.json,-                      primitives/GHC.Typelits.json,-                      primitives/GHC.Types.json,-                      primitives/Unsafe.Coerce.json- Cabal-version:        >=1.10  source-repository head   type: git-  location: https://github.com/christiaanb/clash2.git--Flag standalone-  Description: Build compiler for non-cabal installation-  Default: False+  location: https://github.com/clash-lang/clash-compiler.git  Executable clash   HS-Source-Dirs:     src-ghc src-bin@@ -85,8 +56,6 @@                       base                 >= 4.3.1.0 && < 5,                       bifunctors           >= 4.1.1,                       bytestring           >= 0.9,-                      clash-lib            >= 0.4.1,-                      clash-prelude        >= 0.6,                       containers           >= 0.5.4.0,                       directory            >= 1.2,                       filepath             >= 1.3,@@ -98,9 +67,14 @@                       mtl                  >= 2.1.1,                       text                 >= 0.11.3.1,                       transformers         >= 0.3,-                      unbound              >= 0.4.0.2,-                      unordered-containers >= 0.2.1.0+                      unbound-generics     >= 0.1,+                      unordered-containers >= 0.2.1.0, +                      clash-lib            >= 0.5,+                      clash-vhdl           >= 0.5,+                      clash-systemverilog  >= 0.5,+                      clash-prelude        >= 0.7+   if os(windows)     Build-Depends:    Win32   else@@ -124,9 +98,4 @@                       CLaSH.GHC.LoadInterfaceFiles                       CLaSH.GHC.LoadModules                       CLaSH.GHC.NetlistTypes--  if flag(standalone)-    CPP-Options:      -DSTANDALONE-  else-    Build-Depends:    ghc-paths-    Other-Modules:    Paths_clash_ghc+                      Paths_clash_ghc
− primitives/CLaSH.GHC.GHC2Core.json
@@ -1,16 +0,0 @@-[ { "BlackBox" :-    { "name"      : "EmptyCase"-    , "templateE" : "~ERRORO"-    }-  }-, { "Primitive" :-    { "name"     : "_CO_"-    , "primType" : "Constructor"-    }-  }-, { "Primitive" :-    { "name"     : "_TY_"-    , "primType" : "Constructor"-    }-  }-]
− primitives/CLaSH.Prelude.BlockRam.json
@@ -1,34 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Prelude.BlockRam.cblockRam"-    , "comment"   :-    "cblockRam :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])-          => SClock clk                    -- clk,  ARG[2]-          -> Vec n a                       -- init, ARG[3]-          -> CSignal clk (Unsigned m)      -- wr,   ARG[4]-          -> CSignal clk (Unsigned m)      -- rd,   ARG[5]-          -> CSignal clk Bool              -- wren, ARG[6]-          -> CSignal clk a                 -- din,  ARG[7]-          -> CSignal clk a"-    , "templateD" :-"blockram_~SYM[0] : block-  signal ~SYM[1] : ~TYP[3] := ~LIT[3]; -- ram-  signal ~SYM[2] : ~TYP[7]; -- inp-  signal ~SYM[3] : ~TYP[7]; -- outp-begin-  ~SYM[2] <= ~ARG[7];--  process(~CLK[2])-  begin-    if rising_edge(~CLK[2]) then-      if ~ARG[6] then-        ~SYM[1](to_integer(~ARG[4])) <= ~SYM[2];-      end if;-      ~SYM[3] <= ~SYM[1](to_integer(~ARG[5]));-    end if;-  end process;--  ~RESULT <= ~SYM[3];-end block;"-    }-  }-]
− primitives/CLaSH.Prelude.Testbench.json
@@ -1,24 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Prelude.Testbench.csassert"-    , "comment"   :-    "csassert :: (Eq a,Show a) -- (ARG[0],ARG[1])-         => CSignal t a -- ^ Checked value (ARG[2])-         -> CSignal t a -- ^ Expected value (ARG[3])-         -> CSignal t b -- ^ Return valued (ARG[4])-         -> CSignal t b"-    , "templateD" :-"assert_~SYM[0] : block-begin-  -- pragma translate_off-  process(~CLK[2],~RST[2],~ARG[2],~ARG[3]) is-  begin-    if (rising_edge(~CLK[2]) or rising_edge(~RST[2])) then-      assert (~ARG[2] = ~ARG[3]) report (\"expected: \" & to_string (~ARG[3]) & \", actual: \" & to_string (~ARG[2])) severity error;-    end if;-  end process;-  -- pragma translate_on-  ~RESULT <= ~ARG[4];-end block;"-    }-  }-]
− primitives/CLaSH.Promoted.Nat.json
@@ -1,11 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Promoted.Nat.SNat"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Promoted.Nat.snatToInteger"-    , "templateE" : "~LIT[0]"-    }-  }-]
− primitives/CLaSH.Promoted.Symbol.json
@@ -1,11 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Promoted.Symbol.SSymbol"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Promoted.Symbol.symbolToString"-    , "templateE" : "~LIT[0]"-    }-  }-]
− primitives/CLaSH.Signal.Bundle.json
@@ -1,6 +0,0 @@-[ { "Primitive" :-    { "name"      : "CLaSH.Signal.Bundle.vecBundle#"-    , "primType"  : "Function"-    }-  }-]
− primitives/CLaSH.Signal.Explicit.json
@@ -1,6 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Signal.Explicit.veryUnsafeSynchronizer"-    , "templateE" : "~ARG[2]"-    }-  }-]
− primitives/CLaSH.Signal.Internal.json
@@ -1,86 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Signal.Internal.register#"-    , "comment"   :-    "register# :: SClock clk     -- ARG[0]-               -> a              -- ARG[1]-               -> CSignal clk a  -- ARG[2]-               -> CSignal clk a"-    , "templateD" :-"register_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[1];--  process(~CLK[0],~RST[0],~SYM[1])-  begin-    if ~RST[0] = '0' then-      ~SYM[2] <= ~SYM[1];-    elsif rising_edge(~CLK[0]) then-      ~SYM[2] <= ~ARG[2];-    end if;-  end process;--  ~RESULT <= ~SYM[2];-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Signal.Internal.regEn#"-    , "comment"   :-    "regEn# :: SClock clk       -- ARG[0]-            -> a                -- ARG[1]-            -> CSignal clk Bool -- ARG[2]-            -> CSignal clk a    -- ARG[3]-            -> CSignal clk a"-    , "templateD" :-"regEn_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-  signal ~SYM[3] : ~TYP[3];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];--  process(~CLK[0],~RST[0],~SYM[1],~SYM[2])-  begin-    if ~RST[0] = '0' then-      ~SYM[3] <= ~SYM[1];-    elsif rising_edge(~CLK[0]) then-      if ~SYM[2] then-        ~SYM[3] <= ~ARG[3];-      end if;-    end if;-  end process;--  ~RESULT <= ~SYM[3];-end block;"-    }-  }--, { "Primitive" :-    { "name"      : "CLaSH.Signal.Internal.signal#"-    , "primType"  : "Function"-    }-  }-, { "Primitive" :-    { "name"      : "CLaSH.Signal.Internal.mapSignal#"-    , "primType"  : "Function"-    }-  }-, { "Primitive" :-    { "name"      : "CLaSH.Signal.Internal.appSignal#"-    , "primType"  : "Function"-    }-  }-, { "Primitive" :-    { "name"      : "CLaSH.Signal.Internal.foldr#"-    , "primType"  : "Function"-    }-  }-, { "Primitive" :-    { "name"      : "CLaSH.Signal.Internal.traverse#"-    , "primType"  : "Function"-    }-  }-]
− primitives/CLaSH.Sized.Internal.BitVector.json
@@ -1,432 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.size#"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.maxIndex#"-    , "templateE" : "~LIT[0] - 1"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.high"-    , "templateE" : "\"1\""-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.low"-    , "templateE" : "\"0\""-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.++#"-    , "templateE" : "std_logic_vector'(~ARG[1]) & std_logic_vector'(~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceAnd#"-    , "templateD"  :-"reduceAnd_~SYM[0] : block-  function and_reduce (arg : std_logic_vector) return std_logic is-    variable upper, lower : std_logic;-    variable half         : integer;-    variable argi         : std_logic_vector (arg'length - 1 downto 0);-    variable result       : std_logic;-  begin-    if (arg'length < 1) then-      result := '1';-    else-      argi := arg;-      if (argi'length = 1) then-        result := argi(argi'left);-      else-        half   := (argi'length + 1) / 2; -- lsb-biased tree-        upper  := and_reduce (argi (argi'left downto half));-        lower  := and_reduce (argi (half - 1 downto argi'right));-        result := upper and lower;-      end if;-    end if;-    return result;-  end;-begin-  ~RESULT <= (0 => and_reduce(~ARG[1]));-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceOr#"-    , "templateD"  :-"reduceOr_~SYM[0] : block-  function or_reduce (arg : std_logic_vector) return std_logic is-    variable upper, lower : std_logic;-    variable half         : integer;-    variable argi         : std_logic_vector (arg'length - 1 downto 0);-    variable result       : std_logic;-  begin-    if (arg'length < 1) then-      result := '0';-    else-      argi := arg;-      if (argi'length = 1) then-        result := argi(argi'left);-      else-        half   := (argi'length + 1) / 2; -- lsb-biased tree-        upper  := or_reduce (argi (argi'left downto half));-        lower  := or_reduce (argi (half - 1 downto argi'right));-        result := upper or lower;-      end if;-    end if;-    return result;-  end;-begin-  ~RESULT <= (0 => or_reduce(~ARG[0]));-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceXor#"-    , "templateD"  :-"reduceXor_~SYM[0] : block-  function xor_reduce (arg : std_logic_vector) return std_logic is-    variable upper, lower : std_logic;-    variable half         : integer;-    variable argi         : std_logic_vector (arg'length - 1 downto 0);-    variable result       : std_logic;-  begin-    if (arg'length < 1) then-      result := '0';-    else-      argi := arg;-      if (argi'length = 1) then-        result := argi(argi'left);-      else-        half   := (argi'length + 1) / 2; -- lsb-biased tree-        upper  := xor_reduce (argi (argi'left downto half));-        lower  := xor_reduce (argi (half - 1 downto argi'right));-        result := upper xor lower;-      end if;-    end if;-    return result;-  end;-begin-  ~RESULT <= (0 => xor_reduce(~ARG[0]));-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.index#"-    , "comment"   :-    "index# :: KnownNat n  -- ARG[0]-            => BitVector n -- ARG[1]-            -> Int         -- ARG[2]-            -> Bit"-    , "templateD" :-"indexBit_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];-  -- pragma translate_off-  process (~SYM[1],~SYM[2])-  begin-    if ~SYM[2] < ~SYM[1]'low or ~SYM[2] > ~SYM[1]'high then-      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;-      ~RESULT <= ~ERRORO;-    else-    -- pragma translate_on-      ~RESULT <= ~SYM[1](~SYM[2] downto ~SYM[2]);-    -- pragma translate_off-    end if;-  end process;-  -- pragma translate_on-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.replaceBit#"-    , "comment"   :-    "replaceBit# :: KnownNat n  -- ARG[0]-                 => BitVector n -- ARG[1]-                 -> Int         -- ARG[2]-                 -> Bit         -- ARG[3]-                 -> BitVector n"-    , "templateD" :-"replaceBit_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-  signal ~SYM[3] : ~TYP[3];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];-  ~SYM[3] <= ~ARG[3];-  process(~SYM[1],~SYM[2],~SYM[3])-    variable ~SYM[4] : ~TYP[1];-  begin-    ~SYM[4] := ~SYM[1];-    -- pragma translate_off-    if ~SYM[2] < ~SYM[4]'low or ~SYM[2] > ~SYM[4]'high then-      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;-      ~SYM[4] := ~ERROR[1];-    else-      -- pragma translate_on-      ~SYM[4](~SYM[2] downto ~SYM[2]) := ~SYM[3];-      -- pragma translate_off-    end if;-    -- pragma translate_on-    ~RESULT <= ~SYM[4];-  end process;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.setSlice#"-    , "comment"   :-    "setSlice# :: BitVector (m + 1 + i) -- ARG[0]-               -> SNat m                -- ARG[1]-               -> SNat n                -- ARG[2]-               -> BitVector (m + 1 - n) -- ARG[3]-               -> BitVector (m + 1 + i)"-    , "templateD" :-"setSlice_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-  signal ~SYM[2] : ~TYP[3];-begin-  ~SYM[1] <= ~ARG[0];-  ~SYM[2] <= ~ARG[3];-  process(~SYM[1],~SYM[2])-    variable ~SYM[3] : ~TYP[0];-  begin-    ~SYM[3] := ~SYM[1];-    ~SYM[3](~LIT[1] downto ~LIT[2]) := ~SYM[2];-    ~RESULT <= ~SYM[3];-  end process;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.slice#"-    , "comment"   :-    "slice# :: BitVector (m + 1 + i) -- ARG[0]-            -> SNat m                -- ARG[1]-            -> SNat n                -- ARG[2]-            -> BitVector (m + 1 - n)"-    , "templateD" :-"slice_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];-  ~RESULT <= ~SYM[1](~LIT[1] downto ~LIT[2]);-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.split#"-    , "comment"   :-    "split# :: KnownNat n        -- ARG[0]-            => BitVector (m + n) -- ARG[1]-            -> (BitVector m, BitVector n)"-    , "templateD" :-"split_~SYM[0]: block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[1];-  ~RESULT <= ( ~SYM[1](~RESULT.~TYPMO_sel0'left + ~RESULT.~TYPMO_sel1'length downto-               ~RESULT.~TYPMO_sel0'right + ~RESULT.~TYPMO_sel1'length)-             , ~SYM[1](~RESULT.~TYPMO_sel1'left downto ~RESULT.~TYPMO_sel1'right)-             );-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.msb#"-    , "comment"   :-    "msb# :: KnownNat n  -- ARG[0]-          => BitVector n -- ARG[1]-          -> Bit"-    , "templateD" :-"msb_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[2]_generate : if ~SYM[1]'length = 0 generate-  begin-    ~RESULT <= \"0\";-  end generate;--  ~SYM[3]_generate : if ~SYM[1]'length /= 0 generate-    ~SYM[1] <= ~ARG[1];-    ~RESULT <= ~SYM[1](~SYM[1]'high downto ~SYM[1]'high);-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.lsb#"-    , "comment"   :-    "lsb# :: BitVector n -- ARG[0]-          -> Bit"-    , "templateD" :-"lsb_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[2]_generate : if ~SYM[1]'length = 0 generate-  begin-    ~RESULT <= \"0\";-  end generate;--  ~SYM[3]_generate : if ~SYM[1]'length /= 0 generate-  begin-    ~SYM[1] <= ~ARG[0];-    ~RESULT <= ~SYM[1](0 downto 0);-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.eq#"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.neq#"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.lt#"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.ge#"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.gt#"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.le#"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.minBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '0');"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.maxBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '1');"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.+#"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) + unsigned(~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.-#"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) - unsigned(~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.*#"-    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]) * unsigned(~ARG[2]), ~LIT[0]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.negate#"-    , "templateE" : "std_logic_vector(-(signed(~ARG[1])))"-    }-  }-, { "Primitive" :-    { "name"     : "CLaSH.Sized.Internal.BitVector.fromInteger#"-    , "primType" : "Function"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.plus#"-    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]) + resize(unsigned(~ARG[2]),~LIT[0]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.minus#"-    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]) - resize(unsigned(~ARG[2]),~LIT[0]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.times#"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) * unsigned(~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.quot#"-    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) / unsigned(~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.rem#"-    , "templateE" : "~ARG[1] rem ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.mod#"-    , "templateE" : "~ARG[1] mod ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.toInteger#"-    , "templateE" : "to_integer(unsigned(~ARG[0]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.and#"-    , "templateE" : "~ARG[0] and ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.or#"-    , "templateE" : "~ARG[0] or ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.xor#"-    , "templateE" : "~ARG[0] xor ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.complement#"-    , "templateE" : "not ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.shiftL#"-    , "templateE" : "std_logic_vector(shift_left(unsigned(~ARG[1]),~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.shiftR#"-    , "templateE" : "std_logic_vector(shift_right(unsigned(~ARG[1]),~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.rotateL#"-    , "templateE" : "std_logic_vector(rotate_left(unsigned(~ARG[1]),~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.rotateR#"-    , "templateE" : "std_logic_vector(rotate_right(unsigned(~ARG[1]),~ARG[2]))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.BitVector.resize#"-    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]))"-    }-  }-]
− primitives/CLaSH.Sized.Internal.Index.json
@@ -1,76 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.eq#"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.neq#"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.lt#"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.ge#"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.gt#"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.le#"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.maxBound#"-    , "templateE" : "to_unsigned(max(0,~LIT[0]-1),~RESULT'length);"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.+#"-    , "templateE" : "~ARG[1] + ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.-#"-    , "templateE" : "~ARG[1] - ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.*#"-    , "templateE" : "resize(~ARG[1] * ~ARG[2], ~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.fromInteger#"-    , "templateE" : "to_unsigned(~ARG[1],integer(ceil(log2(real(max(2,~LIT[0]))))))"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.quot#"-    , "templateE" : "~ARG[1] / ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.rem#"-    , "templateE" : "~ARG[1] rem ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.mod#"-    , "templateE" : "~ARG[1] mod ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Index.toInteger#"-    , "templateE" : "to_integer(~ARG[0])"-    }-  }-]
− primitives/CLaSH.Sized.Internal.Signed.json
@@ -1,186 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Internal.Signed.size#"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.pack#"-    , "templateE" : "std_logic_vector(~ARG[1])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.unpack#"-    , "templateE" : "signed(~ARG[1])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.eq#"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.neq#"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.lt#"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.ge#"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.gt#"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.le#"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.minBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "comment2"  : "the quantification with signed gives the array an ascending index"-    , "templateE" : "signed'(0 => '1', 1 to ~LIT[0]-1 => '0')"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.maxBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "comment2"  : "the quantification with signed gives the array an ascending index"-    , "templateE" : "signed'(0 => '0', 1 to ~LIT[0]-1  => '1')"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.+#"-    , "templateE" : "~ARG[1] + ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.-#"-    , "templateE" : "~ARG[1] - ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.*#"-    , "templateE" : "resize(~ARG[1] * ~ARG[2], ~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.negate#"-    , "templateE" : "-~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.abs#"-    , "templateE" : "abs ~ARG[1]"-    }-  }-, { "Primitive" :-    { "name"     : "CLaSH.Sized.Internal.Signed.fromInteger#"-    , "primType" : "Function"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.plus#"-    , "templateE" : "resize(~ARG[1],~LIT[0]) + resize(~ARG[2],~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.minus#"-    , "templateE" : "resize(~ARG[1],~LIT[0]) - resize(~ARG[2],~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.times#"-    , "templateE" : "~ARG[1] * ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.quot#"-    , "templateE" : "~ARG[1] / ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.rem#"-    , "templateE" : "~ARG[1] rem ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.div#"-    , "templateD" :-"divSigned_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-  signal ~SYM[3] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];-  ~SYM[3] <= ~SYM[1] / ~SYM[2];-  ~RESULT <= ~SYM[3] - to_signed(1,~LIT[0]) when ~SYM[1](~SYM[1]'high) = not (~SYM[2](~SYM[2]'high)) else-             ~SYM[3];-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.mod#"-    , "templateE" : "~ARG[1] mod ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.toInteger#"-    , "templateE" : "to_integer(~ARG[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.and#"-    , "templateE" : "~ARG[1] and ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.or#"-    , "templateE" : "~ARG[1] or ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.xor#"-    , "templateE" : "~ARG[1] xor ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.complement#"-    , "templateE" : "not ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.shiftL#"-    , "templateE" : "shift_left(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.shiftR#"-    , "templateE" : "shift_right(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.rotateL#"-    , "templateE" : "rotate_left(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.rotateR#"-    , "templateE" : "rotate_right(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Signed.resize#"-    , "templateE" : "resize(~ARG[2],~LIT[1])"-    }-  }-]
− primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -1,163 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.size#"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.pack#"-    , "templateE" : "std_logic_vector(~ARG[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.unpack#"-    , "templateE" : "unsigned(~ARG[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.eq#"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.neq#"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.lt#"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.ge#"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.gt#"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.le#"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.minBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '0');"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.maxBound#"-    , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '1');"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.+#"-    , "templateE" : "~ARG[1] + ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.-#"-    , "templateE" : "~ARG[1] - ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.*#"-    , "templateE" : "resize(~ARG[1] * ~ARG[2], ~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.negate#"-    , "templateE" : "unsigned(std_logic_vector(-(signed(std_logic_vector(~ARG[1])))))"-    }-  }-, { "Primitive" :-    { "name"     : "CLaSH.Sized.Internal.Unsigned.fromInteger#"-    , "primType" : "Function"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.plus#"-    , "templateE" : "resize(~ARG[1],~LIT[0]) + resize(~ARG[2],~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.minus#"-    , "templateE" : "resize(~ARG[1],~LIT[0]) - resize(~ARG[2],~LIT[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.times#"-    , "templateE" : "~ARG[1] * ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.quot#"-    , "templateE" : "~ARG[1] / ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.rem#"-    , "templateE" : "~ARG[1] rem ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.mod#"-    , "templateE" : "~ARG[1] mod ~ARG[2]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.toInteger#"-    , "templateE" : "to_integer(~ARG[0])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.and#"-    , "templateE" : "~ARG[0] and ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.or#"-    , "templateE" : "~ARG[0] or ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.xor#"-    , "templateE" : "~ARG[0] xor ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.complement#"-    , "templateE" : "not ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.shiftL#"-    , "templateE" : "shift_left(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.shiftR#"-    , "templateE" : "shift_right(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateL#"-    , "templateE" : "rotate_left(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.rotateR#"-    , "templateE" : "rotate_right(~ARG[1],~ARG[2])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Internal.Unsigned.resize#"-    , "templateE" : "resize(~ARG[1],~LIT[0])"-    }-  }-]
− primitives/CLaSH.Sized.Vector.json
@@ -1,365 +0,0 @@-[ { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.eq#"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.neq#"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.head"-    , "templateD" :-"head_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];-  ~RESULT <= ~SYM[1](0);-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.tail"-    , "templateD" :-"tail_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];-  ~RESULT <= ~SYM[1](1 to ~SYM[1]'high);-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.last"-    , "templateD" :-"last_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];-  ~RESULT <= ~SYM[1](~SYM[1]'high);-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.init"-    , "templateD" :-"init_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];-  ~RESULT <= ~SYM[1](0 to ~SYM[1]'high - 1);-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.select"-    , "comment"   :-    "select :: (CmpNat (i + s) (s * n) ~ GT) -- ARG[0]-            => SNat f                        -- ARG[1]-            -> SNat s                        -- ARG[2]-            -> SNat n                        -- ARG[3]-            -> Vec i a                       -- ARG[4]-            -> Vec n a"-    , "templateD" :-"select_~SYM[0] : block-  signal ~SYM[1] : ~TYP[4];-begin-  ~SYM[1] <= ~ARG[4];--  selectZ_~SYM[2] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  selectSN_~SYM[3] : if ~RESULT'length /= 0 generate-    selectIter_~SYM[4] : for ~SYM[5] in ~RESULT'range generate-    begin-      ~RESULT(~SYM[5]) <= ~SYM[1](~LIT[1]+(~LIT[2]*~SYM[5]));-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.++"-    , "templateE" : "~TYPM[0]'(~ARG[0]) & ~TYPM[1]'(~ARG[1])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.concat"-    , "templateD" :-"concat_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];--  concatZ_~SYM[2] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  concatSN_~SYM[3] : if ~RESULT'length /= 0 generate-    concatIter_~SYM[4] : for ~SYM[5] in ~SYM[1]'range generate-    begin-      ~RESULT((~SYM[5] * ~SYM[1](0)'length) to ((~SYM[5] * ~SYM[1](0)'length) + ~SYM[1](0)'high)) <= ~SYM[1](~SYM[5]);-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.splitAt"-    , "templateD" :-"splitAt_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[1];-  ~RESULT <= (~SYM[1](~RESULT.~TYPMO_sel0'left to ~RESULT.~TYPMO_sel0'right)-             ,~SYM[1](~RESULT.~TYPMO_sel1'left + ~RESULT.~TYPMO_sel0'length to ~RESULT.~TYPMO_sel1'right + ~RESULT.~TYPMO_sel0'length));-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.unconcat"-    , "comment"   :-    "unconcat :: KnownNat n     -- ARG[0]-              => SNat m         -- ARG[1]-              -> Vec (n * m) a  -- ARG[2]-              -> Vec n (Vec m a)"-    , "templateD" :-"unconcat_~SYM[0] : block-  signal ~SYM[1] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[2];--  unconcatZ_~SYM[2] : if ~SYM[1]'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  unconcatSN_~SYM[3] : if ~SYM[1]'length /= 0 generate-    unconcatIter_~SYM[4] : for ~SYM[5] in ~RESULT'range generate-    begin-      ~RESULT(~SYM[5]) <= ~SYM[1]((~SYM[5] * ~LIT[1]) to ((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1));-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.merge"-    , "templateD" :-"merge_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-  signal ~SYM[2] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[0];-  ~SYM[2] <= ~ARG[1];--  mergeZ_~SYM[3] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  mergeSN_~SYM[4] : if ~RESULT'length /= 0 generate-    mergeIter_~SYM[5] : for ~SYM[6] in ~SYM[1]'range generate-    begin-      ~RESULT(2*~SYM[6])   <= ~SYM[1](~SYM[6]);-      ~RESULT(2*~SYM[6]+1) <= ~SYM[2](~SYM[6]);-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.map"-    , "templateD" :-"map_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[1];--  mapZ_~SYM[2] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  mapSN_~SYM[3] : if ~RESULT'length /= 0 generate-    mapIter_~SYM[4] : for ~SYM[5] in ~RESULT'range generate-    begin-      ~INST 0-        ~OUTPUT <= ~RESULT(~SYM[5])~ ~TYPEL[~TYPO]~-        ~INPUT  <= ~SYM[1](~SYM[5])~ ~TYPEL[~TYP[1]]~-      ~INST-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.zipWith"-    , "templateD" :-"zipWith_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];--  zipWithZ_~SYM[3] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  zipWithSN_~SYM[4] : if ~RESULT'length /= 0 generate-    zipWithIter_~SYM[5] : for ~SYM[6] in ~RESULT'range generate-    begin-      ~INST 0-        ~OUTPUT <= ~RESULT(~SYM[6])~ ~TYPEL[~TYPO]~-        ~INPUT  <= ~SYM[1](~SYM[6])~ ~TYPEL[~TYP[1]]~-        ~INPUT  <= ~SYM[2](~SYM[6])~ ~TYPEL[~TYP[2]]~-      ~INST-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.index_integer"-    , "templateD" :-"indexVec_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];-  -- pragma translate_off-  process (~SYM[1],~SYM[2])-  begin-    if ~SYM[2] < ~SYM[1]'low or ~SYM[2] > ~SYM[1]'high then-      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" to \" & integer'image(~SYM[1]'high)) severity warning;-      ~RESULT <= ~ERRORO;-    else-    -- pragma translate_on-      ~RESULT <= ~SYM[1](~SYM[2]);-    -- pragma translate_off-    end if;-  end process;-  -- pragma translate_on-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.replace_integer"-    , "templateD" :-"replaceVec_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-  signal ~SYM[2] : ~TYP[2];-  signal ~SYM[3] : ~TYP[3];-begin-  ~SYM[1] <= ~ARG[1];-  ~SYM[2] <= ~ARG[2];-  ~SYM[3] <= ~ARG[3];-  process(~SYM[1],~SYM[2],~SYM[3])-    variable ~SYM[4] : ~TYP[1];-  begin-    ~SYM[4] := ~SYM[1];-    -- pragma translate_off-    if ~SYM[2] < ~SYM[4]'low or ~SYM[2] > ~SYM[4]'high then-      assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" to \" & integer'image(~SYM[1]'high)) severity warning;-      ~SYM[4] := ~ERROR[1];-    else-      -- pragma translate_on-      ~SYM[4](~SYM[2]) := ~SYM[3];-      -- pragma translate_off-    end if;-    -- pragma translate_on-    ~RESULT <= ~SYM[4];-  end process;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.maxIndex"-    , "templateE" : "~LIT[0] - 1"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.length"-    , "templateE" : "~LIT[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.replicate"-    , "templateE" : "~TYPMO'(0 to ~LIT[0]-1 => ~ARG[1])"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.reverse"-    , "templateD" :-"reverse_~SYM[0] : block-  signal ~SYM[1] : ~TYP[0];-begin-  ~SYM[1] <= ~ARG[0];--  reverseZ_~SYM[2] : if ~RESULT'length = 0 generate-    ~RESULT <= ~SYM[1];-  end generate;--  reverseSN_~SYM[3] : if ~RESULT'length /= 0 generate-    reverseIter_~SYM[4] : for ~SYM[5] in ~SYM[1]'range generate-      ~RESULT(~SYM[1]'high - ~SYM[5]) <= ~SYM[1](~SYM[5]);-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.lazyV"-    , "templateE" : "~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.concatBitVector#"-    , "comment"   :-      "concatBitVector# :: KnownNat m           -- ARG[0]-                        => Vec n (BitVector m)  -- ARG[1]-                        -> BitVector (n * m)"-    , "templateD" :-"concatBitVector_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[1];--  concatBitVectorZ_~SYM[2] : if ~RESULT'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  concatBitVectorSN_~SYM[3] : if ~RESULT'length /= 0 generate-    concatBitVectorIter_~SYM[4] : for ~SYM[5] in ~SYM[1]'range generate-      ~RESULT(((~SYM[5] * ~LIT[0]) + ~LIT[0] - 1) downto (~SYM[5] * ~LIT[0])) <= ~TYPMO(~SYM[1](~SYM[5]));-    end generate;-  end generate;-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "CLaSH.Sized.Vector.unconcatBitVector#"-    , "comment"   :-      "unconcatBitVector# :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])-                          => BitVector (n * m)        -- ARG[2]-                          -> Vec n (BitVector m)"-    , "templateD" :-"unconcatBitVector_~SYM[0] : block-  signal ~SYM[1] : ~TYP[2];-begin-  ~SYM[1] <= ~ARG[2];--  unconcatBitVectorZ_~SYM[2] : if ~SYM[1]'length = 0 generate-    ~RESULT <= ~ERRORO;-  end generate;--  unconcatBitVectorSN_~SYM[3] : if ~SYM[1]'length /= 0 generate-    unconcatBitVectorIter_~SYM[4] : for ~SYM[5] in ~RESULT'range generate-      ~RESULT(~SYM[5]) <= ~SYM[1](((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1) downto (~SYM[5] * ~LIT[1]));-    end generate;-  end generate;-end block;"-    }-  }-]
− primitives/Control.Exception.Base.json
@@ -1,21 +0,0 @@-[ { "BlackBox" :-    { "name"      : "Control.Exception.Base.patError"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "Control.Exception.Base.irrefutPatError"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "Control.Exception.Base.recSelError"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "Control.Exception.Base.absentError"-    , "templateE" : "~ERRORO"-    }-  }-]
− primitives/GHC.Base.json
@@ -1,33 +0,0 @@-[ { "Primitive" :-    { "name"      : "GHC.Base.$"-    , "primType"  : "Function"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Base.quotInt"-    , "templateE" : "~ARG[0] div ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Base.remInt"-    , "templateE" : "~ARG[0] rem ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Base.divInt"-    , "templateD" :-"divInt_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[0] / ~ARG[1];-  ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else-             ~SYM[1];-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Base.modInt"-    , "templateE" : "~ARG[0] mod ~ARG[1]"-    }-  }-]
− primitives/GHC.CString.json
@@ -1,11 +0,0 @@-[ { "Primitive" :-    { "name"     : "GHC.CString.unpackCString#"-    , "primType" : "Function"-    }-  }-, { "Primitive" :-    { "name"     : "GHC.CString.unpackCStringUtf8#"-    , "primType" : "Function"-    }-  }-]
− primitives/GHC.Classes.json
@@ -1,63 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.Classes.eqInt"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.neInt"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.gtInt"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.geInt"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.ltInt"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.leInt"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.&&"-    , "templateE" : "~ARG[0] and ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.||"-    , "templateE" : "~ARG[0] or ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.not"-    , "templateE" : "not ~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.divInt#"-    , "templateD" :-"divInt_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[0] / ~ARG[1];-  ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else-             ~SYM[1];-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Classes.modInt#"-    , "templateE" : "~ARG[0] mod ~ARG[1]"-    }-  }-]
− primitives/GHC.Err.json
@@ -1,11 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.Err.error"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Err.undefined"-    , "templateE" : "~ERRORO"-    }-  }-]
− primitives/GHC.Integer.Type.json
@@ -1,133 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.Integer.Type.smallInteger"-    , "templateE" : "~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.integerToInt"-    , "templateE" : "~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.plusInteger"-    , "templateE" : "~ARG[0] + ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.minusInteger"-    , "templateE" : "~ARG[0] - ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.timesInteger"-    , "templateE" : "~ARG[0] * ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.negateInteger"-    , "templateE" : "-~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.absInteger"-    , "templateE" : "abs ~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.divInteger"-    , "templateD" :-"divInteger_~SYM[0] : block-  signal ~SYM[1] : ~TYP[1];-begin-  ~SYM[1] <= ~ARG[0] / ~ARG[1];-  ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else-             ~SYM[1];-end block;"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.modInteger"-    , "templateE" : "~ARG[0] mod ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.quotInteger"-    , "templateE" : "~ARG[0] div ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.remInteger"-    , "templateE" : "~ARG[0] rem ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.eqInteger"-    , "templateE" : "~ARG[0] = ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.neqInteger"-    , "templateE" : "~ARG[0] /= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.leInteger"-    , "templateE" : "~ARG[0] <= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.gtInteger"-    , "templateE" : "~ARG[0] > ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.ltInteger"-    , "templateE" : "~ARG[0] < ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.geInteger"-    , "templateE" : "~ARG[0] >= ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.eqInteger#"-    , "templateE" : "1 when ~ARG[0] = ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.neqInteger#"-    , "templateE" : "1 when ~ARG[0] /= ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.leInteger#"-    , "templateE" : "1 when ~ARG[0] <= ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.gtInteger#"-    , "templateE" : "1 when ~ARG[0] > ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.ltInteger#"-    , "templateE" : "1 when ~ARG[0] < ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.geInteger#"-    , "templateE" : "1 when ~ARG[0] >= ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.shiftRInteger"-    , "templateE" : "~ARG[0] / (2**~ARG[1])"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Integer.Type.shiftLInteger"-    , "templateE" : "~ARG[0] * (2**~ARG[1])"-    }-  }-]
− primitives/GHC.Prim.json
@@ -1,76 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.Prim.+#"-    , "templateE" : "~ARG[0] + ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.-#"-    , "templateE" : "~ARG[0] - ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.*#"-    , "templateE" : "~ARG[0] * ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.quotInt#"-    , "templateE" : "~ARG[0] div ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.remInt#"-    , "templateE" : "~ARG[0] rem ~ARG[1]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.negateInt#"-    , "templateE" : "-~ARG[0]"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.>#"-    , "templateE" : "1 when ~ARG[0] > ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.>=#"-    , "templateE" : "1 when ~ARG[0] >= ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.==#"-    , "templateE" : "1 when ~ARG[0] = ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim./=#"-    , "templateE" : "1 when ~ARG[0] /= ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.<#"-    , "templateE" : "1 when ~ARG[0] < ~ARG[1] else 0"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.<=#"-    , "templateE" : "1 when ~ARG[0] <= ~ARG[1] else 0"-    }-  }-, { "Primitive" :-    { "name"     : "GHC.Prim.dataToTag#"-    , "primType" : "Function"-    }-  }-, { "Primitive" :-    { "name"     : "GHC.Prim.tagToEnum#"-    , "primType" : "Function"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Prim.unsafeCoerce#"-    , "templateE" : "~ARG[0]"-    }-  }-]
− primitives/GHC.Real.json
@@ -1,16 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.Real.divZeroError"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Real.ratioZeroDenominatorError"-    , "templateE" : "~ERRORO"-    }-  }-, { "BlackBox" :-    { "name"      : "GHC.Real.overflowError"-    , "templateE" : "~ERRORO"-    }-  }-]
− primitives/GHC.Typelits.json
@@ -1,6 +0,0 @@-[ { "BlackBox" :-    { "name"      : "GHC.TypeLits.natVal"-    , "templateE" : "~LIT[0]"-    }-  }-]
− primitives/GHC.Types.json
@@ -1,11 +0,0 @@-[ { "Primitive" :-    { "name"      : "GHC.Types.Eq#"-    , "primType"  : "Constructor"-    }-  }-, { "Primitive" :-    { "name"      : "GHC.Types.MkCoercible"-    , "primType"  : "Constructor"-    }-  }-]
− primitives/Unsafe.Coerce.json
@@ -1,6 +0,0 @@-[ { "BlackBox" :-    { "name"      : "Unsafe.Coerce.unsafeCoerce"-    , "templateE" : "~ARG[0]"-    }-  }-]
src-bin/InteractiveUI.hs view
@@ -14,7 +14,8 @@         GhciSettings(..),         defaultGhciSettings,         ghciCommands,-        ghciWelcomeMsg+        ghciWelcomeMsg,+        makeHDL     ) where  #include "HsVersions.h"@@ -102,6 +103,9 @@ import GHC.IO.Handle ( hFlushAll ) import GHC.TopHandler ( topHandler ) +import qualified CLaSH.Backend+import           CLaSH.Backend.VHDL (VHDLState)+import           CLaSH.Backend.SystemVerilog (SystemVerilogState) import qualified CLaSH.Driver import           CLaSH.GHC.Evaluator import           CLaSH.GHC.GenerateBindings@@ -112,23 +116,6 @@ import qualified Data.Version as Data.Version import qualified Paths_clash_ghc -#ifdef STANDALONE--import qualified Control.Exception--getDefPrimDir :: IO FilePath-getDefPrimDir = catchIO_ (getEnv "CLASH_PRIMDIR") (error "Environment variable \"CLASH_PRIMDIR\" undefined")--catchIO_ :: IO a -> (Exception.IOException -> IO a) -> IO a-catchIO_ = Control.Exception.catch--#else--getDefPrimDir :: IO FilePath-getDefPrimDir = Paths_clash_ghc.getDataFileName "primitives"--#endif- -----------------------------------------------------------------------------  data GhciSettings = GhciSettings {@@ -211,7 +198,8 @@   ("trace",     keepGoing traceCmd,             completeExpression),   ("undef",     keepGoing undefineMacro,        completeMacro),   ("unset",     keepGoing unsetOptions,         completeSetOptions),-  ("vhdl",      keepGoingPaths makeVHDL,        completeHomeModuleOrFile)+  ("vhdl",      keepGoingPaths makeVHDL,        completeHomeModuleOrFile),+  ("systemverilog",   keepGoingPaths makeSystemVerilog,     completeHomeModuleOrFile)   ]  @@ -1493,27 +1481,40 @@   when (verbosity dflags > 0) $      liftIO $ putStrLn $ showSDocForUser dflags unqual msg -makeVHDL :: [FilePath] -> InputT GHCi ()-makeVHDL [] = do-  modGraph <- GHC.getModuleGraph-  dflags <- getDynFlags-  let sortedGraph = GHC.topSortModuleGraph False modGraph Nothing-  case (reverse sortedGraph) of-    (AcyclicSCC top):_ -> do-      let loc = (GHC.ml_hs_file . GHC.ms_location) top-      maybe (return ()) (\src -> liftIO $ do primDir <- getDefPrimDir-                                             primMap <- CLaSH.Primitives.Util.generatePrimMap [primDir,"."]-                                             (bindingsMap,tcm) <- generateBindings primMap src (Just dflags)-                                             CLaSH.Driver.generateVHDL bindingsMap primMap tcm ghcTypeToHWType reduceConstant DebugNone-                        ) loc-    _ -> return ()-makeVHDL srcs = do-  dflags <- getDynFlags-  liftIO $ do primDir <- getDefPrimDir+makeHDL' :: CLaSH.Backend.Backend backend+         => backend+         -> [FilePath]+         -> InputT GHCi ()+makeHDL' backend lst = makeHDL backend =<< case lst of+  srcs@(_:_) -> return srcs+  []         -> do+    modGraph <- GHC.getModuleGraph+    let sortedGraph = GHC.topSortModuleGraph False modGraph Nothing+    return $ case (reverse sortedGraph) of+      ((AcyclicSCC top) : _) -> maybeToList $ (GHC.ml_hs_file . GHC.ms_location) top+      _                      -> []++makeHDL :: GHC.GhcMonad m+        => CLaSH.Backend.Backend backend+        => backend+        -> [FilePath]+        -> m ()+makeHDL backend srcs = do+  dflags <- GHC.getSessionDynFlags+  liftIO $ do primDir <- CLaSH.Backend.primDir backend               primMap <- CLaSH.Primitives.Util.generatePrimMap [primDir,"."]-              mapM_ (\src -> do (bindingsMap,tcm) <- generateBindings primMap src (Just dflags)-                                CLaSH.Driver.generateVHDL bindingsMap primMap tcm ghcTypeToHWType reduceConstant DebugNone-                    ) srcs+              forM_ srcs $ \src -> do+                (bindingsMap,tcm) <- generateBindings primMap src (Just dflags)+                CLaSH.Driver.generateHDL bindingsMap (Just backend) primMap tcm+                  ghcTypeToHWType reduceConstant DebugNone++++makeVHDL :: [FilePath] -> InputT GHCi ()+makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: VHDLState)++makeSystemVerilog :: [FilePath] -> InputT GHCi ()+makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: SystemVerilogState)  ----------------------------------------------------------------------------- -- :type
src-bin/Main.hs view
@@ -63,25 +63,18 @@ import Data.Maybe  -- clash additions-#ifdef STANDALONE import           System.Process (runInteractiveCommand, waitForProcess)-import qualified Control.Exception as Exception-#else-import qualified GHC.Paths import           Paths_clash_ghc-#endif+import           InteractiveUI (makeHDL) import           Exception (gcatch) import qualified Data.Version (showVersion) import           Control.Exception (ErrorCall (..))-import qualified CLaSH.Driver-import           CLaSH.GHC.Evaluator-import           CLaSH.GHC.GenerateBindings-import           CLaSH.GHC.NetlistTypes-import qualified CLaSH.Primitives.Util-import           CLaSH.Rewrite.Types (DebugLevel(..))++import qualified CLaSH.Backend+import           CLaSH.Backend.VHDL    (VHDLState)+import           CLaSH.Backend.SystemVerilog (SystemVerilogState) import           CLaSH.Util (clashLibVersion) -#ifdef STANDALONE ghcLibDir :: IO FilePath ghcLibDir = do (libDir,exitCode) <- getProcessOutput "ghc --print-libdir"                case exitCode of@@ -99,20 +92,6 @@      -- return both the output and the exit code.      return (output, exitCode) -getDefPrimDir :: IO FilePath-getDefPrimDir = catchIO (getEnv "CLASH_PRIMDIR") (error "Environment variable \"CLASH_PRIMDIR\" undefined")--catchIO :: IO a -> (Exception.IOException -> IO a) -> IO a-catchIO = Exception.catch-#else-ghcLibDir :: IO FilePath-ghcLibDir = return GHC.Paths.libdir--getDefPrimDir :: IO FilePath-getDefPrimDir = getDataFileName "primitives"-#endif-- ----------------------------------------------------------------------------- -- ToDo: @@ -207,6 +186,7 @@                DoMkDependHS    -> (MkDepend,    dflt_target,    LinkBinary)                DoAbiHash       -> (OneShot,     dflt_target,    LinkBinary)                DoVHDL          -> (CompManager, dflt_target,    LinkInMemory)+               DoSystemVerilog -> (CompManager, dflt_target,    LinkInMemory)                _               -> (OneShot,     dflt_target,    LinkBinary)    let dflags1 = case lang of@@ -283,10 +263,13 @@   liftIO $ checkOptions postLoadMode dflags6 srcs objs    ---------------- Do the business ------------  handleSourceError (\e -> do-       GHC.printException e-       liftIO $ exitWith (ExitFailure 1)) $ do-    case postLoadMode of+  handleSourceError+    (\e -> do+        GHC.printException e+        liftIO $ exitWith (ExitFailure 1))+    $ do+      let clash fun = gcatch (fun srcs) (\(ErrorCall e) -> throwOneError $ mkPlainErrMsg dflags6 noSrcSpan (text ("CLaSH Error:\n" ++ e)))+      case postLoadMode of        ShowInterface f        -> liftIO $ doShowIface dflags6 f        DoMake                 -> doMake srcs        DoMkDependHS           -> doMkDependHS (map fst srcs)@@ -294,7 +277,8 @@        DoInteractive          -> ghciUI srcs Nothing        DoEval exprs           -> ghciUI srcs $ Just $ reverse exprs        DoAbiHash              -> abiHash srcs-       DoVHDL                 -> gcatch (doVHDL srcs) (\(ErrorCall e) -> throwOneError $ mkPlainErrMsg dflags6 noSrcSpan (text ("CLaSH Error:\n" ++ e)))+       DoVHDL                 -> clash makeVHDL+       DoSystemVerilog        -> clash makeSystemVerilog    liftIO $ dumpFinalStats dflags6 @@ -494,13 +478,15 @@   | DoEval [String]         -- ghc -e foo -e bar => DoEval ["bar", "foo"]   | DoAbiHash               -- ghc --abi-hash   | DoVHDL                  -- ghc --vhdl+  | DoSystemVerilog         -- ghc --systemverilog -doMkDependHSMode, doMakeMode, doInteractiveMode, doAbiHashMode, doVHDLMode :: Mode+doMkDependHSMode, doMakeMode, doInteractiveMode, doAbiHashMode, doVHDLMode, doSystemVerilogMode :: Mode doMkDependHSMode = mkPostLoadMode DoMkDependHS doMakeMode = mkPostLoadMode DoMake doInteractiveMode = mkPostLoadMode DoInteractive doAbiHashMode = mkPostLoadMode DoAbiHash doVHDLMode = mkPostLoadMode DoVHDL+doSystemVerilogMode = mkPostLoadMode DoSystemVerilog  showInterfaceMode :: FilePath -> Mode showInterfaceMode fp = mkPostLoadMode (ShowInterface fp)@@ -543,6 +529,7 @@ needsInputsMode (StopBefore _)  = True needsInputsMode DoMake          = True needsInputsMode DoVHDL          = True+needsInputsMode DoSystemVerilog = True needsInputsMode _               = False  -- True if we are going to attempt to link in this mode.@@ -553,14 +540,16 @@ isLinkMode DoInteractive       = True isLinkMode (DoEval _)          = True isLinkMode DoVHDL              = True+isLinkMode DoSystemVerilog     = True isLinkMode _                   = False  isCompManagerMode :: PostLoadMode -> Bool-isCompManagerMode DoMake        = True-isCompManagerMode DoInteractive = True-isCompManagerMode (DoEval _)    = True-isCompManagerMode DoVHDL        = True-isCompManagerMode _             = False+isCompManagerMode DoMake          = True+isCompManagerMode DoInteractive   = True+isCompManagerMode (DoEval _)      = True+isCompManagerMode DoVHDL          = True+isCompManagerMode DoSystemVerilog = True+isCompManagerMode _               = False  -- ----------------------------------------------------------------------------- -- Parsing the mode flag@@ -623,25 +612,26 @@         replaceSpace c   = c   ] ++       ------- interfaces -----------------------------------------------------  [ Flag "-show-iface"  (HasArg (\f -> setMode (showInterfaceMode f)+  [ Flag "-show-iface"    (HasArg (\f -> setMode (showInterfaceMode f)                                                "--show-iface"))        ------- primary modes -------------------------------------------------  , Flag "c"            (PassFlag (\f -> do setMode (stopBeforeMode StopLn) f-                                            addFlag "-no-link" f))-  , Flag "M"            (PassFlag (setMode doMkDependHSMode))-  , Flag "E"            (PassFlag (setMode (stopBeforeMode anyHsc)))-  , Flag "C"            (PassFlag (setMode (stopBeforeMode HCc)))+  , Flag "c"              (PassFlag (\f -> do setMode (stopBeforeMode StopLn) f+                                              addFlag "-no-link" f))+  , Flag "M"              (PassFlag (setMode doMkDependHSMode))+  , Flag "E"              (PassFlag (setMode (stopBeforeMode anyHsc)))+  , Flag "C"              (PassFlag (setMode (stopBeforeMode HCc))) #if MIN_VERSION_ghc(7,8,3)-  , Flag "S"            (PassFlag (setMode (stopBeforeMode (As False))))+  , Flag "S"              (PassFlag (setMode (stopBeforeMode (As False)))) #else-  , Flag "S"            (PassFlag (setMode (stopBeforeMode As)))+  , Flag "S"              (PassFlag (setMode (stopBeforeMode As))) #endif-  , Flag "-make"        (PassFlag (setMode doMakeMode))-  , Flag "-interactive" (PassFlag (setMode doInteractiveMode))-  , Flag "-abi-hash"    (PassFlag (setMode doAbiHashMode))-  , Flag "e"            (SepArg   (\s -> setMode (doEvalMode s) "-e"))-  , Flag "-vhdl"        (PassFlag (setMode doVHDLMode))+  , Flag "-make"          (PassFlag (setMode doMakeMode))+  , Flag "-interactive"   (PassFlag (setMode doInteractiveMode))+  , Flag "-abi-hash"      (PassFlag (setMode doAbiHashMode))+  , Flag "e"              (SepArg   (\s -> setMode (doEvalMode s) "-e"))+  , Flag "-vhdl"          (PassFlag (setMode doVHDLMode))+  , Flag "-systemverilog" (PassFlag (setMode doSystemVerilogMode))   ]  setMode :: Mode -> String -> EwM ModeM ()@@ -897,15 +887,15 @@ -- ----------------------------------------------------------------------------- -- VHDL Generation -doVHDL :: [(String,Maybe Phase)] -> Ghc ()-doVHDL []   = throwGhcException (CmdLineError "No input files")-doVHDL srcs = do-  dflags <- GHC.getSessionDynFlags-  liftIO $ do primDir <- getDefPrimDir-              primMap <- CLaSH.Primitives.Util.generatePrimMap [primDir,"."]-              mapM_ (\(src,_) -> do (bindingsMap,tcm) <- generateBindings primMap src (Just dflags)-                                    CLaSH.Driver.generateVHDL bindingsMap primMap tcm ghcTypeToHWType reduceConstant DebugNone-                    ) srcs+makeHDL' :: CLaSH.Backend.Backend backend => backend -> [(String,Maybe Phase)] -> Ghc ()+makeHDL' _       []   = throwGhcException (CmdLineError "No input files")+makeHDL' backend srcs = makeHDL backend $ fmap fst srcs++makeVHDL :: [(String, Maybe Phase)] -> Ghc ()+makeVHDL = makeHDL' (CLaSH.Backend.initBackend :: VHDLState)++makeSystemVerilog :: [(String, Maybe Phase)] -> Ghc ()+makeSystemVerilog = makeHDL' (CLaSH.Backend.initBackend :: SystemVerilogState)  -- ----------------------------------------------------------------------------- -- Util
src-ghc/CLaSH/GHC/Evaluator.hs view
@@ -7,7 +7,7 @@ import qualified Data.Either         as Either import qualified Data.HashMap.Strict as HashMap import qualified Data.List           as List-import           Unbound.LocallyNameless (bind, embed, string2Name)+import           Unbound.Generics.LocallyNameless (bind, embed, string2Name)  import           CLaSH.Core.DataCon  (dcTag) import           CLaSH.Core.Literal  (Literal (..))@@ -26,13 +26,13 @@         | i == j    -> Literal (IntegerLiteral 1)         | otherwise -> Literal (IntegerLiteral 0)       _ -> e-  | nm == "GHC.Integer.Type.gtInteger#"+  | nm == "GHC.Prim.>#" || nm == "GHC.Integer.Type.gtInteger#"   = case (map (reduceConstant tcm) . Either.lefts) args of       [Literal (IntegerLiteral i), Literal (IntegerLiteral j)]         | i > j     -> Literal (IntegerLiteral 1)         | otherwise -> Literal (IntegerLiteral 0)       _ -> e-  | nm == "GHC.Integer.Type.ltInteger#"+  | nm == "GHC.Prim.<#" || nm == "GHC.Integer.Type.ltInteger#"   = case (map (reduceConstant tcm) . Either.lefts) args of       [Literal (IntegerLiteral i), Literal (IntegerLiteral j)]         | i < j     -> Literal (IntegerLiteral 1)
src-ghc/CLaSH/GHC/GHC2Core.hs view
@@ -26,10 +26,11 @@ import           Data.Maybe                  (fromMaybe) import           Data.Text                   (isInfixOf,pack) import qualified Data.Traversable            as T-import           Unbound.LocallyNameless     (Rep, bind, embed, rebind, rec,+import           Data.Typeable               (Typeable)+import           Unbound.Generics.LocallyNameless     (bind, embed, rebind, rec,                                               runFreshM, string2Name, unbind,                                               unembed)-import qualified Unbound.LocallyNameless     as Unbound+import qualified Unbound.Generics.LocallyNameless     as Unbound  -- GHC API import           CLaSH.GHC.Compat.FastString (unpackFB, unpackFS)@@ -378,7 +379,7 @@ coreToId i =   C.Id <$> (coreToVar i) <*> (embed <$> coreToType (varType i)) -coreToVar :: Rep a+coreToVar :: Typeable a           => Var           -> State GHC2CoreState (Unbound.Name a) coreToVar = coreToName varName varUnique qualfiedNameStringM@@ -387,7 +388,7 @@               -> State GHC2CoreState (Unbound.Name C.Term) coreToPrimVar = coreToName varName varUnique qualfiedNameString -coreToName :: Rep a+coreToName :: Typeable a            => (b -> Name)            -> (b -> Unique)            -> (Name -> State GHC2CoreState String)@@ -420,13 +421,13 @@  -- | Given the type: ----- @forall a. forall b. forall clk. (a -> b) -> CSignal clk a -> CSignal clk b@+-- @forall a. forall b. forall clk. (a -> b) -> Signal' clk a -> Signal' clk b@ -- -- Generate the term: -- -- @--- /\(a:*)./\(b:*)./\(clk:Clock).\(f : (CSignal clk a -> CSignal clk b)).--- \(x : CSignal clk a).f x+-- /\(a:*)./\(b:*)./\(clk:Clock).\(f : (Signal' clk a -> Signal' clk b)).+-- \(x : Signal' clk a).f x -- @ mapSignalTerm :: C.Type               -> C.Term@@ -456,11 +457,11 @@  -- | Given the type: ----- @forall a. forall clk. a -> CSignal clk a@+-- @forall a. forall clk. a -> Signal' clk a@ -- -- Generate the term ----- @/\(a:*)./\(clk:Clock).\(x:CSignal clk a).x@+-- @/\(a:*)./\(clk:Clock).\(x:Signal' clk a).x@ signalTerm :: C.Type            -> C.Term signalTerm (C.ForAllTy tvATy) =@@ -483,15 +484,15 @@ -- | Given the type: -- -- @--- forall clk. forall a. forall b. CSignal clk (a -> b) -> CSignal clk a ->--- CSignal clk b+-- forall clk. forall a. forall b. Signal' clk (a -> b) -> Signal' clk a ->+-- Signal' clk b -- @ -- -- Generate the term: -- -- @--- /\(clk:Clock)./\(a:*)./\(b:*).\(f : (CSignal clk a -> CSignal clk b)).--- \(x : CSignal clk a).f x+-- /\(clk:Clock)./\(a:*)./\(b:*).\(f : (Signal' clk a -> Signal' clk b)).+-- \(x : Signal' clk a).f x -- @ appSignalTerm :: C.Type               -> C.Term@@ -522,14 +523,14 @@ -- | Given the type: -- -- @--- forall t.forall n.forall a.SClock t -> Vec n (CSignal t a) ->--- CSignal t (Vec n a)+-- forall t.forall n.forall a.SClock t -> Vec n (Signal' t a) ->+-- Signal' t (Vec n a) -- @ -- -- Generate the term: -- -- @--- /\(t:Clock)./\(n:Nat)./\(a:*).\(sclk:SClock t).\(vs:CSignal (Vec n a)).vs+-- /\(t:Clock)./\(n:Nat)./\(a:*).\(sclk:SClock t).\(vs:Signal' (Vec n a)).vs -- @ vecUnwrapTerm :: C.Type               -> C.Term@@ -560,14 +561,14 @@ -- -- @ -- forall f.forall a.forall b.forall clk.Applicative f => (a -> f b) ->--- CSignal clk a -> f (CSignal clk b)+-- CSignal clk a -> f (Signal' clk b) -- @ -- -- Generate the term: -- -- @ -- /\(f:* -> *)./\(a:*)./\(b:*)./\(clk:Clock).\(dict:Applicative f).--- \(g:a -> f b).\(x:CSignal clk a).g x+-- \(g:a -> f b).\(x:Signal' clk a).g x -- @ traverseTerm :: C.Type              -> C.Term
src-ghc/CLaSH/GHC/GenerateBindings.hs view
@@ -9,7 +9,8 @@ import qualified Data.HashMap.Strict     as HashMap import           Data.List               (isSuffixOf) import qualified Data.Set                as Set-import           Unbound.LocallyNameless (name2String, runFreshM, unembed)+import qualified Data.Set.Lens           as Lens+import           Unbound.Generics.LocallyNameless (name2String, runFreshM, unembed)  import qualified CoreSyn                 as GHC import qualified DynFlags                as GHC@@ -58,7 +59,7 @@ retype tcm (visited,bindings) current = (visited', HashMap.insert current (ty',tm') bindings')   where     (_,tm)               = bindings HashMap.! current-    used                 = Set.toList $ termFreeIds tm+    used                 = Set.toList $ Lens.setOf termFreeIds tm     (visited',bindings') = foldl (retype tcm) (current:visited,bindings) (filter (`notElem` visited) used)     usedTys              = map (fst . (bindings' HashMap.!)) used     usedVars             = zipWith Var usedTys used
src-ghc/CLaSH/GHC/LoadModules.hs view
@@ -8,14 +8,10 @@ where  -- External Modules-#ifdef STANDALONE import           System.Exit                  (ExitCode (..)) import           System.IO                    (hGetLine) import           System.Process               (runInteractiveCommand,                                                waitForProcess)-#else-import qualified GHC.Paths-#endif  -- GHC API import           CLaSH.GHC.Compat.DynFlags    (dopt_set, dopt_unset)@@ -40,7 +36,6 @@ import           CLaSH.GHC.LoadInterfaceFiles import           CLaSH.Util                   (curLoc,first) -#ifdef STANDALONE ghcLibDir :: IO FilePath ghcLibDir = do (libDir,exitCode) <- getProcessOutput "ghc --print-libdir"                case exitCode of@@ -57,10 +52,6 @@      output   <- hGetLine pOut      -- return both the output and the exit code.      return (output, exitCode)-#else-ghcLibDir :: IO FilePath-ghcLibDir = return GHC.Paths.libdir-#endif  loadModules ::   String@@ -166,7 +157,6 @@              , Opt_ForceRecomp -- Force recompilation: never bad              , Opt_EnableRewriteRules -- Reduce number of functions              , Opt_SimplPreInlining -- Inlines simple functions, we only care about the major first-order structure-             , Opt_Strictness -- Strictness analysis helps with dead-code analysis              , Opt_StaticArgumentTransformation -- Turn on the static argument transformation, which turns a recursive function into a non-recursive one with a local recursive loop.              , Opt_FloatIn -- Moves let-bindings inwards, although it defeats the normal-form with a single top-level let-binding, it helps with other transformations              , Opt_DictsStrict -- Hopefully helps remove class method selectors@@ -192,4 +182,23 @@                , Opt_OmitInterfacePragmas -- We need all the unfoldings we can get                , Opt_IrrefutableTuples -- Introduce irrefutPatError: avoid                , Opt_Loopification -- STG pass, don't care+               -- TODO: Enable this optimization again. At the moment we disable+               -- it because it causes GHC to do the so-called "Constructed+               -- Product Result" (CPR) analysis, which in turn creates an+               -- annoying worker/wrapper which does the following:+               --+               --   * Scrutinise a Signal, and pack the head and tail of the+               --     Signal in an unboxed tuple.+               --   * Scrutinise on the unboxed tuple, and recreate the Signal.+               --+               -- This is problematic because the 'Signal' type is essentially treated as a "transparent"+               -- type by the CLaSH compiler, so observing its constructor leads to all kinds+               -- of problems.+               --+               -- Ultimately we should stop treating Signal as a "transparent" type and deal+               -- handling of the Signal type, and the involved co-recursive functions,+               -- properly. At the moment, CLaSH cannot deal with this recursive type and the+               -- recursive functions involved, and hence we need to disable this useful transformation. After+               -- everything is done properly, we should enable it again.+               , Opt_Strictness -- Strictness analysis helps with dead-code analysis... but,see TODO above                ]
src-ghc/CLaSH/GHC/NetlistTypes.hs view
@@ -6,7 +6,7 @@  import Data.HashMap.Strict       (HashMap,(!)) import Control.Monad.Trans.Error (ErrorT(..))-import Unbound.LocallyNameless   (name2String)+import Unbound.Generics.LocallyNameless   (name2String)  import CLaSH.Core.Pretty         (showDoc) import CLaSH.Core.TyCon          (TyCon (..), TyConName)@@ -32,7 +32,7 @@     "GHC.Prim.~#"                   ->       fail $ "Can't translate type: " ++ showDoc ty -    "CLaSH.Signal.Internal.CSignal" ->+    "CLaSH.Signal.Internal.Signal'" ->       ErrorT $ return $ coreTypeToHWType ghcTypeToHWType m (args !! 1)      "CLaSH.Sized.Internal.BitVector.BitVector" ->