diff --git a/CHANGELOG.md b/CHANGELOG.md --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # Revision history for bindings-libpci +## 0.2.0.0 -- 2020-12-10 +* Add pkgconfig bounds for libpci + ## 0.1.0.0 -- 2020-11-23 * First version. diff --git a/bindings-libpci.cabal b/bindings-libpci.cabal --- a/bindings-libpci.cabal +++ b/bindings-libpci.cabal @@ -1,6 +1,6 @@ cabal-version: 2.4 name: bindings-libpci -version: 0.1.0.0 +version: 0.2.0.0 synopsis: Low level bindings to libpci description: Low level bindings to libpci: . @@ -24,9 +24,38 @@ location: git://github.com/standardsemiconductor/bindings-libpci.git branch: main +flag libpci-352 + description: + libpci is 3.5.2 or later + +flag libpci-353 + description: + libpci is 3.5.3 or later + +flag libpci-355 + description: + libpci is 3.5.5 or later + +flag libpci-360 + description: + libpci is 3.6.0 or later + +flag libpci-363 + description: + libpci is 3.6.3 or later + +flag libpci-364 + description: + libpci is 3.6.4 or later + +flag libpci-370 + description: + libpci is 3.7.0 or later + library hs-source-dirs: src - default-extensions: ForeignFunctionInterface + default-extensions: ForeignFunctionInterface, + CPP build-depends: base >= 4.12 && < 4.15, bindings-DSL >= 1.0.24 && < 1.1 @@ -39,4 +68,24 @@ includes: pci.h extra-libraries: libpci else - pkgconfig-depends: libpci >= 3.5.2 + if flag(libpci-352) + pkgconfig-depends: libpci >= 3.5.2 + cpp-options: -DMIN_VERSION_LIBPCI_3_5_2 + if flag(libpci-353) + pkgconfig-depends: libpci >= 3.5.3 + cpp-options: -DMIN_VERSION_LIBPCI_3_5_3 + if flag(libpci-355) + pkgconfig-depends: libpci >= 3.5.5 + cpp-options: -DMIN_VERSION_LIBPCI_3_5_5 + if flag(libpci-360) + pkgconfig-depends: libpci >= 3.6.0 + cpp-options: -DMIN_VERSION_LIBPCI_3_6_0 + if flag(libpci-363) + pkgconfig-depends: libpci >= 3.6.3 + cpp-options: -DMIN_VERSION_LIBPCI_3_6_3 + if flag(libpci-364) + pkgconfig-depends: libpci >= 3.6.4 + cpp-options: -DMIN_VERSION_LIBPCI_3_6_4 + if flag(libpci-370) + pkgconfig-depends: libpci >= 3.7.0 + cpp-options: -DMIN_VERSION_LIBPCI_3_7_0 diff --git a/src/Bindings/Libpci/Header.hsc b/src/Bindings/Libpci/Header.hsc --- a/src/Bindings/Libpci/Header.hsc +++ b/src/Bindings/Libpci/Header.hsc @@ -6,30 +6,73 @@ import Foreign.Ptr #strict_import - +-- Under PCI, each device has 256 bytes of configuration address space, +-- of which the first 64 bytes are standardized as follows: +-- | 0x00 16 bits #num PCI_VENDOR_ID + +-- | 0x02 16 bits #num PCI_DEVICE_ID + +-- | 0x04 16 bits #num PCI_COMMAND + +-- | 0x1 Enable response in I/O space #num PCI_COMMAND_IO + +-- | 0x2 Enable response in Memory space #num PCI_COMMAND_MEMORY + +-- | 0x4 Enable bus mastering #num PCI_COMMAND_MASTER + +-- | 0x8 Enable response to special cycles #num PCI_COMMAND_SPECIAL + +-- | 0x10 Use memory write and invalidate #num PCI_COMMAND_INVALIDATE + +-- | 0x20 Enable palette snooping #num PCI_COMMAND_VGA_PALETTE + +-- | 0x40 Enable parity checking #num PCI_COMMAND_PARITY + +-- | 0x80 Enable address/data stepping #num PCI_COMMAND_WAIT + +-- | 0x100 Enable SERR #num PCI_COMMAND_SERR + +-- | 0x200 Enable back-to-back writes #num PCI_COMMAND_FAST_BACK + +-- | 0x400 PCIE: Disable INTx interrupts #num PCI_COMMAND_DISABLE_INTx + +-- | 0x06 16 bits #num PCI_STATUS + +-- | 0x08 PCIE: INTx interrupt pending #num PCI_STATUS_INTx + +-- | 0x10 Support Capability List #num PCI_STATUS_CAP_LIST + +-- | 0x20 Support 66 Mhz PCI 2.1 bus #num PCI_STATUS_66MHZ + +-- | 0x40 Support User Definable Features [obsolete] #num PCI_STATUS_UDF + +-- | 0x80 Accept fast-back to back #num PCI_STATUS_FAST_BACK + +-- | 0x100 Detected parity error #num PCI_STATUS_PARITY + #num PCI_STATUS_DEVSEL_MASK #num PCI_STATUS_DEVSEL_FAST #num PCI_STATUS_DEVSEL_MEDIUM @@ -120,7 +163,12 @@ #num PCI_BRIDGE_CTL_SERR #num PCI_BRIDGE_CTL_NO_ISA #num PCI_BRIDGE_CTL_VGA --- #num PCI_BRIDGE_CTL_VGA_16BIT + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +-- | 0x10 VGA 16-bit decode +#num PCI_BRIDGE_CTL_VGA_16BIT +#endif + #num PCI_BRIDGE_CTL_MASTER_ABORT #num PCI_BRIDGE_CTL_BUS_RESET #num PCI_BRIDGE_CTL_FAST_BACK @@ -164,7 +212,11 @@ #num PCI_CB_LEGACY_MODE_BASE #num PCI_CAP_LIST_ID --- #num PCI_CAP_ID_NULL + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_CAP_ID_NULL +#endif + #num PCI_CAP_ID_PM #num PCI_CAP_ID_AGP #num PCI_CAP_ID_VPD @@ -190,8 +242,10 @@ #num PCI_CAP_SIZEOF +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_NULL +#endif --- #num PCI_EXT_CAP_ID_NULL #num PCI_EXT_CAP_ID_AER #num PCI_EXT_CAP_ID_VC #num PCI_EXT_CAP_ID_DSN @@ -201,41 +255,63 @@ #num PCI_EXT_CAP_ID_RCECOLL #num PCI_EXT_CAP_ID_MFVC #num PCI_EXT_CAP_ID_VC2 --- #num PCI_EXT_CAP_ID_RCRB + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_RCRB +#endif + #num PCI_EXT_CAP_ID_VNDR #num PCI_EXT_CAP_ID_ACS #num PCI_EXT_CAP_ID_ARI #num PCI_EXT_CAP_ID_ATS #num PCI_EXT_CAP_ID_SRIOV --- #num PCI_EXT_CAP_ID_MRIOV --- #num PCI_EXT_CAP_ID_MCAST + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_MRIOV +#num PCI_EXT_CAP_ID_MCAST +#endif + #num PCI_EXT_CAP_ID_PRI --- #num PCI_EXT_CAP_ID_REBAR --- #num PCI_EXT_CAP_ID_DPA + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_REBAR +#num PCI_EXT_CAP_ID_DPA +#endif + #num PCI_EXT_CAP_ID_TPH #num PCI_EXT_CAP_ID_LTR --- #num PCI_EXT_CAP_ID_SECPCI --- #num PCI_EXT_CAP_ID_PMUX + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_SECPCI +#num PCI_EXT_CAP_ID_PMUX +#endif + #num PCI_EXT_CAP_ID_PASID --- #num PCI_EXT_CAP_ID_LNR + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_LNR +#endif + #num PCI_EXT_CAP_ID_DPC #num PCI_EXT_CAP_ID_L1PM #num PCI_EXT_CAP_ID_PTM --- #num PCI_EXT_CAP_ID_M_PCIE --- #num PCI_EXT_CAP_ID_FRS --- #num PCI_EXT_CAP_ID_RTR --- #num PCI_EXT_CAP_ID_DVSEC --- #num PCI_EXT_CAP_ID_VF_REBAR --- #num PCI_EXT_CAP_ID_DLNK --- #num PCI_EXT_CAP_ID_16GT --- #num PCI_EXT_CAP_ID_LMR --- #num PCI_EXT_CAP_ID_HIER_ID --- #num PCI_EXT_CAP_ID_NPEM - +#ifdef MIN_VERSION_LIBPCI_3_6_0 +#num PCI_EXT_CAP_ID_M_PCIE +#num PCI_EXT_CAP_ID_FRS +#num PCI_EXT_CAP_ID_RTR +#num PCI_EXT_CAP_ID_DVSEC +#num PCI_EXT_CAP_ID_VF_REBAR +#num PCI_EXT_CAP_ID_DLNK +#num PCI_EXT_CAP_ID_16GT +#num PCI_EXT_CAP_ID_LMR +#num PCI_EXT_CAP_ID_HIER_ID +#num PCI_EXT_CAP_ID_NPEM +#endif +-- Power Management Registers #num PCI_PM_CAP_VER_MASK #num PCI_PM_CAP_PME_CLOCK #num PCI_PM_CAP_DSI @@ -260,8 +336,7 @@ #num PCI_PM_DATA_REGISTER #num PCI_PM_SIZEOF - - +-- AGP Registers #num PCI_AGP_VERSION #num PCI_AGP_RFU #num PCI_AGP_STATUS @@ -293,22 +368,19 @@ #num PCI_AGP_COMMAND_RATE1 #num PCI_AGP_SIZEOF - - +-- Vital Product Data #num PCI_VPD_ADDR #num PCI_VPD_ADDR_MASK #num PCI_VPD_ADDR_F #num PCI_VPD_DATA - - +-- Slot Identification #num PCI_SID_ESR #num PCI_SID_ESR_NSLOTS #num PCI_SID_ESR_FIC #num PCI_SID_CHASSIS_NR - - +-- Message Signaled Interrupts registers #num PCI_MSI_FLAGS #num PCI_MSI_FLAGS_MASK_BIT #num PCI_MSI_FLAGS_64BIT @@ -325,7 +397,7 @@ #num PCI_MSI_PENDING_32 #num PCI_MSI_PENDING_64 - +-- PCI-X #num PCI_PCIX_COMMAND #num PCI_PCIX_COMMAND_DPERE #num PCI_PCIX_COMMAND_ERO @@ -852,30 +924,79 @@ #num PCI_EXP_RTSTA_PME_STATUS #num PCI_EXP_RTSTA_PME_PENDING #num PCI_EXP_DEVCAP2 --- #num PCI_EXP_DEVCAP2_NROPRPRP + +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | 0x0400 No RO-enabled PR-PR Passing +#num PCI_EXP_DEVCAP2_NROPRPRP +#endif + #num PCI_EXP_DEVCAP2_LTR + +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | TPH Completer Supported #cinline PCI_EXP_DEVCAP2_TPH_COMP , CUInt -> CUInt + +-- | LN System CLS Supported #cinline PCI_EXP_DEVCAP2_LN_CLS , CUInt -> CUInt --- #num PCI_EXP_DEVCAP2_10BIT_TAG_COMP --- #num PCI_EXP_DEVCAP2_10BIT_TAG_REQ + +-- | 0x00010000 10 Bit Tag Completer +#num PCI_EXP_DEVCAP2_10BIT_TAG_COMP + +-- | 0x00020000 10 Bit Tag Requester +#num PCI_EXP_DEVCAP2_10BIT_TAG_REQ +#endif + #cinline PCI_EXP_DEVCAP2_OBFF , CUInt -> CUInt --- #num PCI_EXP_DEVCAP2_EXTFMT --- #num PCI_EXP_DEVCAP2_EE_TLP + +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | 0x00100000 Extended Fmt Field Supported +#num PCI_EXP_DEVCAP2_EXTFMT + +-- | 0x00200000 End-End TLP Prefix Supported +#num PCI_EXP_DEVCAP2_EE_TLP + +-- | Max End-End TLP Prefixes #cinline PCI_EXP_DEVCAP2_MEE_TLP, CUInt -> CUInt + +-- | Emergency Power Reduction Supported #cinline PCI_EXP_DEVCAP2_EPR , CUInt -> CUInt --- #num PCI_EXP_DEVCAP2_EPR_INIT --- #num PCI_EXP_DEVCAP2_FRS + +-- | 0x04000000 Emergency Power Reduction Initialization Required +#num PCI_EXP_DEVCAP2_EPR_INIT + +-- | 0x80000000 FRS supported +#num PCI_EXP_DEVCAP2_FRS +#endif + #num PCI_EXP_DEVCTL2 #cinline PCI_EXP_DEV2_TIMEOUT_RANGE , CUInt -> CUInt #cinline PCI_EXP_DEV2_TIMEOUT_VALUE , CUShort -> CUShort #num PCI_EXP_DEV2_TIMEOUT_DIS --- #num PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN --- #num PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK + +#ifdef MIN_VERSION_LIBPCI_3_5_3 +-- | 0x0040 AtomicOp RequesterEnable +#num PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN + +-- | 0x0080 AtomicOp Egress Blocking +#num PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK +#endif + #num PCI_EXP_DEV2_ARI --- #num PCI_EXP_DEVCAP2_ATOMICOP_ROUTING --- #num PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP --- #num PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP --- #num PCI_EXP_DEVCAP2_128BIT_CAS_COMP + +#ifdef MIN_VERSION_LIBPCI_3_5_3 +-- | 0x0040 AtomicOp Routing Supported +#num PCI_EXP_DEVCAP2_ATOMICOP_ROUTING + +-- | 0x0080 32bit AtomicOp Completer Supported +#num PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP + +-- | 0x0100 64bit AtomicOp Completer Supported +#num PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP + +-- | 0x0200 128bit CAS Completer Supported +#num PCI_EXP_DEVCAP2_128BIT_CAS_COMP +#endif + #num PCI_EXP_DEV2_LTR #cinline PCI_EXP_DEV2_OBFF , CUShort -> CUShort #num PCI_EXP_DEVSTA2 @@ -933,8 +1054,6 @@ #num PCI_EA_CAP_ENT_ENABLE - - #num PCI_ERR_UNCOR_STATUS #num PCI_ERR_UNC_TRAIN #num PCI_ERR_UNC_DLP @@ -968,16 +1087,38 @@ #num PCI_ERR_CAP_ECRC_GENE #num PCI_ERR_CAP_ECRC_CHKC #num PCI_ERR_CAP_ECRC_CHKE --- #num PCI_ERR_CAP_MULT_HDRC --- #num PCI_ERR_CAP_MULT_HDRE --- #num PCI_ERR_CAP_TLP_PFX --- #num PCI_ERR_CAP_HDR_LOG + +#ifdef MIN_VERSION_LIBPCI_3_5_5 +-- | 0x00000200 Multiple Header Capable +#num PCI_ERR_CAP_MULT_HDRC + +-- | 0x00000400 Multiple Header Enable +#num PCI_ERR_CAP_MULT_HDRE + +-- | 0x00000800 TLP Prefix Log Present +#num PCI_ERR_CAP_TLP_PFX + +-- | 0x00001000 Completion Timeout Prefix/Header Log Capable +#num PCI_ERR_CAP_HDR_LOG +#endif + #num PCI_ERR_HEADER_LOG #num PCI_ERR_ROOT_COMMAND --- #num PCI_ERR_ROOT_CMD_COR_EN --- #num PCI_ERR_ROOT_CMD_NONFATAL_EN --- #num PCI_ERR_ROOT_CMD_FATAL_EN + +#ifdef MIN_VERSION_LIBPCI_3_5_5 +-- | 0x00000001 Correctable Error Reporting Enable +#num PCI_ERR_ROOT_CMD_COR_EN + +-- | 0x00000002 Non-Fatal Error Reporting Enable +#num PCI_ERR_ROOT_CMD_NONFATAL_EN + +-- | 0x00000004 Fatal Error Reporting Enable +#num PCI_ERR_ROOT_CMD_FATAL_EN +#endif + #num PCI_ERR_ROOT_STATUS + +#ifdef MIN_VERSION_LIBPCI_3_5_5 -- #num PCI_ERR_ROOT_COR_RCV -- #num PCI_ERR_ROOT_MULTI_COR_RCV -- #num PCI_ERR_ROOT_UNCOR_RCV @@ -986,6 +1127,8 @@ -- #num PCI_ERR_ROOT_NONFATAL_RCV -- #num PCI_ERR_ROOT_FATAL_RCV #cinline PCI_ERR_MSG_NUM , CUInt -> CUInt +#endif + #num PCI_ERR_ROOT_COR_SRC #num PCI_ERR_ROOT_SRC @@ -1085,25 +1228,51 @@ #cinline PCI_IOV_MSA_BIR , CUInt -> CUInt #cinline PCI_IOV_MSA_OFFSET , CUInt -> CUInt +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | Multicast --- #num PCI_MCAST_CAP +-- | 0x04 Multicast Capability +#num PCI_MCAST_CAP + #cinline PCI_MCAST_CAP_MAX_GROUP , CUShort -> CUShort #cinline PCI_MCAST_CAP_WIN_SIZE , CUShort -> CUShort --- #num PCI_MCAST_CAP_ECRC --- #num PCI_MCAST_CTRL + +-- | 0x8000 ECRC Regeneration Supported +#num PCI_MCAST_CAP_ECRC + +-- | 0x06 Multicast Control +#num PCI_MCAST_CTRL + #cinline PCI_MCAST_CTRL_NUM_GROUP , CUShort -> CUShort --- #num PCI_MCAST_CTRL_ENABLE --- #num PCI_MCAST_BAR + +-- | 0x8000 MC Enabled +#num PCI_MCAST_CTRL_ENABLE + +-- | 0x08 Base Address +#num PCI_MCAST_BAR + #cinline PCI_MCAST_BAR_INDEX_POS , CULong -> CUInt --- #num PCI_MCAST_BAR_MASK --- #num PCI_MCAST_RCV --- #num PCI_MCAST_BLOCK --- #num PCI_MCAST_BLOCK_UNTRANS --- #num PCI_MCAST_OVL_BAR + +#num PCI_MCAST_BAR_MASK + +-- | 0x10 Receive +#num PCI_MCAST_RCV + +-- | 0x18 Block All +#num PCI_MCAST_BLOCK + +-- | 0x20 Block Untranslated +#num PCI_MCAST_BLOCK_UNTRANS + +-- | 0x28 Overlay BAR +#num PCI_MCAST_OVL_BAR + #cinline PCI_MCAST_OVL_SIZE , CULong -> CUInt --- #num PCI_MCAST_OVL_MASK +#num PCI_MCAST_OVL_MASK +#endif +-- | Page Request Interface #num PCI_PRI_CTRL #num PCI_PRI_CTRL_ENABLE #num PCI_PRI_CTRL_RESET @@ -1133,16 +1302,36 @@ #num PCI_LTR_MAX_NOSNOOP --- #num PCI_SEC_LNKCTL3 --- #num PCI_SEC_LNKCTL3_PERFORM_LINK_EQU --- #num PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | Secondary PCI Express Extended Capability + +-- | 4 Link Control 3 register +#num PCI_SEC_LNKCTL3 + +-- | 0x01 +#num PCI_SEC_LNKCTL3_PERFORM_LINK_EQU + +-- | 0x02 +#num PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN + #cinline PCI_SEC_LNKCTL3_ENBL_LOWER_SKP_OS_GEN_VEC , CUInt -> CUInt --- #num PCI_SEC_LANE_ERR --- #num PCI_SEC_LANE_EQU_CTRL +-- | 8 Lane Error status register +#num PCI_SEC_LANE_ERR +-- | 12 Lane Equalization Control register +#num PCI_SEC_LANE_EQU_CTRL + +#endif + +-- | Process Address Space ID + +-- | 0x04 PASID feature register #num PCI_PASID_CAP + +-- | 0x02 Exec permissions Supported #num PCI_PASID_CAP_EXEC + #num PCI_PASID_CAP_PRIV #cinline PCI_PASID_CAP_WIDTH , CUShort -> CUShort #num PCI_PASID_CTRL @@ -1189,19 +1378,11 @@ #num PCI_L1PM_SUBSTAT_CTL2 - - - - - - - #cinline PCI_DEVFN , CUChar -> CUChar -> CUChar #cinline PCI_SLOT , CUChar -> CUChar #cinline PCI_FUNC , CUChar -> CUChar - #num PCI_CLASS_NOT_DEFINED #num PCI_CLASS_NOT_DEFINED_VGA @@ -1324,4 +1505,3 @@ #num PCI_VENDOR_ID_INTEL #num PCI_VENDOR_ID_COMPAQ #num PCI_IORESOURCE_PCI_EA_BEI - diff --git a/src/Bindings/Libpci/Pci.hsc b/src/Bindings/Libpci/Pci.hsc --- a/src/Bindings/Libpci/Pci.hsc +++ b/src/Bindings/Libpci/Pci.hsc @@ -35,19 +35,50 @@ PCI_ACCESS_MAX }; -} #integral_t enum pci_access_type + +-- | Autodetection #num PCI_ACCESS_AUTO + +-- | Linux /sys/bus/pci #num PCI_ACCESS_SYS_BUS_PCI + +-- | Linux /proc/bus/pci #num PCI_ACCESS_PROC_BUS_PCI + +-- | i386 ports, type 1 #num PCI_ACCESS_I386_TYPE1 + +-- | i386 ports, type 2 #num PCI_ACCESS_I386_TYPE2 + +-- | FreeBSD /dev/pci #num PCI_ACCESS_FBSD_DEVICE + +-- | /dev/pci0, /dev/bus0, etc. #num PCI_ACCESS_AIX_DEVICE + +-- | NetBSD libpci #num PCI_ACCESS_NBSD_LIBPCI + +-- | OpenBSD /dev/pci #num PCI_ACCESS_OBSD_DEVICE + +-- | Dump file #num PCI_ACCESS_DUMP + +-- | Darwin #num PCI_ACCESS_DARWIN --- #num PCI_ACCESS_SYLIXOS_DEVICE --- #num PCI_ACCESS_HURD + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +-- | SylixOS pci +#num PCI_ACCESS_SYLIXOS_DEVICE +#endif + +#ifdef MIN_VERSION_LIBPCI_3_6_4 +-- | GNU/Hurd +#num PCI_ACCESS_HURD +#endif + #num PCI_ACCESS_MAX {- struct pci_access { unsigned int method; @@ -76,41 +107,96 @@ int fd_vpd; struct pci_dev * cached_dev; }; -} +-- | PCI Access Structure #starttype struct pci_access -#field method , CUInt + +-- | Access method +#field method , CUInt + #field writeable , CInt +-- ^ Open in read/write mode + +-- | Bus-centric view of the world #field buscentric , CInt + +-- | Name of ID list file (use pci_set_name_list_path()) #field id_file_name , CString + +-- | Set if id_file_name is malloced #field free_id_name , CInt + +-- | Enforce PCI_LOOKUP_NUMERIC (>1 => PCI_LOOKUP_MIXED) #field numeric_ids , CInt + +-- | pci_lookup_mode flags which are set automatically +-- Default: PCI_LOOKUP_CACHE #field id_lookup_mode , CUInt + +-- | Turn on debugging messages #field debugging , CInt + +-- | Write error message and quit #field error , FunPtr (CString -> IO ()) + +-- | Write a warning message #field warning , FunPtr (CString -> IO ()) + +-- | Write a debugging message #field debug , FunPtr (CString -> IO ()) + +-- | Devices found on this bus #field devices , Ptr + #field methods , Ptr #field params , Ptr + +-- | names.c #field id_hash , Ptr (Ptr ) #field current_id_bucket , Ptr #field id_load_failed , CInt + +-- | 0=not read, 1=read, 2=dirty #field id_cache_status , CInt + +-- | names-hwdb.c #field id_udev , Ptr #field id_udev_hwdb , Ptr + +-- | proc/sys: fd for config space #field fd , CInt + +-- | proc/sys: fd opened read-write #field fd_rw , CInt + +-- | proc/sys: current position #field fd_pos , CInt + +-- | sys: fd for VPD #field fd_vpd , CInt + +-- | proc/sys: device the fds are for #field cached_dev , Ptr #stoptype + +-- | Initialize PCI access #ccall pci_alloc , IO (Ptr ) #ccall pci_init , Ptr -> IO () #ccall pci_cleanup , Ptr -> IO () + +-- | Scanning of devices #ccall pci_scan_bus , Ptr -> IO () + +-- | Raw access to specified device #ccall pci_get_dev , Ptr -> CInt -> CInt -> CInt -> CInt -> IO (Ptr ) #ccall pci_free_dev , Ptr -> IO () + +-- | Names of access methods +-- | Returns -1 if not found #ccall pci_lookup_method , CString -> IO CInt + +-- | Returns "" if unavailable, NULL if index out of range #ccall pci_get_method_name , CInt -> IO CString + {- struct pci_param { struct pci_param * next; char * param; @@ -118,16 +204,33 @@ int value_malloced; char * help; }; -} +-- | Named parameters #starttype struct pci_param + +-- | Please use pci_walk_params() for traversing the list #field next , Ptr + +-- | Name of the parameter #field param , CString + +-- | Value of the parameter #field value , CString + +-- | used internally #field value_malloced , CInt + +-- | Explanation of the parameter #field help , CString #stoptype + #ccall pci_get_param , Ptr -> CString -> IO CString + +-- | 0 on success, -1 if no such parameter #ccall pci_set_param , Ptr -> CString -> CString -> IO CInt + +-- | To traverse the list, call pci_walk_params repeatedly, first with prev=NULL, and do not modify the parameters during traversal #ccall pci_walk_params , Ptr -> Ptr -> IO (Ptr ) + {- struct pci_dev { struct pci_dev * next; u16 domain_16; @@ -157,38 +260,96 @@ struct pci_property * properties; struct pci_cap * last_cap; }; -} +-- | Devices #starttype struct pci_dev + +-- | Next device in the chain #field next , Ptr + +-- | 16-bit version of the PCI domain for backward compatibility #field domain_16 , CUShort + +-- | Bus inside domain, device and function #field bus , CUChar #field dev , CUChar #field func , CUChar + +-- | These fields are set by pci_fill_info() +-- | Set of info fields already known (see pci_fill_info()) #field known_fields , CInt + +-- | Identity of the device #field vendor_id , CUShort + +-- | Identity of the device #field device_id , CUShort + +-- | PCI device class #field device_class , CUShort + +-- | IRQ number #field irq , CInt + +-- | Base addresses including flags in lower bits #array_field base_addr , CULong + +-- | Region sizes #array_field size , CULong + +-- | Expansion ROM base address #field rom_base_addr , CULong + +-- | Expansion ROM size #field rom_size , CULong + +-- | List of capabilities #field first_cap , Ptr + +-- | Physical slot #field phy_slot , CString + +-- | Linux kernel module alias #field module_alias , CString + +-- | Device name as exported by BIOS #field label , CString + +-- | NUMA node #field numa_node , CInt + +-- | PCI_IORESOURCE_* flags for regions #array_field flags , CULong + +-- | PCI_IORESOURCE_* flags for expansion ROM #field rom_flags , CULong + +-- | PCI domain (host bridge) #field domain , CInt #field access , Ptr #field methods , Ptr + +-- | Cached config registers #field cache , Ptr CUChar #field cache_len , CInt + +-- | Cached low 7 bits of header type, -1 if unknown #field hdrtype , CInt + +-- | Auxiliary data for use by the back-end #field aux , Ptr () --- #field properties , Ptr --- #field last_cap , Ptr + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +-- | A linked list of extra properties +#field properties , Ptr +#endif + +#ifdef MIN_VERSION_LIBPCI_3_6_3 +-- | Last capability in the list +#field last_cap , Ptr +#endif #stoptype + +-- | Access to configuration space #ccall pci_read_byte , Ptr -> CInt -> IO CUChar #ccall pci_read_word , Ptr -> CInt -> IO CUShort #ccall pci_read_long , Ptr -> CInt -> IO CUInt @@ -198,6 +359,23 @@ #ccall pci_write_word , Ptr -> CInt -> CUShort -> IO CInt #ccall pci_write_long , Ptr -> CInt -> CUInt -> IO CInt #ccall pci_write_block , Ptr -> CInt -> Ptr CUChar -> CInt -> IO CInt + +-- | Most device properties take some effort to obtain, so libpci does not +-- initialize them during default bus scan. Instead, you have to call +-- pci_fill_info() with the proper PCI_FILL_xxx constants OR'ed together. +-- +-- Some properties are stored directly in the pci_dev structure. +-- The remaining ones can be accessed through pci_get_string_property(). +-- +-- pci_fill_info() returns the current value of pci_dev->known_fields. +-- This is a bit mask of all fields, which were already obtained during +-- the lifetime of the device. This includes fields which are not supported +-- by the particular device -- in that case, the field is left at its default +-- value, which is 0 for integer fields and NULL for pointers. On the other +-- hand, we never consider known fields unsupported by the current back-end; +-- such fields always contain the default value. +-- +-- XXX: flags and the result should be unsigned, but we do not want to break the ABI. #ccall pci_fill_info , Ptr -> CInt -> IO CInt #ccall pci_get_string_property , Ptr -> CUInt -> IO CString @@ -214,22 +392,40 @@ #num PCI_FILL_LABEL #num PCI_FILL_NUMA_NODE #num PCI_FILL_IO_FLAGS --- #num PCI_FILL_DT_NODE --- #num PCI_FILL_IOMMU_GROUP + +#ifdef MIN_VERSION_LIBPCI_3_6_0 +-- | Device tree node +#num PCI_FILL_DT_NODE +#endif + +#ifdef MIN_VERSION_LIBPCI_3_7_0 +#num PCI_FILL_IOMMU_GROUP +#endif + #num PCI_FILL_RESCAN #ccall pci_setup_cache , Ptr -> Ptr CUChar -> CInt -> IO () {- struct pci_cap { struct pci_cap * next; u16 id; u16 type; unsigned int addr; }; -} +-- | Capabilities #starttype struct pci_cap #field next , Ptr + +-- | PCI_CAP_ID_xxx #field id , CUShort + +-- | PCI_CAP_xxx #field type , CUShort + +-- | Position in the config space #field addr , CUInt #stoptype +-- | Traditional PCI capabilities #num PCI_CAP_NORMAL + +-- | PCIe extended capabilities #num PCI_CAP_EXTENDED #ccall pci_find_cap , Ptr -> CUInt -> CUInt -> IO (Ptr ) @@ -239,10 +435,19 @@ int vendor, device, device_class; int rfu[3]; }; -} +-- | Filters #starttype struct pci_filter + +-- | -1 = ANY #field domain , CInt + +-- | -1 = ANY #field bus , CInt + +-- | -1 = ANY #field slot , CInt + +-- | -1 = ANY #field func , CInt #field vendor , CInt #field device , CInt @@ -254,9 +459,23 @@ #ccall pci_filter_parse_id , Ptr -> CString -> IO CString #ccall pci_filter_match , Ptr -> Ptr -> IO CInt +-- | Conversion of PCI ID's to names (according to the pci.ids file) +-- Call pci_lookup_name() to identify different types of ID's: +-- VENDOR(vendorID) -> vendor +-- DEVICE(vendorID, deviceID) -> device +-- VENDOR | DEVICE(vendorID, deviceID) -> combined vendor and device +-- SUBSYSTEM | VENDOR(subvendorID) -> subsystem vendor +-- SUBSYSTEM | DEVICE(vendorID, deviceID, subvendorID, subdevID) -> subsystem device +-- SUBSYSTEM | VENDOR | DEVICE(vendorID, deviceID, subvendorID, subdevID) -> combined subsystem v+d +-- SUBSYSTEM | ...(-1, -1, subvendorID, subdevID) -> generic subsystem +-- CLASS(classID) -> class +-- PROGIF(classID, progif) -> programming interface #ccall pci_lookup_name , Ptr -> CString -> CInt -> CUInt -> CInt -> CInt -> CInt -> CInt -> IO CString +-- | Called automatically by pci_lookup_*() when needed; returns success #ccall pci_load_name_list , Ptr -> IO CInt + +-- | Called automatically by pci_cleanup #ccall pci_free_name_list , Ptr -> IO () #ccall pci_set_name_list_path , Ptr -> CString -> CInt -> IO () #ccall pci_id_cache_flush , Ptr -> IO () @@ -276,16 +495,42 @@ PCI_LOOKUP_NO_HWDB = 0x800000 }; -} #integral_t enum pci_lookup_mode + +-- | 1 Vendor name (args: vendorID) #num PCI_LOOKUP_VENDOR + +-- | 2 Device name (args: vendorID, deviceID) #num PCI_LOOKUP_DEVICE + +-- | 4 Device class (args: classID) #num PCI_LOOKUP_CLASS + +-- | 8 #num PCI_LOOKUP_SUBSYSTEM + +-- | 16 Programming interface (args: classID, prog_if) #num PCI_LOOKUP_PROGIF + +-- | 0x10000 Want only formatted numbers; default if access->numeric_id is set #num PCI_LOOKUP_NUMERIC + +-- | 0x20000 Return NULL if not found in the database; default is to print numerically #num PCI_LOOKUP_NO_NUMBERS + +-- | 0x40000 Include both numbers and names #num PCI_LOOKUP_MIXED + +-- | 0x80000 Try to resolve unknown ID's by DNS #num PCI_LOOKUP_NETWORK + +-- | 0x100000 Do not consult local database #num PCI_LOOKUP_SKIP_LOCAL + +-- | 0x200000 Consult the local cache before using DNS #num PCI_LOOKUP_CACHE + +-- | 0x400000 Forget all previously cached entries, but still allow updating the cache #num PCI_LOOKUP_REFRESH_CACHE + +-- | 0x800000 Do not ask udev's hwdb #num PCI_LOOKUP_NO_HWDB