STM32F103xx-SVD (empty) → 0.1

raw patch · 4 files changed

+11724/−0 lines, 4 filesdep +basesetup-changed

Dependencies added: base

Files

• Device.hs +11665/−0
• LicenseInfo +30/−0
• STM32F103xx-SVD.cabal +26/−0
• Setup.hs +3/−0

@@ -0,0 +1,11665 @@+-- Generated from STM32F103xx.svd+module Device+where+import Data.Word (Word32)++data Peripheral+    =ADC1+    |ADC2+    |ADC3+    |AFIO+    |BKP+    |CAN+    |CRC+    |DAC+    |DBG+    |DMA1+    |DMA2+    |EXTI+    |FLASH+    |FSMC+    |GPIOA+    |GPIOB+    |GPIOC+    |GPIOD+    |GPIOE+    |GPIOF+    |GPIOG+    |I2C1+    |I2C2+    |IWDG+    |NVIC+    |PWR+    |RCC+    |RTC+    |SDIO+    |SPI1+    |SPI2+    |SPI3+    |TIM1+    |TIM10+    |TIM11+    |TIM12+    |TIM13+    |TIM14+    |TIM2+    |TIM3+    |TIM4+    |TIM5+    |TIM6+    |TIM7+    |TIM8+    |TIM9+    |UART4+    |UART5+    |USART1+    |USART2+    |USART3+    |USB+    |WWDG+    deriving (Show,Eq,Ord)++data Register+    =ACR+    |AHBENR+    |ALRH+    |ALRL+    |APB1ENR+    |APB1RSTR+    |APB2ENR+    |APB2RSTR+    |AR+    |ARG+    |ARR+    |BCR1+    |BCR2+    |BCR3+    |BCR4+    |BDCR+    |BDTR+    |BRR+    |BSRR+    |BTABLE+    |BTR1+    |BTR2+    |BTR3+    |BTR4+    |BWTR1+    |BWTR2+    |BWTR3+    |BWTR4+    |CAN_BTR+    |CAN_ESR+    |CAN_FA1R+    |CAN_FFA1R+    |CAN_FM1R+    |CAN_FMR+    |CAN_FS1R+    |CAN_IER+    |CAN_MCR+    |CAN_MSR+    |CAN_RDH0R+    |CAN_RDH1R+    |CAN_RDL0R+    |CAN_RDL1R+    |CAN_RDT0R+    |CAN_RDT1R+    |CAN_RF0R+    |CAN_RF1R+    |CAN_RI0R+    |CAN_RI1R+    |CAN_TDH0R+    |CAN_TDH1R+    |CAN_TDH2R+    |CAN_TDL0R+    |CAN_TDL1R+    |CAN_TDL2R+    |CAN_TDT0R+    |CAN_TDT1R+    |CAN_TDT2R+    |CAN_TI0R+    |CAN_TI1R+    |CAN_TI2R+    |CAN_TSR+    |CCER+    |CCMR1_Input+    |CCMR1_Output+    |CCMR2_Input+    |CCMR2_Output+    |CCR+    |CCR1+    |CCR2+    |CCR3+    |CCR4+    |CCR5+    |CCR6+    |CCR7+    |CFGR+    |CFR+    |CIR+    |CLKCR+    |CMAR1+    |CMAR2+    |CMAR3+    |CMAR4+    |CMAR5+    |CMAR6+    |CMAR7+    |CMD+    |CNDTR1+    |CNDTR2+    |CNDTR3+    |CNDTR4+    |CNDTR5+    |CNDTR6+    |CNDTR7+    |CNT+    |CNTH+    |CNTL+    |CNTR+    |CPAR1+    |CPAR2+    |CPAR3+    |CPAR4+    |CPAR5+    |CPAR6+    |CPAR7+    |CR+    |CR1+    |CR2+    |CR3+    |CRCPR+    |CRH+    |CRL+    |CSR+    |DADDR+    |DCOUNT+    |DCR+    |DCTRL+    |DHR12L1+    |DHR12L2+    |DHR12LD+    |DHR12R1+    |DHR12R2+    |DHR12RD+    |DHR8R1+    |DHR8R2+    |DHR8RD+    |DIER+    |DIVH+    |DIVL+    |DLEN+    |DMAR+    |DOR1+    |DOR2+    |DR+    |DR1+    |DR10+    |DR11+    |DR12+    |DR13+    |DR14+    |DR15+    |DR16+    |DR17+    |DR18+    |DR19+    |DR2+    |DR20+    |DR21+    |DR22+    |DR23+    |DR24+    |DR25+    |DR26+    |DR27+    |DR28+    |DR29+    |DR3+    |DR30+    |DR31+    |DR32+    |DR33+    |DR34+    |DR35+    |DR36+    |DR37+    |DR38+    |DR39+    |DR4+    |DR40+    |DR41+    |DR42+    |DR5+    |DR6+    |DR7+    |DR8+    |DR9+    |DTIMER+    |ECCR2+    |ECCR3+    |EGR+    |EMR+    |EP0R+    |EP1R+    |EP2R+    |EP3R+    |EP4R+    |EP5R+    |EP6R+    |EP7R+    |EVCR+    |EXTICR1+    |EXTICR2+    |EXTICR3+    |EXTICR4+    |F0R1+    |F0R2+    |F10R1+    |F10R2+    |F11R1+    |F11R2+    |F12R1+    |F12R2+    |F13R1+    |F13R2+    |F1R1+    |F1R2+    |F2R1+    |F2R2+    |F3R1+    |F3R2+    |F4R1+    |F4R2+    |F5R1+    |F5R2+    |F6R1+    |F6R2+    |F7R1+    |F7R2+    |F8R1+    |F8R2+    |F9R1+    |F9R2+    |FIFO+    |FIFOCNT+    |FNR+    |FTSR+    |GTPR+    |HTR+    |I2SCFGR+    |I2SPR+    |IABR0+    |IABR1+    |ICER0+    |ICER1+    |ICPR0+    |ICPR1+    |ICR+    |ICTR+    |IDCODE+    |IDR+    |IFCR+    |IMR+    |IPR0+    |IPR1+    |IPR10+    |IPR11+    |IPR12+    |IPR13+    |IPR14+    |IPR2+    |IPR3+    |IPR4+    |IPR5+    |IPR6+    |IPR7+    |IPR8+    |IPR9+    |ISER0+    |ISER1+    |ISPR0+    |ISPR1+    |ISR+    |ISTR+    |JDR1+    |JDR2+    |JDR3+    |JDR4+    |JOFR1+    |JOFR2+    |JOFR3+    |JOFR4+    |JSQR+    |KEYR+    |KR+    |LCKR+    |LTR+    |MAPR+    |MAPR2+    |MASK+    |OAR1+    |OAR2+    |OBR+    |ODR+    |OPTKEYR+    |PATT2+    |PATT3+    |PATT4+    |PCR2+    |PCR3+    |PCR4+    |PIO4+    |PMEM2+    |PMEM3+    |PMEM4+    |POWER+    |PR+    |PRLH+    |PRLL+    |PSC+    |RCR+    |RESP2+    |RESP3+    |RESP4+    |RESPCMD+    |RESPI1+    |RLR+    |RTCCR+    |RTSR+    |RXCRCR+    |SMCR+    |SMPR1+    |SMPR2+    |SQR1+    |SQR2+    |SQR3+    |SR+    |SR1+    |SR2+    |SR3+    |SR4+    |STA+    |STIR+    |SWIER+    |SWTRIGR+    |TRISE+    |TXCRCR+    |WRPR+    deriving (Show,Eq,Ord)++data Field+    =ACR_HLFCYA+    |ACR_LATENCY+    |ACR_PRFTBE+    |ACR_PRFTBS+    |AHBENR_CRCEN+    |AHBENR_DMA1EN+    |AHBENR_DMA2EN+    |AHBENR_FLITFEN+    |AHBENR_FSMCEN+    |AHBENR_SDIOEN+    |AHBENR_SRAMEN+    |ALRH_ALRH+    |ALRL_ALRL+    |APB1ENR_BKPEN+    |APB1ENR_CANEN+    |APB1ENR_DACEN+    |APB1ENR_I2C1EN+    |APB1ENR_I2C2EN+    |APB1ENR_PWREN+    |APB1ENR_SPI2EN+    |APB1ENR_SPI3EN+    |APB1ENR_TIM12EN+    |APB1ENR_TIM13EN+    |APB1ENR_TIM14EN+    |APB1ENR_TIM2EN+    |APB1ENR_TIM3EN+    |APB1ENR_TIM4EN+    |APB1ENR_TIM5EN+    |APB1ENR_TIM6EN+    |APB1ENR_TIM7EN+    |APB1ENR_UART4EN+    |APB1ENR_UART5EN+    |APB1ENR_USART2EN+    |APB1ENR_USART3EN+    |APB1ENR_USBEN+    |APB1ENR_WWDGEN+    |APB1RSTR_BKPRST+    |APB1RSTR_CANRST+    |APB1RSTR_DACRST+    |APB1RSTR_I2C1RST+    |APB1RSTR_I2C2RST+    |APB1RSTR_PWRRST+    |APB1RSTR_SPI2RST+    |APB1RSTR_SPI3RST+    |APB1RSTR_TIM12RST+    |APB1RSTR_TIM13RST+    |APB1RSTR_TIM14RST+    |APB1RSTR_TIM2RST+    |APB1RSTR_TIM3RST+    |APB1RSTR_TIM4RST+    |APB1RSTR_TIM5RST+    |APB1RSTR_TIM6RST+    |APB1RSTR_TIM7RST+    |APB1RSTR_UART4RST+    |APB1RSTR_UART5RST+    |APB1RSTR_USART2RST+    |APB1RSTR_USART3RST+    |APB1RSTR_USBRST+    |APB1RSTR_WWDGRST+    |APB2ENR_ADC1EN+    |APB2ENR_ADC2EN+    |APB2ENR_ADC3EN+    |APB2ENR_AFIOEN+    |APB2ENR_IOPAEN+    |APB2ENR_IOPBEN+    |APB2ENR_IOPCEN+    |APB2ENR_IOPDEN+    |APB2ENR_IOPEEN+    |APB2ENR_IOPFEN+    |APB2ENR_IOPGEN+    |APB2ENR_SPI1EN+    |APB2ENR_TIM10EN+    |APB2ENR_TIM11EN+    |APB2ENR_TIM1EN+    |APB2ENR_TIM8EN+    |APB2ENR_TIM9EN+    |APB2ENR_USART1EN+    |APB2RSTR_ADC1RST+    |APB2RSTR_ADC2RST+    |APB2RSTR_ADC3RST+    |APB2RSTR_AFIORST+    |APB2RSTR_IOPARST+    |APB2RSTR_IOPBRST+    |APB2RSTR_IOPCRST+    |APB2RSTR_IOPDRST+    |APB2RSTR_IOPERST+    |APB2RSTR_IOPFRST+    |APB2RSTR_IOPGRST+    |APB2RSTR_SPI1RST+    |APB2RSTR_TIM10RST+    |APB2RSTR_TIM11RST+    |APB2RSTR_TIM1RST+    |APB2RSTR_TIM8RST+    |APB2RSTR_TIM9RST+    |APB2RSTR_USART1RST+    |ARG_CMDARG+    |ARR_ARR+    |AR_FAR+    |BCR1_ASYNCWAIT+    |BCR1_BURSTEN+    |BCR1_CBURSTRW+    |BCR1_EXTMOD+    |BCR1_FACCEN+    |BCR1_MBKEN+    |BCR1_MTYP+    |BCR1_MUXEN+    |BCR1_MWID+    |BCR1_WAITCFG+    |BCR1_WAITEN+    |BCR1_WAITPOL+    |BCR1_WREN+    |BCR2_ASYNCWAIT+    |BCR2_BURSTEN+    |BCR2_CBURSTRW+    |BCR2_EXTMOD+    |BCR2_FACCEN+    |BCR2_MBKEN+    |BCR2_MTYP+    |BCR2_MUXEN+    |BCR2_MWID+    |BCR2_WAITCFG+    |BCR2_WAITEN+    |BCR2_WAITPOL+    |BCR2_WRAPMOD+    |BCR2_WREN+    |BCR3_ASYNCWAIT+    |BCR3_BURSTEN+    |BCR3_CBURSTRW+    |BCR3_EXTMOD+    |BCR3_FACCEN+    |BCR3_MBKEN+    |BCR3_MTYP+    |BCR3_MUXEN+    |BCR3_MWID+    |BCR3_WAITCFG+    |BCR3_WAITEN+    |BCR3_WAITPOL+    |BCR3_WRAPMOD+    |BCR3_WREN+    |BCR4_ASYNCWAIT+    |BCR4_BURSTEN+    |BCR4_CBURSTRW+    |BCR4_EXTMOD+    |BCR4_FACCEN+    |BCR4_MBKEN+    |BCR4_MTYP+    |BCR4_MUXEN+    |BCR4_MWID+    |BCR4_WAITCFG+    |BCR4_WAITEN+    |BCR4_WAITPOL+    |BCR4_WRAPMOD+    |BCR4_WREN+    |BDCR_BDRST+    |BDCR_LSEBYP+    |BDCR_LSEON+    |BDCR_LSERDY+    |BDCR_RTCEN+    |BDCR_RTCSEL+    |BDTR_AOE+    |BDTR_BKE+    |BDTR_BKP+    |BDTR_DTG+    |BDTR_LOCK+    |BDTR_MOE+    |BDTR_OSSI+    |BDTR_OSSR+    |BRR_BR0+    |BRR_BR1+    |BRR_BR10+    |BRR_BR11+    |BRR_BR12+    |BRR_BR13+    |BRR_BR14+    |BRR_BR15+    |BRR_BR2+    |BRR_BR3+    |BRR_BR4+    |BRR_BR5+    |BRR_BR6+    |BRR_BR7+    |BRR_BR8+    |BRR_BR9+    |BRR_DIV_Fraction+    |BRR_DIV_Mantissa+    |BSRR_BR0+    |BSRR_BR1+    |BSRR_BR10+    |BSRR_BR11+    |BSRR_BR12+    |BSRR_BR13+    |BSRR_BR14+    |BSRR_BR15+    |BSRR_BR2+    |BSRR_BR3+    |BSRR_BR4+    |BSRR_BR5+    |BSRR_BR6+    |BSRR_BR7+    |BSRR_BR8+    |BSRR_BR9+    |BSRR_BS0+    |BSRR_BS1+    |BSRR_BS10+    |BSRR_BS11+    |BSRR_BS12+    |BSRR_BS13+    |BSRR_BS14+    |BSRR_BS15+    |BSRR_BS2+    |BSRR_BS3+    |BSRR_BS4+    |BSRR_BS5+    |BSRR_BS6+    |BSRR_BS7+    |BSRR_BS8+    |BSRR_BS9+    |BTABLE_BTABLE+    |BTR1_ACCMOD+    |BTR1_ADDHLD+    |BTR1_ADDSET+    |BTR1_BUSTURN+    |BTR1_CLKDIV+    |BTR1_DATAST+    |BTR1_DATLAT+    |BTR2_ACCMOD+    |BTR2_ADDHLD+    |BTR2_ADDSET+    |BTR2_BUSTURN+    |BTR2_CLKDIV+    |BTR2_DATAST+    |BTR2_DATLAT+    |BTR3_ACCMOD+    |BTR3_ADDHLD+    |BTR3_ADDSET+    |BTR3_BUSTURN+    |BTR3_CLKDIV+    |BTR3_DATAST+    |BTR3_DATLAT+    |BTR4_ACCMOD+    |BTR4_ADDHLD+    |BTR4_ADDSET+    |BTR4_BUSTURN+    |BTR4_CLKDIV+    |BTR4_DATAST+    |BTR4_DATLAT+    |BWTR1_ACCMOD+    |BWTR1_ADDHLD+    |BWTR1_ADDSET+    |BWTR1_CLKDIV+    |BWTR1_DATAST+    |BWTR1_DATLAT+    |BWTR2_ACCMOD+    |BWTR2_ADDHLD+    |BWTR2_ADDSET+    |BWTR2_CLKDIV+    |BWTR2_DATAST+    |BWTR2_DATLAT+    |BWTR3_ACCMOD+    |BWTR3_ADDHLD+    |BWTR3_ADDSET+    |BWTR3_CLKDIV+    |BWTR3_DATAST+    |BWTR3_DATLAT+    |BWTR4_ACCMOD+    |BWTR4_ADDHLD+    |BWTR4_ADDSET+    |BWTR4_CLKDIV+    |BWTR4_DATAST+    |BWTR4_DATLAT+    |CAN_BTR_BRP+    |CAN_BTR_LBKM+    |CAN_BTR_SILM+    |CAN_BTR_SJW+    |CAN_BTR_TS1+    |CAN_BTR_TS2+    |CAN_ESR_BOFF+    |CAN_ESR_EPVF+    |CAN_ESR_EWGF+    |CAN_ESR_LEC+    |CAN_ESR_REC+    |CAN_ESR_TEC+    |CAN_FA1R_FACT0+    |CAN_FA1R_FACT1+    |CAN_FA1R_FACT10+    |CAN_FA1R_FACT11+    |CAN_FA1R_FACT12+    |CAN_FA1R_FACT13+    |CAN_FA1R_FACT2+    |CAN_FA1R_FACT3+    |CAN_FA1R_FACT4+    |CAN_FA1R_FACT5+    |CAN_FA1R_FACT6+    |CAN_FA1R_FACT7+    |CAN_FA1R_FACT8+    |CAN_FA1R_FACT9+    |CAN_FFA1R_FFA0+    |CAN_FFA1R_FFA1+    |CAN_FFA1R_FFA10+    |CAN_FFA1R_FFA11+    |CAN_FFA1R_FFA12+    |CAN_FFA1R_FFA13+    |CAN_FFA1R_FFA2+    |CAN_FFA1R_FFA3+    |CAN_FFA1R_FFA4+    |CAN_FFA1R_FFA5+    |CAN_FFA1R_FFA6+    |CAN_FFA1R_FFA7+    |CAN_FFA1R_FFA8+    |CAN_FFA1R_FFA9+    |CAN_FM1R_FBM0+    |CAN_FM1R_FBM1+    |CAN_FM1R_FBM10+    |CAN_FM1R_FBM11+    |CAN_FM1R_FBM12+    |CAN_FM1R_FBM13+    |CAN_FM1R_FBM2+    |CAN_FM1R_FBM3+    |CAN_FM1R_FBM4+    |CAN_FM1R_FBM5+    |CAN_FM1R_FBM6+    |CAN_FM1R_FBM7+    |CAN_FM1R_FBM8+    |CAN_FM1R_FBM9+    |CAN_FMR_FINIT+    |CAN_FS1R_FSC0+    |CAN_FS1R_FSC1+    |CAN_FS1R_FSC10+    |CAN_FS1R_FSC11+    |CAN_FS1R_FSC12+    |CAN_FS1R_FSC13+    |CAN_FS1R_FSC2+    |CAN_FS1R_FSC3+    |CAN_FS1R_FSC4+    |CAN_FS1R_FSC5+    |CAN_FS1R_FSC6+    |CAN_FS1R_FSC7+    |CAN_FS1R_FSC8+    |CAN_FS1R_FSC9+    |CAN_IER_BOFIE+    |CAN_IER_EPVIE+    |CAN_IER_ERRIE+    |CAN_IER_EWGIE+    |CAN_IER_FFIE0+    |CAN_IER_FFIE1+    |CAN_IER_FMPIE0+    |CAN_IER_FMPIE1+    |CAN_IER_FOVIE0+    |CAN_IER_FOVIE1+    |CAN_IER_LECIE+    |CAN_IER_SLKIE+    |CAN_IER_TMEIE+    |CAN_IER_WKUIE+    |CAN_MCR_ABOM+    |CAN_MCR_AWUM+    |CAN_MCR_DBF+    |CAN_MCR_INRQ+    |CAN_MCR_NART+    |CAN_MCR_RESET+    |CAN_MCR_RFLM+    |CAN_MCR_SLEEP+    |CAN_MCR_TTCM+    |CAN_MCR_TXFP+    |CAN_MSR_ERRI+    |CAN_MSR_INAK+    |CAN_MSR_RX+    |CAN_MSR_RXM+    |CAN_MSR_SAMP+    |CAN_MSR_SLAK+    |CAN_MSR_SLAKI+    |CAN_MSR_TXM+    |CAN_MSR_WKUI+    |CAN_RDH0R_DATA4+    |CAN_RDH0R_DATA5+    |CAN_RDH0R_DATA6+    |CAN_RDH0R_DATA7+    |CAN_RDH1R_DATA4+    |CAN_RDH1R_DATA5+    |CAN_RDH1R_DATA6+    |CAN_RDH1R_DATA7+    |CAN_RDL0R_DATA0+    |CAN_RDL0R_DATA1+    |CAN_RDL0R_DATA2+    |CAN_RDL0R_DATA3+    |CAN_RDL1R_DATA0+    |CAN_RDL1R_DATA1+    |CAN_RDL1R_DATA2+    |CAN_RDL1R_DATA3+    |CAN_RDT0R_DLC+    |CAN_RDT0R_FMI+    |CAN_RDT0R_TIME+    |CAN_RDT1R_DLC+    |CAN_RDT1R_FMI+    |CAN_RDT1R_TIME+    |CAN_RF0R_FMP0+    |CAN_RF0R_FOVR0+    |CAN_RF0R_FULL0+    |CAN_RF0R_RFOM0+    |CAN_RF1R_FMP1+    |CAN_RF1R_FOVR1+    |CAN_RF1R_FULL1+    |CAN_RF1R_RFOM1+    |CAN_RI0R_EXID+    |CAN_RI0R_IDE+    |CAN_RI0R_RTR+    |CAN_RI0R_STID+    |CAN_RI1R_EXID+    |CAN_RI1R_IDE+    |CAN_RI1R_RTR+    |CAN_RI1R_STID+    |CAN_TDH0R_DATA4+    |CAN_TDH0R_DATA5+    |CAN_TDH0R_DATA6+    |CAN_TDH0R_DATA7+    |CAN_TDH1R_DATA4+    |CAN_TDH1R_DATA5+    |CAN_TDH1R_DATA6+    |CAN_TDH1R_DATA7+    |CAN_TDH2R_DATA4+    |CAN_TDH2R_DATA5+    |CAN_TDH2R_DATA6+    |CAN_TDH2R_DATA7+    |CAN_TDL0R_DATA0+    |CAN_TDL0R_DATA1+    |CAN_TDL0R_DATA2+    |CAN_TDL0R_DATA3+    |CAN_TDL1R_DATA0+    |CAN_TDL1R_DATA1+    |CAN_TDL1R_DATA2+    |CAN_TDL1R_DATA3+    |CAN_TDL2R_DATA0+    |CAN_TDL2R_DATA1+    |CAN_TDL2R_DATA2+    |CAN_TDL2R_DATA3+    |CAN_TDT0R_DLC+    |CAN_TDT0R_TGT+    |CAN_TDT0R_TIME+    |CAN_TDT1R_DLC+    |CAN_TDT1R_TGT+    |CAN_TDT1R_TIME+    |CAN_TDT2R_DLC+    |CAN_TDT2R_TGT+    |CAN_TDT2R_TIME+    |CAN_TI0R_EXID+    |CAN_TI0R_IDE+    |CAN_TI0R_RTR+    |CAN_TI0R_STID+    |CAN_TI0R_TXRQ+    |CAN_TI1R_EXID+    |CAN_TI1R_IDE+    |CAN_TI1R_RTR+    |CAN_TI1R_STID+    |CAN_TI1R_TXRQ+    |CAN_TI2R_EXID+    |CAN_TI2R_IDE+    |CAN_TI2R_RTR+    |CAN_TI2R_STID+    |CAN_TI2R_TXRQ+    |CAN_TSR_ABRQ0+    |CAN_TSR_ABRQ1+    |CAN_TSR_ABRQ2+    |CAN_TSR_ALST0+    |CAN_TSR_ALST1+    |CAN_TSR_ALST2+    |CAN_TSR_CODE+    |CAN_TSR_LOW0+    |CAN_TSR_LOW1+    |CAN_TSR_LOW2+    |CAN_TSR_RQCP0+    |CAN_TSR_RQCP1+    |CAN_TSR_RQCP2+    |CAN_TSR_TERR0+    |CAN_TSR_TERR1+    |CAN_TSR_TERR2+    |CAN_TSR_TME0+    |CAN_TSR_TME1+    |CAN_TSR_TME2+    |CAN_TSR_TXOK0+    |CAN_TSR_TXOK1+    |CAN_TSR_TXOK2+    |CCER_CC1E+    |CCER_CC1NE+    |CCER_CC1NP+    |CCER_CC1P+    |CCER_CC2E+    |CCER_CC2NE+    |CCER_CC2NP+    |CCER_CC2P+    |CCER_CC3E+    |CCER_CC3NE+    |CCER_CC3NP+    |CCER_CC3P+    |CCER_CC4E+    |CCER_CC4P+    |CCMR1_Input_CC1S+    |CCMR1_Input_CC2S+    |CCMR1_Input_IC1F+    |CCMR1_Input_IC1PSC+    |CCMR1_Input_IC2F+    |CCMR1_Input_IC2PCS+    |CCMR1_Input_IC2PSC+    |CCMR1_Input_ICPCS+    |CCMR1_Output_CC1S+    |CCMR1_Output_CC2S+    |CCMR1_Output_OC1CE+    |CCMR1_Output_OC1FE+    |CCMR1_Output_OC1M+    |CCMR1_Output_OC1PE+    |CCMR1_Output_OC2CE+    |CCMR1_Output_OC2FE+    |CCMR1_Output_OC2M+    |CCMR1_Output_OC2PE+    |CCMR2_Input_CC3S+    |CCMR2_Input_CC4S+    |CCMR2_Input_IC3F+    |CCMR2_Input_IC3PSC+    |CCMR2_Input_IC4F+    |CCMR2_Input_IC4PSC+    |CCMR2_Output_CC3S+    |CCMR2_Output_CC4S+    |CCMR2_Output_O24CE+    |CCMR2_Output_OC3CE+    |CCMR2_Output_OC3FE+    |CCMR2_Output_OC3M+    |CCMR2_Output_OC3PE+    |CCMR2_Output_OC4CE+    |CCMR2_Output_OC4FE+    |CCMR2_Output_OC4M+    |CCMR2_Output_OC4PE+    |CCR1_CCR1+    |CCR1_CIRC+    |CCR1_DIR+    |CCR1_EN+    |CCR1_HTIE+    |CCR1_MEM2MEM+    |CCR1_MINC+    |CCR1_MSIZE+    |CCR1_PINC+    |CCR1_PL+    |CCR1_PSIZE+    |CCR1_TCIE+    |CCR1_TEIE+    |CCR2_CCR2+    |CCR2_CIRC+    |CCR2_DIR+    |CCR2_EN+    |CCR2_HTIE+    |CCR2_MEM2MEM+    |CCR2_MINC+    |CCR2_MSIZE+    |CCR2_PINC+    |CCR2_PL+    |CCR2_PSIZE+    |CCR2_TCIE+    |CCR2_TEIE+    |CCR3_CCR3+    |CCR3_CIRC+    |CCR3_DIR+    |CCR3_EN+    |CCR3_HTIE+    |CCR3_MEM2MEM+    |CCR3_MINC+    |CCR3_MSIZE+    |CCR3_PINC+    |CCR3_PL+    |CCR3_PSIZE+    |CCR3_TCIE+    |CCR3_TEIE+    |CCR4_CCR4+    |CCR4_CIRC+    |CCR4_DIR+    |CCR4_EN+    |CCR4_HTIE+    |CCR4_MEM2MEM+    |CCR4_MINC+    |CCR4_MSIZE+    |CCR4_PINC+    |CCR4_PL+    |CCR4_PSIZE+    |CCR4_TCIE+    |CCR4_TEIE+    |CCR5_CIRC+    |CCR5_DIR+    |CCR5_EN+    |CCR5_HTIE+    |CCR5_MEM2MEM+    |CCR5_MINC+    |CCR5_MSIZE+    |CCR5_PINC+    |CCR5_PL+    |CCR5_PSIZE+    |CCR5_TCIE+    |CCR5_TEIE+    |CCR6_CIRC+    |CCR6_DIR+    |CCR6_EN+    |CCR6_HTIE+    |CCR6_MEM2MEM+    |CCR6_MINC+    |CCR6_MSIZE+    |CCR6_PINC+    |CCR6_PL+    |CCR6_PSIZE+    |CCR6_TCIE+    |CCR6_TEIE+    |CCR7_CIRC+    |CCR7_DIR+    |CCR7_EN+    |CCR7_HTIE+    |CCR7_MEM2MEM+    |CCR7_MINC+    |CCR7_MSIZE+    |CCR7_PINC+    |CCR7_PL+    |CCR7_PSIZE+    |CCR7_TCIE+    |CCR7_TEIE+    |CCR_CCR+    |CCR_DUTY+    |CCR_F_S+    |CFGR_ADCPRE+    |CFGR_HPRE+    |CFGR_MCO+    |CFGR_OTGFSPRE+    |CFGR_PLLMUL+    |CFGR_PLLSRC+    |CFGR_PLLXTPRE+    |CFGR_PPRE1+    |CFGR_PPRE2+    |CFGR_SW+    |CFGR_SWS+    |CFR_EWI+    |CFR_W+    |CFR_WDGTB+    |CIR_CSSC+    |CIR_CSSF+    |CIR_HSERDYC+    |CIR_HSERDYF+    |CIR_HSERDYIE+    |CIR_HSIRDYC+    |CIR_HSIRDYF+    |CIR_HSIRDYIE+    |CIR_LSERDYC+    |CIR_LSERDYF+    |CIR_LSERDYIE+    |CIR_LSIRDYC+    |CIR_LSIRDYF+    |CIR_LSIRDYIE+    |CIR_PLLRDYC+    |CIR_PLLRDYF+    |CIR_PLLRDYIE+    |CLKCR_BYPASS+    |CLKCR_CLKDIV+    |CLKCR_CLKEN+    |CLKCR_HWFC_EN+    |CLKCR_NEGEDGE+    |CLKCR_PWRSAV+    |CLKCR_WIDBUS+    |CMAR1_MA+    |CMAR2_MA+    |CMAR3_MA+    |CMAR4_MA+    |CMAR5_MA+    |CMAR6_MA+    |CMAR7_MA+    |CMD_CE_ATACMD+    |CMD_CMDINDEX+    |CMD_CPSMEN+    |CMD_ENCMDcompl+    |CMD_SDIOSuspend+    |CMD_WAITINT+    |CMD_WAITPEND+    |CMD_WAITRESP+    |CMD_nIEN+    |CNDTR1_NDT+    |CNDTR2_NDT+    |CNDTR3_NDT+    |CNDTR4_NDT+    |CNDTR5_NDT+    |CNDTR6_NDT+    |CNDTR7_NDT+    |CNTH_CNTH+    |CNTL_CNTL+    |CNTR_CTRM+    |CNTR_ERRM+    |CNTR_ESOFM+    |CNTR_FRES+    |CNTR_FSUSP+    |CNTR_LPMODE+    |CNTR_PDWN+    |CNTR_PMAOVRM+    |CNTR_RESETM+    |CNTR_RESUME+    |CNTR_SOFM+    |CNTR_SUSPM+    |CNTR_WKUPM+    |CNT_CNT+    |CPAR1_PA+    |CPAR2_PA+    |CPAR3_PA+    |CPAR4_PA+    |CPAR5_PA+    |CPAR6_PA+    |CPAR7_PA+    |CR1_ACK+    |CR1_ALERT+    |CR1_ARPE+    |CR1_AWDCH+    |CR1_AWDEN+    |CR1_AWDIE+    |CR1_AWDSGL+    |CR1_BIDIMODE+    |CR1_BIDIOE+    |CR1_BR+    |CR1_CEN+    |CR1_CKD+    |CR1_CMS+    |CR1_CPHA+    |CR1_CPOL+    |CR1_CRCEN+    |CR1_CRCNEXT+    |CR1_DFF+    |CR1_DIR+    |CR1_DISCEN+    |CR1_DISCNUM+    |CR1_DUALMOD+    |CR1_ENARP+    |CR1_ENGC+    |CR1_ENPEC+    |CR1_EOCIE+    |CR1_IDLEIE+    |CR1_JAUTO+    |CR1_JAWDEN+    |CR1_JDISCEN+    |CR1_JEOCIE+    |CR1_LSBFIRST+    |CR1_M+    |CR1_MSTR+    |CR1_NOSTRETCH+    |CR1_OPM+    |CR1_PCE+    |CR1_PE+    |CR1_PEC+    |CR1_PEIE+    |CR1_POS+    |CR1_PS+    |CR1_RE+    |CR1_RWU+    |CR1_RXNEIE+    |CR1_RXONLY+    |CR1_SBK+    |CR1_SCAN+    |CR1_SMBTYPE+    |CR1_SMBUS+    |CR1_SPE+    |CR1_SSI+    |CR1_SSM+    |CR1_START+    |CR1_STOP+    |CR1_SWRST+    |CR1_TCIE+    |CR1_TE+    |CR1_TXEIE+    |CR1_UDIS+    |CR1_UE+    |CR1_URS+    |CR1_WAKE+    |CR2_ADD+    |CR2_ADON+    |CR2_ALIGN+    |CR2_CAL+    |CR2_CCDS+    |CR2_CCPC+    |CR2_CCUS+    |CR2_CLKEN+    |CR2_CONT+    |CR2_CPHA+    |CR2_CPOL+    |CR2_DMA+    |CR2_DMAEN+    |CR2_ERRIE+    |CR2_EXTSEL+    |CR2_EXTTRIG+    |CR2_FREQ+    |CR2_ITBUFEN+    |CR2_ITERREN+    |CR2_ITEVTEN+    |CR2_JEXTSEL+    |CR2_JEXTTRIG+    |CR2_JSWSTART+    |CR2_LAST+    |CR2_LBCL+    |CR2_LBDIE+    |CR2_LBDL+    |CR2_LINEN+    |CR2_MMS+    |CR2_OIS1+    |CR2_OIS1N+    |CR2_OIS2+    |CR2_OIS2N+    |CR2_OIS3+    |CR2_OIS3N+    |CR2_OIS4+    |CR2_RSTCAL+    |CR2_RXDMAEN+    |CR2_RXNEIE+    |CR2_SSOE+    |CR2_STOP+    |CR2_SWSTART+    |CR2_TI1S+    |CR2_TSVREFE+    |CR2_TXDMAEN+    |CR2_TXEIE+    |CR3_CTSE+    |CR3_CTSIE+    |CR3_DMAR+    |CR3_DMAT+    |CR3_EIE+    |CR3_HDSEL+    |CR3_IREN+    |CR3_IRLP+    |CR3_NACK+    |CR3_RTSE+    |CR3_SCEN+    |CRCPR_CRCPOLY+    |CRH_ALRIE+    |CRH_CNF10+    |CRH_CNF11+    |CRH_CNF12+    |CRH_CNF13+    |CRH_CNF14+    |CRH_CNF15+    |CRH_CNF8+    |CRH_CNF9+    |CRH_MODE10+    |CRH_MODE11+    |CRH_MODE12+    |CRH_MODE13+    |CRH_MODE14+    |CRH_MODE15+    |CRH_MODE8+    |CRH_MODE9+    |CRH_OWIE+    |CRH_SECIE+    |CRL_ALRF+    |CRL_CNF+    |CRL_CNF0+    |CRL_CNF1+    |CRL_CNF2+    |CRL_CNF3+    |CRL_CNF4+    |CRL_CNF5+    |CRL_CNF6+    |CRL_CNF7+    |CRL_MODE0+    |CRL_MODE1+    |CRL_MODE2+    |CRL_MODE3+    |CRL_MODE4+    |CRL_MODE5+    |CRL_MODE6+    |CRL_MODE7+    |CRL_OWF+    |CRL_RSF+    |CRL_RTOFF+    |CRL_SECF+    |CR_BOFF1+    |CR_BOFF2+    |CR_CSBF+    |CR_CSSON+    |CR_CWUF+    |CR_DBG_CAN1_STOP+    |CR_DBG_CAN2_STOP+    |CR_DBG_I2C1_SMBUS_TIMEOUT+    |CR_DBG_I2C2_SMBUS_TIMEOUT+    |CR_DBG_IWDG_STOP+    |CR_DBG_SLEEP+    |CR_DBG_STANDBY+    |CR_DBG_STOP+    |CR_DBG_TIM1_STOP+    |CR_DBG_TIM2_STOP+    |CR_DBG_TIM3_STOP+    |CR_DBG_TIM4_STOP+    |CR_DBG_TIM5_STOP+    |CR_DBG_TIM6_STOP+    |CR_DBG_TIM7_STOP+    |CR_DBG_TIM8_STOP+    |CR_DBG_WWDG_STOP+    |CR_DBP+    |CR_DMAEN1+    |CR_DMAEN2+    |CR_EN1+    |CR_EN2+    |CR_EOPIE+    |CR_ERRIE+    |CR_HSEBYP+    |CR_HSEON+    |CR_HSERDY+    |CR_HSICAL+    |CR_HSION+    |CR_HSIRDY+    |CR_HSITRIM+    |CR_LOCK+    |CR_LPDS+    |CR_MAMP1+    |CR_MAMP2+    |CR_MER+    |CR_OPTER+    |CR_OPTPG+    |CR_OPTWRE+    |CR_PDDS+    |CR_PER+    |CR_PG+    |CR_PLLON+    |CR_PLLRDY+    |CR_PLS+    |CR_PVDE+    |CR_RESET+    |CR_STRT+    |CR_T+    |CR_TEN1+    |CR_TEN2+    |CR_TPAL+    |CR_TPE+    |CR_TRACE_IOEN+    |CR_TRACE_MODE+    |CR_TSEL1+    |CR_TSEL2+    |CR_WAVE1+    |CR_WAVE2+    |CR_WDGA+    |CSR_CTE+    |CSR_CTI+    |CSR_EWUP+    |CSR_IWDGRSTF+    |CSR_LPWRRSTF+    |CSR_LSION+    |CSR_LSIRDY+    |CSR_PINRSTF+    |CSR_PORRSTF+    |CSR_PVDO+    |CSR_RMVF+    |CSR_SBF+    |CSR_SFTRSTF+    |CSR_TEF+    |CSR_TIF+    |CSR_TPIE+    |CSR_WUF+    |CSR_WWDGRSTF+    |DADDR_ADD+    |DADDR_EF+    |DCOUNT_DATACOUNT+    |DCR_DBA+    |DCR_DBL+    |DCTRL_DBLOCKSIZE+    |DCTRL_DMAEN+    |DCTRL_DTDIR+    |DCTRL_DTEN+    |DCTRL_DTMODE+    |DCTRL_PWSTART+    |DCTRL_PWSTOP+    |DCTRL_RWMOD+    |DCTRL_SDIOEN+    |DHR12L1_DACC1DHR+    |DHR12L2_DACC2DHR+    |DHR12LD_DACC1DHR+    |DHR12LD_DACC2DHR+    |DHR12R1_DACC1DHR+    |DHR12R2_DACC2DHR+    |DHR12RD_DACC1DHR+    |DHR12RD_DACC2DHR+    |DHR8R1_DACC1DHR+    |DHR8R2_DACC2DHR+    |DHR8RD_DACC1DHR+    |DHR8RD_DACC2DHR+    |DIER_BIE+    |DIER_CC1DE+    |DIER_CC1IE+    |DIER_CC2DE+    |DIER_CC2IE+    |DIER_CC3DE+    |DIER_CC3IE+    |DIER_CC4DE+    |DIER_CC4IE+    |DIER_COMDE+    |DIER_COMIE+    |DIER_TDE+    |DIER_TIE+    |DIER_UDE+    |DIER_UIE+    |DIVH_DIVH+    |DIVL_DIVL+    |DLEN_DATALENGTH+    |DMAR_DMAB+    |DOR1_DACC1DOR+    |DOR2_DACC2DOR+    |DR10_D10+    |DR11_DR11+    |DR12_DR12+    |DR13_DR13+    |DR14_D14+    |DR15_D15+    |DR16_D16+    |DR17_D17+    |DR18_D18+    |DR19_D19+    |DR1_D1+    |DR20_D20+    |DR21_D21+    |DR22_D22+    |DR23_D23+    |DR24_D24+    |DR25_D25+    |DR26_D26+    |DR27_D27+    |DR28_D28+    |DR29_D29+    |DR2_D2+    |DR30_D30+    |DR31_D31+    |DR32_D32+    |DR33_D33+    |DR34_D34+    |DR35_D35+    |DR36_D36+    |DR37_D37+    |DR38_D38+    |DR39_D39+    |DR3_D3+    |DR40_D40+    |DR41_D41+    |DR42_D42+    |DR4_D4+    |DR5_D5+    |DR6_D6+    |DR7_D7+    |DR8_D8+    |DR9_D9+    |DR_ADC2DATA+    |DR_DATA+    |DR_DR+    |DTIMER_DATATIME+    |ECCR2_ECCx+    |ECCR3_ECCx+    |EGR_BG+    |EGR_CC1G+    |EGR_CC2G+    |EGR_CC3G+    |EGR_CC4G+    |EGR_COMG+    |EGR_TG+    |EGR_UG+    |EMR_MR0+    |EMR_MR1+    |EMR_MR10+    |EMR_MR11+    |EMR_MR12+    |EMR_MR13+    |EMR_MR14+    |EMR_MR15+    |EMR_MR16+    |EMR_MR17+    |EMR_MR18+    |EMR_MR2+    |EMR_MR3+    |EMR_MR4+    |EMR_MR5+    |EMR_MR6+    |EMR_MR7+    |EMR_MR8+    |EMR_MR9+    |EP0R_CTR_RX+    |EP0R_CTR_TX+    |EP0R_DTOG_RX+    |EP0R_DTOG_TX+    |EP0R_EA+    |EP0R_EP_KIND+    |EP0R_EP_TYPE+    |EP0R_SETUP+    |EP0R_STAT_RX+    |EP0R_STAT_TX+    |EP1R_CTR_RX+    |EP1R_CTR_TX+    |EP1R_DTOG_RX+    |EP1R_DTOG_TX+    |EP1R_EA+    |EP1R_EP_KIND+    |EP1R_EP_TYPE+    |EP1R_SETUP+    |EP1R_STAT_RX+    |EP1R_STAT_TX+    |EP2R_CTR_RX+    |EP2R_CTR_TX+    |EP2R_DTOG_RX+    |EP2R_DTOG_TX+    |EP2R_EA+    |EP2R_EP_KIND+    |EP2R_EP_TYPE+    |EP2R_SETUP+    |EP2R_STAT_RX+    |EP2R_STAT_TX+    |EP3R_CTR_RX+    |EP3R_CTR_TX+    |EP3R_DTOG_RX+    |EP3R_DTOG_TX+    |EP3R_EA+    |EP3R_EP_KIND+    |EP3R_EP_TYPE+    |EP3R_SETUP+    |EP3R_STAT_RX+    |EP3R_STAT_TX+    |EP4R_CTR_RX+    |EP4R_CTR_TX+    |EP4R_DTOG_RX+    |EP4R_DTOG_TX+    |EP4R_EA+    |EP4R_EP_KIND+    |EP4R_EP_TYPE+    |EP4R_SETUP+    |EP4R_STAT_RX+    |EP4R_STAT_TX+    |EP5R_CTR_RX+    |EP5R_CTR_TX+    |EP5R_DTOG_RX+    |EP5R_DTOG_TX+    |EP5R_EA+    |EP5R_EP_KIND+    |EP5R_EP_TYPE+    |EP5R_SETUP+    |EP5R_STAT_RX+    |EP5R_STAT_TX+    |EP6R_CTR_RX+    |EP6R_CTR_TX+    |EP6R_DTOG_RX+    |EP6R_DTOG_TX+    |EP6R_EA+    |EP6R_EP_KIND+    |EP6R_EP_TYPE+    |EP6R_SETUP+    |EP6R_STAT_RX+    |EP6R_STAT_TX+    |EP7R_CTR_RX+    |EP7R_CTR_TX+    |EP7R_DTOG_RX+    |EP7R_DTOG_TX+    |EP7R_EA+    |EP7R_EP_KIND+    |EP7R_EP_TYPE+    |EP7R_SETUP+    |EP7R_STAT_RX+    |EP7R_STAT_TX+    |EVCR_EVOE+    |EVCR_PIN+    |EVCR_PORT+    |EXTICR1_EXTI0+    |EXTICR1_EXTI1+    |EXTICR1_EXTI2+    |EXTICR1_EXTI3+    |EXTICR2_EXTI4+    |EXTICR2_EXTI5+    |EXTICR2_EXTI6+    |EXTICR2_EXTI7+    |EXTICR3_EXTI10+    |EXTICR3_EXTI11+    |EXTICR3_EXTI8+    |EXTICR3_EXTI9+    |EXTICR4_EXTI12+    |EXTICR4_EXTI13+    |EXTICR4_EXTI14+    |EXTICR4_EXTI15+    |F0R1_FB0+    |F0R1_FB1+    |F0R1_FB10+    |F0R1_FB11+    |F0R1_FB12+    |F0R1_FB13+    |F0R1_FB14+    |F0R1_FB15+    |F0R1_FB16+    |F0R1_FB17+    |F0R1_FB18+    |F0R1_FB19+    |F0R1_FB2+    |F0R1_FB20+    |F0R1_FB21+    |F0R1_FB22+    |F0R1_FB23+    |F0R1_FB24+    |F0R1_FB25+    |F0R1_FB26+    |F0R1_FB27+    |F0R1_FB28+    |F0R1_FB29+    |F0R1_FB3+    |F0R1_FB30+    |F0R1_FB31+    |F0R1_FB4+    |F0R1_FB5+    |F0R1_FB6+    |F0R1_FB7+    |F0R1_FB8+    |F0R1_FB9+    |F0R2_FB0+    |F0R2_FB1+    |F0R2_FB10+    |F0R2_FB11+    |F0R2_FB12+    |F0R2_FB13+    |F0R2_FB14+    |F0R2_FB15+    |F0R2_FB16+    |F0R2_FB17+    |F0R2_FB18+    |F0R2_FB19+    |F0R2_FB2+    |F0R2_FB20+    |F0R2_FB21+    |F0R2_FB22+    |F0R2_FB23+    |F0R2_FB24+    |F0R2_FB25+    |F0R2_FB26+    |F0R2_FB27+    |F0R2_FB28+    |F0R2_FB29+    |F0R2_FB3+    |F0R2_FB30+    |F0R2_FB31+    |F0R2_FB4+    |F0R2_FB5+    |F0R2_FB6+    |F0R2_FB7+    |F0R2_FB8+    |F0R2_FB9+    |F10R1_FB0+    |F10R1_FB1+    |F10R1_FB10+    |F10R1_FB11+    |F10R1_FB12+    |F10R1_FB13+    |F10R1_FB14+    |F10R1_FB15+    |F10R1_FB16+    |F10R1_FB17+    |F10R1_FB18+    |F10R1_FB19+    |F10R1_FB2+    |F10R1_FB20+    |F10R1_FB21+    |F10R1_FB22+    |F10R1_FB23+    |F10R1_FB24+    |F10R1_FB25+    |F10R1_FB26+    |F10R1_FB27+    |F10R1_FB28+    |F10R1_FB29+    |F10R1_FB3+    |F10R1_FB30+    |F10R1_FB31+    |F10R1_FB4+    |F10R1_FB5+    |F10R1_FB6+    |F10R1_FB7+    |F10R1_FB8+    |F10R1_FB9+    |F10R2_FB0+    |F10R2_FB1+    |F10R2_FB10+    |F10R2_FB11+    |F10R2_FB12+    |F10R2_FB13+    |F10R2_FB14+    |F10R2_FB15+    |F10R2_FB16+    |F10R2_FB17+    |F10R2_FB18+    |F10R2_FB19+    |F10R2_FB2+    |F10R2_FB20+    |F10R2_FB21+    |F10R2_FB22+    |F10R2_FB23+    |F10R2_FB24+    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|F6R1_FB12+    |F6R1_FB13+    |F6R1_FB14+    |F6R1_FB15+    |F6R1_FB16+    |F6R1_FB17+    |F6R1_FB18+    |F6R1_FB19+    |F6R1_FB2+    |F6R1_FB20+    |F6R1_FB21+    |F6R1_FB22+    |F6R1_FB23+    |F6R1_FB24+    |F6R1_FB25+    |F6R1_FB26+    |F6R1_FB27+    |F6R1_FB28+    |F6R1_FB29+    |F6R1_FB3+    |F6R1_FB30+    |F6R1_FB31+    |F6R1_FB4+    |F6R1_FB5+    |F6R1_FB6+    |F6R1_FB7+    |F6R1_FB8+    |F6R1_FB9+    |F6R2_FB0+    |F6R2_FB1+    |F6R2_FB10+    |F6R2_FB11+    |F6R2_FB12+    |F6R2_FB13+    |F6R2_FB14+    |F6R2_FB15+    |F6R2_FB16+    |F6R2_FB17+    |F6R2_FB18+    |F6R2_FB19+    |F6R2_FB2+    |F6R2_FB20+    |F6R2_FB21+    |F6R2_FB22+    |F6R2_FB23+    |F6R2_FB24+    |F6R2_FB25+    |F6R2_FB26+    |F6R2_FB27+    |F6R2_FB28+    |F6R2_FB29+    |F6R2_FB3+    |F6R2_FB30+    |F6R2_FB31+    |F6R2_FB4+    |F6R2_FB5+    |F6R2_FB6+    |F6R2_FB7+    |F6R2_FB8+    |F6R2_FB9+    |F7R1_FB0+    |F7R1_FB1+    |F7R1_FB10+    |F7R1_FB11+    |F7R1_FB12+    |F7R1_FB13+    |F7R1_FB14+    |F7R1_FB15+    |F7R1_FB16+    |F7R1_FB17+    |F7R1_FB18+    |F7R1_FB19+    |F7R1_FB2+    |F7R1_FB20+    |F7R1_FB21+    |F7R1_FB22+    |F7R1_FB23+    |F7R1_FB24+    |F7R1_FB25+    |F7R1_FB26+    |F7R1_FB27+    |F7R1_FB28+    |F7R1_FB29+    |F7R1_FB3+    |F7R1_FB30+    |F7R1_FB31+    |F7R1_FB4+    |F7R1_FB5+    |F7R1_FB6+    |F7R1_FB7+    |F7R1_FB8+    |F7R1_FB9+    |F7R2_FB0+    |F7R2_FB1+    |F7R2_FB10+    |F7R2_FB11+    |F7R2_FB12+    |F7R2_FB13+    |F7R2_FB14+    |F7R2_FB15+    |F7R2_FB16+    |F7R2_FB17+    |F7R2_FB18+    |F7R2_FB19+    |F7R2_FB2+    |F7R2_FB20+    |F7R2_FB21+    |F7R2_FB22+    |F7R2_FB23+    |F7R2_FB24+    |F7R2_FB25+    |F7R2_FB26+    |F7R2_FB27+    |F7R2_FB28+    |F7R2_FB29+    |F7R2_FB3+    |F7R2_FB30+    |F7R2_FB31+    |F7R2_FB4+    |F7R2_FB5+    |F7R2_FB6+    |F7R2_FB7+    |F7R2_FB8+    |F7R2_FB9+    |F8R1_FB0+    |F8R1_FB1+    |F8R1_FB10+    |F8R1_FB11+    |F8R1_FB12+    |F8R1_FB13+    |F8R1_FB14+    |F8R1_FB15+    |F8R1_FB16+    |F8R1_FB17+    |F8R1_FB18+    |F8R1_FB19+    |F8R1_FB2+    |F8R1_FB20+    |F8R1_FB21+    |F8R1_FB22+    |F8R1_FB23+    |F8R1_FB24+    |F8R1_FB25+    |F8R1_FB26+    |F8R1_FB27+    |F8R1_FB28+    |F8R1_FB29+    |F8R1_FB3+    |F8R1_FB30+    |F8R1_FB31+    |F8R1_FB4+    |F8R1_FB5+    |F8R1_FB6+    |F8R1_FB7+    |F8R1_FB8+    |F8R1_FB9+    |F8R2_FB0+    |F8R2_FB1+    |F8R2_FB10+    |F8R2_FB11+    |F8R2_FB12+    |F8R2_FB13+    |F8R2_FB14+    |F8R2_FB15+    |F8R2_FB16+    |F8R2_FB17+    |F8R2_FB18+    |F8R2_FB19+    |F8R2_FB2+    |F8R2_FB20+    |F8R2_FB21+    |F8R2_FB22+    |F8R2_FB23+    |F8R2_FB24+    |F8R2_FB25+    |F8R2_FB26+    |F8R2_FB27+    |F8R2_FB28+    |F8R2_FB29+    |F8R2_FB3+    |F8R2_FB30+    |F8R2_FB31+    |F8R2_FB4+    |F8R2_FB5+    |F8R2_FB6+    |F8R2_FB7+    |F8R2_FB8+    |F8R2_FB9+    |F9R1_FB0+    |F9R1_FB1+    |F9R1_FB10+    |F9R1_FB11+    |F9R1_FB12+    |F9R1_FB13+    |F9R1_FB14+    |F9R1_FB15+    |F9R1_FB16+    |F9R1_FB17+    |F9R1_FB18+    |F9R1_FB19+    |F9R1_FB2+    |F9R1_FB20+    |F9R1_FB21+    |F9R1_FB22+    |F9R1_FB23+    |F9R1_FB24+    |F9R1_FB25+    |F9R1_FB26+    |F9R1_FB27+    |F9R1_FB28+    |F9R1_FB29+    |F9R1_FB3+    |F9R1_FB30+    |F9R1_FB31+    |F9R1_FB4+    |F9R1_FB5+    |F9R1_FB6+    |F9R1_FB7+    |F9R1_FB8+    |F9R1_FB9+    |F9R2_FB0+    |F9R2_FB1+    |F9R2_FB10+    |F9R2_FB11+    |F9R2_FB12+    |F9R2_FB13+    |F9R2_FB14+    |F9R2_FB15+    |F9R2_FB16+    |F9R2_FB17+    |F9R2_FB18+    |F9R2_FB19+    |F9R2_FB2+    |F9R2_FB20+    |F9R2_FB21+    |F9R2_FB22+    |F9R2_FB23+    |F9R2_FB24+    |F9R2_FB25+    |F9R2_FB26+    |F9R2_FB27+    |F9R2_FB28+    |F9R2_FB29+    |F9R2_FB3+    |F9R2_FB30+    |F9R2_FB31+    |F9R2_FB4+    |F9R2_FB5+    |F9R2_FB6+    |F9R2_FB7+    |F9R2_FB8+    |F9R2_FB9+    |FIFOCNT_FIF0COUNT+    |FIFO_FIFOData+    |FNR_FN+    |FNR_LCK+    |FNR_LSOF+    |FNR_RXDM+    |FNR_RXDP+    |FTSR_TR0+    |FTSR_TR1+    |FTSR_TR10+    |FTSR_TR11+    |FTSR_TR12+    |FTSR_TR13+    |FTSR_TR14+    |FTSR_TR15+    |FTSR_TR16+    |FTSR_TR17+    |FTSR_TR18+    |FTSR_TR2+    |FTSR_TR3+    |FTSR_TR4+    |FTSR_TR5+    |FTSR_TR6+    |FTSR_TR7+    |FTSR_TR8+    |FTSR_TR9+    |GTPR_GT+    |GTPR_PSC+    |HTR_HT+    |I2SCFGR_CHLEN+    |I2SCFGR_CKPOL+    |I2SCFGR_DATLEN+    |I2SCFGR_I2SCFG+    |I2SCFGR_I2SE+    |I2SCFGR_I2SMOD+    |I2SCFGR_I2SSTD+    |I2SCFGR_PCMSYNC+    |I2SPR_I2SDIV+    |I2SPR_MCKOE+    |I2SPR_ODD+    |IABR0_ACTIVE+    |IABR1_ACTIVE+    |ICER0_CLRENA+    |ICER1_CLRENA+    |ICPR0_CLRPEND+    |ICPR1_CLRPEND+    |ICR_CCRCFAILC+    |ICR_CEATAENDC+    |ICR_CMDRENDC+    |ICR_CMDSENTC+    |ICR_CTIMEOUTC+    |ICR_DATAENDC+    |ICR_DBCKENDC+    |ICR_DCRCFAILC+    |ICR_DTIMEOUTC+    |ICR_RXOVERRC+    |ICR_SDIOITC+    |ICR_STBITERRC+    |ICR_TXUNDERRC+    |ICTR_INTLINESNUM+    |IDCODE_DEV_ID+    |IDCODE_REV_ID+    |IDR_IDR+    |IDR_IDR0+    |IDR_IDR1+    |IDR_IDR10+    |IDR_IDR11+    |IDR_IDR12+    |IDR_IDR13+    |IDR_IDR14+    |IDR_IDR15+    |IDR_IDR2+    |IDR_IDR3+    |IDR_IDR4+    |IDR_IDR5+    |IDR_IDR6+    |IDR_IDR7+    |IDR_IDR8+    |IDR_IDR9+    |IFCR_CGIF1+    |IFCR_CGIF2+    |IFCR_CGIF3+    |IFCR_CGIF4+    |IFCR_CGIF5+    |IFCR_CGIF6+    |IFCR_CGIF7+    |IFCR_CHTIF1+    |IFCR_CHTIF2+    |IFCR_CHTIF3+    |IFCR_CHTIF4+    |IFCR_CHTIF5+    |IFCR_CHTIF6+    |IFCR_CHTIF7+    |IFCR_CTCIF1+    |IFCR_CTCIF2+    |IFCR_CTCIF3+    |IFCR_CTCIF4+    |IFCR_CTCIF5+    |IFCR_CTCIF6+    |IFCR_CTCIF7+    |IFCR_CTEIF1+    |IFCR_CTEIF2+    |IFCR_CTEIF3+    |IFCR_CTEIF4+    |IFCR_CTEIF5+    |IFCR_CTEIF6+    |IFCR_CTEIF7+    |IMR_MR0+    |IMR_MR1+    |IMR_MR10+    |IMR_MR11+    |IMR_MR12+    |IMR_MR13+    |IMR_MR14+    |IMR_MR15+    |IMR_MR16+    |IMR_MR17+    |IMR_MR18+    |IMR_MR2+    |IMR_MR3+    |IMR_MR4+    |IMR_MR5+    |IMR_MR6+    |IMR_MR7+    |IMR_MR8+    |IMR_MR9+    |IPR0_IPR_N0+    |IPR0_IPR_N1+    |IPR0_IPR_N2+    |IPR0_IPR_N3+    |IPR10_IPR_N0+    |IPR10_IPR_N1+    |IPR10_IPR_N2+    |IPR10_IPR_N3+    |IPR11_IPR_N0+    |IPR11_IPR_N1+    |IPR11_IPR_N2+    |IPR11_IPR_N3+    |IPR12_IPR_N0+    |IPR12_IPR_N1+    |IPR12_IPR_N2+    |IPR12_IPR_N3+    |IPR13_IPR_N0+    |IPR13_IPR_N1+    |IPR13_IPR_N2+    |IPR13_IPR_N3+    |IPR14_IPR_N0+    |IPR14_IPR_N1+    |IPR14_IPR_N2+    |IPR14_IPR_N3+    |IPR1_IPR_N0+    |IPR1_IPR_N1+    |IPR1_IPR_N2+    |IPR1_IPR_N3+    |IPR2_IPR_N0+    |IPR2_IPR_N1+    |IPR2_IPR_N2+    |IPR2_IPR_N3+    |IPR3_IPR_N0+    |IPR3_IPR_N1+    |IPR3_IPR_N2+    |IPR3_IPR_N3+    |IPR4_IPR_N0+    |IPR4_IPR_N1+    |IPR4_IPR_N2+    |IPR4_IPR_N3+    |IPR5_IPR_N0+    |IPR5_IPR_N1+    |IPR5_IPR_N2+    |IPR5_IPR_N3+    |IPR6_IPR_N0+    |IPR6_IPR_N1+    |IPR6_IPR_N2+    |IPR6_IPR_N3+    |IPR7_IPR_N0+    |IPR7_IPR_N1+    |IPR7_IPR_N2+    |IPR7_IPR_N3+    |IPR8_IPR_N0+    |IPR8_IPR_N1+    |IPR8_IPR_N2+    |IPR8_IPR_N3+    |IPR9_IPR_N0+    |IPR9_IPR_N1+    |IPR9_IPR_N2+    |IPR9_IPR_N3+    |ISER0_SETENA+    |ISER1_SETENA+    |ISPR0_SETPEND+    |ISPR1_SETPEND+    |ISR_GIF1+    |ISR_GIF2+    |ISR_GIF3+    |ISR_GIF4+    |ISR_GIF5+    |ISR_GIF6+    |ISR_GIF7+    |ISR_HTIF1+    |ISR_HTIF2+    |ISR_HTIF3+    |ISR_HTIF4+    |ISR_HTIF5+    |ISR_HTIF6+    |ISR_HTIF7+    |ISR_TCIF1+    |ISR_TCIF2+    |ISR_TCIF3+    |ISR_TCIF4+    |ISR_TCIF5+    |ISR_TCIF6+    |ISR_TCIF7+    |ISR_TEIF1+    |ISR_TEIF2+    |ISR_TEIF3+    |ISR_TEIF4+    |ISR_TEIF5+    |ISR_TEIF6+    |ISR_TEIF7+    |ISTR_CTR+    |ISTR_DIR+    |ISTR_EP_ID+    |ISTR_ERR+    |ISTR_ESOF+    |ISTR_PMAOVR+    |ISTR_RESET+    |ISTR_SOF+    |ISTR_SUSP+    |ISTR_WKUP+    |JDR1_JDATA+    |JDR2_JDATA+    |JDR3_JDATA+    |JDR4_JDATA+    |JOFR1_JOFFSET1+    |JOFR2_JOFFSET2+    |JOFR3_JOFFSET3+    |JOFR4_JOFFSET4+    |JSQR_JL+    |JSQR_JSQ1+    |JSQR_JSQ2+    |JSQR_JSQ3+    |JSQR_JSQ4+    |KEYR_KEY+    |KR_KEY+    |LCKR_LCK0+    |LCKR_LCK1+    |LCKR_LCK10+    |LCKR_LCK11+    |LCKR_LCK12+    |LCKR_LCK13+    |LCKR_LCK14+    |LCKR_LCK15+    |LCKR_LCK2+    |LCKR_LCK3+    |LCKR_LCK4+    |LCKR_LCK5+    |LCKR_LCK6+    |LCKR_LCK7+    |LCKR_LCK8+    |LCKR_LCK9+    |LCKR_LCKK+    |LTR_LT+    |MAPR2_FSMC_NADV+    |MAPR2_TIM10_REMAP+    |MAPR2_TIM11_REMAP+    |MAPR2_TIM13_REMAP+    |MAPR2_TIM14_REMAP+    |MAPR2_TIM9_REMAP+    |MAPR_ADC1_ETRGINJ_REMAP+    |MAPR_ADC1_ETRGREG_REMAP+    |MAPR_ADC2_ETRGINJ_REMAP+    |MAPR_ADC2_ETRGREG_REMAP+    |MAPR_CAN_REMAP+    |MAPR_I2C1_REMAP+    |MAPR_PD01_REMAP+    |MAPR_SPI1_REMAP+    |MAPR_SWJ_CFG+    |MAPR_TIM1_REMAP+    |MAPR_TIM2_REMAP+    |MAPR_TIM3_REMAP+    |MAPR_TIM4_REMAP+    |MAPR_TIM5CH4_IREMAP+    |MAPR_USART1_REMAP+    |MAPR_USART2_REMAP+    |MAPR_USART3_REMAP+    |MASK_CCRCFAILIE+    |MASK_CEATENDIE+    |MASK_CMDACTIE+    |MASK_CMDRENDIE+    |MASK_CMDSENTIE+    |MASK_CTIMEOUTIE+    |MASK_DATAENDIE+    |MASK_DBACKENDIE+    |MASK_DCRCFAILIE+    |MASK_DTIMEOUTIE+    |MASK_RXACTIE+    |MASK_RXDAVLIE+    |MASK_RXFIFOEIE+    |MASK_RXFIFOFIE+    |MASK_RXFIFOHFIE+    |MASK_RXOVERRIE+    |MASK_SDIOITIE+    |MASK_STBITERRIE+    |MASK_TXACTIE+    |MASK_TXDAVLIE+    |MASK_TXFIFOEIE+    |MASK_TXFIFOFIE+    |MASK_TXFIFOHEIE+    |MASK_TXUNDERRIE+    |OAR1_ADD0+    |OAR1_ADD10+    |OAR1_ADD7+    |OAR1_ADDMODE+    |OAR2_ADD2+    |OAR2_ENDUAL+    |OBR_Data0+    |OBR_Data1+    |OBR_OPTERR+    |OBR_RDPRT+    |OBR_WDG_SW+    |OBR_nRST_STDBY+    |OBR_nRST_STOP+    |ODR_ODR0+    |ODR_ODR1+    |ODR_ODR10+    |ODR_ODR11+    |ODR_ODR12+    |ODR_ODR13+    |ODR_ODR14+    |ODR_ODR15+    |ODR_ODR2+    |ODR_ODR3+    |ODR_ODR4+    |ODR_ODR5+    |ODR_ODR6+    |ODR_ODR7+    |ODR_ODR8+    |ODR_ODR9+    |OPTKEYR_OPTKEY+    |PATT2_ATTHIZx+    |PATT2_ATTHOLDx+    |PATT2_ATTSETx+    |PATT2_ATTWAITx+    |PATT3_ATTHIZx+    |PATT3_ATTHOLDx+    |PATT3_ATTSETx+    |PATT3_ATTWAITx+    |PATT4_ATTHIZx+    |PATT4_ATTHOLDx+    |PATT4_ATTSETx+    |PATT4_ATTWAITx+    |PCR2_ECCEN+    |PCR2_ECCPS+    |PCR2_PBKEN+    |PCR2_PTYP+    |PCR2_PWAITEN+    |PCR2_PWID+    |PCR2_TAR+    |PCR2_TCLR+    |PCR3_ECCEN+    |PCR3_ECCPS+    |PCR3_PBKEN+    |PCR3_PTYP+    |PCR3_PWAITEN+    |PCR3_PWID+    |PCR3_TAR+    |PCR3_TCLR+    |PCR4_ECCEN+    |PCR4_ECCPS+    |PCR4_PBKEN+    |PCR4_PTYP+    |PCR4_PWAITEN+    |PCR4_PWID+    |PCR4_TAR+    |PCR4_TCLR+    |PIO4_IOHIZx+    |PIO4_IOHOLDx+    |PIO4_IOSETx+    |PIO4_IOWAITx+    |PMEM2_MEMHIZx+    |PMEM2_MEMHOLDx+    |PMEM2_MEMSETx+    |PMEM2_MEMWAITx+    |PMEM3_MEMHIZx+    |PMEM3_MEMHOLDx+    |PMEM3_MEMSETx+    |PMEM3_MEMWAITx+    |PMEM4_MEMHIZx+    |PMEM4_MEMHOLDx+    |PMEM4_MEMSETx+    |PMEM4_MEMWAITx+    |POWER_PWRCTRL+    |PRLH_PRLH+    |PRLL_PRLL+    |PR_PR+    |PR_PR0+    |PR_PR1+    |PR_PR10+    |PR_PR11+    |PR_PR12+    |PR_PR13+    |PR_PR14+    |PR_PR15+    |PR_PR16+    |PR_PR17+    |PR_PR18+    |PR_PR2+    |PR_PR3+    |PR_PR4+    |PR_PR5+    |PR_PR6+    |PR_PR7+    |PR_PR8+    |PR_PR9+    |PSC_PSC+    |RCR_REP+    |RESP2_CARDSTATUS2+    |RESP3_CARDSTATUS3+    |RESP4_CARDSTATUS4+    |RESPCMD_RESPCMD+    |RESPI1_CARDSTATUS1+    |RLR_RL+    |RTCCR_ASOE+    |RTCCR_ASOS+    |RTCCR_CAL+    |RTCCR_CCO+    |RTSR_TR0+    |RTSR_TR1+    |RTSR_TR10+    |RTSR_TR11+    |RTSR_TR12+    |RTSR_TR13+    |RTSR_TR14+    |RTSR_TR15+    |RTSR_TR16+    |RTSR_TR17+    |RTSR_TR18+    |RTSR_TR2+    |RTSR_TR3+    |RTSR_TR4+    |RTSR_TR5+    |RTSR_TR6+    |RTSR_TR7+    |RTSR_TR8+    |RTSR_TR9+    |RXCRCR_RxCRC+    |SMCR_ECE+    |SMCR_ETF+    |SMCR_ETP+    |SMCR_ETPS+    |SMCR_MSM+    |SMCR_SMS+    |SMCR_TS+    |SMPR1_SMP10+    |SMPR1_SMP11+    |SMPR1_SMP12+    |SMPR1_SMP13+    |SMPR1_SMP14+    |SMPR1_SMP15+    |SMPR1_SMP16+    |SMPR1_SMP17+    |SMPR2_SMP0+    |SMPR2_SMP1+    |SMPR2_SMP2+    |SMPR2_SMP3+    |SMPR2_SMP4+    |SMPR2_SMP5+    |SMPR2_SMP6+    |SMPR2_SMP7+    |SMPR2_SMP8+    |SMPR2_SMP9+    |SQR1_L+    |SQR1_SQ13+    |SQR1_SQ14+    |SQR1_SQ15+    |SQR1_SQ16+    |SQR2_SQ10+    |SQR2_SQ11+    |SQR2_SQ12+    |SQR2_SQ7+    |SQR2_SQ8+    |SQR2_SQ9+    |SQR3_SQ1+    |SQR3_SQ2+    |SQR3_SQ3+    |SQR3_SQ4+    |SQR3_SQ5+    |SQR3_SQ6+    |SR1_ADD10+    |SR1_ADDR+    |SR1_AF+    |SR1_ARLO+    |SR1_BERR+    |SR1_BTF+    |SR1_OVR+    |SR1_PECERR+    |SR1_RxNE+    |SR1_SB+    |SR1_SMBALERT+    |SR1_STOPF+    |SR1_TIMEOUT+    |SR1_TxE+    |SR2_BUSY+    |SR2_DUALF+    |SR2_FEMPT+    |SR2_GENCALL+    |SR2_IFEN+    |SR2_IFS+    |SR2_ILEN+    |SR2_ILS+    |SR2_IREN+    |SR2_IRS+    |SR2_MSL+    |SR2_PEC+    |SR2_SMBDEFAULT+    |SR2_SMBHOST+    |SR2_TRA+    |SR3_FEMPT+    |SR3_IFEN+    |SR3_IFS+    |SR3_ILEN+    |SR3_ILS+    |SR3_IREN+    |SR3_IRS+    |SR4_FEMPT+    |SR4_IFEN+    |SR4_IFS+    |SR4_ILEN+    |SR4_ILS+    |SR4_IREN+    |SR4_IRS+    |SR_AWD+    |SR_BIF+    |SR_BSY+    |SR_CC1IF+    |SR_CC1OF+    |SR_CC2IF+    |SR_CC2OF+    |SR_CC3IF+    |SR_CC3OF+    |SR_CC4IF+    |SR_CC4OF+    |SR_CHSIDE+    |SR_COMIF+    |SR_CRCERR+    |SR_CTS+    |SR_EOC+    |SR_EOP+    |SR_EWI+    |SR_FE+    |SR_IDLE+    |SR_JEOC+    |SR_JSTRT+    |SR_LBD+    |SR_MODF+    |SR_NE+    |SR_ORE+    |SR_OVR+    |SR_PE+    |SR_PGERR+    |SR_PVU+    |SR_RVU+    |SR_RXNE+    |SR_STRT+    |SR_TC+    |SR_TIF+    |SR_TXE+    |SR_UDR+    |SR_UIF+    |SR_WRPRTERR+    |STA_CCRCFAIL+    |STA_CEATAEND+    |STA_CMDACT+    |STA_CMDREND+    |STA_CMDSENT+    |STA_CTIMEOUT+    |STA_DATAEND+    |STA_DBCKEND+    |STA_DCRCFAIL+    |STA_DTIMEOUT+    |STA_RXACT+    |STA_RXDAVL+    |STA_RXFIFOE+    |STA_RXFIFOF+    |STA_RXFIFOHF+    |STA_RXOVERR+    |STA_SDIOIT+    |STA_STBITERR+    |STA_TXACT+    |STA_TXDAVL+    |STA_TXFIFOE+    |STA_TXFIFOF+    |STA_TXFIFOHE+    |STA_TXUNDERR+    |STIR_INTID+    |SWIER_SWIER0+    |SWIER_SWIER1+    |SWIER_SWIER10+    |SWIER_SWIER11+    |SWIER_SWIER12+    |SWIER_SWIER13+    |SWIER_SWIER14+    |SWIER_SWIER15+    |SWIER_SWIER16+    |SWIER_SWIER17+    |SWIER_SWIER18+    |SWIER_SWIER2+    |SWIER_SWIER3+    |SWIER_SWIER4+    |SWIER_SWIER5+    |SWIER_SWIER6+    |SWIER_SWIER7+    |SWIER_SWIER8+    |SWIER_SWIER9+    |SWTRIGR_SWTRIG1+    |SWTRIGR_SWTRIG2+    |TRISE_TRISE+    |TXCRCR_TxCRC+    |WRPR_WRP+    deriving (Show,Eq,Ord)++peripheralBase :: Peripheral -> Word32+peripheralBase FSMC = 0xA0000000+peripheralBase PWR = 0x40007000+peripheralBase RCC = 0x40021000+peripheralBase GPIOA = 0x40010800+peripheralBase GPIOB = 0x40010C00+peripheralBase GPIOC = 0x40011000+peripheralBase GPIOD = 0x40011400+peripheralBase GPIOE = 0x40011800+peripheralBase GPIOF = 0x40011C00+peripheralBase GPIOG = 0x40012000+peripheralBase AFIO = 0x40010000+peripheralBase EXTI = 0x40010400+peripheralBase DMA1 = 0x40020000+peripheralBase DMA2 = 0x40020400+peripheralBase SDIO = 0x40018000+peripheralBase RTC = 0x40002800+peripheralBase BKP = 0x40006C04+peripheralBase IWDG = 0x40003000+peripheralBase WWDG = 0x40002C00+peripheralBase TIM1 = 0x40012C00+peripheralBase TIM8 = 0x40013400+peripheralBase TIM2 = 0x40000000+peripheralBase TIM3 = 0x40000400+peripheralBase TIM4 = 0x40000800+peripheralBase TIM5 = 0x40000C00+peripheralBase TIM9 = 0x40014C00+peripheralBase TIM12 = 0x40001800+peripheralBase TIM10 = 0x40015000+peripheralBase TIM11 = 0x40015400+peripheralBase TIM13 = 0x40001C00+peripheralBase TIM14 = 0x40002000+peripheralBase TIM6 = 0x40001000+peripheralBase TIM7 = 0x40001400+peripheralBase I2C1 = 0x40005400+peripheralBase I2C2 = 0x40005800+peripheralBase SPI1 = 0x40013000+peripheralBase SPI2 = 0x40003800+peripheralBase SPI3 = 0x40003C00+peripheralBase USART1 = 0x40013800+peripheralBase USART2 = 0x40004400+peripheralBase USART3 = 0x40004800+peripheralBase ADC1 = 0x40012400+peripheralBase ADC2 = 0x40012800+peripheralBase ADC3 = 0x40013C00+peripheralBase CAN = 0x40006400+peripheralBase DAC = 0x40007400+peripheralBase DBG = 0xE0042000+peripheralBase UART4 = 0x40004C00+peripheralBase UART5 = 0x40005000+peripheralBase CRC = 0x40023000+peripheralBase FLASH = 0x40022000+peripheralBase NVIC = 0xE000E000+peripheralBase USB = 0x40005C00++registerOffset :: Peripheral -> Register -> Word32+registerOffset FSMC BCR1 = 0x0+registerOffset FSMC BTR1 = 0x4+registerOffset FSMC BCR2 = 0x8+registerOffset FSMC BTR2 = 0xC+registerOffset FSMC BCR3 = 0x10+registerOffset FSMC BTR3 = 0x14+registerOffset FSMC BCR4 = 0x18+registerOffset FSMC BTR4 = 0x1C+registerOffset FSMC PCR2 = 0x60+registerOffset FSMC SR2 = 0x64+registerOffset FSMC PMEM2 = 0x68+registerOffset FSMC PATT2 = 0x6C+registerOffset FSMC ECCR2 = 0x74+registerOffset FSMC PCR3 = 0x80+registerOffset FSMC SR3 = 0x84+registerOffset FSMC PMEM3 = 0x88+registerOffset FSMC PATT3 = 0x8C+registerOffset FSMC ECCR3 = 0x94+registerOffset FSMC PCR4 = 0xA0+registerOffset FSMC SR4 = 0xA4+registerOffset FSMC PMEM4 = 0xA8+registerOffset FSMC PATT4 = 0xAC+registerOffset FSMC PIO4 = 0xB0+registerOffset FSMC BWTR1 = 0x104+registerOffset FSMC BWTR2 = 0x10C+registerOffset FSMC BWTR3 = 0x114+registerOffset FSMC BWTR4 = 0x11C+registerOffset PWR CR = 0x0+registerOffset PWR CSR = 0x4+registerOffset RCC CR = 0x0+registerOffset RCC CFGR = 0x4+registerOffset RCC CIR = 0x8+registerOffset RCC APB2RSTR = 0xC+registerOffset RCC APB1RSTR = 0x10+registerOffset RCC AHBENR = 0x14+registerOffset RCC APB2ENR = 0x18+registerOffset RCC APB1ENR = 0x1C+registerOffset RCC BDCR = 0x20+registerOffset RCC CSR = 0x24+registerOffset GPIOA CRL = 0x0+registerOffset GPIOA CRH = 0x4+registerOffset GPIOA IDR = 0x8+registerOffset GPIOA ODR = 0xC+registerOffset GPIOA BSRR = 0x10+registerOffset GPIOA BRR = 0x14+registerOffset GPIOA LCKR = 0x18+registerOffset AFIO EVCR = 0x0+registerOffset AFIO MAPR = 0x4+registerOffset AFIO EXTICR1 = 0x8+registerOffset AFIO EXTICR2 = 0xC+registerOffset AFIO EXTICR3 = 0x10+registerOffset AFIO EXTICR4 = 0x14+registerOffset AFIO MAPR2 = 0x1C+registerOffset EXTI IMR = 0x0+registerOffset EXTI EMR = 0x4+registerOffset EXTI RTSR = 0x8+registerOffset EXTI FTSR = 0xC+registerOffset EXTI SWIER = 0x10+registerOffset EXTI PR = 0x14+registerOffset DMA1 ISR = 0x0+registerOffset DMA1 IFCR = 0x4+registerOffset DMA1 CCR1 = 0x8+registerOffset DMA1 CNDTR1 = 0xC+registerOffset DMA1 CPAR1 = 0x10+registerOffset DMA1 CMAR1 = 0x14+registerOffset DMA1 CCR2 = 0x1C+registerOffset DMA1 CNDTR2 = 0x20+registerOffset DMA1 CPAR2 = 0x24+registerOffset DMA1 CMAR2 = 0x28+registerOffset DMA1 CCR3 = 0x30+registerOffset DMA1 CNDTR3 = 0x34+registerOffset DMA1 CPAR3 = 0x38+registerOffset DMA1 CMAR3 = 0x3C+registerOffset DMA1 CCR4 = 0x44+registerOffset DMA1 CNDTR4 = 0x48+registerOffset DMA1 CPAR4 = 0x4C+registerOffset DMA1 CMAR4 = 0x50+registerOffset DMA1 CCR5 = 0x58+registerOffset DMA1 CNDTR5 = 0x5C+registerOffset DMA1 CPAR5 = 0x60+registerOffset DMA1 CMAR5 = 0x64+registerOffset DMA1 CCR6 = 0x6C+registerOffset DMA1 CNDTR6 = 0x70+registerOffset DMA1 CPAR6 = 0x74+registerOffset DMA1 CMAR6 = 0x78+registerOffset DMA1 CCR7 = 0x80+registerOffset DMA1 CNDTR7 = 0x84+registerOffset DMA1 CPAR7 = 0x88+registerOffset DMA1 CMAR7 = 0x8C+registerOffset SDIO POWER = 0x0+registerOffset SDIO CLKCR = 0x4+registerOffset SDIO ARG = 0x8+registerOffset SDIO CMD = 0xC+registerOffset SDIO RESPCMD = 0x10+registerOffset SDIO RESPI1 = 0x14+registerOffset SDIO RESP2 = 0x18+registerOffset SDIO RESP3 = 0x1C+registerOffset SDIO RESP4 = 0x20+registerOffset SDIO DTIMER = 0x24+registerOffset SDIO DLEN = 0x28+registerOffset SDIO DCTRL = 0x2C+registerOffset SDIO DCOUNT = 0x30+registerOffset SDIO STA = 0x34+registerOffset SDIO ICR = 0x38+registerOffset SDIO MASK = 0x3C+registerOffset SDIO FIFOCNT = 0x48+registerOffset SDIO FIFO = 0x80+registerOffset RTC CRH = 0x0+registerOffset RTC CRL = 0x4+registerOffset RTC PRLH = 0x8+registerOffset RTC PRLL = 0xC+registerOffset RTC DIVH = 0x10+registerOffset RTC DIVL = 0x14+registerOffset RTC CNTH = 0x18+registerOffset RTC CNTL = 0x1C+registerOffset RTC ALRH = 0x20+registerOffset RTC ALRL = 0x24+registerOffset BKP DR1 = 0x0+registerOffset BKP DR2 = 0x4+registerOffset BKP DR3 = 0x8+registerOffset BKP DR4 = 0xC+registerOffset BKP DR5 = 0x10+registerOffset BKP DR6 = 0x14+registerOffset BKP DR7 = 0x18+registerOffset BKP DR8 = 0x1C+registerOffset BKP DR9 = 0x20+registerOffset BKP DR10 = 0x24+registerOffset BKP DR11 = 0x3C+registerOffset BKP DR12 = 0x40+registerOffset BKP DR13 = 0x44+registerOffset BKP DR14 = 0x48+registerOffset BKP DR15 = 0x4C+registerOffset BKP DR16 = 0x50+registerOffset BKP DR17 = 0x54+registerOffset BKP DR18 = 0x58+registerOffset BKP DR19 = 0x5C+registerOffset BKP DR20 = 0x60+registerOffset BKP DR21 = 0x64+registerOffset BKP DR22 = 0x68+registerOffset BKP DR23 = 0x6C+registerOffset BKP DR24 = 0x70+registerOffset BKP DR25 = 0x74+registerOffset BKP DR26 = 0x78+registerOffset BKP DR27 = 0x7C+registerOffset BKP DR28 = 0x80+registerOffset BKP DR29 = 0x84+registerOffset BKP DR30 = 0x88+registerOffset BKP DR31 = 0x8C+registerOffset BKP DR32 = 0x90+registerOffset BKP DR33 = 0x94+registerOffset BKP DR34 = 0x98+registerOffset BKP DR35 = 0x9C+registerOffset BKP DR36 = 0xA0+registerOffset BKP DR37 = 0xA4+registerOffset BKP DR38 = 0xA8+registerOffset BKP DR39 = 0xAC+registerOffset BKP DR40 = 0xB0+registerOffset BKP DR41 = 0xB4+registerOffset BKP DR42 = 0xB8+registerOffset BKP RTCCR = 0x28+registerOffset BKP CR = 0x2C+registerOffset BKP CSR = 0x30+registerOffset IWDG KR = 0x0+registerOffset IWDG PR = 0x4+registerOffset IWDG RLR = 0x8+registerOffset IWDG SR = 0xC+registerOffset WWDG CR = 0x0+registerOffset WWDG CFR = 0x4+registerOffset WWDG SR = 0x8+registerOffset TIM1 CR1 = 0x0+registerOffset TIM1 CR2 = 0x4+registerOffset TIM1 SMCR = 0x8+registerOffset TIM1 DIER = 0xC+registerOffset TIM1 SR = 0x10+registerOffset TIM1 EGR = 0x14+registerOffset TIM1 CCMR1_Output = 0x18+registerOffset TIM1 CCMR1_Input = 0x18+registerOffset TIM1 CCMR2_Output = 0x1C+registerOffset TIM1 CCMR2_Input = 0x1C+registerOffset TIM1 CCER = 0x20+registerOffset TIM1 CNT = 0x24+registerOffset TIM1 PSC = 0x28+registerOffset TIM1 ARR = 0x2C+registerOffset TIM1 CCR1 = 0x34+registerOffset TIM1 CCR2 = 0x38+registerOffset TIM1 CCR3 = 0x3C+registerOffset TIM1 CCR4 = 0x40+registerOffset TIM1 DCR = 0x48+registerOffset TIM1 DMAR = 0x4C+registerOffset TIM1 RCR = 0x30+registerOffset TIM1 BDTR = 0x44+registerOffset TIM2 CR1 = 0x0+registerOffset TIM2 CR2 = 0x4+registerOffset TIM2 SMCR = 0x8+registerOffset TIM2 DIER = 0xC+registerOffset TIM2 SR = 0x10+registerOffset TIM2 EGR = 0x14+registerOffset TIM2 CCMR1_Output = 0x18+registerOffset TIM2 CCMR1_Input = 0x18+registerOffset TIM2 CCMR2_Output = 0x1C+registerOffset TIM2 CCMR2_Input = 0x1C+registerOffset TIM2 CCER = 0x20+registerOffset TIM2 CNT = 0x24+registerOffset TIM2 PSC = 0x28+registerOffset TIM2 ARR = 0x2C+registerOffset TIM2 CCR1 = 0x34+registerOffset TIM2 CCR2 = 0x38+registerOffset TIM2 CCR3 = 0x3C+registerOffset TIM2 CCR4 = 0x40+registerOffset TIM2 DCR = 0x48+registerOffset TIM2 DMAR = 0x4C+registerOffset TIM9 CR1 = 0x0+registerOffset TIM9 CR2 = 0x4+registerOffset TIM9 SMCR = 0x8+registerOffset TIM9 DIER = 0xC+registerOffset TIM9 SR = 0x10+registerOffset TIM9 EGR = 0x14+registerOffset TIM9 CCMR1_Output = 0x18+registerOffset TIM9 CCMR1_Input = 0x18+registerOffset TIM9 CCER = 0x20+registerOffset TIM9 CNT = 0x24+registerOffset TIM9 PSC = 0x28+registerOffset TIM9 ARR = 0x2C+registerOffset TIM9 CCR1 = 0x34+registerOffset TIM9 CCR2 = 0x38+registerOffset TIM10 CR1 = 0x0+registerOffset TIM10 CR2 = 0x4+registerOffset TIM10 DIER = 0xC+registerOffset TIM10 SR = 0x10+registerOffset TIM10 EGR = 0x14+registerOffset TIM10 CCMR1_Output = 0x18+registerOffset TIM10 CCMR1_Input = 0x18+registerOffset TIM10 CCER = 0x20+registerOffset TIM10 CNT = 0x24+registerOffset TIM10 PSC = 0x28+registerOffset TIM10 ARR = 0x2C+registerOffset TIM10 CCR1 = 0x34+registerOffset TIM6 CR1 = 0x0+registerOffset TIM6 CR2 = 0x4+registerOffset TIM6 DIER = 0xC+registerOffset TIM6 SR = 0x10+registerOffset TIM6 EGR = 0x14+registerOffset TIM6 CNT = 0x24+registerOffset TIM6 PSC = 0x28+registerOffset TIM6 ARR = 0x2C+registerOffset I2C1 CR1 = 0x0+registerOffset I2C1 CR2 = 0x4+registerOffset I2C1 OAR1 = 0x8+registerOffset I2C1 OAR2 = 0xC+registerOffset I2C1 DR = 0x10+registerOffset I2C1 SR1 = 0x14+registerOffset I2C1 SR2 = 0x18+registerOffset I2C1 CCR = 0x1C+registerOffset I2C1 TRISE = 0x20+registerOffset SPI1 CR1 = 0x0+registerOffset SPI1 CR2 = 0x4+registerOffset SPI1 SR = 0x8+registerOffset SPI1 DR = 0xC+registerOffset SPI1 CRCPR = 0x10+registerOffset SPI1 RXCRCR = 0x14+registerOffset SPI1 TXCRCR = 0x18+registerOffset SPI1 I2SCFGR = 0x1C+registerOffset SPI1 I2SPR = 0x20+registerOffset USART1 SR = 0x0+registerOffset USART1 DR = 0x4+registerOffset USART1 BRR = 0x8+registerOffset USART1 CR1 = 0xC+registerOffset USART1 CR2 = 0x10+registerOffset USART1 CR3 = 0x14+registerOffset USART1 GTPR = 0x18+registerOffset ADC1 SR = 0x0+registerOffset ADC1 CR1 = 0x4+registerOffset ADC1 CR2 = 0x8+registerOffset ADC1 SMPR1 = 0xC+registerOffset ADC1 SMPR2 = 0x10+registerOffset ADC1 JOFR1 = 0x14+registerOffset ADC1 JOFR2 = 0x18+registerOffset ADC1 JOFR3 = 0x1C+registerOffset ADC1 JOFR4 = 0x20+registerOffset ADC1 HTR = 0x24+registerOffset ADC1 LTR = 0x28+registerOffset ADC1 SQR1 = 0x2C+registerOffset ADC1 SQR2 = 0x30+registerOffset ADC1 SQR3 = 0x34+registerOffset ADC1 JSQR = 0x38+registerOffset ADC1 JDR1 = 0x3C+registerOffset ADC1 JDR2 = 0x40+registerOffset ADC1 JDR3 = 0x44+registerOffset ADC1 JDR4 = 0x48+registerOffset ADC1 DR = 0x4C+registerOffset ADC2 SR = 0x0+registerOffset ADC2 CR1 = 0x4+registerOffset ADC2 CR2 = 0x8+registerOffset ADC2 SMPR1 = 0xC+registerOffset ADC2 SMPR2 = 0x10+registerOffset ADC2 JOFR1 = 0x14+registerOffset ADC2 JOFR2 = 0x18+registerOffset ADC2 JOFR3 = 0x1C+registerOffset ADC2 JOFR4 = 0x20+registerOffset ADC2 HTR = 0x24+registerOffset ADC2 LTR = 0x28+registerOffset ADC2 SQR1 = 0x2C+registerOffset ADC2 SQR2 = 0x30+registerOffset ADC2 SQR3 = 0x34+registerOffset ADC2 JSQR = 0x38+registerOffset ADC2 JDR1 = 0x3C+registerOffset ADC2 JDR2 = 0x40+registerOffset ADC2 JDR3 = 0x44+registerOffset ADC2 JDR4 = 0x48+registerOffset ADC2 DR = 0x4C+registerOffset CAN CAN_MCR = 0x0+registerOffset CAN CAN_MSR = 0x4+registerOffset CAN CAN_TSR = 0x8+registerOffset CAN CAN_RF0R = 0xC+registerOffset CAN CAN_RF1R = 0x10+registerOffset CAN CAN_IER = 0x14+registerOffset CAN CAN_ESR = 0x18+registerOffset CAN CAN_BTR = 0x1C+registerOffset CAN CAN_TI0R = 0x180+registerOffset CAN CAN_TDT0R = 0x184+registerOffset CAN CAN_TDL0R = 0x188+registerOffset CAN CAN_TDH0R = 0x18C+registerOffset CAN CAN_TI1R = 0x190+registerOffset CAN CAN_TDT1R = 0x194+registerOffset CAN CAN_TDL1R = 0x198+registerOffset CAN CAN_TDH1R = 0x19C+registerOffset CAN CAN_TI2R = 0x1A0+registerOffset CAN CAN_TDT2R = 0x1A4+registerOffset CAN CAN_TDL2R = 0x1A8+registerOffset CAN CAN_TDH2R = 0x1AC+registerOffset CAN CAN_RI0R = 0x1B0+registerOffset CAN CAN_RDT0R = 0x1B4+registerOffset CAN CAN_RDL0R = 0x1B8+registerOffset CAN CAN_RDH0R = 0x1BC+registerOffset CAN CAN_RI1R = 0x1C0+registerOffset CAN CAN_RDT1R = 0x1C4+registerOffset CAN CAN_RDL1R = 0x1C8+registerOffset CAN CAN_RDH1R = 0x1CC+registerOffset CAN CAN_FMR = 0x200+registerOffset CAN CAN_FM1R = 0x204+registerOffset CAN CAN_FS1R = 0x20C+registerOffset CAN CAN_FFA1R = 0x214+registerOffset CAN CAN_FA1R = 0x21C+registerOffset CAN F0R1 = 0x240+registerOffset CAN F0R2 = 0x244+registerOffset CAN F1R1 = 0x248+registerOffset CAN F1R2 = 0x24C+registerOffset CAN F2R1 = 0x250+registerOffset CAN F2R2 = 0x254+registerOffset CAN F3R1 = 0x258+registerOffset CAN F3R2 = 0x25C+registerOffset CAN F4R1 = 0x260+registerOffset CAN F4R2 = 0x264+registerOffset CAN F5R1 = 0x268+registerOffset CAN F5R2 = 0x26C+registerOffset CAN F6R1 = 0x270+registerOffset CAN F6R2 = 0x274+registerOffset CAN F7R1 = 0x278+registerOffset CAN F7R2 = 0x27C+registerOffset CAN F8R1 = 0x280+registerOffset CAN F8R2 = 0x284+registerOffset CAN F9R1 = 0x288+registerOffset CAN F9R2 = 0x28C+registerOffset CAN F10R1 = 0x290+registerOffset CAN F10R2 = 0x294+registerOffset CAN F11R1 = 0x298+registerOffset CAN F11R2 = 0x29C+registerOffset CAN F12R1 = 0x2A0+registerOffset CAN F12R2 = 0x2A4+registerOffset CAN F13R1 = 0x2A8+registerOffset CAN F13R2 = 0x2AC+registerOffset DAC CR = 0x0+registerOffset DAC SWTRIGR = 0x4+registerOffset DAC DHR12R1 = 0x8+registerOffset DAC DHR12L1 = 0xC+registerOffset DAC DHR8R1 = 0x10+registerOffset DAC DHR12R2 = 0x14+registerOffset DAC DHR12L2 = 0x18+registerOffset DAC DHR8R2 = 0x1C+registerOffset DAC DHR12RD = 0x20+registerOffset DAC DHR12LD = 0x24+registerOffset DAC DHR8RD = 0x28+registerOffset DAC DOR1 = 0x2C+registerOffset DAC DOR2 = 0x30+registerOffset DBG IDCODE = 0x0+registerOffset DBG CR = 0x4+registerOffset UART4 SR = 0x0+registerOffset UART4 DR = 0x4+registerOffset UART4 BRR = 0x8+registerOffset UART4 CR1 = 0xC+registerOffset UART4 CR2 = 0x10+registerOffset UART4 CR3 = 0x14+registerOffset UART5 SR = 0x0+registerOffset UART5 DR = 0x4+registerOffset UART5 BRR = 0x8+registerOffset UART5 CR1 = 0xC+registerOffset UART5 CR2 = 0x10+registerOffset UART5 CR3 = 0x14+registerOffset CRC DR = 0x0+registerOffset CRC IDR = 0x4+registerOffset CRC CR = 0x8+registerOffset FLASH ACR = 0x0+registerOffset FLASH KEYR = 0x4+registerOffset FLASH OPTKEYR = 0x8+registerOffset FLASH SR = 0xC+registerOffset FLASH CR = 0x10+registerOffset FLASH AR = 0x14+registerOffset FLASH OBR = 0x1C+registerOffset FLASH WRPR = 0x20+registerOffset NVIC ICTR = 0x4+registerOffset NVIC STIR = 0xF00+registerOffset NVIC ISER0 = 0x100+registerOffset NVIC ISER1 = 0x104+registerOffset NVIC ICER0 = 0x180+registerOffset NVIC ICER1 = 0x184+registerOffset NVIC ISPR0 = 0x200+registerOffset NVIC ISPR1 = 0x204+registerOffset NVIC ICPR0 = 0x280+registerOffset NVIC ICPR1 = 0x284+registerOffset NVIC IABR0 = 0x300+registerOffset NVIC IABR1 = 0x304+registerOffset NVIC IPR0 = 0x400+registerOffset NVIC IPR1 = 0x404+registerOffset NVIC IPR2 = 0x408+registerOffset NVIC IPR3 = 0x40C+registerOffset NVIC IPR4 = 0x410+registerOffset NVIC IPR5 = 0x414+registerOffset NVIC IPR6 = 0x418+registerOffset NVIC IPR7 = 0x41C+registerOffset NVIC IPR8 = 0x420+registerOffset NVIC IPR9 = 0x424+registerOffset NVIC IPR10 = 0x428+registerOffset NVIC IPR11 = 0x42C+registerOffset NVIC IPR12 = 0x430+registerOffset NVIC IPR13 = 0x434+registerOffset NVIC IPR14 = 0x438+registerOffset USB EP0R = 0x0+registerOffset USB EP1R = 0x4+registerOffset USB EP2R = 0x8+registerOffset USB EP3R = 0xC+registerOffset USB EP4R = 0x10+registerOffset USB EP5R = 0x14+registerOffset USB EP6R = 0x18+registerOffset USB EP7R = 0x1C+registerOffset USB CNTR = 0x40+registerOffset USB ISTR = 0x44+registerOffset USB FNR = 0x48+registerOffset USB DADDR = 0x4C+registerOffset USB BTABLE = 0x50+--derived peripherals+registerOffset GPIOB reg = registerOffset GPIOA reg+registerOffset GPIOC reg = registerOffset GPIOA reg+registerOffset GPIOD reg = registerOffset GPIOA reg+registerOffset GPIOE reg = registerOffset GPIOA reg+registerOffset GPIOF reg = registerOffset GPIOA reg+registerOffset GPIOG reg = registerOffset GPIOA reg+registerOffset DMA2 reg = registerOffset DMA1 reg+registerOffset TIM8 reg = registerOffset TIM1 reg+registerOffset TIM3 reg = registerOffset TIM2 reg+registerOffset TIM4 reg = registerOffset TIM2 reg+registerOffset TIM5 reg = registerOffset TIM2 reg+registerOffset TIM12 reg = registerOffset TIM9 reg+registerOffset TIM11 reg = registerOffset TIM10 reg+registerOffset TIM13 reg = registerOffset TIM10 reg+registerOffset TIM14 reg = registerOffset TIM10 reg+registerOffset TIM7 reg = registerOffset TIM6 reg+registerOffset I2C2 reg = registerOffset I2C1 reg+registerOffset SPI2 reg = registerOffset SPI1 reg+registerOffset SPI3 reg = registerOffset SPI1 reg+registerOffset USART2 reg = registerOffset USART1 reg+registerOffset USART3 reg = registerOffset USART1 reg+registerOffset ADC3 reg = registerOffset ADC2 reg+--catch all+registerOffset p r = error $ show ("undefined registerOffset",p ,r)++fieldToRegister :: Field -> Register+fieldToRegister ACR_HLFCYA = ACR+fieldToRegister ACR_LATENCY = ACR+fieldToRegister ACR_PRFTBE = ACR+fieldToRegister ACR_PRFTBS = ACR+fieldToRegister AHBENR_CRCEN = AHBENR+fieldToRegister AHBENR_DMA1EN = AHBENR+fieldToRegister AHBENR_DMA2EN = AHBENR+fieldToRegister AHBENR_FLITFEN = AHBENR+fieldToRegister AHBENR_FSMCEN = AHBENR+fieldToRegister AHBENR_SDIOEN = AHBENR+fieldToRegister AHBENR_SRAMEN = AHBENR+fieldToRegister ALRH_ALRH = ALRH+fieldToRegister ALRL_ALRL = ALRL+fieldToRegister APB1ENR_BKPEN = APB1ENR+fieldToRegister APB1ENR_CANEN = APB1ENR+fieldToRegister APB1ENR_DACEN = APB1ENR+fieldToRegister APB1ENR_I2C1EN = APB1ENR+fieldToRegister APB1ENR_I2C2EN = APB1ENR+fieldToRegister APB1ENR_PWREN = APB1ENR+fieldToRegister APB1ENR_SPI2EN = APB1ENR+fieldToRegister APB1ENR_SPI3EN = APB1ENR+fieldToRegister APB1ENR_TIM12EN = APB1ENR+fieldToRegister APB1ENR_TIM13EN = APB1ENR+fieldToRegister APB1ENR_TIM14EN = APB1ENR+fieldToRegister APB1ENR_TIM2EN = APB1ENR+fieldToRegister APB1ENR_TIM3EN = APB1ENR+fieldToRegister APB1ENR_TIM4EN = APB1ENR+fieldToRegister APB1ENR_TIM5EN = APB1ENR+fieldToRegister APB1ENR_TIM6EN = APB1ENR+fieldToRegister APB1ENR_TIM7EN = APB1ENR+fieldToRegister APB1ENR_UART4EN = APB1ENR+fieldToRegister APB1ENR_UART5EN = APB1ENR+fieldToRegister APB1ENR_USART2EN = APB1ENR+fieldToRegister APB1ENR_USART3EN = APB1ENR+fieldToRegister APB1ENR_USBEN = APB1ENR+fieldToRegister APB1ENR_WWDGEN = APB1ENR+fieldToRegister APB1RSTR_BKPRST = APB1RSTR+fieldToRegister APB1RSTR_CANRST = APB1RSTR+fieldToRegister APB1RSTR_DACRST = APB1RSTR+fieldToRegister APB1RSTR_I2C1RST = APB1RSTR+fieldToRegister APB1RSTR_I2C2RST = APB1RSTR+fieldToRegister APB1RSTR_PWRRST = APB1RSTR+fieldToRegister APB1RSTR_SPI2RST = APB1RSTR+fieldToRegister APB1RSTR_SPI3RST = APB1RSTR+fieldToRegister APB1RSTR_TIM12RST = APB1RSTR+fieldToRegister APB1RSTR_TIM13RST = APB1RSTR+fieldToRegister APB1RSTR_TIM14RST = APB1RSTR+fieldToRegister APB1RSTR_TIM2RST = APB1RSTR+fieldToRegister APB1RSTR_TIM3RST = APB1RSTR+fieldToRegister APB1RSTR_TIM4RST = APB1RSTR+fieldToRegister APB1RSTR_TIM5RST = APB1RSTR+fieldToRegister APB1RSTR_TIM6RST = APB1RSTR+fieldToRegister APB1RSTR_TIM7RST = APB1RSTR+fieldToRegister APB1RSTR_UART4RST = APB1RSTR+fieldToRegister APB1RSTR_UART5RST = APB1RSTR+fieldToRegister APB1RSTR_USART2RST = APB1RSTR+fieldToRegister APB1RSTR_USART3RST = APB1RSTR+fieldToRegister APB1RSTR_USBRST = APB1RSTR+fieldToRegister APB1RSTR_WWDGRST = APB1RSTR+fieldToRegister APB2ENR_ADC1EN = APB2ENR+fieldToRegister APB2ENR_ADC2EN = APB2ENR+fieldToRegister APB2ENR_ADC3EN = APB2ENR+fieldToRegister APB2ENR_AFIOEN = APB2ENR+fieldToRegister APB2ENR_IOPAEN = APB2ENR+fieldToRegister APB2ENR_IOPBEN = APB2ENR+fieldToRegister APB2ENR_IOPCEN = APB2ENR+fieldToRegister APB2ENR_IOPDEN = APB2ENR+fieldToRegister APB2ENR_IOPEEN = APB2ENR+fieldToRegister APB2ENR_IOPFEN = APB2ENR+fieldToRegister APB2ENR_IOPGEN = APB2ENR+fieldToRegister APB2ENR_SPI1EN = APB2ENR+fieldToRegister APB2ENR_TIM10EN = APB2ENR+fieldToRegister APB2ENR_TIM11EN = APB2ENR+fieldToRegister APB2ENR_TIM1EN = APB2ENR+fieldToRegister APB2ENR_TIM8EN = APB2ENR+fieldToRegister APB2ENR_TIM9EN = APB2ENR+fieldToRegister APB2ENR_USART1EN = APB2ENR+fieldToRegister APB2RSTR_ADC1RST = APB2RSTR+fieldToRegister APB2RSTR_ADC2RST = APB2RSTR+fieldToRegister APB2RSTR_ADC3RST = APB2RSTR+fieldToRegister APB2RSTR_AFIORST = APB2RSTR+fieldToRegister APB2RSTR_IOPARST = APB2RSTR+fieldToRegister APB2RSTR_IOPBRST = APB2RSTR+fieldToRegister APB2RSTR_IOPCRST = APB2RSTR+fieldToRegister APB2RSTR_IOPDRST = APB2RSTR+fieldToRegister APB2RSTR_IOPERST = APB2RSTR+fieldToRegister APB2RSTR_IOPFRST = APB2RSTR+fieldToRegister APB2RSTR_IOPGRST = APB2RSTR+fieldToRegister APB2RSTR_SPI1RST = APB2RSTR+fieldToRegister APB2RSTR_TIM10RST = APB2RSTR+fieldToRegister APB2RSTR_TIM11RST = APB2RSTR+fieldToRegister APB2RSTR_TIM1RST = APB2RSTR+fieldToRegister APB2RSTR_TIM8RST = APB2RSTR+fieldToRegister APB2RSTR_TIM9RST = APB2RSTR+fieldToRegister APB2RSTR_USART1RST = APB2RSTR+fieldToRegister AR_FAR = AR+fieldToRegister ARG_CMDARG = ARG+fieldToRegister ARR_ARR = ARR+fieldToRegister BCR1_ASYNCWAIT = BCR1+fieldToRegister BCR1_BURSTEN = BCR1+fieldToRegister BCR1_CBURSTRW = BCR1+fieldToRegister BCR1_EXTMOD = BCR1+fieldToRegister BCR1_FACCEN = BCR1+fieldToRegister BCR1_MBKEN = BCR1+fieldToRegister BCR1_MTYP = BCR1+fieldToRegister BCR1_MUXEN = BCR1+fieldToRegister BCR1_MWID = BCR1+fieldToRegister BCR1_WAITCFG = BCR1+fieldToRegister BCR1_WAITEN = BCR1+fieldToRegister BCR1_WAITPOL = BCR1+fieldToRegister BCR1_WREN = BCR1+fieldToRegister BCR2_ASYNCWAIT = BCR2+fieldToRegister BCR2_BURSTEN = BCR2+fieldToRegister BCR2_CBURSTRW = BCR2+fieldToRegister BCR2_EXTMOD = BCR2+fieldToRegister BCR2_FACCEN = BCR2+fieldToRegister BCR2_MBKEN = BCR2+fieldToRegister BCR2_MTYP = BCR2+fieldToRegister BCR2_MUXEN = BCR2+fieldToRegister BCR2_MWID = BCR2+fieldToRegister BCR2_WAITCFG = BCR2+fieldToRegister BCR2_WAITEN = BCR2+fieldToRegister BCR2_WAITPOL = BCR2+fieldToRegister BCR2_WRAPMOD = BCR2+fieldToRegister BCR2_WREN = BCR2+fieldToRegister BCR3_ASYNCWAIT = BCR3+fieldToRegister BCR3_BURSTEN = BCR3+fieldToRegister BCR3_CBURSTRW = BCR3+fieldToRegister BCR3_EXTMOD = BCR3+fieldToRegister BCR3_FACCEN = BCR3+fieldToRegister BCR3_MBKEN = BCR3+fieldToRegister BCR3_MTYP = BCR3+fieldToRegister BCR3_MUXEN = BCR3+fieldToRegister BCR3_MWID = BCR3+fieldToRegister BCR3_WAITCFG = BCR3+fieldToRegister BCR3_WAITEN = BCR3+fieldToRegister BCR3_WAITPOL = BCR3+fieldToRegister BCR3_WRAPMOD = BCR3+fieldToRegister BCR3_WREN = BCR3+fieldToRegister BCR4_ASYNCWAIT = BCR4+fieldToRegister BCR4_BURSTEN = BCR4+fieldToRegister BCR4_CBURSTRW = BCR4+fieldToRegister BCR4_EXTMOD = BCR4+fieldToRegister BCR4_FACCEN = BCR4+fieldToRegister BCR4_MBKEN = BCR4+fieldToRegister BCR4_MTYP = BCR4+fieldToRegister BCR4_MUXEN = BCR4+fieldToRegister BCR4_MWID = BCR4+fieldToRegister BCR4_WAITCFG = BCR4+fieldToRegister BCR4_WAITEN = BCR4+fieldToRegister BCR4_WAITPOL = BCR4+fieldToRegister BCR4_WRAPMOD = BCR4+fieldToRegister BCR4_WREN = BCR4+fieldToRegister BDCR_BDRST = BDCR+fieldToRegister BDCR_LSEBYP = BDCR+fieldToRegister BDCR_LSEON = BDCR+fieldToRegister BDCR_LSERDY = BDCR+fieldToRegister BDCR_RTCEN = BDCR+fieldToRegister BDCR_RTCSEL = BDCR+fieldToRegister BDTR_AOE = BDTR+fieldToRegister BDTR_BKE = BDTR+fieldToRegister BDTR_BKP = BDTR+fieldToRegister BDTR_DTG = BDTR+fieldToRegister BDTR_LOCK = BDTR+fieldToRegister BDTR_MOE = BDTR+fieldToRegister BDTR_OSSI = BDTR+fieldToRegister BDTR_OSSR = BDTR+fieldToRegister BRR_BR0 = BRR+fieldToRegister BRR_BR1 = BRR+fieldToRegister BRR_BR10 = BRR+fieldToRegister BRR_BR11 = BRR+fieldToRegister BRR_BR12 = BRR+fieldToRegister BRR_BR13 = BRR+fieldToRegister BRR_BR14 = BRR+fieldToRegister BRR_BR15 = BRR+fieldToRegister BRR_BR2 = BRR+fieldToRegister BRR_BR3 = BRR+fieldToRegister BRR_BR4 = BRR+fieldToRegister BRR_BR5 = BRR+fieldToRegister BRR_BR6 = BRR+fieldToRegister BRR_BR7 = BRR+fieldToRegister BRR_BR8 = BRR+fieldToRegister BRR_BR9 = BRR+fieldToRegister BRR_DIV_Fraction = BRR+fieldToRegister BRR_DIV_Mantissa = BRR+fieldToRegister BSRR_BR0 = BSRR+fieldToRegister BSRR_BR1 = BSRR+fieldToRegister BSRR_BR10 = BSRR+fieldToRegister BSRR_BR11 = BSRR+fieldToRegister BSRR_BR12 = BSRR+fieldToRegister BSRR_BR13 = BSRR+fieldToRegister BSRR_BR14 = BSRR+fieldToRegister BSRR_BR15 = BSRR+fieldToRegister BSRR_BR2 = BSRR+fieldToRegister BSRR_BR3 = BSRR+fieldToRegister BSRR_BR4 = BSRR+fieldToRegister BSRR_BR5 = BSRR+fieldToRegister BSRR_BR6 = BSRR+fieldToRegister BSRR_BR7 = BSRR+fieldToRegister BSRR_BR8 = BSRR+fieldToRegister BSRR_BR9 = BSRR+fieldToRegister BSRR_BS0 = BSRR+fieldToRegister BSRR_BS1 = BSRR+fieldToRegister BSRR_BS10 = BSRR+fieldToRegister BSRR_BS11 = BSRR+fieldToRegister BSRR_BS12 = BSRR+fieldToRegister BSRR_BS13 = BSRR+fieldToRegister BSRR_BS14 = BSRR+fieldToRegister BSRR_BS15 = BSRR+fieldToRegister BSRR_BS2 = BSRR+fieldToRegister BSRR_BS3 = BSRR+fieldToRegister BSRR_BS4 = BSRR+fieldToRegister BSRR_BS5 = BSRR+fieldToRegister BSRR_BS6 = BSRR+fieldToRegister BSRR_BS7 = BSRR+fieldToRegister BSRR_BS8 = BSRR+fieldToRegister BSRR_BS9 = BSRR+fieldToRegister BTABLE_BTABLE = BTABLE+fieldToRegister BTR1_ACCMOD = BTR1+fieldToRegister BTR1_ADDHLD = BTR1+fieldToRegister BTR1_ADDSET = BTR1+fieldToRegister BTR1_BUSTURN = BTR1+fieldToRegister BTR1_CLKDIV = BTR1+fieldToRegister BTR1_DATAST = BTR1+fieldToRegister BTR1_DATLAT = BTR1+fieldToRegister BTR2_ACCMOD = BTR2+fieldToRegister BTR2_ADDHLD = BTR2+fieldToRegister BTR2_ADDSET = BTR2+fieldToRegister BTR2_BUSTURN = BTR2+fieldToRegister BTR2_CLKDIV = BTR2+fieldToRegister BTR2_DATAST = BTR2+fieldToRegister BTR2_DATLAT = BTR2+fieldToRegister BTR3_ACCMOD = BTR3+fieldToRegister BTR3_ADDHLD = BTR3+fieldToRegister BTR3_ADDSET = BTR3+fieldToRegister BTR3_BUSTURN = BTR3+fieldToRegister BTR3_CLKDIV = BTR3+fieldToRegister BTR3_DATAST = BTR3+fieldToRegister BTR3_DATLAT = BTR3+fieldToRegister BTR4_ACCMOD = BTR4+fieldToRegister BTR4_ADDHLD = BTR4+fieldToRegister BTR4_ADDSET = BTR4+fieldToRegister BTR4_BUSTURN = BTR4+fieldToRegister BTR4_CLKDIV = BTR4+fieldToRegister BTR4_DATAST = BTR4+fieldToRegister BTR4_DATLAT = BTR4+fieldToRegister BWTR1_ACCMOD = BWTR1+fieldToRegister BWTR1_ADDHLD = BWTR1+fieldToRegister BWTR1_ADDSET = BWTR1+fieldToRegister BWTR1_CLKDIV = BWTR1+fieldToRegister BWTR1_DATAST = BWTR1+fieldToRegister BWTR1_DATLAT = BWTR1+fieldToRegister BWTR2_ACCMOD = BWTR2+fieldToRegister BWTR2_ADDHLD = BWTR2+fieldToRegister BWTR2_ADDSET = BWTR2+fieldToRegister BWTR2_CLKDIV = BWTR2+fieldToRegister BWTR2_DATAST = BWTR2+fieldToRegister BWTR2_DATLAT = BWTR2+fieldToRegister BWTR3_ACCMOD = BWTR3+fieldToRegister BWTR3_ADDHLD = BWTR3+fieldToRegister BWTR3_ADDSET = BWTR3+fieldToRegister BWTR3_CLKDIV = BWTR3+fieldToRegister BWTR3_DATAST = BWTR3+fieldToRegister BWTR3_DATLAT = BWTR3+fieldToRegister BWTR4_ACCMOD = BWTR4+fieldToRegister BWTR4_ADDHLD = BWTR4+fieldToRegister BWTR4_ADDSET = BWTR4+fieldToRegister BWTR4_CLKDIV = BWTR4+fieldToRegister BWTR4_DATAST = BWTR4+fieldToRegister BWTR4_DATLAT = BWTR4+fieldToRegister CAN_BTR_BRP = CAN_BTR+fieldToRegister CAN_BTR_LBKM = CAN_BTR+fieldToRegister CAN_BTR_SILM = CAN_BTR+fieldToRegister CAN_BTR_SJW = CAN_BTR+fieldToRegister CAN_BTR_TS1 = CAN_BTR+fieldToRegister CAN_BTR_TS2 = CAN_BTR+fieldToRegister CAN_ESR_BOFF = CAN_ESR+fieldToRegister CAN_ESR_EPVF = CAN_ESR+fieldToRegister CAN_ESR_EWGF = CAN_ESR+fieldToRegister CAN_ESR_LEC = CAN_ESR+fieldToRegister CAN_ESR_REC = CAN_ESR+fieldToRegister CAN_ESR_TEC = CAN_ESR+fieldToRegister CAN_FA1R_FACT0 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT1 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT10 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT11 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT12 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT13 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT2 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT3 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT4 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT5 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT6 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT7 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT8 = CAN_FA1R+fieldToRegister CAN_FA1R_FACT9 = CAN_FA1R+fieldToRegister CAN_FFA1R_FFA0 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA1 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA10 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA11 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA12 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA13 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA2 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA3 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA4 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA5 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA6 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA7 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA8 = CAN_FFA1R+fieldToRegister CAN_FFA1R_FFA9 = CAN_FFA1R+fieldToRegister CAN_FM1R_FBM0 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM1 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM10 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM11 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM12 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM13 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM2 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM3 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM4 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM5 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM6 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM7 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM8 = CAN_FM1R+fieldToRegister CAN_FM1R_FBM9 = CAN_FM1R+fieldToRegister CAN_FMR_FINIT = CAN_FMR+fieldToRegister CAN_FS1R_FSC0 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC1 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC10 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC11 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC12 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC13 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC2 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC3 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC4 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC5 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC6 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC7 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC8 = CAN_FS1R+fieldToRegister CAN_FS1R_FSC9 = CAN_FS1R+fieldToRegister CAN_IER_BOFIE = CAN_IER+fieldToRegister CAN_IER_EPVIE = CAN_IER+fieldToRegister CAN_IER_ERRIE = CAN_IER+fieldToRegister CAN_IER_EWGIE = CAN_IER+fieldToRegister CAN_IER_FFIE0 = CAN_IER+fieldToRegister CAN_IER_FFIE1 = CAN_IER+fieldToRegister CAN_IER_FMPIE0 = CAN_IER+fieldToRegister CAN_IER_FMPIE1 = CAN_IER+fieldToRegister CAN_IER_FOVIE0 = CAN_IER+fieldToRegister CAN_IER_FOVIE1 = CAN_IER+fieldToRegister CAN_IER_LECIE = CAN_IER+fieldToRegister CAN_IER_SLKIE = CAN_IER+fieldToRegister CAN_IER_TMEIE = CAN_IER+fieldToRegister CAN_IER_WKUIE = CAN_IER+fieldToRegister CAN_MCR_ABOM = CAN_MCR+fieldToRegister CAN_MCR_AWUM = CAN_MCR+fieldToRegister CAN_MCR_DBF = CAN_MCR+fieldToRegister CAN_MCR_INRQ = CAN_MCR+fieldToRegister CAN_MCR_NART = CAN_MCR+fieldToRegister CAN_MCR_RESET = CAN_MCR+fieldToRegister CAN_MCR_RFLM = CAN_MCR+fieldToRegister CAN_MCR_SLEEP = CAN_MCR+fieldToRegister CAN_MCR_TTCM = CAN_MCR+fieldToRegister CAN_MCR_TXFP = CAN_MCR+fieldToRegister CAN_MSR_ERRI = CAN_MSR+fieldToRegister CAN_MSR_INAK = CAN_MSR+fieldToRegister CAN_MSR_RX = CAN_MSR+fieldToRegister CAN_MSR_RXM = CAN_MSR+fieldToRegister CAN_MSR_SAMP = CAN_MSR+fieldToRegister CAN_MSR_SLAK = CAN_MSR+fieldToRegister CAN_MSR_SLAKI = CAN_MSR+fieldToRegister CAN_MSR_TXM = CAN_MSR+fieldToRegister CAN_MSR_WKUI = CAN_MSR+fieldToRegister CAN_RDH0R_DATA4 = CAN_RDH0R+fieldToRegister CAN_RDH0R_DATA5 = CAN_RDH0R+fieldToRegister CAN_RDH0R_DATA6 = CAN_RDH0R+fieldToRegister CAN_RDH0R_DATA7 = CAN_RDH0R+fieldToRegister CAN_RDH1R_DATA4 = CAN_RDH1R+fieldToRegister CAN_RDH1R_DATA5 = CAN_RDH1R+fieldToRegister CAN_RDH1R_DATA6 = CAN_RDH1R+fieldToRegister CAN_RDH1R_DATA7 = CAN_RDH1R+fieldToRegister CAN_RDL0R_DATA0 = CAN_RDL0R+fieldToRegister CAN_RDL0R_DATA1 = CAN_RDL0R+fieldToRegister CAN_RDL0R_DATA2 = CAN_RDL0R+fieldToRegister CAN_RDL0R_DATA3 = CAN_RDL0R+fieldToRegister CAN_RDL1R_DATA0 = CAN_RDL1R+fieldToRegister CAN_RDL1R_DATA1 = CAN_RDL1R+fieldToRegister CAN_RDL1R_DATA2 = CAN_RDL1R+fieldToRegister CAN_RDL1R_DATA3 = CAN_RDL1R+fieldToRegister CAN_RDT0R_DLC = CAN_RDT0R+fieldToRegister CAN_RDT0R_FMI = CAN_RDT0R+fieldToRegister CAN_RDT0R_TIME = CAN_RDT0R+fieldToRegister CAN_RDT1R_DLC = CAN_RDT1R+fieldToRegister CAN_RDT1R_FMI = CAN_RDT1R+fieldToRegister CAN_RDT1R_TIME = CAN_RDT1R+fieldToRegister CAN_RF0R_FMP0 = CAN_RF0R+fieldToRegister CAN_RF0R_FOVR0 = CAN_RF0R+fieldToRegister CAN_RF0R_FULL0 = CAN_RF0R+fieldToRegister CAN_RF0R_RFOM0 = CAN_RF0R+fieldToRegister CAN_RF1R_FMP1 = CAN_RF1R+fieldToRegister CAN_RF1R_FOVR1 = CAN_RF1R+fieldToRegister CAN_RF1R_FULL1 = CAN_RF1R+fieldToRegister CAN_RF1R_RFOM1 = CAN_RF1R+fieldToRegister CAN_RI0R_EXID = CAN_RI0R+fieldToRegister CAN_RI0R_IDE = CAN_RI0R+fieldToRegister CAN_RI0R_RTR = CAN_RI0R+fieldToRegister CAN_RI0R_STID = CAN_RI0R+fieldToRegister CAN_RI1R_EXID = CAN_RI1R+fieldToRegister CAN_RI1R_IDE = CAN_RI1R+fieldToRegister CAN_RI1R_RTR = CAN_RI1R+fieldToRegister CAN_RI1R_STID = CAN_RI1R+fieldToRegister CAN_TDH0R_DATA4 = CAN_TDH0R+fieldToRegister CAN_TDH0R_DATA5 = CAN_TDH0R+fieldToRegister CAN_TDH0R_DATA6 = CAN_TDH0R+fieldToRegister CAN_TDH0R_DATA7 = CAN_TDH0R+fieldToRegister CAN_TDH1R_DATA4 = CAN_TDH1R+fieldToRegister CAN_TDH1R_DATA5 = CAN_TDH1R+fieldToRegister CAN_TDH1R_DATA6 = CAN_TDH1R+fieldToRegister CAN_TDH1R_DATA7 = CAN_TDH1R+fieldToRegister CAN_TDH2R_DATA4 = CAN_TDH2R+fieldToRegister CAN_TDH2R_DATA5 = CAN_TDH2R+fieldToRegister CAN_TDH2R_DATA6 = CAN_TDH2R+fieldToRegister CAN_TDH2R_DATA7 = CAN_TDH2R+fieldToRegister CAN_TDL0R_DATA0 = CAN_TDL0R+fieldToRegister CAN_TDL0R_DATA1 = CAN_TDL0R+fieldToRegister CAN_TDL0R_DATA2 = CAN_TDL0R+fieldToRegister CAN_TDL0R_DATA3 = CAN_TDL0R+fieldToRegister CAN_TDL1R_DATA0 = CAN_TDL1R+fieldToRegister CAN_TDL1R_DATA1 = CAN_TDL1R+fieldToRegister CAN_TDL1R_DATA2 = CAN_TDL1R+fieldToRegister CAN_TDL1R_DATA3 = CAN_TDL1R+fieldToRegister CAN_TDL2R_DATA0 = CAN_TDL2R+fieldToRegister CAN_TDL2R_DATA1 = CAN_TDL2R+fieldToRegister CAN_TDL2R_DATA2 = CAN_TDL2R+fieldToRegister CAN_TDL2R_DATA3 = CAN_TDL2R+fieldToRegister CAN_TDT0R_DLC = CAN_TDT0R+fieldToRegister CAN_TDT0R_TGT = CAN_TDT0R+fieldToRegister CAN_TDT0R_TIME = CAN_TDT0R+fieldToRegister CAN_TDT1R_DLC = CAN_TDT1R+fieldToRegister CAN_TDT1R_TGT = CAN_TDT1R+fieldToRegister CAN_TDT1R_TIME = CAN_TDT1R+fieldToRegister CAN_TDT2R_DLC = CAN_TDT2R+fieldToRegister CAN_TDT2R_TGT = CAN_TDT2R+fieldToRegister CAN_TDT2R_TIME = CAN_TDT2R+fieldToRegister CAN_TI0R_EXID = CAN_TI0R+fieldToRegister CAN_TI0R_IDE = CAN_TI0R+fieldToRegister CAN_TI0R_RTR = CAN_TI0R+fieldToRegister CAN_TI0R_STID = CAN_TI0R+fieldToRegister CAN_TI0R_TXRQ = CAN_TI0R+fieldToRegister CAN_TI1R_EXID = CAN_TI1R+fieldToRegister CAN_TI1R_IDE = CAN_TI1R+fieldToRegister CAN_TI1R_RTR = CAN_TI1R+fieldToRegister CAN_TI1R_STID = CAN_TI1R+fieldToRegister CAN_TI1R_TXRQ = CAN_TI1R+fieldToRegister CAN_TI2R_EXID = CAN_TI2R+fieldToRegister CAN_TI2R_IDE = CAN_TI2R+fieldToRegister CAN_TI2R_RTR = CAN_TI2R+fieldToRegister CAN_TI2R_STID = CAN_TI2R+fieldToRegister CAN_TI2R_TXRQ = CAN_TI2R+fieldToRegister CAN_TSR_ABRQ0 = CAN_TSR+fieldToRegister CAN_TSR_ABRQ1 = CAN_TSR+fieldToRegister CAN_TSR_ABRQ2 = CAN_TSR+fieldToRegister CAN_TSR_ALST0 = CAN_TSR+fieldToRegister CAN_TSR_ALST1 = CAN_TSR+fieldToRegister CAN_TSR_ALST2 = CAN_TSR+fieldToRegister CAN_TSR_CODE = CAN_TSR+fieldToRegister CAN_TSR_LOW0 = CAN_TSR+fieldToRegister CAN_TSR_LOW1 = CAN_TSR+fieldToRegister CAN_TSR_LOW2 = CAN_TSR+fieldToRegister CAN_TSR_RQCP0 = CAN_TSR+fieldToRegister CAN_TSR_RQCP1 = CAN_TSR+fieldToRegister CAN_TSR_RQCP2 = CAN_TSR+fieldToRegister CAN_TSR_TERR0 = CAN_TSR+fieldToRegister CAN_TSR_TERR1 = CAN_TSR+fieldToRegister CAN_TSR_TERR2 = CAN_TSR+fieldToRegister CAN_TSR_TME0 = CAN_TSR+fieldToRegister CAN_TSR_TME1 = CAN_TSR+fieldToRegister CAN_TSR_TME2 = CAN_TSR+fieldToRegister CAN_TSR_TXOK0 = CAN_TSR+fieldToRegister CAN_TSR_TXOK1 = CAN_TSR+fieldToRegister CAN_TSR_TXOK2 = CAN_TSR+fieldToRegister CCER_CC1E = CCER+fieldToRegister CCER_CC1NE = CCER+fieldToRegister CCER_CC1NP = CCER+fieldToRegister CCER_CC1P = CCER+fieldToRegister CCER_CC2E = CCER+fieldToRegister CCER_CC2NE = CCER+fieldToRegister CCER_CC2NP = CCER+fieldToRegister CCER_CC2P = CCER+fieldToRegister CCER_CC3E = CCER+fieldToRegister CCER_CC3NE = CCER+fieldToRegister CCER_CC3NP = CCER+fieldToRegister CCER_CC3P = CCER+fieldToRegister CCER_CC4E = CCER+fieldToRegister CCER_CC4P = CCER+fieldToRegister CCMR1_Input_CC1S = CCMR1_Input+fieldToRegister CCMR1_Input_CC2S = CCMR1_Input+fieldToRegister CCMR1_Input_IC1F = CCMR1_Input+fieldToRegister CCMR1_Input_IC1PSC = CCMR1_Input+fieldToRegister CCMR1_Input_IC2F = CCMR1_Input+fieldToRegister CCMR1_Input_IC2PCS = CCMR1_Input+fieldToRegister CCMR1_Input_IC2PSC = CCMR1_Input+fieldToRegister CCMR1_Input_ICPCS = CCMR1_Input+fieldToRegister CCMR1_Output_CC1S = CCMR1_Output+fieldToRegister CCMR1_Output_CC2S = CCMR1_Output+fieldToRegister CCMR1_Output_OC1CE = CCMR1_Output+fieldToRegister CCMR1_Output_OC1FE = CCMR1_Output+fieldToRegister CCMR1_Output_OC1M = CCMR1_Output+fieldToRegister CCMR1_Output_OC1PE = CCMR1_Output+fieldToRegister CCMR1_Output_OC2CE = CCMR1_Output+fieldToRegister CCMR1_Output_OC2FE = CCMR1_Output+fieldToRegister CCMR1_Output_OC2M = CCMR1_Output+fieldToRegister CCMR1_Output_OC2PE = CCMR1_Output+fieldToRegister CCMR2_Input_CC3S = CCMR2_Input+fieldToRegister CCMR2_Input_CC4S = CCMR2_Input+fieldToRegister CCMR2_Input_IC3F = CCMR2_Input+fieldToRegister CCMR2_Input_IC3PSC = CCMR2_Input+fieldToRegister CCMR2_Input_IC4F = CCMR2_Input+fieldToRegister CCMR2_Input_IC4PSC = CCMR2_Input+fieldToRegister CCMR2_Output_CC3S = CCMR2_Output+fieldToRegister CCMR2_Output_CC4S = CCMR2_Output+fieldToRegister CCMR2_Output_O24CE = CCMR2_Output+fieldToRegister CCMR2_Output_OC3CE = CCMR2_Output+fieldToRegister CCMR2_Output_OC3FE = CCMR2_Output+fieldToRegister CCMR2_Output_OC3M = CCMR2_Output+fieldToRegister CCMR2_Output_OC3PE = CCMR2_Output+fieldToRegister CCMR2_Output_OC4CE = CCMR2_Output+fieldToRegister CCMR2_Output_OC4FE = CCMR2_Output+fieldToRegister CCMR2_Output_OC4M = CCMR2_Output+fieldToRegister CCMR2_Output_OC4PE = CCMR2_Output+fieldToRegister CCR_CCR = CCR+fieldToRegister CCR_DUTY = CCR+fieldToRegister CCR_F_S = CCR+fieldToRegister CCR1_CCR1 = CCR1+fieldToRegister CCR1_CIRC = CCR1+fieldToRegister CCR1_DIR = CCR1+fieldToRegister CCR1_EN = CCR1+fieldToRegister CCR1_HTIE = CCR1+fieldToRegister CCR1_MEM2MEM = CCR1+fieldToRegister CCR1_MINC = CCR1+fieldToRegister CCR1_MSIZE = CCR1+fieldToRegister CCR1_PINC = CCR1+fieldToRegister CCR1_PL = CCR1+fieldToRegister CCR1_PSIZE = CCR1+fieldToRegister CCR1_TCIE = CCR1+fieldToRegister CCR1_TEIE = CCR1+fieldToRegister CCR2_CCR2 = CCR2+fieldToRegister CCR2_CIRC = CCR2+fieldToRegister CCR2_DIR = CCR2+fieldToRegister CCR2_EN = CCR2+fieldToRegister CCR2_HTIE = CCR2+fieldToRegister CCR2_MEM2MEM = CCR2+fieldToRegister CCR2_MINC = CCR2+fieldToRegister CCR2_MSIZE = CCR2+fieldToRegister CCR2_PINC = CCR2+fieldToRegister CCR2_PL = CCR2+fieldToRegister CCR2_PSIZE = CCR2+fieldToRegister CCR2_TCIE = CCR2+fieldToRegister CCR2_TEIE = CCR2+fieldToRegister CCR3_CCR3 = CCR3+fieldToRegister CCR3_CIRC = CCR3+fieldToRegister CCR3_DIR = CCR3+fieldToRegister CCR3_EN = CCR3+fieldToRegister CCR3_HTIE = CCR3+fieldToRegister CCR3_MEM2MEM = CCR3+fieldToRegister CCR3_MINC = CCR3+fieldToRegister CCR3_MSIZE = CCR3+fieldToRegister CCR3_PINC = CCR3+fieldToRegister CCR3_PL = CCR3+fieldToRegister CCR3_PSIZE = CCR3+fieldToRegister CCR3_TCIE = CCR3+fieldToRegister CCR3_TEIE = CCR3+fieldToRegister CCR4_CCR4 = CCR4+fieldToRegister CCR4_CIRC = CCR4+fieldToRegister CCR4_DIR = CCR4+fieldToRegister CCR4_EN = CCR4+fieldToRegister CCR4_HTIE = CCR4+fieldToRegister CCR4_MEM2MEM = CCR4+fieldToRegister CCR4_MINC = CCR4+fieldToRegister CCR4_MSIZE = CCR4+fieldToRegister CCR4_PINC = CCR4+fieldToRegister CCR4_PL = CCR4+fieldToRegister CCR4_PSIZE = CCR4+fieldToRegister CCR4_TCIE = CCR4+fieldToRegister CCR4_TEIE = CCR4+fieldToRegister CCR5_CIRC = CCR5+fieldToRegister CCR5_DIR = CCR5+fieldToRegister CCR5_EN = CCR5+fieldToRegister CCR5_HTIE = CCR5+fieldToRegister CCR5_MEM2MEM = CCR5+fieldToRegister CCR5_MINC = CCR5+fieldToRegister CCR5_MSIZE = CCR5+fieldToRegister CCR5_PINC = CCR5+fieldToRegister CCR5_PL = CCR5+fieldToRegister CCR5_PSIZE = CCR5+fieldToRegister CCR5_TCIE = CCR5+fieldToRegister CCR5_TEIE = CCR5+fieldToRegister CCR6_CIRC = CCR6+fieldToRegister CCR6_DIR = CCR6+fieldToRegister CCR6_EN = CCR6+fieldToRegister CCR6_HTIE = CCR6+fieldToRegister CCR6_MEM2MEM = CCR6+fieldToRegister CCR6_MINC = CCR6+fieldToRegister CCR6_MSIZE = CCR6+fieldToRegister CCR6_PINC = CCR6+fieldToRegister CCR6_PL = CCR6+fieldToRegister CCR6_PSIZE = CCR6+fieldToRegister CCR6_TCIE = CCR6+fieldToRegister CCR6_TEIE = CCR6+fieldToRegister CCR7_CIRC = CCR7+fieldToRegister CCR7_DIR = CCR7+fieldToRegister CCR7_EN = CCR7+fieldToRegister CCR7_HTIE = CCR7+fieldToRegister CCR7_MEM2MEM = CCR7+fieldToRegister CCR7_MINC = CCR7+fieldToRegister CCR7_MSIZE = CCR7+fieldToRegister CCR7_PINC = CCR7+fieldToRegister CCR7_PL = CCR7+fieldToRegister CCR7_PSIZE = CCR7+fieldToRegister CCR7_TCIE = CCR7+fieldToRegister CCR7_TEIE = CCR7+fieldToRegister CFGR_ADCPRE = CFGR+fieldToRegister CFGR_HPRE = CFGR+fieldToRegister CFGR_MCO = CFGR+fieldToRegister CFGR_OTGFSPRE = CFGR+fieldToRegister CFGR_PLLMUL = CFGR+fieldToRegister CFGR_PLLSRC = CFGR+fieldToRegister CFGR_PLLXTPRE = CFGR+fieldToRegister CFGR_PPRE1 = CFGR+fieldToRegister CFGR_PPRE2 = CFGR+fieldToRegister CFGR_SW = CFGR+fieldToRegister CFGR_SWS = CFGR+fieldToRegister CFR_EWI = CFR+fieldToRegister CFR_W = CFR+fieldToRegister CFR_WDGTB = CFR+fieldToRegister CIR_CSSC = CIR+fieldToRegister CIR_CSSF = CIR+fieldToRegister CIR_HSERDYC = CIR+fieldToRegister CIR_HSERDYF = CIR+fieldToRegister CIR_HSERDYIE = CIR+fieldToRegister CIR_HSIRDYC = CIR+fieldToRegister CIR_HSIRDYF = CIR+fieldToRegister CIR_HSIRDYIE = CIR+fieldToRegister CIR_LSERDYC = CIR+fieldToRegister CIR_LSERDYF = CIR+fieldToRegister CIR_LSERDYIE = CIR+fieldToRegister CIR_LSIRDYC = CIR+fieldToRegister CIR_LSIRDYF = CIR+fieldToRegister CIR_LSIRDYIE = CIR+fieldToRegister CIR_PLLRDYC = CIR+fieldToRegister CIR_PLLRDYF = CIR+fieldToRegister CIR_PLLRDYIE = CIR+fieldToRegister CLKCR_BYPASS = CLKCR+fieldToRegister CLKCR_CLKDIV = CLKCR+fieldToRegister CLKCR_CLKEN = CLKCR+fieldToRegister CLKCR_HWFC_EN = CLKCR+fieldToRegister CLKCR_NEGEDGE = CLKCR+fieldToRegister CLKCR_PWRSAV = CLKCR+fieldToRegister CLKCR_WIDBUS = CLKCR+fieldToRegister CMAR1_MA = CMAR1+fieldToRegister CMAR2_MA = CMAR2+fieldToRegister CMAR3_MA = CMAR3+fieldToRegister CMAR4_MA = CMAR4+fieldToRegister CMAR5_MA = CMAR5+fieldToRegister CMAR6_MA = CMAR6+fieldToRegister CMAR7_MA = CMAR7+fieldToRegister CMD_CE_ATACMD = CMD+fieldToRegister CMD_CMDINDEX = CMD+fieldToRegister CMD_CPSMEN = CMD+fieldToRegister CMD_ENCMDcompl = CMD+fieldToRegister CMD_SDIOSuspend = CMD+fieldToRegister CMD_WAITINT = CMD+fieldToRegister CMD_WAITPEND = CMD+fieldToRegister CMD_WAITRESP = CMD+fieldToRegister CMD_nIEN = CMD+fieldToRegister CNDTR1_NDT = CNDTR1+fieldToRegister CNDTR2_NDT = CNDTR2+fieldToRegister CNDTR3_NDT = CNDTR3+fieldToRegister CNDTR4_NDT = CNDTR4+fieldToRegister CNDTR5_NDT = CNDTR5+fieldToRegister CNDTR6_NDT = CNDTR6+fieldToRegister CNDTR7_NDT = CNDTR7+fieldToRegister CNT_CNT = CNT+fieldToRegister CNTH_CNTH = CNTH+fieldToRegister CNTL_CNTL = CNTL+fieldToRegister CNTR_CTRM = CNTR+fieldToRegister CNTR_ERRM = CNTR+fieldToRegister CNTR_ESOFM = CNTR+fieldToRegister CNTR_FRES = CNTR+fieldToRegister CNTR_FSUSP = CNTR+fieldToRegister CNTR_LPMODE = CNTR+fieldToRegister CNTR_PDWN = CNTR+fieldToRegister CNTR_PMAOVRM = CNTR+fieldToRegister CNTR_RESETM = CNTR+fieldToRegister CNTR_RESUME = CNTR+fieldToRegister CNTR_SOFM = CNTR+fieldToRegister CNTR_SUSPM = CNTR+fieldToRegister CNTR_WKUPM = CNTR+fieldToRegister CPAR1_PA = CPAR1+fieldToRegister CPAR2_PA = CPAR2+fieldToRegister CPAR3_PA = CPAR3+fieldToRegister CPAR4_PA = CPAR4+fieldToRegister CPAR5_PA = CPAR5+fieldToRegister CPAR6_PA = CPAR6+fieldToRegister CPAR7_PA = CPAR7+fieldToRegister CR_BOFF1 = CR+fieldToRegister CR_BOFF2 = CR+fieldToRegister CR_CSBF = CR+fieldToRegister CR_CSSON = CR+fieldToRegister CR_CWUF = CR+fieldToRegister CR_DBG_CAN1_STOP = CR+fieldToRegister CR_DBG_CAN2_STOP = CR+fieldToRegister CR_DBG_I2C1_SMBUS_TIMEOUT = CR+fieldToRegister CR_DBG_I2C2_SMBUS_TIMEOUT = CR+fieldToRegister CR_DBG_IWDG_STOP = CR+fieldToRegister CR_DBG_SLEEP = CR+fieldToRegister CR_DBG_STANDBY = CR+fieldToRegister CR_DBG_STOP = CR+fieldToRegister CR_DBG_TIM1_STOP = CR+fieldToRegister CR_DBG_TIM2_STOP = CR+fieldToRegister CR_DBG_TIM3_STOP = CR+fieldToRegister CR_DBG_TIM4_STOP = CR+fieldToRegister CR_DBG_TIM5_STOP = CR+fieldToRegister CR_DBG_TIM6_STOP = CR+fieldToRegister CR_DBG_TIM7_STOP = CR+fieldToRegister CR_DBG_TIM8_STOP = CR+fieldToRegister CR_DBG_WWDG_STOP = CR+fieldToRegister CR_DBP = CR+fieldToRegister CR_DMAEN1 = CR+fieldToRegister CR_DMAEN2 = CR+fieldToRegister CR_EN1 = CR+fieldToRegister CR_EN2 = CR+fieldToRegister CR_EOPIE = CR+fieldToRegister CR_ERRIE = CR+fieldToRegister CR_HSEBYP = CR+fieldToRegister CR_HSEON = CR+fieldToRegister CR_HSERDY = CR+fieldToRegister CR_HSICAL = CR+fieldToRegister CR_HSION = CR+fieldToRegister CR_HSIRDY = CR+fieldToRegister CR_HSITRIM = CR+fieldToRegister CR_LOCK = CR+fieldToRegister CR_LPDS = CR+fieldToRegister CR_MAMP1 = CR+fieldToRegister CR_MAMP2 = CR+fieldToRegister CR_MER = CR+fieldToRegister CR_OPTER = CR+fieldToRegister CR_OPTPG = CR+fieldToRegister CR_OPTWRE = CR+fieldToRegister CR_PDDS = CR+fieldToRegister CR_PER = CR+fieldToRegister CR_PG = CR+fieldToRegister CR_PLLON = CR+fieldToRegister CR_PLLRDY = CR+fieldToRegister CR_PLS = CR+fieldToRegister CR_PVDE = CR+fieldToRegister CR_RESET = CR+fieldToRegister CR_STRT = CR+fieldToRegister CR_T = CR+fieldToRegister CR_TEN1 = CR+fieldToRegister CR_TEN2 = CR+fieldToRegister CR_TPAL = CR+fieldToRegister CR_TPE = CR+fieldToRegister CR_TRACE_IOEN = CR+fieldToRegister CR_TRACE_MODE = CR+fieldToRegister CR_TSEL1 = CR+fieldToRegister CR_TSEL2 = CR+fieldToRegister CR_WAVE1 = CR+fieldToRegister CR_WAVE2 = CR+fieldToRegister CR_WDGA = CR+fieldToRegister CR1_ACK = CR1+fieldToRegister CR1_ALERT = CR1+fieldToRegister CR1_ARPE = CR1+fieldToRegister CR1_AWDCH = CR1+fieldToRegister CR1_AWDEN = CR1+fieldToRegister CR1_AWDIE = CR1+fieldToRegister CR1_AWDSGL = CR1+fieldToRegister CR1_BIDIMODE = CR1+fieldToRegister CR1_BIDIOE = CR1+fieldToRegister CR1_BR = CR1+fieldToRegister CR1_CEN = CR1+fieldToRegister CR1_CKD = CR1+fieldToRegister CR1_CMS = CR1+fieldToRegister CR1_CPHA = CR1+fieldToRegister CR1_CPOL = CR1+fieldToRegister CR1_CRCEN = CR1+fieldToRegister CR1_CRCNEXT = CR1+fieldToRegister CR1_DFF = CR1+fieldToRegister CR1_DIR = CR1+fieldToRegister CR1_DISCEN = CR1+fieldToRegister CR1_DISCNUM = CR1+fieldToRegister CR1_DUALMOD = CR1+fieldToRegister CR1_ENARP = CR1+fieldToRegister CR1_ENGC = CR1+fieldToRegister CR1_ENPEC = CR1+fieldToRegister CR1_EOCIE = CR1+fieldToRegister CR1_IDLEIE = CR1+fieldToRegister CR1_JAUTO = CR1+fieldToRegister CR1_JAWDEN = CR1+fieldToRegister CR1_JDISCEN = CR1+fieldToRegister CR1_JEOCIE = CR1+fieldToRegister CR1_LSBFIRST = CR1+fieldToRegister CR1_M = CR1+fieldToRegister CR1_MSTR = CR1+fieldToRegister CR1_NOSTRETCH = CR1+fieldToRegister CR1_OPM = CR1+fieldToRegister CR1_PCE = CR1+fieldToRegister CR1_PE = CR1+fieldToRegister CR1_PEC = CR1+fieldToRegister CR1_PEIE = CR1+fieldToRegister CR1_POS = CR1+fieldToRegister CR1_PS = CR1+fieldToRegister CR1_RE = CR1+fieldToRegister CR1_RWU = CR1+fieldToRegister CR1_RXNEIE = CR1+fieldToRegister CR1_RXONLY = CR1+fieldToRegister CR1_SBK = CR1+fieldToRegister CR1_SCAN = CR1+fieldToRegister CR1_SMBTYPE = CR1+fieldToRegister CR1_SMBUS = CR1+fieldToRegister CR1_SPE = CR1+fieldToRegister CR1_SSI = CR1+fieldToRegister CR1_SSM = CR1+fieldToRegister CR1_START = CR1+fieldToRegister CR1_STOP = CR1+fieldToRegister CR1_SWRST = CR1+fieldToRegister CR1_TCIE = CR1+fieldToRegister CR1_TE = CR1+fieldToRegister CR1_TXEIE = CR1+fieldToRegister CR1_UDIS = CR1+fieldToRegister CR1_UE = CR1+fieldToRegister CR1_URS = CR1+fieldToRegister CR1_WAKE = CR1+fieldToRegister CR2_ADD = CR2+fieldToRegister CR2_ADON = CR2+fieldToRegister CR2_ALIGN = CR2+fieldToRegister CR2_CAL = CR2+fieldToRegister CR2_CCDS = CR2+fieldToRegister CR2_CCPC = CR2+fieldToRegister CR2_CCUS = CR2+fieldToRegister CR2_CLKEN = CR2+fieldToRegister CR2_CONT = CR2+fieldToRegister CR2_CPHA = CR2+fieldToRegister CR2_CPOL = CR2+fieldToRegister CR2_DMA = CR2+fieldToRegister CR2_DMAEN = CR2+fieldToRegister CR2_ERRIE = CR2+fieldToRegister CR2_EXTSEL = CR2+fieldToRegister CR2_EXTTRIG = CR2+fieldToRegister CR2_FREQ = CR2+fieldToRegister CR2_ITBUFEN = CR2+fieldToRegister CR2_ITERREN = CR2+fieldToRegister CR2_ITEVTEN = CR2+fieldToRegister CR2_JEXTSEL = CR2+fieldToRegister CR2_JEXTTRIG = CR2+fieldToRegister CR2_JSWSTART = CR2+fieldToRegister CR2_LAST = CR2+fieldToRegister CR2_LBCL = CR2+fieldToRegister CR2_LBDIE = CR2+fieldToRegister CR2_LBDL = CR2+fieldToRegister CR2_LINEN = CR2+fieldToRegister CR2_MMS = CR2+fieldToRegister CR2_OIS1 = CR2+fieldToRegister CR2_OIS1N = CR2+fieldToRegister CR2_OIS2 = CR2+fieldToRegister CR2_OIS2N = CR2+fieldToRegister CR2_OIS3 = CR2+fieldToRegister CR2_OIS3N = CR2+fieldToRegister CR2_OIS4 = CR2+fieldToRegister CR2_RSTCAL = CR2+fieldToRegister CR2_RXDMAEN = CR2+fieldToRegister CR2_RXNEIE = CR2+fieldToRegister CR2_SSOE = CR2+fieldToRegister CR2_STOP = CR2+fieldToRegister CR2_SWSTART = CR2+fieldToRegister CR2_TI1S = CR2+fieldToRegister CR2_TSVREFE = CR2+fieldToRegister CR2_TXDMAEN = CR2+fieldToRegister CR2_TXEIE = CR2+fieldToRegister CR3_CTSE = CR3+fieldToRegister CR3_CTSIE = CR3+fieldToRegister CR3_DMAR = CR3+fieldToRegister CR3_DMAT = CR3+fieldToRegister CR3_EIE = CR3+fieldToRegister CR3_HDSEL = CR3+fieldToRegister CR3_IREN = CR3+fieldToRegister CR3_IRLP = CR3+fieldToRegister CR3_NACK = CR3+fieldToRegister CR3_RTSE = CR3+fieldToRegister CR3_SCEN = CR3+fieldToRegister CRCPR_CRCPOLY = CRCPR+fieldToRegister CRH_ALRIE = CRH+fieldToRegister CRH_CNF10 = CRH+fieldToRegister CRH_CNF11 = CRH+fieldToRegister CRH_CNF12 = CRH+fieldToRegister CRH_CNF13 = CRH+fieldToRegister CRH_CNF14 = CRH+fieldToRegister CRH_CNF15 = CRH+fieldToRegister CRH_CNF8 = CRH+fieldToRegister CRH_CNF9 = CRH+fieldToRegister CRH_MODE10 = CRH+fieldToRegister CRH_MODE11 = CRH+fieldToRegister CRH_MODE12 = CRH+fieldToRegister CRH_MODE13 = CRH+fieldToRegister CRH_MODE14 = CRH+fieldToRegister CRH_MODE15 = CRH+fieldToRegister CRH_MODE8 = CRH+fieldToRegister CRH_MODE9 = CRH+fieldToRegister CRH_OWIE = CRH+fieldToRegister CRH_SECIE = CRH+fieldToRegister CRL_ALRF = CRL+fieldToRegister CRL_CNF = CRL+fieldToRegister CRL_CNF0 = CRL+fieldToRegister CRL_CNF1 = CRL+fieldToRegister CRL_CNF2 = CRL+fieldToRegister CRL_CNF3 = CRL+fieldToRegister CRL_CNF4 = CRL+fieldToRegister CRL_CNF5 = CRL+fieldToRegister CRL_CNF6 = CRL+fieldToRegister CRL_CNF7 = CRL+fieldToRegister CRL_MODE0 = CRL+fieldToRegister CRL_MODE1 = CRL+fieldToRegister CRL_MODE2 = CRL+fieldToRegister CRL_MODE3 = CRL+fieldToRegister CRL_MODE4 = CRL+fieldToRegister CRL_MODE5 = CRL+fieldToRegister CRL_MODE6 = CRL+fieldToRegister CRL_MODE7 = CRL+fieldToRegister CRL_OWF = CRL+fieldToRegister CRL_RSF = CRL+fieldToRegister CRL_RTOFF = CRL+fieldToRegister CRL_SECF = CRL+fieldToRegister CSR_CTE = CSR+fieldToRegister CSR_CTI = CSR+fieldToRegister CSR_EWUP = CSR+fieldToRegister CSR_IWDGRSTF = CSR+fieldToRegister CSR_LPWRRSTF = CSR+fieldToRegister CSR_LSION = CSR+fieldToRegister CSR_LSIRDY = CSR+fieldToRegister CSR_PINRSTF = CSR+fieldToRegister CSR_PORRSTF = CSR+fieldToRegister CSR_PVDO = CSR+fieldToRegister CSR_RMVF = CSR+fieldToRegister CSR_SBF = CSR+fieldToRegister CSR_SFTRSTF = CSR+fieldToRegister CSR_TEF = CSR+fieldToRegister CSR_TIF = CSR+fieldToRegister CSR_TPIE = CSR+fieldToRegister CSR_WUF = CSR+fieldToRegister CSR_WWDGRSTF = CSR+fieldToRegister DADDR_ADD = DADDR+fieldToRegister DADDR_EF = DADDR+fieldToRegister DCOUNT_DATACOUNT = DCOUNT+fieldToRegister DCR_DBA = DCR+fieldToRegister DCR_DBL = DCR+fieldToRegister DCTRL_DBLOCKSIZE = DCTRL+fieldToRegister DCTRL_DMAEN = DCTRL+fieldToRegister DCTRL_DTDIR = DCTRL+fieldToRegister DCTRL_DTEN = DCTRL+fieldToRegister DCTRL_DTMODE = DCTRL+fieldToRegister DCTRL_PWSTART = DCTRL+fieldToRegister DCTRL_PWSTOP = DCTRL+fieldToRegister DCTRL_RWMOD = DCTRL+fieldToRegister DCTRL_SDIOEN = DCTRL+fieldToRegister DHR12L1_DACC1DHR = DHR12L1+fieldToRegister DHR12L2_DACC2DHR = DHR12L2+fieldToRegister DHR12LD_DACC1DHR = DHR12LD+fieldToRegister DHR12LD_DACC2DHR = DHR12LD+fieldToRegister DHR12R1_DACC1DHR = DHR12R1+fieldToRegister DHR12R2_DACC2DHR = DHR12R2+fieldToRegister DHR12RD_DACC1DHR = DHR12RD+fieldToRegister DHR12RD_DACC2DHR = DHR12RD+fieldToRegister DHR8R1_DACC1DHR = DHR8R1+fieldToRegister DHR8R2_DACC2DHR = DHR8R2+fieldToRegister DHR8RD_DACC1DHR = DHR8RD+fieldToRegister DHR8RD_DACC2DHR = DHR8RD+fieldToRegister DIER_BIE = DIER+fieldToRegister DIER_CC1DE = DIER+fieldToRegister DIER_CC1IE = DIER+fieldToRegister DIER_CC2DE = DIER+fieldToRegister DIER_CC2IE = DIER+fieldToRegister DIER_CC3DE = DIER+fieldToRegister DIER_CC3IE = DIER+fieldToRegister DIER_CC4DE = DIER+fieldToRegister DIER_CC4IE = DIER+fieldToRegister DIER_COMDE = DIER+fieldToRegister DIER_COMIE = DIER+fieldToRegister DIER_TDE = DIER+fieldToRegister DIER_TIE = DIER+fieldToRegister DIER_UDE = DIER+fieldToRegister DIER_UIE = DIER+fieldToRegister DIVH_DIVH = DIVH+fieldToRegister DIVL_DIVL = DIVL+fieldToRegister DLEN_DATALENGTH = DLEN+fieldToRegister DMAR_DMAB = DMAR+fieldToRegister DOR1_DACC1DOR = DOR1+fieldToRegister DOR2_DACC2DOR = DOR2+fieldToRegister DR_ADC2DATA = DR+fieldToRegister DR_DATA = DR+fieldToRegister DR_DR = DR+fieldToRegister DR1_D1 = DR1+fieldToRegister DR10_D10 = DR10+fieldToRegister DR11_DR11 = DR11+fieldToRegister DR12_DR12 = DR12+fieldToRegister DR13_DR13 = DR13+fieldToRegister DR14_D14 = DR14+fieldToRegister DR15_D15 = DR15+fieldToRegister DR16_D16 = DR16+fieldToRegister DR17_D17 = DR17+fieldToRegister DR18_D18 = DR18+fieldToRegister DR19_D19 = DR19+fieldToRegister DR2_D2 = DR2+fieldToRegister DR20_D20 = DR20+fieldToRegister DR21_D21 = DR21+fieldToRegister DR22_D22 = DR22+fieldToRegister DR23_D23 = DR23+fieldToRegister DR24_D24 = DR24+fieldToRegister DR25_D25 = DR25+fieldToRegister DR26_D26 = DR26+fieldToRegister DR27_D27 = DR27+fieldToRegister DR28_D28 = DR28+fieldToRegister DR29_D29 = DR29+fieldToRegister DR3_D3 = DR3+fieldToRegister DR30_D30 = DR30+fieldToRegister DR31_D31 = DR31+fieldToRegister DR32_D32 = DR32+fieldToRegister DR33_D33 = DR33+fieldToRegister DR34_D34 = DR34+fieldToRegister DR35_D35 = DR35+fieldToRegister DR36_D36 = DR36+fieldToRegister DR37_D37 = DR37+fieldToRegister DR38_D38 = DR38+fieldToRegister DR39_D39 = DR39+fieldToRegister DR4_D4 = DR4+fieldToRegister DR40_D40 = DR40+fieldToRegister DR41_D41 = DR41+fieldToRegister DR42_D42 = DR42+fieldToRegister DR5_D5 = DR5+fieldToRegister DR6_D6 = DR6+fieldToRegister DR7_D7 = DR7+fieldToRegister DR8_D8 = DR8+fieldToRegister DR9_D9 = DR9+fieldToRegister DTIMER_DATATIME = DTIMER+fieldToRegister ECCR2_ECCx = ECCR2+fieldToRegister ECCR3_ECCx = ECCR3+fieldToRegister EGR_BG = EGR+fieldToRegister EGR_CC1G = EGR+fieldToRegister EGR_CC2G = EGR+fieldToRegister EGR_CC3G = EGR+fieldToRegister EGR_CC4G = EGR+fieldToRegister EGR_COMG = EGR+fieldToRegister EGR_TG = EGR+fieldToRegister EGR_UG = EGR+fieldToRegister EMR_MR0 = EMR+fieldToRegister EMR_MR1 = EMR+fieldToRegister EMR_MR10 = EMR+fieldToRegister EMR_MR11 = EMR+fieldToRegister EMR_MR12 = EMR+fieldToRegister EMR_MR13 = EMR+fieldToRegister EMR_MR14 = EMR+fieldToRegister EMR_MR15 = EMR+fieldToRegister EMR_MR16 = EMR+fieldToRegister EMR_MR17 = EMR+fieldToRegister EMR_MR18 = EMR+fieldToRegister EMR_MR2 = EMR+fieldToRegister EMR_MR3 = EMR+fieldToRegister EMR_MR4 = EMR+fieldToRegister EMR_MR5 = EMR+fieldToRegister EMR_MR6 = EMR+fieldToRegister EMR_MR7 = EMR+fieldToRegister EMR_MR8 = EMR+fieldToRegister EMR_MR9 = EMR+fieldToRegister EP0R_CTR_RX = EP0R+fieldToRegister EP0R_CTR_TX = EP0R+fieldToRegister EP0R_DTOG_RX = EP0R+fieldToRegister EP0R_DTOG_TX = EP0R+fieldToRegister EP0R_EA = EP0R+fieldToRegister EP0R_EP_KIND = EP0R+fieldToRegister EP0R_EP_TYPE = EP0R+fieldToRegister EP0R_SETUP = EP0R+fieldToRegister EP0R_STAT_RX = EP0R+fieldToRegister EP0R_STAT_TX = EP0R+fieldToRegister EP1R_CTR_RX = EP1R+fieldToRegister EP1R_CTR_TX = EP1R+fieldToRegister EP1R_DTOG_RX = EP1R+fieldToRegister EP1R_DTOG_TX = EP1R+fieldToRegister EP1R_EA = EP1R+fieldToRegister EP1R_EP_KIND = EP1R+fieldToRegister EP1R_EP_TYPE = EP1R+fieldToRegister EP1R_SETUP = EP1R+fieldToRegister EP1R_STAT_RX = EP1R+fieldToRegister EP1R_STAT_TX = EP1R+fieldToRegister EP2R_CTR_RX = EP2R+fieldToRegister EP2R_CTR_TX = EP2R+fieldToRegister EP2R_DTOG_RX = EP2R+fieldToRegister EP2R_DTOG_TX = EP2R+fieldToRegister EP2R_EA = EP2R+fieldToRegister EP2R_EP_KIND = EP2R+fieldToRegister EP2R_EP_TYPE = EP2R+fieldToRegister EP2R_SETUP = EP2R+fieldToRegister EP2R_STAT_RX = EP2R+fieldToRegister EP2R_STAT_TX = EP2R+fieldToRegister EP3R_CTR_RX = EP3R+fieldToRegister EP3R_CTR_TX = EP3R+fieldToRegister EP3R_DTOG_RX = EP3R+fieldToRegister EP3R_DTOG_TX = EP3R+fieldToRegister EP3R_EA = EP3R+fieldToRegister EP3R_EP_KIND = EP3R+fieldToRegister EP3R_EP_TYPE = EP3R+fieldToRegister EP3R_SETUP = EP3R+fieldToRegister EP3R_STAT_RX = EP3R+fieldToRegister EP3R_STAT_TX = EP3R+fieldToRegister EP4R_CTR_RX = EP4R+fieldToRegister EP4R_CTR_TX = EP4R+fieldToRegister EP4R_DTOG_RX = EP4R+fieldToRegister EP4R_DTOG_TX = EP4R+fieldToRegister EP4R_EA = EP4R+fieldToRegister EP4R_EP_KIND = EP4R+fieldToRegister EP4R_EP_TYPE = EP4R+fieldToRegister EP4R_SETUP = EP4R+fieldToRegister EP4R_STAT_RX = EP4R+fieldToRegister EP4R_STAT_TX = EP4R+fieldToRegister EP5R_CTR_RX = EP5R+fieldToRegister EP5R_CTR_TX = EP5R+fieldToRegister EP5R_DTOG_RX = EP5R+fieldToRegister EP5R_DTOG_TX = EP5R+fieldToRegister EP5R_EA = EP5R+fieldToRegister EP5R_EP_KIND = EP5R+fieldToRegister EP5R_EP_TYPE = EP5R+fieldToRegister EP5R_SETUP = EP5R+fieldToRegister EP5R_STAT_RX = EP5R+fieldToRegister EP5R_STAT_TX = EP5R+fieldToRegister EP6R_CTR_RX = EP6R+fieldToRegister EP6R_CTR_TX = EP6R+fieldToRegister EP6R_DTOG_RX = EP6R+fieldToRegister EP6R_DTOG_TX = EP6R+fieldToRegister EP6R_EA = EP6R+fieldToRegister EP6R_EP_KIND = EP6R+fieldToRegister EP6R_EP_TYPE = EP6R+fieldToRegister EP6R_SETUP = EP6R+fieldToRegister EP6R_STAT_RX = EP6R+fieldToRegister EP6R_STAT_TX = EP6R+fieldToRegister EP7R_CTR_RX = EP7R+fieldToRegister EP7R_CTR_TX = EP7R+fieldToRegister EP7R_DTOG_RX = EP7R+fieldToRegister EP7R_DTOG_TX = EP7R+fieldToRegister EP7R_EA = EP7R+fieldToRegister EP7R_EP_KIND = EP7R+fieldToRegister EP7R_EP_TYPE = EP7R+fieldToRegister EP7R_SETUP = EP7R+fieldToRegister EP7R_STAT_RX = EP7R+fieldToRegister EP7R_STAT_TX = EP7R+fieldToRegister EVCR_EVOE = EVCR+fieldToRegister EVCR_PIN = EVCR+fieldToRegister EVCR_PORT = EVCR+fieldToRegister EXTICR1_EXTI0 = EXTICR1+fieldToRegister EXTICR1_EXTI1 = EXTICR1+fieldToRegister EXTICR1_EXTI2 = EXTICR1+fieldToRegister EXTICR1_EXTI3 = EXTICR1+fieldToRegister EXTICR2_EXTI4 = EXTICR2+fieldToRegister EXTICR2_EXTI5 = EXTICR2+fieldToRegister EXTICR2_EXTI6 = EXTICR2+fieldToRegister EXTICR2_EXTI7 = EXTICR2+fieldToRegister EXTICR3_EXTI10 = EXTICR3+fieldToRegister EXTICR3_EXTI11 = EXTICR3+fieldToRegister EXTICR3_EXTI8 = EXTICR3+fieldToRegister EXTICR3_EXTI9 = EXTICR3+fieldToRegister EXTICR4_EXTI12 = EXTICR4+fieldToRegister EXTICR4_EXTI13 = EXTICR4+fieldToRegister EXTICR4_EXTI14 = EXTICR4+fieldToRegister EXTICR4_EXTI15 = EXTICR4+fieldToRegister F0R1_FB0 = F0R1+fieldToRegister F0R1_FB1 = F0R1+fieldToRegister F0R1_FB10 = F0R1+fieldToRegister F0R1_FB11 = F0R1+fieldToRegister F0R1_FB12 = F0R1+fieldToRegister F0R1_FB13 = F0R1+fieldToRegister F0R1_FB14 = F0R1+fieldToRegister F0R1_FB15 = F0R1+fieldToRegister F0R1_FB16 = F0R1+fieldToRegister F0R1_FB17 = F0R1+fieldToRegister F0R1_FB18 = F0R1+fieldToRegister F0R1_FB19 = F0R1+fieldToRegister F0R1_FB2 = F0R1+fieldToRegister F0R1_FB20 = F0R1+fieldToRegister F0R1_FB21 = F0R1+fieldToRegister F0R1_FB22 = F0R1+fieldToRegister F0R1_FB23 = F0R1+fieldToRegister F0R1_FB24 = F0R1+fieldToRegister F0R1_FB25 = F0R1+fieldToRegister F0R1_FB26 = F0R1+fieldToRegister F0R1_FB27 = F0R1+fieldToRegister F0R1_FB28 = F0R1+fieldToRegister F0R1_FB29 = F0R1+fieldToRegister F0R1_FB3 = F0R1+fieldToRegister F0R1_FB30 = F0R1+fieldToRegister F0R1_FB31 = F0R1+fieldToRegister F0R1_FB4 = F0R1+fieldToRegister F0R1_FB5 = F0R1+fieldToRegister F0R1_FB6 = F0R1+fieldToRegister F0R1_FB7 = F0R1+fieldToRegister F0R1_FB8 = F0R1+fieldToRegister F0R1_FB9 = F0R1+fieldToRegister F0R2_FB0 = F0R2+fieldToRegister F0R2_FB1 = F0R2+fieldToRegister F0R2_FB10 = F0R2+fieldToRegister F0R2_FB11 = F0R2+fieldToRegister F0R2_FB12 = F0R2+fieldToRegister F0R2_FB13 = F0R2+fieldToRegister F0R2_FB14 = F0R2+fieldToRegister F0R2_FB15 = F0R2+fieldToRegister F0R2_FB16 = F0R2+fieldToRegister F0R2_FB17 = F0R2+fieldToRegister F0R2_FB18 = F0R2+fieldToRegister F0R2_FB19 = F0R2+fieldToRegister F0R2_FB2 = F0R2+fieldToRegister F0R2_FB20 = F0R2+fieldToRegister F0R2_FB21 = F0R2+fieldToRegister F0R2_FB22 = F0R2+fieldToRegister F0R2_FB23 = F0R2+fieldToRegister F0R2_FB24 = F0R2+fieldToRegister F0R2_FB25 = F0R2+fieldToRegister F0R2_FB26 = F0R2+fieldToRegister F0R2_FB27 = F0R2+fieldToRegister F0R2_FB28 = F0R2+fieldToRegister F0R2_FB29 = F0R2+fieldToRegister F0R2_FB3 = F0R2+fieldToRegister F0R2_FB30 = F0R2+fieldToRegister F0R2_FB31 = F0R2+fieldToRegister F0R2_FB4 = F0R2+fieldToRegister F0R2_FB5 = F0R2+fieldToRegister F0R2_FB6 = F0R2+fieldToRegister F0R2_FB7 = F0R2+fieldToRegister F0R2_FB8 = F0R2+fieldToRegister F0R2_FB9 = F0R2+fieldToRegister F10R1_FB0 = F10R1+fieldToRegister F10R1_FB1 = F10R1+fieldToRegister F10R1_FB10 = F10R1+fieldToRegister F10R1_FB11 = F10R1+fieldToRegister F10R1_FB12 = F10R1+fieldToRegister F10R1_FB13 = F10R1+fieldToRegister F10R1_FB14 = F10R1+fieldToRegister F10R1_FB15 = F10R1+fieldToRegister F10R1_FB16 = F10R1+fieldToRegister F10R1_FB17 = F10R1+fieldToRegister F10R1_FB18 = F10R1+fieldToRegister F10R1_FB19 = F10R1+fieldToRegister F10R1_FB2 = F10R1+fieldToRegister F10R1_FB20 = F10R1+fieldToRegister F10R1_FB21 = F10R1+fieldToRegister F10R1_FB22 = F10R1+fieldToRegister F10R1_FB23 = F10R1+fieldToRegister F10R1_FB24 = F10R1+fieldToRegister F10R1_FB25 = F10R1+fieldToRegister F10R1_FB26 = F10R1+fieldToRegister F10R1_FB27 = F10R1+fieldToRegister F10R1_FB28 = F10R1+fieldToRegister F10R1_FB29 = F10R1+fieldToRegister F10R1_FB3 = F10R1+fieldToRegister F10R1_FB30 = F10R1+fieldToRegister F10R1_FB31 = F10R1+fieldToRegister F10R1_FB4 = F10R1+fieldToRegister F10R1_FB5 = F10R1+fieldToRegister F10R1_FB6 = F10R1+fieldToRegister F10R1_FB7 = F10R1+fieldToRegister F10R1_FB8 = F10R1+fieldToRegister F10R1_FB9 = F10R1+fieldToRegister F10R2_FB0 = F10R2+fieldToRegister F10R2_FB1 = F10R2+fieldToRegister F10R2_FB10 = F10R2+fieldToRegister F10R2_FB11 = F10R2+fieldToRegister F10R2_FB12 = F10R2+fieldToRegister F10R2_FB13 = F10R2+fieldToRegister F10R2_FB14 = F10R2+fieldToRegister F10R2_FB15 = F10R2+fieldToRegister F10R2_FB16 = F10R2+fieldToRegister F10R2_FB17 = F10R2+fieldToRegister F10R2_FB18 = F10R2+fieldToRegister F10R2_FB19 = F10R2+fieldToRegister F10R2_FB2 = F10R2+fieldToRegister F10R2_FB20 = F10R2+fieldToRegister F10R2_FB21 = F10R2+fieldToRegister F10R2_FB22 = F10R2+fieldToRegister F10R2_FB23 = F10R2+fieldToRegister F10R2_FB24 = F10R2+fieldToRegister F10R2_FB25 = F10R2+fieldToRegister F10R2_FB26 = F10R2+fieldToRegister F10R2_FB27 = F10R2+fieldToRegister F10R2_FB28 = F10R2+fieldToRegister F10R2_FB29 = F10R2+fieldToRegister F10R2_FB3 = F10R2+fieldToRegister F10R2_FB30 = F10R2+fieldToRegister F10R2_FB31 = F10R2+fieldToRegister F10R2_FB4 = F10R2+fieldToRegister F10R2_FB5 = F10R2+fieldToRegister F10R2_FB6 = F10R2+fieldToRegister F10R2_FB7 = F10R2+fieldToRegister F10R2_FB8 = F10R2+fieldToRegister F10R2_FB9 = F10R2+fieldToRegister F11R1_FB0 = F11R1+fieldToRegister F11R1_FB1 = F11R1+fieldToRegister F11R1_FB10 = F11R1+fieldToRegister F11R1_FB11 = F11R1+fieldToRegister F11R1_FB12 = F11R1+fieldToRegister F11R1_FB13 = F11R1+fieldToRegister F11R1_FB14 = F11R1+fieldToRegister F11R1_FB15 = F11R1+fieldToRegister F11R1_FB16 = F11R1+fieldToRegister F11R1_FB17 = F11R1+fieldToRegister F11R1_FB18 = F11R1+fieldToRegister F11R1_FB19 = F11R1+fieldToRegister F11R1_FB2 = F11R1+fieldToRegister F11R1_FB20 = F11R1+fieldToRegister F11R1_FB21 = F11R1+fieldToRegister F11R1_FB22 = F11R1+fieldToRegister F11R1_FB23 = F11R1+fieldToRegister F11R1_FB24 = F11R1+fieldToRegister F11R1_FB25 = F11R1+fieldToRegister F11R1_FB26 = F11R1+fieldToRegister F11R1_FB27 = F11R1+fieldToRegister F11R1_FB28 = F11R1+fieldToRegister F11R1_FB29 = F11R1+fieldToRegister F11R1_FB3 = F11R1+fieldToRegister F11R1_FB30 = F11R1+fieldToRegister F11R1_FB31 = F11R1+fieldToRegister F11R1_FB4 = F11R1+fieldToRegister F11R1_FB5 = F11R1+fieldToRegister F11R1_FB6 = F11R1+fieldToRegister F11R1_FB7 = F11R1+fieldToRegister F11R1_FB8 = F11R1+fieldToRegister F11R1_FB9 = F11R1+fieldToRegister F11R2_FB0 = F11R2+fieldToRegister F11R2_FB1 = F11R2+fieldToRegister F11R2_FB10 = F11R2+fieldToRegister F11R2_FB11 = F11R2+fieldToRegister F11R2_FB12 = F11R2+fieldToRegister F11R2_FB13 = F11R2+fieldToRegister F11R2_FB14 = F11R2+fieldToRegister F11R2_FB15 = F11R2+fieldToRegister F11R2_FB16 = F11R2+fieldToRegister F11R2_FB17 = F11R2+fieldToRegister F11R2_FB18 = F11R2+fieldToRegister F11R2_FB19 = F11R2+fieldToRegister F11R2_FB2 = F11R2+fieldToRegister F11R2_FB20 = F11R2+fieldToRegister F11R2_FB21 = F11R2+fieldToRegister F11R2_FB22 = F11R2+fieldToRegister F11R2_FB23 = F11R2+fieldToRegister F11R2_FB24 = F11R2+fieldToRegister F11R2_FB25 = F11R2+fieldToRegister F11R2_FB26 = F11R2+fieldToRegister F11R2_FB27 = F11R2+fieldToRegister F11R2_FB28 = F11R2+fieldToRegister F11R2_FB29 = F11R2+fieldToRegister F11R2_FB3 = F11R2+fieldToRegister F11R2_FB30 = F11R2+fieldToRegister F11R2_FB31 = F11R2+fieldToRegister F11R2_FB4 = F11R2+fieldToRegister F11R2_FB5 = F11R2+fieldToRegister F11R2_FB6 = F11R2+fieldToRegister F11R2_FB7 = F11R2+fieldToRegister F11R2_FB8 = F11R2+fieldToRegister F11R2_FB9 = F11R2+fieldToRegister F12R1_FB0 = F12R1+fieldToRegister F12R1_FB1 = F12R1+fieldToRegister F12R1_FB10 = F12R1+fieldToRegister F12R1_FB11 = F12R1+fieldToRegister F12R1_FB12 = F12R1+fieldToRegister F12R1_FB13 = F12R1+fieldToRegister F12R1_FB14 = F12R1+fieldToRegister F12R1_FB15 = F12R1+fieldToRegister F12R1_FB16 = F12R1+fieldToRegister F12R1_FB17 = F12R1+fieldToRegister F12R1_FB18 = F12R1+fieldToRegister F12R1_FB19 = F12R1+fieldToRegister F12R1_FB2 = F12R1+fieldToRegister F12R1_FB20 = F12R1+fieldToRegister F12R1_FB21 = F12R1+fieldToRegister F12R1_FB22 = F12R1+fieldToRegister F12R1_FB23 = F12R1+fieldToRegister F12R1_FB24 = F12R1+fieldToRegister F12R1_FB25 = F12R1+fieldToRegister F12R1_FB26 = F12R1+fieldToRegister F12R1_FB27 = F12R1+fieldToRegister F12R1_FB28 = F12R1+fieldToRegister F12R1_FB29 = F12R1+fieldToRegister F12R1_FB3 = F12R1+fieldToRegister F12R1_FB30 = F12R1+fieldToRegister F12R1_FB31 = F12R1+fieldToRegister F12R1_FB4 = F12R1+fieldToRegister F12R1_FB5 = F12R1+fieldToRegister F12R1_FB6 = F12R1+fieldToRegister F12R1_FB7 = F12R1+fieldToRegister F12R1_FB8 = F12R1+fieldToRegister F12R1_FB9 = F12R1+fieldToRegister F12R2_FB0 = F12R2+fieldToRegister F12R2_FB1 = F12R2+fieldToRegister F12R2_FB10 = F12R2+fieldToRegister F12R2_FB11 = F12R2+fieldToRegister F12R2_FB12 = F12R2+fieldToRegister F12R2_FB13 = F12R2+fieldToRegister F12R2_FB14 = F12R2+fieldToRegister F12R2_FB15 = F12R2+fieldToRegister F12R2_FB16 = F12R2+fieldToRegister F12R2_FB17 = F12R2+fieldToRegister F12R2_FB18 = F12R2+fieldToRegister F12R2_FB19 = F12R2+fieldToRegister F12R2_FB2 = F12R2+fieldToRegister F12R2_FB20 = F12R2+fieldToRegister F12R2_FB21 = F12R2+fieldToRegister F12R2_FB22 = F12R2+fieldToRegister F12R2_FB23 = F12R2+fieldToRegister F12R2_FB24 = F12R2+fieldToRegister F12R2_FB25 = F12R2+fieldToRegister F12R2_FB26 = F12R2+fieldToRegister F12R2_FB27 = F12R2+fieldToRegister F12R2_FB28 = F12R2+fieldToRegister F12R2_FB29 = F12R2+fieldToRegister F12R2_FB3 = F12R2+fieldToRegister F12R2_FB30 = F12R2+fieldToRegister F12R2_FB31 = F12R2+fieldToRegister F12R2_FB4 = F12R2+fieldToRegister F12R2_FB5 = F12R2+fieldToRegister F12R2_FB6 = F12R2+fieldToRegister F12R2_FB7 = F12R2+fieldToRegister F12R2_FB8 = F12R2+fieldToRegister F12R2_FB9 = F12R2+fieldToRegister F13R1_FB0 = F13R1+fieldToRegister F13R1_FB1 = F13R1+fieldToRegister F13R1_FB10 = F13R1+fieldToRegister F13R1_FB11 = F13R1+fieldToRegister F13R1_FB12 = F13R1+fieldToRegister F13R1_FB13 = F13R1+fieldToRegister F13R1_FB14 = F13R1+fieldToRegister F13R1_FB15 = F13R1+fieldToRegister F13R1_FB16 = F13R1+fieldToRegister F13R1_FB17 = F13R1+fieldToRegister F13R1_FB18 = F13R1+fieldToRegister F13R1_FB19 = F13R1+fieldToRegister F13R1_FB2 = F13R1+fieldToRegister F13R1_FB20 = F13R1+fieldToRegister F13R1_FB21 = F13R1+fieldToRegister F13R1_FB22 = F13R1+fieldToRegister F13R1_FB23 = F13R1+fieldToRegister F13R1_FB24 = F13R1+fieldToRegister F13R1_FB25 = F13R1+fieldToRegister F13R1_FB26 = F13R1+fieldToRegister F13R1_FB27 = F13R1+fieldToRegister F13R1_FB28 = F13R1+fieldToRegister F13R1_FB29 = F13R1+fieldToRegister F13R1_FB3 = F13R1+fieldToRegister F13R1_FB30 = F13R1+fieldToRegister F13R1_FB31 = F13R1+fieldToRegister F13R1_FB4 = F13R1+fieldToRegister F13R1_FB5 = F13R1+fieldToRegister F13R1_FB6 = F13R1+fieldToRegister F13R1_FB7 = F13R1+fieldToRegister F13R1_FB8 = F13R1+fieldToRegister F13R1_FB9 = F13R1+fieldToRegister F13R2_FB0 = F13R2+fieldToRegister F13R2_FB1 = F13R2+fieldToRegister F13R2_FB10 = F13R2+fieldToRegister F13R2_FB11 = F13R2+fieldToRegister F13R2_FB12 = F13R2+fieldToRegister F13R2_FB13 = F13R2+fieldToRegister F13R2_FB14 = F13R2+fieldToRegister F13R2_FB15 = F13R2+fieldToRegister F13R2_FB16 = F13R2+fieldToRegister F13R2_FB17 = F13R2+fieldToRegister F13R2_FB18 = F13R2+fieldToRegister F13R2_FB19 = F13R2+fieldToRegister F13R2_FB2 = F13R2+fieldToRegister F13R2_FB20 = F13R2+fieldToRegister F13R2_FB21 = F13R2+fieldToRegister F13R2_FB22 = F13R2+fieldToRegister F13R2_FB23 = F13R2+fieldToRegister F13R2_FB24 = F13R2+fieldToRegister F13R2_FB25 = F13R2+fieldToRegister F13R2_FB26 = F13R2+fieldToRegister F13R2_FB27 = F13R2+fieldToRegister F13R2_FB28 = F13R2+fieldToRegister F13R2_FB29 = F13R2+fieldToRegister F13R2_FB3 = F13R2+fieldToRegister F13R2_FB30 = F13R2+fieldToRegister F13R2_FB31 = F13R2+fieldToRegister F13R2_FB4 = F13R2+fieldToRegister F13R2_FB5 = F13R2+fieldToRegister F13R2_FB6 = F13R2+fieldToRegister F13R2_FB7 = F13R2+fieldToRegister F13R2_FB8 = F13R2+fieldToRegister F13R2_FB9 = F13R2+fieldToRegister F1R1_FB0 = F1R1+fieldToRegister F1R1_FB1 = F1R1+fieldToRegister F1R1_FB10 = F1R1+fieldToRegister F1R1_FB11 = F1R1+fieldToRegister F1R1_FB12 = F1R1+fieldToRegister F1R1_FB13 = F1R1+fieldToRegister F1R1_FB14 = F1R1+fieldToRegister F1R1_FB15 = F1R1+fieldToRegister F1R1_FB16 = F1R1+fieldToRegister F1R1_FB17 = F1R1+fieldToRegister F1R1_FB18 = F1R1+fieldToRegister F1R1_FB19 = F1R1+fieldToRegister F1R1_FB2 = F1R1+fieldToRegister F1R1_FB20 = F1R1+fieldToRegister F1R1_FB21 = F1R1+fieldToRegister F1R1_FB22 = F1R1+fieldToRegister F1R1_FB23 = F1R1+fieldToRegister F1R1_FB24 = F1R1+fieldToRegister F1R1_FB25 = F1R1+fieldToRegister F1R1_FB26 = F1R1+fieldToRegister F1R1_FB27 = F1R1+fieldToRegister F1R1_FB28 = F1R1+fieldToRegister F1R1_FB29 = F1R1+fieldToRegister F1R1_FB3 = F1R1+fieldToRegister F1R1_FB30 = F1R1+fieldToRegister F1R1_FB31 = F1R1+fieldToRegister F1R1_FB4 = F1R1+fieldToRegister F1R1_FB5 = F1R1+fieldToRegister F1R1_FB6 = F1R1+fieldToRegister F1R1_FB7 = F1R1+fieldToRegister F1R1_FB8 = F1R1+fieldToRegister F1R1_FB9 = F1R1+fieldToRegister F1R2_FB0 = F1R2+fieldToRegister F1R2_FB1 = F1R2+fieldToRegister F1R2_FB10 = F1R2+fieldToRegister F1R2_FB11 = F1R2+fieldToRegister F1R2_FB12 = F1R2+fieldToRegister F1R2_FB13 = F1R2+fieldToRegister F1R2_FB14 = F1R2+fieldToRegister F1R2_FB15 = F1R2+fieldToRegister F1R2_FB16 = F1R2+fieldToRegister F1R2_FB17 = F1R2+fieldToRegister F1R2_FB18 = F1R2+fieldToRegister F1R2_FB19 = F1R2+fieldToRegister F1R2_FB2 = F1R2+fieldToRegister F1R2_FB20 = F1R2+fieldToRegister F1R2_FB21 = F1R2+fieldToRegister F1R2_FB22 = F1R2+fieldToRegister F1R2_FB23 = F1R2+fieldToRegister F1R2_FB24 = F1R2+fieldToRegister F1R2_FB25 = F1R2+fieldToRegister F1R2_FB26 = F1R2+fieldToRegister F1R2_FB27 = F1R2+fieldToRegister F1R2_FB28 = F1R2+fieldToRegister F1R2_FB29 = F1R2+fieldToRegister F1R2_FB3 = F1R2+fieldToRegister F1R2_FB30 = F1R2+fieldToRegister F1R2_FB31 = F1R2+fieldToRegister F1R2_FB4 = F1R2+fieldToRegister F1R2_FB5 = F1R2+fieldToRegister F1R2_FB6 = F1R2+fieldToRegister F1R2_FB7 = F1R2+fieldToRegister F1R2_FB8 = F1R2+fieldToRegister F1R2_FB9 = F1R2+fieldToRegister F2R1_FB0 = F2R1+fieldToRegister F2R1_FB1 = F2R1+fieldToRegister F2R1_FB10 = F2R1+fieldToRegister F2R1_FB11 = F2R1+fieldToRegister F2R1_FB12 = F2R1+fieldToRegister F2R1_FB13 = F2R1+fieldToRegister F2R1_FB14 = F2R1+fieldToRegister F2R1_FB15 = F2R1+fieldToRegister F2R1_FB16 = F2R1+fieldToRegister F2R1_FB17 = F2R1+fieldToRegister F2R1_FB18 = F2R1+fieldToRegister F2R1_FB19 = F2R1+fieldToRegister F2R1_FB2 = F2R1+fieldToRegister F2R1_FB20 = F2R1+fieldToRegister F2R1_FB21 = F2R1+fieldToRegister F2R1_FB22 = F2R1+fieldToRegister F2R1_FB23 = F2R1+fieldToRegister F2R1_FB24 = F2R1+fieldToRegister F2R1_FB25 = F2R1+fieldToRegister F2R1_FB26 = F2R1+fieldToRegister F2R1_FB27 = F2R1+fieldToRegister F2R1_FB28 = F2R1+fieldToRegister F2R1_FB29 = F2R1+fieldToRegister F2R1_FB3 = F2R1+fieldToRegister F2R1_FB30 = F2R1+fieldToRegister F2R1_FB31 = F2R1+fieldToRegister F2R1_FB4 = F2R1+fieldToRegister F2R1_FB5 = F2R1+fieldToRegister F2R1_FB6 = F2R1+fieldToRegister F2R1_FB7 = F2R1+fieldToRegister F2R1_FB8 = F2R1+fieldToRegister F2R1_FB9 = F2R1+fieldToRegister F2R2_FB0 = F2R2+fieldToRegister F2R2_FB1 = F2R2+fieldToRegister F2R2_FB10 = F2R2+fieldToRegister F2R2_FB11 = F2R2+fieldToRegister F2R2_FB12 = F2R2+fieldToRegister F2R2_FB13 = F2R2+fieldToRegister F2R2_FB14 = F2R2+fieldToRegister F2R2_FB15 = F2R2+fieldToRegister F2R2_FB16 = F2R2+fieldToRegister F2R2_FB17 = F2R2+fieldToRegister F2R2_FB18 = F2R2+fieldToRegister F2R2_FB19 = F2R2+fieldToRegister F2R2_FB2 = F2R2+fieldToRegister F2R2_FB20 = F2R2+fieldToRegister F2R2_FB21 = F2R2+fieldToRegister F2R2_FB22 = F2R2+fieldToRegister F2R2_FB23 = F2R2+fieldToRegister F2R2_FB24 = F2R2+fieldToRegister F2R2_FB25 = F2R2+fieldToRegister F2R2_FB26 = F2R2+fieldToRegister F2R2_FB27 = F2R2+fieldToRegister F2R2_FB28 = F2R2+fieldToRegister F2R2_FB29 = F2R2+fieldToRegister F2R2_FB3 = F2R2+fieldToRegister F2R2_FB30 = F2R2+fieldToRegister F2R2_FB31 = F2R2+fieldToRegister F2R2_FB4 = F2R2+fieldToRegister F2R2_FB5 = F2R2+fieldToRegister F2R2_FB6 = F2R2+fieldToRegister F2R2_FB7 = F2R2+fieldToRegister F2R2_FB8 = F2R2+fieldToRegister F2R2_FB9 = F2R2+fieldToRegister F3R1_FB0 = F3R1+fieldToRegister F3R1_FB1 = F3R1+fieldToRegister F3R1_FB10 = F3R1+fieldToRegister F3R1_FB11 = F3R1+fieldToRegister F3R1_FB12 = F3R1+fieldToRegister F3R1_FB13 = F3R1+fieldToRegister F3R1_FB14 = F3R1+fieldToRegister F3R1_FB15 = F3R1+fieldToRegister F3R1_FB16 = F3R1+fieldToRegister F3R1_FB17 = F3R1+fieldToRegister F3R1_FB18 = F3R1+fieldToRegister F3R1_FB19 = F3R1+fieldToRegister F3R1_FB2 = F3R1+fieldToRegister F3R1_FB20 = F3R1+fieldToRegister F3R1_FB21 = F3R1+fieldToRegister F3R1_FB22 = F3R1+fieldToRegister F3R1_FB23 = F3R1+fieldToRegister F3R1_FB24 = F3R1+fieldToRegister F3R1_FB25 = F3R1+fieldToRegister F3R1_FB26 = F3R1+fieldToRegister F3R1_FB27 = F3R1+fieldToRegister F3R1_FB28 = F3R1+fieldToRegister F3R1_FB29 = F3R1+fieldToRegister F3R1_FB3 = F3R1+fieldToRegister F3R1_FB30 = F3R1+fieldToRegister F3R1_FB31 = F3R1+fieldToRegister F3R1_FB4 = F3R1+fieldToRegister F3R1_FB5 = F3R1+fieldToRegister F3R1_FB6 = F3R1+fieldToRegister F3R1_FB7 = F3R1+fieldToRegister F3R1_FB8 = F3R1+fieldToRegister F3R1_FB9 = F3R1+fieldToRegister F3R2_FB0 = F3R2+fieldToRegister F3R2_FB1 = F3R2+fieldToRegister F3R2_FB10 = F3R2+fieldToRegister F3R2_FB11 = F3R2+fieldToRegister F3R2_FB12 = F3R2+fieldToRegister F3R2_FB13 = F3R2+fieldToRegister F3R2_FB14 = F3R2+fieldToRegister F3R2_FB15 = F3R2+fieldToRegister F3R2_FB16 = F3R2+fieldToRegister F3R2_FB17 = F3R2+fieldToRegister F3R2_FB18 = F3R2+fieldToRegister F3R2_FB19 = F3R2+fieldToRegister F3R2_FB2 = F3R2+fieldToRegister F3R2_FB20 = F3R2+fieldToRegister F3R2_FB21 = F3R2+fieldToRegister F3R2_FB22 = F3R2+fieldToRegister F3R2_FB23 = F3R2+fieldToRegister F3R2_FB24 = F3R2+fieldToRegister F3R2_FB25 = F3R2+fieldToRegister F3R2_FB26 = F3R2+fieldToRegister F3R2_FB27 = F3R2+fieldToRegister F3R2_FB28 = F3R2+fieldToRegister F3R2_FB29 = F3R2+fieldToRegister F3R2_FB3 = F3R2+fieldToRegister F3R2_FB30 = F3R2+fieldToRegister F3R2_FB31 = F3R2+fieldToRegister F3R2_FB4 = F3R2+fieldToRegister F3R2_FB5 = F3R2+fieldToRegister F3R2_FB6 = F3R2+fieldToRegister F3R2_FB7 = F3R2+fieldToRegister F3R2_FB8 = F3R2+fieldToRegister F3R2_FB9 = F3R2+fieldToRegister F4R1_FB0 = F4R1+fieldToRegister F4R1_FB1 = F4R1+fieldToRegister F4R1_FB10 = F4R1+fieldToRegister F4R1_FB11 = F4R1+fieldToRegister F4R1_FB12 = F4R1+fieldToRegister F4R1_FB13 = F4R1+fieldToRegister F4R1_FB14 = F4R1+fieldToRegister F4R1_FB15 = F4R1+fieldToRegister F4R1_FB16 = F4R1+fieldToRegister F4R1_FB17 = F4R1+fieldToRegister F4R1_FB18 = F4R1+fieldToRegister F4R1_FB19 = F4R1+fieldToRegister F4R1_FB2 = F4R1+fieldToRegister F4R1_FB20 = F4R1+fieldToRegister F4R1_FB21 = F4R1+fieldToRegister F4R1_FB22 = F4R1+fieldToRegister F4R1_FB23 = F4R1+fieldToRegister F4R1_FB24 = F4R1+fieldToRegister F4R1_FB25 = F4R1+fieldToRegister F4R1_FB26 = F4R1+fieldToRegister F4R1_FB27 = F4R1+fieldToRegister F4R1_FB28 = F4R1+fieldToRegister F4R1_FB29 = F4R1+fieldToRegister F4R1_FB3 = F4R1+fieldToRegister F4R1_FB30 = F4R1+fieldToRegister F4R1_FB31 = F4R1+fieldToRegister F4R1_FB4 = F4R1+fieldToRegister F4R1_FB5 = F4R1+fieldToRegister F4R1_FB6 = F4R1+fieldToRegister F4R1_FB7 = F4R1+fieldToRegister F4R1_FB8 = F4R1+fieldToRegister F4R1_FB9 = F4R1+fieldToRegister F4R2_FB0 = F4R2+fieldToRegister F4R2_FB1 = F4R2+fieldToRegister F4R2_FB10 = F4R2+fieldToRegister F4R2_FB11 = F4R2+fieldToRegister F4R2_FB12 = F4R2+fieldToRegister F4R2_FB13 = F4R2+fieldToRegister F4R2_FB14 = F4R2+fieldToRegister F4R2_FB15 = F4R2+fieldToRegister F4R2_FB16 = F4R2+fieldToRegister F4R2_FB17 = F4R2+fieldToRegister F4R2_FB18 = F4R2+fieldToRegister F4R2_FB19 = F4R2+fieldToRegister F4R2_FB2 = F4R2+fieldToRegister F4R2_FB20 = F4R2+fieldToRegister F4R2_FB21 = F4R2+fieldToRegister F4R2_FB22 = F4R2+fieldToRegister F4R2_FB23 = F4R2+fieldToRegister F4R2_FB24 = F4R2+fieldToRegister F4R2_FB25 = F4R2+fieldToRegister F4R2_FB26 = F4R2+fieldToRegister F4R2_FB27 = F4R2+fieldToRegister F4R2_FB28 = F4R2+fieldToRegister F4R2_FB29 = F4R2+fieldToRegister F4R2_FB3 = F4R2+fieldToRegister F4R2_FB30 = F4R2+fieldToRegister F4R2_FB31 = F4R2+fieldToRegister F4R2_FB4 = F4R2+fieldToRegister F4R2_FB5 = F4R2+fieldToRegister F4R2_FB6 = F4R2+fieldToRegister F4R2_FB7 = F4R2+fieldToRegister F4R2_FB8 = F4R2+fieldToRegister F4R2_FB9 = F4R2+fieldToRegister F5R1_FB0 = F5R1+fieldToRegister F5R1_FB1 = F5R1+fieldToRegister F5R1_FB10 = F5R1+fieldToRegister F5R1_FB11 = F5R1+fieldToRegister F5R1_FB12 = F5R1+fieldToRegister F5R1_FB13 = F5R1+fieldToRegister F5R1_FB14 = F5R1+fieldToRegister F5R1_FB15 = F5R1+fieldToRegister F5R1_FB16 = F5R1+fieldToRegister F5R1_FB17 = F5R1+fieldToRegister F5R1_FB18 = F5R1+fieldToRegister F5R1_FB19 = F5R1+fieldToRegister F5R1_FB2 = F5R1+fieldToRegister F5R1_FB20 = F5R1+fieldToRegister F5R1_FB21 = F5R1+fieldToRegister F5R1_FB22 = F5R1+fieldToRegister F5R1_FB23 = F5R1+fieldToRegister F5R1_FB24 = F5R1+fieldToRegister F5R1_FB25 = F5R1+fieldToRegister F5R1_FB26 = F5R1+fieldToRegister F5R1_FB27 = F5R1+fieldToRegister F5R1_FB28 = F5R1+fieldToRegister F5R1_FB29 = F5R1+fieldToRegister F5R1_FB3 = F5R1+fieldToRegister F5R1_FB30 = F5R1+fieldToRegister F5R1_FB31 = F5R1+fieldToRegister F5R1_FB4 = F5R1+fieldToRegister F5R1_FB5 = F5R1+fieldToRegister F5R1_FB6 = F5R1+fieldToRegister F5R1_FB7 = F5R1+fieldToRegister F5R1_FB8 = F5R1+fieldToRegister F5R1_FB9 = F5R1+fieldToRegister F5R2_FB0 = F5R2+fieldToRegister F5R2_FB1 = F5R2+fieldToRegister F5R2_FB10 = F5R2+fieldToRegister F5R2_FB11 = F5R2+fieldToRegister F5R2_FB12 = F5R2+fieldToRegister F5R2_FB13 = F5R2+fieldToRegister F5R2_FB14 = F5R2+fieldToRegister F5R2_FB15 = F5R2+fieldToRegister F5R2_FB16 = F5R2+fieldToRegister F5R2_FB17 = F5R2+fieldToRegister F5R2_FB18 = F5R2+fieldToRegister F5R2_FB19 = F5R2+fieldToRegister F5R2_FB2 = F5R2+fieldToRegister F5R2_FB20 = F5R2+fieldToRegister F5R2_FB21 = F5R2+fieldToRegister F5R2_FB22 = F5R2+fieldToRegister F5R2_FB23 = F5R2+fieldToRegister F5R2_FB24 = F5R2+fieldToRegister F5R2_FB25 = F5R2+fieldToRegister F5R2_FB26 = F5R2+fieldToRegister F5R2_FB27 = F5R2+fieldToRegister F5R2_FB28 = F5R2+fieldToRegister F5R2_FB29 = F5R2+fieldToRegister F5R2_FB3 = F5R2+fieldToRegister F5R2_FB30 = F5R2+fieldToRegister F5R2_FB31 = F5R2+fieldToRegister F5R2_FB4 = F5R2+fieldToRegister F5R2_FB5 = F5R2+fieldToRegister F5R2_FB6 = F5R2+fieldToRegister F5R2_FB7 = F5R2+fieldToRegister F5R2_FB8 = F5R2+fieldToRegister F5R2_FB9 = F5R2+fieldToRegister F6R1_FB0 = F6R1+fieldToRegister F6R1_FB1 = F6R1+fieldToRegister F6R1_FB10 = F6R1+fieldToRegister F6R1_FB11 = F6R1+fieldToRegister F6R1_FB12 = F6R1+fieldToRegister F6R1_FB13 = F6R1+fieldToRegister F6R1_FB14 = F6R1+fieldToRegister F6R1_FB15 = F6R1+fieldToRegister F6R1_FB16 = F6R1+fieldToRegister F6R1_FB17 = F6R1+fieldToRegister F6R1_FB18 = F6R1+fieldToRegister F6R1_FB19 = F6R1+fieldToRegister F6R1_FB2 = F6R1+fieldToRegister F6R1_FB20 = F6R1+fieldToRegister F6R1_FB21 = F6R1+fieldToRegister F6R1_FB22 = F6R1+fieldToRegister F6R1_FB23 = F6R1+fieldToRegister F6R1_FB24 = F6R1+fieldToRegister F6R1_FB25 = F6R1+fieldToRegister F6R1_FB26 = F6R1+fieldToRegister F6R1_FB27 = F6R1+fieldToRegister F6R1_FB28 = F6R1+fieldToRegister F6R1_FB29 = F6R1+fieldToRegister F6R1_FB3 = F6R1+fieldToRegister F6R1_FB30 = F6R1+fieldToRegister F6R1_FB31 = F6R1+fieldToRegister F6R1_FB4 = F6R1+fieldToRegister F6R1_FB5 = F6R1+fieldToRegister F6R1_FB6 = F6R1+fieldToRegister F6R1_FB7 = F6R1+fieldToRegister F6R1_FB8 = F6R1+fieldToRegister F6R1_FB9 = F6R1+fieldToRegister F6R2_FB0 = F6R2+fieldToRegister F6R2_FB1 = F6R2+fieldToRegister F6R2_FB10 = F6R2+fieldToRegister F6R2_FB11 = F6R2+fieldToRegister F6R2_FB12 = F6R2+fieldToRegister F6R2_FB13 = F6R2+fieldToRegister F6R2_FB14 = F6R2+fieldToRegister F6R2_FB15 = F6R2+fieldToRegister F6R2_FB16 = F6R2+fieldToRegister F6R2_FB17 = F6R2+fieldToRegister F6R2_FB18 = F6R2+fieldToRegister F6R2_FB19 = F6R2+fieldToRegister F6R2_FB2 = F6R2+fieldToRegister F6R2_FB20 = F6R2+fieldToRegister F6R2_FB21 = F6R2+fieldToRegister F6R2_FB22 = F6R2+fieldToRegister F6R2_FB23 = F6R2+fieldToRegister F6R2_FB24 = F6R2+fieldToRegister F6R2_FB25 = F6R2+fieldToRegister F6R2_FB26 = F6R2+fieldToRegister F6R2_FB27 = F6R2+fieldToRegister F6R2_FB28 = F6R2+fieldToRegister F6R2_FB29 = F6R2+fieldToRegister F6R2_FB3 = F6R2+fieldToRegister F6R2_FB30 = F6R2+fieldToRegister F6R2_FB31 = F6R2+fieldToRegister F6R2_FB4 = F6R2+fieldToRegister F6R2_FB5 = F6R2+fieldToRegister F6R2_FB6 = F6R2+fieldToRegister F6R2_FB7 = F6R2+fieldToRegister F6R2_FB8 = F6R2+fieldToRegister F6R2_FB9 = F6R2+fieldToRegister F7R1_FB0 = F7R1+fieldToRegister F7R1_FB1 = F7R1+fieldToRegister F7R1_FB10 = F7R1+fieldToRegister F7R1_FB11 = F7R1+fieldToRegister F7R1_FB12 = F7R1+fieldToRegister F7R1_FB13 = F7R1+fieldToRegister F7R1_FB14 = F7R1+fieldToRegister F7R1_FB15 = F7R1+fieldToRegister F7R1_FB16 = F7R1+fieldToRegister F7R1_FB17 = F7R1+fieldToRegister F7R1_FB18 = F7R1+fieldToRegister F7R1_FB19 = F7R1+fieldToRegister F7R1_FB2 = F7R1+fieldToRegister F7R1_FB20 = F7R1+fieldToRegister F7R1_FB21 = F7R1+fieldToRegister F7R1_FB22 = F7R1+fieldToRegister F7R1_FB23 = F7R1+fieldToRegister F7R1_FB24 = F7R1+fieldToRegister F7R1_FB25 = F7R1+fieldToRegister F7R1_FB26 = F7R1+fieldToRegister F7R1_FB27 = F7R1+fieldToRegister F7R1_FB28 = F7R1+fieldToRegister F7R1_FB29 = F7R1+fieldToRegister F7R1_FB3 = F7R1+fieldToRegister F7R1_FB30 = F7R1+fieldToRegister F7R1_FB31 = F7R1+fieldToRegister F7R1_FB4 = F7R1+fieldToRegister F7R1_FB5 = F7R1+fieldToRegister F7R1_FB6 = F7R1+fieldToRegister F7R1_FB7 = F7R1+fieldToRegister F7R1_FB8 = F7R1+fieldToRegister F7R1_FB9 = F7R1+fieldToRegister F7R2_FB0 = F7R2+fieldToRegister F7R2_FB1 = F7R2+fieldToRegister F7R2_FB10 = F7R2+fieldToRegister F7R2_FB11 = F7R2+fieldToRegister F7R2_FB12 = F7R2+fieldToRegister F7R2_FB13 = F7R2+fieldToRegister F7R2_FB14 = F7R2+fieldToRegister F7R2_FB15 = F7R2+fieldToRegister F7R2_FB16 = F7R2+fieldToRegister F7R2_FB17 = F7R2+fieldToRegister F7R2_FB18 = F7R2+fieldToRegister F7R2_FB19 = F7R2+fieldToRegister F7R2_FB2 = F7R2+fieldToRegister F7R2_FB20 = F7R2+fieldToRegister F7R2_FB21 = F7R2+fieldToRegister F7R2_FB22 = F7R2+fieldToRegister F7R2_FB23 = F7R2+fieldToRegister F7R2_FB24 = F7R2+fieldToRegister F7R2_FB25 = F7R2+fieldToRegister F7R2_FB26 = F7R2+fieldToRegister F7R2_FB27 = F7R2+fieldToRegister F7R2_FB28 = F7R2+fieldToRegister F7R2_FB29 = F7R2+fieldToRegister F7R2_FB3 = F7R2+fieldToRegister F7R2_FB30 = F7R2+fieldToRegister F7R2_FB31 = F7R2+fieldToRegister F7R2_FB4 = F7R2+fieldToRegister F7R2_FB5 = F7R2+fieldToRegister F7R2_FB6 = F7R2+fieldToRegister F7R2_FB7 = F7R2+fieldToRegister F7R2_FB8 = F7R2+fieldToRegister F7R2_FB9 = F7R2+fieldToRegister F8R1_FB0 = F8R1+fieldToRegister F8R1_FB1 = F8R1+fieldToRegister F8R1_FB10 = F8R1+fieldToRegister F8R1_FB11 = F8R1+fieldToRegister F8R1_FB12 = F8R1+fieldToRegister F8R1_FB13 = F8R1+fieldToRegister F8R1_FB14 = F8R1+fieldToRegister F8R1_FB15 = F8R1+fieldToRegister F8R1_FB16 = F8R1+fieldToRegister F8R1_FB17 = F8R1+fieldToRegister F8R1_FB18 = F8R1+fieldToRegister F8R1_FB19 = F8R1+fieldToRegister F8R1_FB2 = F8R1+fieldToRegister F8R1_FB20 = F8R1+fieldToRegister F8R1_FB21 = F8R1+fieldToRegister F8R1_FB22 = F8R1+fieldToRegister F8R1_FB23 = F8R1+fieldToRegister F8R1_FB24 = F8R1+fieldToRegister F8R1_FB25 = F8R1+fieldToRegister F8R1_FB26 = F8R1+fieldToRegister F8R1_FB27 = F8R1+fieldToRegister F8R1_FB28 = F8R1+fieldToRegister F8R1_FB29 = F8R1+fieldToRegister F8R1_FB3 = F8R1+fieldToRegister F8R1_FB30 = F8R1+fieldToRegister F8R1_FB31 = F8R1+fieldToRegister F8R1_FB4 = F8R1+fieldToRegister F8R1_FB5 = F8R1+fieldToRegister F8R1_FB6 = F8R1+fieldToRegister F8R1_FB7 = F8R1+fieldToRegister F8R1_FB8 = F8R1+fieldToRegister F8R1_FB9 = F8R1+fieldToRegister F8R2_FB0 = F8R2+fieldToRegister F8R2_FB1 = F8R2+fieldToRegister F8R2_FB10 = F8R2+fieldToRegister F8R2_FB11 = F8R2+fieldToRegister F8R2_FB12 = F8R2+fieldToRegister F8R2_FB13 = F8R2+fieldToRegister F8R2_FB14 = F8R2+fieldToRegister F8R2_FB15 = F8R2+fieldToRegister F8R2_FB16 = F8R2+fieldToRegister F8R2_FB17 = F8R2+fieldToRegister F8R2_FB18 = F8R2+fieldToRegister F8R2_FB19 = F8R2+fieldToRegister F8R2_FB2 = F8R2+fieldToRegister F8R2_FB20 = F8R2+fieldToRegister F8R2_FB21 = F8R2+fieldToRegister F8R2_FB22 = F8R2+fieldToRegister F8R2_FB23 = F8R2+fieldToRegister F8R2_FB24 = F8R2+fieldToRegister F8R2_FB25 = F8R2+fieldToRegister F8R2_FB26 = F8R2+fieldToRegister F8R2_FB27 = F8R2+fieldToRegister F8R2_FB28 = F8R2+fieldToRegister F8R2_FB29 = F8R2+fieldToRegister F8R2_FB3 = F8R2+fieldToRegister F8R2_FB30 = F8R2+fieldToRegister F8R2_FB31 = F8R2+fieldToRegister F8R2_FB4 = F8R2+fieldToRegister F8R2_FB5 = F8R2+fieldToRegister F8R2_FB6 = F8R2+fieldToRegister F8R2_FB7 = F8R2+fieldToRegister F8R2_FB8 = F8R2+fieldToRegister F8R2_FB9 = F8R2+fieldToRegister F9R1_FB0 = F9R1+fieldToRegister F9R1_FB1 = F9R1+fieldToRegister F9R1_FB10 = F9R1+fieldToRegister F9R1_FB11 = F9R1+fieldToRegister F9R1_FB12 = F9R1+fieldToRegister F9R1_FB13 = F9R1+fieldToRegister F9R1_FB14 = F9R1+fieldToRegister F9R1_FB15 = F9R1+fieldToRegister F9R1_FB16 = F9R1+fieldToRegister F9R1_FB17 = F9R1+fieldToRegister F9R1_FB18 = F9R1+fieldToRegister F9R1_FB19 = F9R1+fieldToRegister F9R1_FB2 = F9R1+fieldToRegister F9R1_FB20 = F9R1+fieldToRegister F9R1_FB21 = F9R1+fieldToRegister F9R1_FB22 = F9R1+fieldToRegister F9R1_FB23 = F9R1+fieldToRegister F9R1_FB24 = F9R1+fieldToRegister F9R1_FB25 = F9R1+fieldToRegister F9R1_FB26 = F9R1+fieldToRegister F9R1_FB27 = F9R1+fieldToRegister F9R1_FB28 = F9R1+fieldToRegister F9R1_FB29 = F9R1+fieldToRegister F9R1_FB3 = F9R1+fieldToRegister F9R1_FB30 = F9R1+fieldToRegister F9R1_FB31 = F9R1+fieldToRegister F9R1_FB4 = F9R1+fieldToRegister F9R1_FB5 = F9R1+fieldToRegister F9R1_FB6 = F9R1+fieldToRegister F9R1_FB7 = F9R1+fieldToRegister F9R1_FB8 = F9R1+fieldToRegister F9R1_FB9 = F9R1+fieldToRegister F9R2_FB0 = F9R2+fieldToRegister F9R2_FB1 = F9R2+fieldToRegister F9R2_FB10 = F9R2+fieldToRegister F9R2_FB11 = F9R2+fieldToRegister F9R2_FB12 = F9R2+fieldToRegister F9R2_FB13 = F9R2+fieldToRegister F9R2_FB14 = F9R2+fieldToRegister F9R2_FB15 = F9R2+fieldToRegister F9R2_FB16 = F9R2+fieldToRegister F9R2_FB17 = F9R2+fieldToRegister F9R2_FB18 = F9R2+fieldToRegister F9R2_FB19 = F9R2+fieldToRegister F9R2_FB2 = F9R2+fieldToRegister F9R2_FB20 = F9R2+fieldToRegister F9R2_FB21 = F9R2+fieldToRegister F9R2_FB22 = F9R2+fieldToRegister F9R2_FB23 = F9R2+fieldToRegister F9R2_FB24 = F9R2+fieldToRegister F9R2_FB25 = F9R2+fieldToRegister F9R2_FB26 = F9R2+fieldToRegister F9R2_FB27 = F9R2+fieldToRegister F9R2_FB28 = F9R2+fieldToRegister F9R2_FB29 = F9R2+fieldToRegister F9R2_FB3 = F9R2+fieldToRegister F9R2_FB30 = F9R2+fieldToRegister F9R2_FB31 = F9R2+fieldToRegister F9R2_FB4 = F9R2+fieldToRegister F9R2_FB5 = F9R2+fieldToRegister F9R2_FB6 = F9R2+fieldToRegister F9R2_FB7 = F9R2+fieldToRegister F9R2_FB8 = F9R2+fieldToRegister F9R2_FB9 = F9R2+fieldToRegister FIFO_FIFOData = FIFO+fieldToRegister FIFOCNT_FIF0COUNT = FIFOCNT+fieldToRegister FNR_FN = FNR+fieldToRegister FNR_LCK = FNR+fieldToRegister FNR_LSOF = FNR+fieldToRegister FNR_RXDM = FNR+fieldToRegister FNR_RXDP = FNR+fieldToRegister FTSR_TR0 = FTSR+fieldToRegister FTSR_TR1 = FTSR+fieldToRegister FTSR_TR10 = FTSR+fieldToRegister FTSR_TR11 = FTSR+fieldToRegister FTSR_TR12 = FTSR+fieldToRegister FTSR_TR13 = FTSR+fieldToRegister FTSR_TR14 = FTSR+fieldToRegister FTSR_TR15 = FTSR+fieldToRegister FTSR_TR16 = FTSR+fieldToRegister FTSR_TR17 = FTSR+fieldToRegister FTSR_TR18 = FTSR+fieldToRegister FTSR_TR2 = FTSR+fieldToRegister FTSR_TR3 = FTSR+fieldToRegister FTSR_TR4 = FTSR+fieldToRegister FTSR_TR5 = FTSR+fieldToRegister FTSR_TR6 = FTSR+fieldToRegister FTSR_TR7 = FTSR+fieldToRegister FTSR_TR8 = FTSR+fieldToRegister FTSR_TR9 = FTSR+fieldToRegister GTPR_GT = GTPR+fieldToRegister GTPR_PSC = GTPR+fieldToRegister HTR_HT = HTR+fieldToRegister I2SCFGR_CHLEN = I2SCFGR+fieldToRegister I2SCFGR_CKPOL = I2SCFGR+fieldToRegister I2SCFGR_DATLEN = I2SCFGR+fieldToRegister I2SCFGR_I2SCFG = I2SCFGR+fieldToRegister I2SCFGR_I2SE = I2SCFGR+fieldToRegister I2SCFGR_I2SMOD = I2SCFGR+fieldToRegister I2SCFGR_I2SSTD = I2SCFGR+fieldToRegister I2SCFGR_PCMSYNC = I2SCFGR+fieldToRegister I2SPR_I2SDIV = I2SPR+fieldToRegister I2SPR_MCKOE = I2SPR+fieldToRegister I2SPR_ODD = I2SPR+fieldToRegister IABR0_ACTIVE = IABR0+fieldToRegister IABR1_ACTIVE = IABR1+fieldToRegister ICER0_CLRENA = ICER0+fieldToRegister ICER1_CLRENA = ICER1+fieldToRegister ICPR0_CLRPEND = ICPR0+fieldToRegister ICPR1_CLRPEND = ICPR1+fieldToRegister ICR_CCRCFAILC = ICR+fieldToRegister ICR_CEATAENDC = ICR+fieldToRegister ICR_CMDRENDC = ICR+fieldToRegister ICR_CMDSENTC = ICR+fieldToRegister ICR_CTIMEOUTC = ICR+fieldToRegister ICR_DATAENDC = ICR+fieldToRegister ICR_DBCKENDC = ICR+fieldToRegister ICR_DCRCFAILC = ICR+fieldToRegister ICR_DTIMEOUTC = ICR+fieldToRegister ICR_RXOVERRC = ICR+fieldToRegister ICR_SDIOITC = ICR+fieldToRegister ICR_STBITERRC = ICR+fieldToRegister ICR_TXUNDERRC = ICR+fieldToRegister ICTR_INTLINESNUM = ICTR+fieldToRegister IDCODE_DEV_ID = IDCODE+fieldToRegister IDCODE_REV_ID = IDCODE+fieldToRegister IDR_IDR = IDR+fieldToRegister IDR_IDR0 = IDR+fieldToRegister IDR_IDR1 = IDR+fieldToRegister IDR_IDR10 = IDR+fieldToRegister IDR_IDR11 = IDR+fieldToRegister IDR_IDR12 = IDR+fieldToRegister IDR_IDR13 = IDR+fieldToRegister IDR_IDR14 = IDR+fieldToRegister IDR_IDR15 = IDR+fieldToRegister IDR_IDR2 = IDR+fieldToRegister IDR_IDR3 = IDR+fieldToRegister IDR_IDR4 = IDR+fieldToRegister IDR_IDR5 = IDR+fieldToRegister IDR_IDR6 = IDR+fieldToRegister IDR_IDR7 = IDR+fieldToRegister IDR_IDR8 = IDR+fieldToRegister IDR_IDR9 = IDR+fieldToRegister IFCR_CGIF1 = IFCR+fieldToRegister IFCR_CGIF2 = IFCR+fieldToRegister IFCR_CGIF3 = IFCR+fieldToRegister IFCR_CGIF4 = IFCR+fieldToRegister IFCR_CGIF5 = IFCR+fieldToRegister IFCR_CGIF6 = IFCR+fieldToRegister IFCR_CGIF7 = IFCR+fieldToRegister IFCR_CHTIF1 = IFCR+fieldToRegister IFCR_CHTIF2 = IFCR+fieldToRegister IFCR_CHTIF3 = IFCR+fieldToRegister IFCR_CHTIF4 = IFCR+fieldToRegister IFCR_CHTIF5 = IFCR+fieldToRegister IFCR_CHTIF6 = IFCR+fieldToRegister IFCR_CHTIF7 = IFCR+fieldToRegister IFCR_CTCIF1 = IFCR+fieldToRegister IFCR_CTCIF2 = IFCR+fieldToRegister IFCR_CTCIF3 = IFCR+fieldToRegister IFCR_CTCIF4 = IFCR+fieldToRegister IFCR_CTCIF5 = IFCR+fieldToRegister IFCR_CTCIF6 = IFCR+fieldToRegister IFCR_CTCIF7 = IFCR+fieldToRegister IFCR_CTEIF1 = IFCR+fieldToRegister IFCR_CTEIF2 = IFCR+fieldToRegister IFCR_CTEIF3 = IFCR+fieldToRegister IFCR_CTEIF4 = IFCR+fieldToRegister IFCR_CTEIF5 = IFCR+fieldToRegister IFCR_CTEIF6 = IFCR+fieldToRegister IFCR_CTEIF7 = IFCR+fieldToRegister IMR_MR0 = IMR+fieldToRegister IMR_MR1 = IMR+fieldToRegister IMR_MR10 = IMR+fieldToRegister IMR_MR11 = IMR+fieldToRegister IMR_MR12 = IMR+fieldToRegister IMR_MR13 = IMR+fieldToRegister IMR_MR14 = IMR+fieldToRegister IMR_MR15 = IMR+fieldToRegister IMR_MR16 = IMR+fieldToRegister IMR_MR17 = IMR+fieldToRegister IMR_MR18 = IMR+fieldToRegister IMR_MR2 = IMR+fieldToRegister IMR_MR3 = IMR+fieldToRegister IMR_MR4 = IMR+fieldToRegister IMR_MR5 = IMR+fieldToRegister IMR_MR6 = IMR+fieldToRegister IMR_MR7 = IMR+fieldToRegister IMR_MR8 = IMR+fieldToRegister IMR_MR9 = IMR+fieldToRegister IPR0_IPR_N0 = IPR0+fieldToRegister IPR0_IPR_N1 = IPR0+fieldToRegister IPR0_IPR_N2 = IPR0+fieldToRegister IPR0_IPR_N3 = IPR0+fieldToRegister IPR1_IPR_N0 = IPR1+fieldToRegister IPR1_IPR_N1 = IPR1+fieldToRegister IPR1_IPR_N2 = IPR1+fieldToRegister IPR1_IPR_N3 = IPR1+fieldToRegister IPR10_IPR_N0 = IPR10+fieldToRegister IPR10_IPR_N1 = IPR10+fieldToRegister IPR10_IPR_N2 = IPR10+fieldToRegister IPR10_IPR_N3 = IPR10+fieldToRegister IPR11_IPR_N0 = IPR11+fieldToRegister IPR11_IPR_N1 = IPR11+fieldToRegister IPR11_IPR_N2 = IPR11+fieldToRegister IPR11_IPR_N3 = IPR11+fieldToRegister IPR12_IPR_N0 = IPR12+fieldToRegister IPR12_IPR_N1 = IPR12+fieldToRegister IPR12_IPR_N2 = IPR12+fieldToRegister IPR12_IPR_N3 = IPR12+fieldToRegister IPR13_IPR_N0 = IPR13+fieldToRegister IPR13_IPR_N1 = IPR13+fieldToRegister IPR13_IPR_N2 = IPR13+fieldToRegister IPR13_IPR_N3 = IPR13+fieldToRegister IPR14_IPR_N0 = IPR14+fieldToRegister IPR14_IPR_N1 = IPR14+fieldToRegister IPR14_IPR_N2 = IPR14+fieldToRegister IPR14_IPR_N3 = IPR14+fieldToRegister IPR2_IPR_N0 = IPR2+fieldToRegister IPR2_IPR_N1 = IPR2+fieldToRegister IPR2_IPR_N2 = IPR2+fieldToRegister IPR2_IPR_N3 = IPR2+fieldToRegister IPR3_IPR_N0 = IPR3+fieldToRegister IPR3_IPR_N1 = IPR3+fieldToRegister IPR3_IPR_N2 = IPR3+fieldToRegister IPR3_IPR_N3 = IPR3+fieldToRegister IPR4_IPR_N0 = IPR4+fieldToRegister IPR4_IPR_N1 = IPR4+fieldToRegister IPR4_IPR_N2 = IPR4+fieldToRegister IPR4_IPR_N3 = IPR4+fieldToRegister IPR5_IPR_N0 = IPR5+fieldToRegister IPR5_IPR_N1 = IPR5+fieldToRegister IPR5_IPR_N2 = IPR5+fieldToRegister IPR5_IPR_N3 = IPR5+fieldToRegister IPR6_IPR_N0 = IPR6+fieldToRegister IPR6_IPR_N1 = IPR6+fieldToRegister IPR6_IPR_N2 = IPR6+fieldToRegister IPR6_IPR_N3 = IPR6+fieldToRegister IPR7_IPR_N0 = IPR7+fieldToRegister IPR7_IPR_N1 = IPR7+fieldToRegister IPR7_IPR_N2 = IPR7+fieldToRegister IPR7_IPR_N3 = IPR7+fieldToRegister IPR8_IPR_N0 = IPR8+fieldToRegister IPR8_IPR_N1 = IPR8+fieldToRegister IPR8_IPR_N2 = IPR8+fieldToRegister IPR8_IPR_N3 = IPR8+fieldToRegister IPR9_IPR_N0 = IPR9+fieldToRegister IPR9_IPR_N1 = IPR9+fieldToRegister IPR9_IPR_N2 = IPR9+fieldToRegister IPR9_IPR_N3 = IPR9+fieldToRegister ISER0_SETENA = ISER0+fieldToRegister ISER1_SETENA = ISER1+fieldToRegister ISPR0_SETPEND = ISPR0+fieldToRegister ISPR1_SETPEND = ISPR1+fieldToRegister ISR_GIF1 = ISR+fieldToRegister ISR_GIF2 = ISR+fieldToRegister ISR_GIF3 = ISR+fieldToRegister ISR_GIF4 = ISR+fieldToRegister ISR_GIF5 = ISR+fieldToRegister ISR_GIF6 = ISR+fieldToRegister ISR_GIF7 = ISR+fieldToRegister ISR_HTIF1 = ISR+fieldToRegister ISR_HTIF2 = ISR+fieldToRegister ISR_HTIF3 = ISR+fieldToRegister ISR_HTIF4 = ISR+fieldToRegister ISR_HTIF5 = ISR+fieldToRegister ISR_HTIF6 = ISR+fieldToRegister ISR_HTIF7 = ISR+fieldToRegister ISR_TCIF1 = ISR+fieldToRegister ISR_TCIF2 = ISR+fieldToRegister ISR_TCIF3 = ISR+fieldToRegister ISR_TCIF4 = ISR+fieldToRegister ISR_TCIF5 = ISR+fieldToRegister ISR_TCIF6 = ISR+fieldToRegister ISR_TCIF7 = ISR+fieldToRegister ISR_TEIF1 = ISR+fieldToRegister ISR_TEIF2 = ISR+fieldToRegister ISR_TEIF3 = ISR+fieldToRegister ISR_TEIF4 = ISR+fieldToRegister ISR_TEIF5 = ISR+fieldToRegister ISR_TEIF6 = ISR+fieldToRegister ISR_TEIF7 = ISR+fieldToRegister ISTR_CTR = ISTR+fieldToRegister ISTR_DIR = ISTR+fieldToRegister ISTR_EP_ID = ISTR+fieldToRegister ISTR_ERR = ISTR+fieldToRegister ISTR_ESOF = ISTR+fieldToRegister ISTR_PMAOVR = ISTR+fieldToRegister ISTR_RESET = ISTR+fieldToRegister ISTR_SOF = ISTR+fieldToRegister ISTR_SUSP = ISTR+fieldToRegister ISTR_WKUP = ISTR+fieldToRegister JDR1_JDATA = JDR1+fieldToRegister JDR2_JDATA = JDR2+fieldToRegister JDR3_JDATA = JDR3+fieldToRegister JDR4_JDATA = JDR4+fieldToRegister JOFR1_JOFFSET1 = JOFR1+fieldToRegister JOFR2_JOFFSET2 = JOFR2+fieldToRegister JOFR3_JOFFSET3 = JOFR3+fieldToRegister JOFR4_JOFFSET4 = JOFR4+fieldToRegister JSQR_JL = JSQR+fieldToRegister JSQR_JSQ1 = JSQR+fieldToRegister JSQR_JSQ2 = JSQR+fieldToRegister JSQR_JSQ3 = JSQR+fieldToRegister JSQR_JSQ4 = JSQR+fieldToRegister KEYR_KEY = KEYR+fieldToRegister KR_KEY = KR+fieldToRegister LCKR_LCK0 = LCKR+fieldToRegister LCKR_LCK1 = LCKR+fieldToRegister LCKR_LCK10 = LCKR+fieldToRegister LCKR_LCK11 = LCKR+fieldToRegister LCKR_LCK12 = LCKR+fieldToRegister LCKR_LCK13 = LCKR+fieldToRegister LCKR_LCK14 = LCKR+fieldToRegister LCKR_LCK15 = LCKR+fieldToRegister LCKR_LCK2 = LCKR+fieldToRegister LCKR_LCK3 = LCKR+fieldToRegister LCKR_LCK4 = LCKR+fieldToRegister LCKR_LCK5 = LCKR+fieldToRegister LCKR_LCK6 = LCKR+fieldToRegister LCKR_LCK7 = LCKR+fieldToRegister LCKR_LCK8 = LCKR+fieldToRegister LCKR_LCK9 = LCKR+fieldToRegister LCKR_LCKK = LCKR+fieldToRegister LTR_LT = LTR+fieldToRegister MAPR_ADC1_ETRGINJ_REMAP = MAPR+fieldToRegister MAPR_ADC1_ETRGREG_REMAP = MAPR+fieldToRegister MAPR_ADC2_ETRGINJ_REMAP = MAPR+fieldToRegister MAPR_ADC2_ETRGREG_REMAP = MAPR+fieldToRegister MAPR_CAN_REMAP = MAPR+fieldToRegister MAPR_I2C1_REMAP = MAPR+fieldToRegister MAPR_PD01_REMAP = MAPR+fieldToRegister MAPR_SPI1_REMAP = MAPR+fieldToRegister MAPR_SWJ_CFG = MAPR+fieldToRegister MAPR_TIM1_REMAP = MAPR+fieldToRegister MAPR_TIM2_REMAP = MAPR+fieldToRegister MAPR_TIM3_REMAP = MAPR+fieldToRegister MAPR_TIM4_REMAP = MAPR+fieldToRegister MAPR_TIM5CH4_IREMAP = MAPR+fieldToRegister MAPR_USART1_REMAP = MAPR+fieldToRegister MAPR_USART2_REMAP = MAPR+fieldToRegister MAPR_USART3_REMAP = MAPR+fieldToRegister MAPR2_FSMC_NADV = MAPR2+fieldToRegister MAPR2_TIM10_REMAP = MAPR2+fieldToRegister MAPR2_TIM11_REMAP = MAPR2+fieldToRegister MAPR2_TIM13_REMAP = MAPR2+fieldToRegister MAPR2_TIM14_REMAP = MAPR2+fieldToRegister MAPR2_TIM9_REMAP = MAPR2+fieldToRegister MASK_CCRCFAILIE = MASK+fieldToRegister MASK_CEATENDIE = MASK+fieldToRegister MASK_CMDACTIE = MASK+fieldToRegister MASK_CMDRENDIE = MASK+fieldToRegister MASK_CMDSENTIE = MASK+fieldToRegister MASK_CTIMEOUTIE = MASK+fieldToRegister MASK_DATAENDIE = MASK+fieldToRegister MASK_DBACKENDIE = MASK+fieldToRegister MASK_DCRCFAILIE = MASK+fieldToRegister MASK_DTIMEOUTIE = MASK+fieldToRegister MASK_RXACTIE = MASK+fieldToRegister MASK_RXDAVLIE = MASK+fieldToRegister MASK_RXFIFOEIE = MASK+fieldToRegister MASK_RXFIFOFIE = MASK+fieldToRegister MASK_RXFIFOHFIE = MASK+fieldToRegister MASK_RXOVERRIE = MASK+fieldToRegister MASK_SDIOITIE = MASK+fieldToRegister MASK_STBITERRIE = MASK+fieldToRegister MASK_TXACTIE = MASK+fieldToRegister MASK_TXDAVLIE = MASK+fieldToRegister MASK_TXFIFOEIE = MASK+fieldToRegister MASK_TXFIFOFIE = MASK+fieldToRegister MASK_TXFIFOHEIE = MASK+fieldToRegister MASK_TXUNDERRIE = MASK+fieldToRegister OAR1_ADD0 = OAR1+fieldToRegister OAR1_ADD10 = OAR1+fieldToRegister OAR1_ADD7 = OAR1+fieldToRegister OAR1_ADDMODE = OAR1+fieldToRegister OAR2_ADD2 = OAR2+fieldToRegister OAR2_ENDUAL = OAR2+fieldToRegister OBR_Data0 = OBR+fieldToRegister OBR_Data1 = OBR+fieldToRegister OBR_OPTERR = OBR+fieldToRegister OBR_RDPRT = OBR+fieldToRegister OBR_WDG_SW = OBR+fieldToRegister OBR_nRST_STDBY = OBR+fieldToRegister OBR_nRST_STOP = OBR+fieldToRegister ODR_ODR0 = ODR+fieldToRegister ODR_ODR1 = ODR+fieldToRegister ODR_ODR10 = ODR+fieldToRegister ODR_ODR11 = ODR+fieldToRegister ODR_ODR12 = ODR+fieldToRegister ODR_ODR13 = ODR+fieldToRegister ODR_ODR14 = ODR+fieldToRegister ODR_ODR15 = ODR+fieldToRegister ODR_ODR2 = ODR+fieldToRegister ODR_ODR3 = ODR+fieldToRegister ODR_ODR4 = ODR+fieldToRegister ODR_ODR5 = ODR+fieldToRegister ODR_ODR6 = ODR+fieldToRegister ODR_ODR7 = ODR+fieldToRegister ODR_ODR8 = ODR+fieldToRegister ODR_ODR9 = ODR+fieldToRegister OPTKEYR_OPTKEY = OPTKEYR+fieldToRegister PATT2_ATTHIZx = PATT2+fieldToRegister PATT2_ATTHOLDx = PATT2+fieldToRegister PATT2_ATTSETx = PATT2+fieldToRegister PATT2_ATTWAITx = PATT2+fieldToRegister PATT3_ATTHIZx = PATT3+fieldToRegister PATT3_ATTHOLDx = PATT3+fieldToRegister PATT3_ATTSETx = PATT3+fieldToRegister PATT3_ATTWAITx = PATT3+fieldToRegister PATT4_ATTHIZx = PATT4+fieldToRegister PATT4_ATTHOLDx = PATT4+fieldToRegister PATT4_ATTSETx = PATT4+fieldToRegister PATT4_ATTWAITx = PATT4+fieldToRegister PCR2_ECCEN = PCR2+fieldToRegister PCR2_ECCPS = PCR2+fieldToRegister PCR2_PBKEN = PCR2+fieldToRegister PCR2_PTYP = PCR2+fieldToRegister PCR2_PWAITEN = PCR2+fieldToRegister PCR2_PWID = PCR2+fieldToRegister PCR2_TAR = PCR2+fieldToRegister PCR2_TCLR = PCR2+fieldToRegister PCR3_ECCEN = PCR3+fieldToRegister PCR3_ECCPS = PCR3+fieldToRegister PCR3_PBKEN = PCR3+fieldToRegister PCR3_PTYP = PCR3+fieldToRegister PCR3_PWAITEN = PCR3+fieldToRegister PCR3_PWID = PCR3+fieldToRegister PCR3_TAR = PCR3+fieldToRegister PCR3_TCLR = PCR3+fieldToRegister PCR4_ECCEN = PCR4+fieldToRegister PCR4_ECCPS = PCR4+fieldToRegister PCR4_PBKEN = PCR4+fieldToRegister PCR4_PTYP = PCR4+fieldToRegister PCR4_PWAITEN = PCR4+fieldToRegister PCR4_PWID = PCR4+fieldToRegister PCR4_TAR = PCR4+fieldToRegister PCR4_TCLR = PCR4+fieldToRegister PIO4_IOHIZx = PIO4+fieldToRegister PIO4_IOHOLDx = PIO4+fieldToRegister PIO4_IOSETx = PIO4+fieldToRegister PIO4_IOWAITx = PIO4+fieldToRegister PMEM2_MEMHIZx = PMEM2+fieldToRegister PMEM2_MEMHOLDx = PMEM2+fieldToRegister PMEM2_MEMSETx = PMEM2+fieldToRegister PMEM2_MEMWAITx = PMEM2+fieldToRegister PMEM3_MEMHIZx = PMEM3+fieldToRegister PMEM3_MEMHOLDx = PMEM3+fieldToRegister PMEM3_MEMSETx = PMEM3+fieldToRegister PMEM3_MEMWAITx = PMEM3+fieldToRegister PMEM4_MEMHIZx = PMEM4+fieldToRegister PMEM4_MEMHOLDx = PMEM4+fieldToRegister PMEM4_MEMSETx = PMEM4+fieldToRegister PMEM4_MEMWAITx = PMEM4+fieldToRegister POWER_PWRCTRL = POWER+fieldToRegister PR_PR = PR+fieldToRegister PR_PR0 = PR+fieldToRegister PR_PR1 = PR+fieldToRegister PR_PR10 = PR+fieldToRegister PR_PR11 = PR+fieldToRegister PR_PR12 = PR+fieldToRegister PR_PR13 = PR+fieldToRegister PR_PR14 = PR+fieldToRegister PR_PR15 = PR+fieldToRegister PR_PR16 = PR+fieldToRegister PR_PR17 = PR+fieldToRegister PR_PR18 = PR+fieldToRegister PR_PR2 = PR+fieldToRegister PR_PR3 = PR+fieldToRegister PR_PR4 = PR+fieldToRegister PR_PR5 = PR+fieldToRegister PR_PR6 = PR+fieldToRegister PR_PR7 = PR+fieldToRegister PR_PR8 = PR+fieldToRegister PR_PR9 = PR+fieldToRegister PRLH_PRLH = PRLH+fieldToRegister PRLL_PRLL = PRLL+fieldToRegister PSC_PSC = PSC+fieldToRegister RCR_REP = RCR+fieldToRegister RESP2_CARDSTATUS2 = RESP2+fieldToRegister RESP3_CARDSTATUS3 = RESP3+fieldToRegister RESP4_CARDSTATUS4 = RESP4+fieldToRegister RESPCMD_RESPCMD = RESPCMD+fieldToRegister RESPI1_CARDSTATUS1 = RESPI1+fieldToRegister RLR_RL = RLR+fieldToRegister RTCCR_ASOE = RTCCR+fieldToRegister RTCCR_ASOS = RTCCR+fieldToRegister RTCCR_CAL = RTCCR+fieldToRegister RTCCR_CCO = RTCCR+fieldToRegister RTSR_TR0 = RTSR+fieldToRegister RTSR_TR1 = RTSR+fieldToRegister RTSR_TR10 = RTSR+fieldToRegister RTSR_TR11 = RTSR+fieldToRegister RTSR_TR12 = RTSR+fieldToRegister RTSR_TR13 = RTSR+fieldToRegister RTSR_TR14 = RTSR+fieldToRegister RTSR_TR15 = RTSR+fieldToRegister RTSR_TR16 = RTSR+fieldToRegister RTSR_TR17 = RTSR+fieldToRegister RTSR_TR18 = RTSR+fieldToRegister RTSR_TR2 = RTSR+fieldToRegister RTSR_TR3 = RTSR+fieldToRegister RTSR_TR4 = RTSR+fieldToRegister RTSR_TR5 = RTSR+fieldToRegister RTSR_TR6 = RTSR+fieldToRegister RTSR_TR7 = RTSR+fieldToRegister RTSR_TR8 = RTSR+fieldToRegister RTSR_TR9 = RTSR+fieldToRegister RXCRCR_RxCRC = RXCRCR+fieldToRegister SMCR_ECE = SMCR+fieldToRegister SMCR_ETF = SMCR+fieldToRegister SMCR_ETP = SMCR+fieldToRegister SMCR_ETPS = SMCR+fieldToRegister SMCR_MSM = SMCR+fieldToRegister SMCR_SMS = SMCR+fieldToRegister SMCR_TS = SMCR+fieldToRegister SMPR1_SMP10 = SMPR1+fieldToRegister SMPR1_SMP11 = SMPR1+fieldToRegister SMPR1_SMP12 = SMPR1+fieldToRegister SMPR1_SMP13 = SMPR1+fieldToRegister SMPR1_SMP14 = SMPR1+fieldToRegister SMPR1_SMP15 = SMPR1+fieldToRegister SMPR1_SMP16 = SMPR1+fieldToRegister SMPR1_SMP17 = SMPR1+fieldToRegister SMPR2_SMP0 = SMPR2+fieldToRegister SMPR2_SMP1 = SMPR2+fieldToRegister SMPR2_SMP2 = SMPR2+fieldToRegister SMPR2_SMP3 = SMPR2+fieldToRegister SMPR2_SMP4 = SMPR2+fieldToRegister SMPR2_SMP5 = SMPR2+fieldToRegister SMPR2_SMP6 = SMPR2+fieldToRegister SMPR2_SMP7 = SMPR2+fieldToRegister SMPR2_SMP8 = SMPR2+fieldToRegister SMPR2_SMP9 = SMPR2+fieldToRegister SQR1_L = SQR1+fieldToRegister SQR1_SQ13 = SQR1+fieldToRegister SQR1_SQ14 = SQR1+fieldToRegister SQR1_SQ15 = SQR1+fieldToRegister SQR1_SQ16 = SQR1+fieldToRegister SQR2_SQ10 = SQR2+fieldToRegister SQR2_SQ11 = SQR2+fieldToRegister SQR2_SQ12 = SQR2+fieldToRegister SQR2_SQ7 = SQR2+fieldToRegister SQR2_SQ8 = SQR2+fieldToRegister SQR2_SQ9 = SQR2+fieldToRegister SQR3_SQ1 = SQR3+fieldToRegister SQR3_SQ2 = SQR3+fieldToRegister SQR3_SQ3 = SQR3+fieldToRegister SQR3_SQ4 = SQR3+fieldToRegister SQR3_SQ5 = SQR3+fieldToRegister SQR3_SQ6 = SQR3+fieldToRegister SR_AWD = SR+fieldToRegister SR_BIF = SR+fieldToRegister SR_BSY = SR+fieldToRegister SR_CC1IF = SR+fieldToRegister SR_CC1OF = SR+fieldToRegister SR_CC2IF = SR+fieldToRegister SR_CC2OF = SR+fieldToRegister SR_CC3IF = SR+fieldToRegister SR_CC3OF = SR+fieldToRegister SR_CC4IF = SR+fieldToRegister SR_CC4OF = SR+fieldToRegister SR_CHSIDE = SR+fieldToRegister SR_COMIF = SR+fieldToRegister SR_CRCERR = SR+fieldToRegister SR_CTS = SR+fieldToRegister SR_EOC = SR+fieldToRegister SR_EOP = SR+fieldToRegister SR_EWI = SR+fieldToRegister SR_FE = SR+fieldToRegister SR_IDLE = SR+fieldToRegister SR_JEOC = SR+fieldToRegister SR_JSTRT = SR+fieldToRegister SR_LBD = SR+fieldToRegister SR_MODF = SR+fieldToRegister SR_NE = SR+fieldToRegister SR_ORE = SR+fieldToRegister SR_OVR = SR+fieldToRegister SR_PE = SR+fieldToRegister SR_PGERR = SR+fieldToRegister SR_PVU = SR+fieldToRegister SR_RVU = SR+fieldToRegister SR_RXNE = SR+fieldToRegister SR_STRT = SR+fieldToRegister SR_TC = SR+fieldToRegister SR_TIF = SR+fieldToRegister SR_TXE = SR+fieldToRegister SR_UDR = SR+fieldToRegister SR_UIF = SR+fieldToRegister SR_WRPRTERR = SR+fieldToRegister SR1_ADD10 = SR1+fieldToRegister SR1_ADDR = SR1+fieldToRegister SR1_AF = SR1+fieldToRegister SR1_ARLO = SR1+fieldToRegister SR1_BERR = SR1+fieldToRegister SR1_BTF = SR1+fieldToRegister SR1_OVR = SR1+fieldToRegister SR1_PECERR = SR1+fieldToRegister SR1_RxNE = SR1+fieldToRegister SR1_SB = SR1+fieldToRegister SR1_SMBALERT = SR1+fieldToRegister SR1_STOPF = SR1+fieldToRegister SR1_TIMEOUT = SR1+fieldToRegister SR1_TxE = SR1+fieldToRegister SR2_BUSY = SR2+fieldToRegister SR2_DUALF = SR2+fieldToRegister SR2_FEMPT = SR2+fieldToRegister SR2_GENCALL = SR2+fieldToRegister SR2_IFEN = SR2+fieldToRegister SR2_IFS = SR2+fieldToRegister SR2_ILEN = SR2+fieldToRegister SR2_ILS = SR2+fieldToRegister SR2_IREN = SR2+fieldToRegister SR2_IRS = SR2+fieldToRegister SR2_MSL = SR2+fieldToRegister SR2_PEC = SR2+fieldToRegister SR2_SMBDEFAULT = SR2+fieldToRegister SR2_SMBHOST = SR2+fieldToRegister SR2_TRA = SR2+fieldToRegister SR3_FEMPT = SR3+fieldToRegister SR3_IFEN = SR3+fieldToRegister SR3_IFS = SR3+fieldToRegister SR3_ILEN = SR3+fieldToRegister SR3_ILS = SR3+fieldToRegister SR3_IREN = SR3+fieldToRegister SR3_IRS = SR3+fieldToRegister SR4_FEMPT = SR4+fieldToRegister SR4_IFEN = SR4+fieldToRegister SR4_IFS = SR4+fieldToRegister SR4_ILEN = SR4+fieldToRegister SR4_ILS = SR4+fieldToRegister SR4_IREN = SR4+fieldToRegister SR4_IRS = SR4+fieldToRegister STA_CCRCFAIL = STA+fieldToRegister STA_CEATAEND = STA+fieldToRegister STA_CMDACT = STA+fieldToRegister STA_CMDREND = STA+fieldToRegister STA_CMDSENT = STA+fieldToRegister STA_CTIMEOUT = STA+fieldToRegister STA_DATAEND = STA+fieldToRegister STA_DBCKEND = STA+fieldToRegister STA_DCRCFAIL = STA+fieldToRegister STA_DTIMEOUT = STA+fieldToRegister STA_RXACT = STA+fieldToRegister STA_RXDAVL = STA+fieldToRegister STA_RXFIFOE = STA+fieldToRegister STA_RXFIFOF = STA+fieldToRegister STA_RXFIFOHF = STA+fieldToRegister STA_RXOVERR = STA+fieldToRegister STA_SDIOIT = STA+fieldToRegister STA_STBITERR = STA+fieldToRegister STA_TXACT = STA+fieldToRegister STA_TXDAVL = STA+fieldToRegister STA_TXFIFOE = STA+fieldToRegister STA_TXFIFOF = STA+fieldToRegister STA_TXFIFOHE = STA+fieldToRegister STA_TXUNDERR = STA+fieldToRegister STIR_INTID = STIR+fieldToRegister SWIER_SWIER0 = SWIER+fieldToRegister SWIER_SWIER1 = SWIER+fieldToRegister SWIER_SWIER10 = SWIER+fieldToRegister SWIER_SWIER11 = SWIER+fieldToRegister SWIER_SWIER12 = SWIER+fieldToRegister SWIER_SWIER13 = SWIER+fieldToRegister SWIER_SWIER14 = SWIER+fieldToRegister SWIER_SWIER15 = SWIER+fieldToRegister SWIER_SWIER16 = SWIER+fieldToRegister SWIER_SWIER17 = SWIER+fieldToRegister SWIER_SWIER18 = SWIER+fieldToRegister SWIER_SWIER2 = SWIER+fieldToRegister SWIER_SWIER3 = SWIER+fieldToRegister SWIER_SWIER4 = SWIER+fieldToRegister SWIER_SWIER5 = SWIER+fieldToRegister SWIER_SWIER6 = SWIER+fieldToRegister SWIER_SWIER7 = SWIER+fieldToRegister SWIER_SWIER8 = SWIER+fieldToRegister SWIER_SWIER9 = SWIER+fieldToRegister SWTRIGR_SWTRIG1 = SWTRIGR+fieldToRegister SWTRIGR_SWTRIG2 = SWTRIGR+fieldToRegister TRISE_TRISE = TRISE+fieldToRegister TXCRCR_TxCRC = TXCRCR+fieldToRegister WRPR_WRP = WRPR++fieldBitOffset :: Field -> Int+fieldBitOffset ACR_HLFCYA = 3+fieldBitOffset ACR_LATENCY = 0+fieldBitOffset ACR_PRFTBE = 4+fieldBitOffset ACR_PRFTBS = 5+fieldBitOffset AHBENR_CRCEN = 6+fieldBitOffset AHBENR_DMA1EN = 0+fieldBitOffset AHBENR_DMA2EN = 1+fieldBitOffset AHBENR_FLITFEN = 4+fieldBitOffset AHBENR_FSMCEN = 8+fieldBitOffset AHBENR_SDIOEN = 10+fieldBitOffset AHBENR_SRAMEN = 2+fieldBitOffset ALRH_ALRH = 0+fieldBitOffset ALRL_ALRL = 0+fieldBitOffset APB1ENR_BKPEN = 27+fieldBitOffset APB1ENR_CANEN = 25+fieldBitOffset APB1ENR_DACEN = 29+fieldBitOffset APB1ENR_I2C1EN = 21+fieldBitOffset APB1ENR_I2C2EN = 22+fieldBitOffset APB1ENR_PWREN = 28+fieldBitOffset APB1ENR_SPI2EN = 14+fieldBitOffset APB1ENR_SPI3EN = 15+fieldBitOffset APB1ENR_TIM12EN = 6+fieldBitOffset APB1ENR_TIM13EN = 7+fieldBitOffset APB1ENR_TIM14EN = 8+fieldBitOffset APB1ENR_TIM2EN = 0+fieldBitOffset APB1ENR_TIM3EN = 1+fieldBitOffset APB1ENR_TIM4EN = 2+fieldBitOffset APB1ENR_TIM5EN = 3+fieldBitOffset APB1ENR_TIM6EN = 4+fieldBitOffset APB1ENR_TIM7EN = 5+fieldBitOffset APB1ENR_UART4EN = 19+fieldBitOffset APB1ENR_UART5EN = 20+fieldBitOffset APB1ENR_USART2EN = 17+fieldBitOffset APB1ENR_USART3EN = 18+fieldBitOffset APB1ENR_USBEN = 23+fieldBitOffset APB1ENR_WWDGEN = 11+fieldBitOffset APB1RSTR_BKPRST = 27+fieldBitOffset APB1RSTR_CANRST = 25+fieldBitOffset APB1RSTR_DACRST = 29+fieldBitOffset APB1RSTR_I2C1RST = 21+fieldBitOffset APB1RSTR_I2C2RST = 22+fieldBitOffset APB1RSTR_PWRRST = 28+fieldBitOffset APB1RSTR_SPI2RST = 14+fieldBitOffset APB1RSTR_SPI3RST = 15+fieldBitOffset APB1RSTR_TIM12RST = 6+fieldBitOffset APB1RSTR_TIM13RST = 7+fieldBitOffset APB1RSTR_TIM14RST = 8+fieldBitOffset APB1RSTR_TIM2RST = 0+fieldBitOffset APB1RSTR_TIM3RST = 1+fieldBitOffset APB1RSTR_TIM4RST = 2+fieldBitOffset APB1RSTR_TIM5RST = 3+fieldBitOffset APB1RSTR_TIM6RST = 4+fieldBitOffset APB1RSTR_TIM7RST = 5+fieldBitOffset APB1RSTR_UART4RST = 19+fieldBitOffset APB1RSTR_UART5RST = 20+fieldBitOffset APB1RSTR_USART2RST = 17+fieldBitOffset APB1RSTR_USART3RST = 18+fieldBitOffset APB1RSTR_USBRST = 23+fieldBitOffset APB1RSTR_WWDGRST = 11+fieldBitOffset APB2ENR_ADC1EN = 9+fieldBitOffset APB2ENR_ADC2EN = 10+fieldBitOffset APB2ENR_ADC3EN = 15+fieldBitOffset APB2ENR_AFIOEN = 0+fieldBitOffset APB2ENR_IOPAEN = 2+fieldBitOffset APB2ENR_IOPBEN = 3+fieldBitOffset APB2ENR_IOPCEN = 4+fieldBitOffset APB2ENR_IOPDEN = 5+fieldBitOffset APB2ENR_IOPEEN = 6+fieldBitOffset APB2ENR_IOPFEN = 7+fieldBitOffset APB2ENR_IOPGEN = 8+fieldBitOffset APB2ENR_SPI1EN = 12+fieldBitOffset APB2ENR_TIM10EN = 20+fieldBitOffset APB2ENR_TIM11EN = 21+fieldBitOffset APB2ENR_TIM1EN = 11+fieldBitOffset APB2ENR_TIM8EN = 13+fieldBitOffset APB2ENR_TIM9EN = 19+fieldBitOffset APB2ENR_USART1EN = 14+fieldBitOffset APB2RSTR_ADC1RST = 9+fieldBitOffset APB2RSTR_ADC2RST = 10+fieldBitOffset APB2RSTR_ADC3RST = 15+fieldBitOffset APB2RSTR_AFIORST = 0+fieldBitOffset APB2RSTR_IOPARST = 2+fieldBitOffset APB2RSTR_IOPBRST = 3+fieldBitOffset APB2RSTR_IOPCRST = 4+fieldBitOffset APB2RSTR_IOPDRST = 5+fieldBitOffset APB2RSTR_IOPERST = 6+fieldBitOffset APB2RSTR_IOPFRST = 7+fieldBitOffset APB2RSTR_IOPGRST = 8+fieldBitOffset APB2RSTR_SPI1RST = 12+fieldBitOffset APB2RSTR_TIM10RST = 20+fieldBitOffset APB2RSTR_TIM11RST = 21+fieldBitOffset APB2RSTR_TIM1RST = 11+fieldBitOffset APB2RSTR_TIM8RST = 13+fieldBitOffset APB2RSTR_TIM9RST = 19+fieldBitOffset APB2RSTR_USART1RST = 14+fieldBitOffset AR_FAR = 0+fieldBitOffset ARG_CMDARG = 0+fieldBitOffset ARR_ARR = 0+fieldBitOffset BCR1_ASYNCWAIT = 15+fieldBitOffset BCR1_BURSTEN = 8+fieldBitOffset BCR1_CBURSTRW = 19+fieldBitOffset BCR1_EXTMOD = 14+fieldBitOffset BCR1_FACCEN = 6+fieldBitOffset BCR1_MBKEN = 0+fieldBitOffset BCR1_MTYP = 2+fieldBitOffset BCR1_MUXEN = 1+fieldBitOffset BCR1_MWID = 4+fieldBitOffset BCR1_WAITCFG = 11+fieldBitOffset BCR1_WAITEN = 13+fieldBitOffset BCR1_WAITPOL = 9+fieldBitOffset BCR1_WREN = 12+fieldBitOffset BCR2_ASYNCWAIT = 15+fieldBitOffset BCR2_BURSTEN = 8+fieldBitOffset BCR2_CBURSTRW = 19+fieldBitOffset BCR2_EXTMOD = 14+fieldBitOffset BCR2_FACCEN = 6+fieldBitOffset BCR2_MBKEN = 0+fieldBitOffset BCR2_MTYP = 2+fieldBitOffset BCR2_MUXEN = 1+fieldBitOffset BCR2_MWID = 4+fieldBitOffset BCR2_WAITCFG = 11+fieldBitOffset BCR2_WAITEN = 13+fieldBitOffset BCR2_WAITPOL = 9+fieldBitOffset BCR2_WRAPMOD = 10+fieldBitOffset BCR2_WREN = 12+fieldBitOffset BCR3_ASYNCWAIT = 15+fieldBitOffset BCR3_BURSTEN = 8+fieldBitOffset BCR3_CBURSTRW = 19+fieldBitOffset BCR3_EXTMOD = 14+fieldBitOffset BCR3_FACCEN = 6+fieldBitOffset BCR3_MBKEN = 0+fieldBitOffset BCR3_MTYP = 2+fieldBitOffset BCR3_MUXEN = 1+fieldBitOffset BCR3_MWID = 4+fieldBitOffset BCR3_WAITCFG = 11+fieldBitOffset BCR3_WAITEN = 13+fieldBitOffset BCR3_WAITPOL = 9+fieldBitOffset BCR3_WRAPMOD = 10+fieldBitOffset BCR3_WREN = 12+fieldBitOffset BCR4_ASYNCWAIT = 15+fieldBitOffset BCR4_BURSTEN = 8+fieldBitOffset BCR4_CBURSTRW = 19+fieldBitOffset BCR4_EXTMOD = 14+fieldBitOffset BCR4_FACCEN = 6+fieldBitOffset BCR4_MBKEN = 0+fieldBitOffset BCR4_MTYP = 2+fieldBitOffset BCR4_MUXEN = 1+fieldBitOffset BCR4_MWID = 4+fieldBitOffset BCR4_WAITCFG = 11+fieldBitOffset BCR4_WAITEN = 13+fieldBitOffset BCR4_WAITPOL = 9+fieldBitOffset BCR4_WRAPMOD = 10+fieldBitOffset BCR4_WREN = 12+fieldBitOffset BDCR_BDRST = 16+fieldBitOffset BDCR_LSEBYP = 2+fieldBitOffset BDCR_LSEON = 0+fieldBitOffset BDCR_LSERDY = 1+fieldBitOffset BDCR_RTCEN = 15+fieldBitOffset BDCR_RTCSEL = 8+fieldBitOffset BDTR_AOE = 14+fieldBitOffset BDTR_BKE = 12+fieldBitOffset BDTR_BKP = 13+fieldBitOffset BDTR_DTG = 0+fieldBitOffset BDTR_LOCK = 8+fieldBitOffset BDTR_MOE = 15+fieldBitOffset BDTR_OSSI = 10+fieldBitOffset BDTR_OSSR = 11+fieldBitOffset BRR_BR0 = 0+fieldBitOffset BRR_BR1 = 1+fieldBitOffset BRR_BR10 = 10+fieldBitOffset BRR_BR11 = 11+fieldBitOffset BRR_BR12 = 12+fieldBitOffset BRR_BR13 = 13+fieldBitOffset BRR_BR14 = 14+fieldBitOffset BRR_BR15 = 15+fieldBitOffset BRR_BR2 = 2+fieldBitOffset BRR_BR3 = 3+fieldBitOffset BRR_BR4 = 4+fieldBitOffset BRR_BR5 = 5+fieldBitOffset BRR_BR6 = 6+fieldBitOffset BRR_BR7 = 7+fieldBitOffset BRR_BR8 = 8+fieldBitOffset BRR_BR9 = 9+fieldBitOffset BRR_DIV_Fraction = 0+fieldBitOffset BRR_DIV_Mantissa = 4+fieldBitOffset BSRR_BR0 = 16+fieldBitOffset BSRR_BR1 = 17+fieldBitOffset BSRR_BR10 = 26+fieldBitOffset BSRR_BR11 = 27+fieldBitOffset BSRR_BR12 = 28+fieldBitOffset BSRR_BR13 = 29+fieldBitOffset BSRR_BR14 = 30+fieldBitOffset BSRR_BR15 = 31+fieldBitOffset BSRR_BR2 = 18+fieldBitOffset BSRR_BR3 = 19+fieldBitOffset BSRR_BR4 = 20+fieldBitOffset BSRR_BR5 = 21+fieldBitOffset BSRR_BR6 = 22+fieldBitOffset BSRR_BR7 = 23+fieldBitOffset BSRR_BR8 = 24+fieldBitOffset BSRR_BR9 = 25+fieldBitOffset BSRR_BS0 = 0+fieldBitOffset BSRR_BS1 = 1+fieldBitOffset BSRR_BS10 = 10+fieldBitOffset BSRR_BS11 = 11+fieldBitOffset BSRR_BS12 = 12+fieldBitOffset BSRR_BS13 = 13+fieldBitOffset BSRR_BS14 = 14+fieldBitOffset BSRR_BS15 = 15+fieldBitOffset BSRR_BS2 = 2+fieldBitOffset BSRR_BS3 = 3+fieldBitOffset BSRR_BS4 = 4+fieldBitOffset BSRR_BS5 = 5+fieldBitOffset BSRR_BS6 = 6+fieldBitOffset BSRR_BS7 = 7+fieldBitOffset BSRR_BS8 = 8+fieldBitOffset BSRR_BS9 = 9+fieldBitOffset BTABLE_BTABLE = 3+fieldBitOffset BTR1_ACCMOD = 28+fieldBitOffset BTR1_ADDHLD = 4+fieldBitOffset BTR1_ADDSET = 0+fieldBitOffset BTR1_BUSTURN = 16+fieldBitOffset BTR1_CLKDIV = 20+fieldBitOffset BTR1_DATAST = 8+fieldBitOffset BTR1_DATLAT = 24+fieldBitOffset BTR2_ACCMOD = 28+fieldBitOffset BTR2_ADDHLD = 4+fieldBitOffset BTR2_ADDSET = 0+fieldBitOffset BTR2_BUSTURN = 16+fieldBitOffset BTR2_CLKDIV = 20+fieldBitOffset BTR2_DATAST = 8+fieldBitOffset BTR2_DATLAT = 24+fieldBitOffset BTR3_ACCMOD = 28+fieldBitOffset BTR3_ADDHLD = 4+fieldBitOffset BTR3_ADDSET = 0+fieldBitOffset BTR3_BUSTURN = 16+fieldBitOffset BTR3_CLKDIV = 20+fieldBitOffset BTR3_DATAST = 8+fieldBitOffset BTR3_DATLAT = 24+fieldBitOffset BTR4_ACCMOD = 28+fieldBitOffset BTR4_ADDHLD = 4+fieldBitOffset BTR4_ADDSET = 0+fieldBitOffset BTR4_BUSTURN = 16+fieldBitOffset BTR4_CLKDIV = 20+fieldBitOffset BTR4_DATAST = 8+fieldBitOffset BTR4_DATLAT = 24+fieldBitOffset BWTR1_ACCMOD = 28+fieldBitOffset BWTR1_ADDHLD = 4+fieldBitOffset BWTR1_ADDSET = 0+fieldBitOffset BWTR1_CLKDIV = 20+fieldBitOffset BWTR1_DATAST = 8+fieldBitOffset BWTR1_DATLAT = 24+fieldBitOffset BWTR2_ACCMOD = 28+fieldBitOffset BWTR2_ADDHLD = 4+fieldBitOffset BWTR2_ADDSET = 0+fieldBitOffset BWTR2_CLKDIV = 20+fieldBitOffset BWTR2_DATAST = 8+fieldBitOffset BWTR2_DATLAT = 24+fieldBitOffset BWTR3_ACCMOD = 28+fieldBitOffset BWTR3_ADDHLD = 4+fieldBitOffset BWTR3_ADDSET = 0+fieldBitOffset BWTR3_CLKDIV = 20+fieldBitOffset BWTR3_DATAST = 8+fieldBitOffset BWTR3_DATLAT = 24+fieldBitOffset BWTR4_ACCMOD = 28+fieldBitOffset BWTR4_ADDHLD = 4+fieldBitOffset BWTR4_ADDSET = 0+fieldBitOffset BWTR4_CLKDIV = 20+fieldBitOffset BWTR4_DATAST = 8+fieldBitOffset BWTR4_DATLAT = 24+fieldBitOffset CAN_BTR_BRP = 0+fieldBitOffset CAN_BTR_LBKM = 30+fieldBitOffset CAN_BTR_SILM = 31+fieldBitOffset CAN_BTR_SJW = 24+fieldBitOffset CAN_BTR_TS1 = 16+fieldBitOffset CAN_BTR_TS2 = 20+fieldBitOffset CAN_ESR_BOFF = 2+fieldBitOffset CAN_ESR_EPVF = 1+fieldBitOffset CAN_ESR_EWGF = 0+fieldBitOffset CAN_ESR_LEC = 4+fieldBitOffset CAN_ESR_REC = 24+fieldBitOffset CAN_ESR_TEC = 16+fieldBitOffset CAN_FA1R_FACT0 = 0+fieldBitOffset CAN_FA1R_FACT1 = 1+fieldBitOffset CAN_FA1R_FACT10 = 10+fieldBitOffset CAN_FA1R_FACT11 = 11+fieldBitOffset CAN_FA1R_FACT12 = 12+fieldBitOffset CAN_FA1R_FACT13 = 13+fieldBitOffset CAN_FA1R_FACT2 = 2+fieldBitOffset CAN_FA1R_FACT3 = 3+fieldBitOffset CAN_FA1R_FACT4 = 4+fieldBitOffset CAN_FA1R_FACT5 = 5+fieldBitOffset CAN_FA1R_FACT6 = 6+fieldBitOffset CAN_FA1R_FACT7 = 7+fieldBitOffset CAN_FA1R_FACT8 = 8+fieldBitOffset CAN_FA1R_FACT9 = 9+fieldBitOffset CAN_FFA1R_FFA0 = 0+fieldBitOffset CAN_FFA1R_FFA1 = 1+fieldBitOffset CAN_FFA1R_FFA10 = 10+fieldBitOffset CAN_FFA1R_FFA11 = 11+fieldBitOffset CAN_FFA1R_FFA12 = 12+fieldBitOffset CAN_FFA1R_FFA13 = 13+fieldBitOffset CAN_FFA1R_FFA2 = 2+fieldBitOffset CAN_FFA1R_FFA3 = 3+fieldBitOffset CAN_FFA1R_FFA4 = 4+fieldBitOffset CAN_FFA1R_FFA5 = 5+fieldBitOffset CAN_FFA1R_FFA6 = 6+fieldBitOffset CAN_FFA1R_FFA7 = 7+fieldBitOffset CAN_FFA1R_FFA8 = 8+fieldBitOffset CAN_FFA1R_FFA9 = 9+fieldBitOffset CAN_FM1R_FBM0 = 0+fieldBitOffset CAN_FM1R_FBM1 = 1+fieldBitOffset CAN_FM1R_FBM10 = 10+fieldBitOffset CAN_FM1R_FBM11 = 11+fieldBitOffset CAN_FM1R_FBM12 = 12+fieldBitOffset CAN_FM1R_FBM13 = 13+fieldBitOffset CAN_FM1R_FBM2 = 2+fieldBitOffset CAN_FM1R_FBM3 = 3+fieldBitOffset CAN_FM1R_FBM4 = 4+fieldBitOffset CAN_FM1R_FBM5 = 5+fieldBitOffset CAN_FM1R_FBM6 = 6+fieldBitOffset CAN_FM1R_FBM7 = 7+fieldBitOffset CAN_FM1R_FBM8 = 8+fieldBitOffset CAN_FM1R_FBM9 = 9+fieldBitOffset CAN_FMR_FINIT = 0+fieldBitOffset CAN_FS1R_FSC0 = 0+fieldBitOffset CAN_FS1R_FSC1 = 1+fieldBitOffset CAN_FS1R_FSC10 = 10+fieldBitOffset CAN_FS1R_FSC11 = 11+fieldBitOffset CAN_FS1R_FSC12 = 12+fieldBitOffset CAN_FS1R_FSC13 = 13+fieldBitOffset CAN_FS1R_FSC2 = 2+fieldBitOffset CAN_FS1R_FSC3 = 3+fieldBitOffset CAN_FS1R_FSC4 = 4+fieldBitOffset CAN_FS1R_FSC5 = 5+fieldBitOffset CAN_FS1R_FSC6 = 6+fieldBitOffset CAN_FS1R_FSC7 = 7+fieldBitOffset CAN_FS1R_FSC8 = 8+fieldBitOffset CAN_FS1R_FSC9 = 9+fieldBitOffset CAN_IER_BOFIE = 10+fieldBitOffset CAN_IER_EPVIE = 9+fieldBitOffset CAN_IER_ERRIE = 15+fieldBitOffset CAN_IER_EWGIE = 8+fieldBitOffset CAN_IER_FFIE0 = 2+fieldBitOffset CAN_IER_FFIE1 = 5+fieldBitOffset CAN_IER_FMPIE0 = 1+fieldBitOffset CAN_IER_FMPIE1 = 4+fieldBitOffset CAN_IER_FOVIE0 = 3+fieldBitOffset CAN_IER_FOVIE1 = 6+fieldBitOffset CAN_IER_LECIE = 11+fieldBitOffset CAN_IER_SLKIE = 17+fieldBitOffset CAN_IER_TMEIE = 0+fieldBitOffset CAN_IER_WKUIE = 16+fieldBitOffset CAN_MCR_ABOM = 6+fieldBitOffset CAN_MCR_AWUM = 5+fieldBitOffset CAN_MCR_DBF = 16+fieldBitOffset CAN_MCR_INRQ = 0+fieldBitOffset CAN_MCR_NART = 4+fieldBitOffset CAN_MCR_RESET = 15+fieldBitOffset CAN_MCR_RFLM = 3+fieldBitOffset CAN_MCR_SLEEP = 1+fieldBitOffset CAN_MCR_TTCM = 7+fieldBitOffset CAN_MCR_TXFP = 2+fieldBitOffset CAN_MSR_ERRI = 2+fieldBitOffset CAN_MSR_INAK = 0+fieldBitOffset CAN_MSR_RX = 11+fieldBitOffset CAN_MSR_RXM = 9+fieldBitOffset CAN_MSR_SAMP = 10+fieldBitOffset CAN_MSR_SLAK = 1+fieldBitOffset CAN_MSR_SLAKI = 4+fieldBitOffset CAN_MSR_TXM = 8+fieldBitOffset CAN_MSR_WKUI = 3+fieldBitOffset CAN_RDH0R_DATA4 = 0+fieldBitOffset CAN_RDH0R_DATA5 = 8+fieldBitOffset CAN_RDH0R_DATA6 = 16+fieldBitOffset CAN_RDH0R_DATA7 = 24+fieldBitOffset CAN_RDH1R_DATA4 = 0+fieldBitOffset CAN_RDH1R_DATA5 = 8+fieldBitOffset CAN_RDH1R_DATA6 = 16+fieldBitOffset CAN_RDH1R_DATA7 = 24+fieldBitOffset CAN_RDL0R_DATA0 = 0+fieldBitOffset CAN_RDL0R_DATA1 = 8+fieldBitOffset CAN_RDL0R_DATA2 = 16+fieldBitOffset CAN_RDL0R_DATA3 = 24+fieldBitOffset CAN_RDL1R_DATA0 = 0+fieldBitOffset CAN_RDL1R_DATA1 = 8+fieldBitOffset CAN_RDL1R_DATA2 = 16+fieldBitOffset CAN_RDL1R_DATA3 = 24+fieldBitOffset CAN_RDT0R_DLC = 0+fieldBitOffset CAN_RDT0R_FMI = 8+fieldBitOffset CAN_RDT0R_TIME = 16+fieldBitOffset CAN_RDT1R_DLC = 0+fieldBitOffset CAN_RDT1R_FMI = 8+fieldBitOffset CAN_RDT1R_TIME = 16+fieldBitOffset CAN_RF0R_FMP0 = 0+fieldBitOffset CAN_RF0R_FOVR0 = 4+fieldBitOffset CAN_RF0R_FULL0 = 3+fieldBitOffset CAN_RF0R_RFOM0 = 5+fieldBitOffset CAN_RF1R_FMP1 = 0+fieldBitOffset CAN_RF1R_FOVR1 = 4+fieldBitOffset CAN_RF1R_FULL1 = 3+fieldBitOffset CAN_RF1R_RFOM1 = 5+fieldBitOffset CAN_RI0R_EXID = 3+fieldBitOffset CAN_RI0R_IDE = 2+fieldBitOffset CAN_RI0R_RTR = 1+fieldBitOffset CAN_RI0R_STID = 21+fieldBitOffset CAN_RI1R_EXID = 3+fieldBitOffset CAN_RI1R_IDE = 2+fieldBitOffset CAN_RI1R_RTR = 1+fieldBitOffset CAN_RI1R_STID = 21+fieldBitOffset CAN_TDH0R_DATA4 = 0+fieldBitOffset CAN_TDH0R_DATA5 = 8+fieldBitOffset CAN_TDH0R_DATA6 = 16+fieldBitOffset CAN_TDH0R_DATA7 = 24+fieldBitOffset CAN_TDH1R_DATA4 = 0+fieldBitOffset CAN_TDH1R_DATA5 = 8+fieldBitOffset CAN_TDH1R_DATA6 = 16+fieldBitOffset CAN_TDH1R_DATA7 = 24+fieldBitOffset CAN_TDH2R_DATA4 = 0+fieldBitOffset CAN_TDH2R_DATA5 = 8+fieldBitOffset CAN_TDH2R_DATA6 = 16+fieldBitOffset CAN_TDH2R_DATA7 = 24+fieldBitOffset CAN_TDL0R_DATA0 = 0+fieldBitOffset CAN_TDL0R_DATA1 = 8+fieldBitOffset CAN_TDL0R_DATA2 = 16+fieldBitOffset CAN_TDL0R_DATA3 = 24+fieldBitOffset CAN_TDL1R_DATA0 = 0+fieldBitOffset CAN_TDL1R_DATA1 = 8+fieldBitOffset CAN_TDL1R_DATA2 = 16+fieldBitOffset CAN_TDL1R_DATA3 = 24+fieldBitOffset CAN_TDL2R_DATA0 = 0+fieldBitOffset CAN_TDL2R_DATA1 = 8+fieldBitOffset CAN_TDL2R_DATA2 = 16+fieldBitOffset CAN_TDL2R_DATA3 = 24+fieldBitOffset CAN_TDT0R_DLC = 0+fieldBitOffset CAN_TDT0R_TGT = 8+fieldBitOffset CAN_TDT0R_TIME = 16+fieldBitOffset CAN_TDT1R_DLC = 0+fieldBitOffset CAN_TDT1R_TGT = 8+fieldBitOffset CAN_TDT1R_TIME = 16+fieldBitOffset CAN_TDT2R_DLC = 0+fieldBitOffset CAN_TDT2R_TGT = 8+fieldBitOffset CAN_TDT2R_TIME = 16+fieldBitOffset CAN_TI0R_EXID = 3+fieldBitOffset CAN_TI0R_IDE = 2+fieldBitOffset CAN_TI0R_RTR = 1+fieldBitOffset CAN_TI0R_STID = 21+fieldBitOffset CAN_TI0R_TXRQ = 0+fieldBitOffset CAN_TI1R_EXID = 3+fieldBitOffset CAN_TI1R_IDE = 2+fieldBitOffset CAN_TI1R_RTR = 1+fieldBitOffset CAN_TI1R_STID = 21+fieldBitOffset CAN_TI1R_TXRQ = 0+fieldBitOffset CAN_TI2R_EXID = 3+fieldBitOffset CAN_TI2R_IDE = 2+fieldBitOffset CAN_TI2R_RTR = 1+fieldBitOffset CAN_TI2R_STID = 21+fieldBitOffset CAN_TI2R_TXRQ = 0+fieldBitOffset CAN_TSR_ABRQ0 = 7+fieldBitOffset CAN_TSR_ABRQ1 = 15+fieldBitOffset CAN_TSR_ABRQ2 = 23+fieldBitOffset CAN_TSR_ALST0 = 2+fieldBitOffset CAN_TSR_ALST1 = 10+fieldBitOffset CAN_TSR_ALST2 = 18+fieldBitOffset CAN_TSR_CODE = 24+fieldBitOffset CAN_TSR_LOW0 = 29+fieldBitOffset CAN_TSR_LOW1 = 30+fieldBitOffset CAN_TSR_LOW2 = 31+fieldBitOffset CAN_TSR_RQCP0 = 0+fieldBitOffset CAN_TSR_RQCP1 = 8+fieldBitOffset CAN_TSR_RQCP2 = 16+fieldBitOffset CAN_TSR_TERR0 = 3+fieldBitOffset CAN_TSR_TERR1 = 11+fieldBitOffset CAN_TSR_TERR2 = 19+fieldBitOffset CAN_TSR_TME0 = 26+fieldBitOffset CAN_TSR_TME1 = 27+fieldBitOffset CAN_TSR_TME2 = 28+fieldBitOffset CAN_TSR_TXOK0 = 1+fieldBitOffset CAN_TSR_TXOK1 = 9+fieldBitOffset CAN_TSR_TXOK2 = 17+fieldBitOffset CCER_CC1E = 0+fieldBitOffset CCER_CC1NE = 2+fieldBitOffset CCER_CC1NP = 3+fieldBitOffset CCER_CC1P = 1+fieldBitOffset CCER_CC2E = 4+fieldBitOffset CCER_CC2NE = 6+fieldBitOffset CCER_CC2NP = 7+fieldBitOffset CCER_CC2P = 5+fieldBitOffset CCER_CC3E = 8+fieldBitOffset CCER_CC3NE = 10+fieldBitOffset CCER_CC3NP = 11+fieldBitOffset CCER_CC3P = 9+fieldBitOffset CCER_CC4E = 12+fieldBitOffset CCER_CC4P = 13+fieldBitOffset CCMR1_Input_CC1S = 0+fieldBitOffset CCMR1_Input_CC2S = 8+fieldBitOffset CCMR1_Input_IC1F = 4+fieldBitOffset CCMR1_Input_IC1PSC = 2+fieldBitOffset CCMR1_Input_IC2F = 12+fieldBitOffset CCMR1_Input_IC2PCS = 10+fieldBitOffset CCMR1_Input_IC2PSC = 10+fieldBitOffset CCMR1_Input_ICPCS = 2+fieldBitOffset CCMR1_Output_CC1S = 0+fieldBitOffset CCMR1_Output_CC2S = 8+fieldBitOffset CCMR1_Output_OC1CE = 7+fieldBitOffset CCMR1_Output_OC1FE = 2+fieldBitOffset CCMR1_Output_OC1M = 4+fieldBitOffset CCMR1_Output_OC1PE = 3+fieldBitOffset CCMR1_Output_OC2CE = 15+fieldBitOffset CCMR1_Output_OC2FE = 10+fieldBitOffset CCMR1_Output_OC2M = 12+fieldBitOffset CCMR1_Output_OC2PE = 11+fieldBitOffset CCMR2_Input_CC3S = 0+fieldBitOffset CCMR2_Input_CC4S = 8+fieldBitOffset CCMR2_Input_IC3F = 4+fieldBitOffset CCMR2_Input_IC3PSC = 2+fieldBitOffset CCMR2_Input_IC4F = 12+fieldBitOffset CCMR2_Input_IC4PSC = 10+fieldBitOffset CCMR2_Output_CC3S = 0+fieldBitOffset CCMR2_Output_CC4S = 8+fieldBitOffset CCMR2_Output_O24CE = 15+fieldBitOffset CCMR2_Output_OC3CE = 7+fieldBitOffset CCMR2_Output_OC3FE = 2+fieldBitOffset CCMR2_Output_OC3M = 4+fieldBitOffset CCMR2_Output_OC3PE = 3+fieldBitOffset CCMR2_Output_OC4CE = 15+fieldBitOffset CCMR2_Output_OC4FE = 10+fieldBitOffset CCMR2_Output_OC4M = 12+fieldBitOffset CCMR2_Output_OC4PE = 11+fieldBitOffset CCR_CCR = 0+fieldBitOffset CCR_DUTY = 14+fieldBitOffset CCR_F_S = 15+fieldBitOffset CCR1_CCR1 = 0+fieldBitOffset CCR1_CIRC = 5+fieldBitOffset CCR1_DIR = 4+fieldBitOffset CCR1_EN = 0+fieldBitOffset CCR1_HTIE = 2+fieldBitOffset CCR1_MEM2MEM = 14+fieldBitOffset CCR1_MINC = 7+fieldBitOffset CCR1_MSIZE = 10+fieldBitOffset CCR1_PINC = 6+fieldBitOffset CCR1_PL = 12+fieldBitOffset CCR1_PSIZE = 8+fieldBitOffset CCR1_TCIE = 1+fieldBitOffset CCR1_TEIE = 3+fieldBitOffset CCR2_CCR2 = 0+fieldBitOffset CCR2_CIRC = 5+fieldBitOffset CCR2_DIR = 4+fieldBitOffset CCR2_EN = 0+fieldBitOffset CCR2_HTIE = 2+fieldBitOffset CCR2_MEM2MEM = 14+fieldBitOffset CCR2_MINC = 7+fieldBitOffset CCR2_MSIZE = 10+fieldBitOffset CCR2_PINC = 6+fieldBitOffset CCR2_PL = 12+fieldBitOffset CCR2_PSIZE = 8+fieldBitOffset CCR2_TCIE = 1+fieldBitOffset CCR2_TEIE = 3+fieldBitOffset CCR3_CCR3 = 0+fieldBitOffset CCR3_CIRC = 5+fieldBitOffset CCR3_DIR = 4+fieldBitOffset CCR3_EN = 0+fieldBitOffset CCR3_HTIE = 2+fieldBitOffset CCR3_MEM2MEM = 14+fieldBitOffset CCR3_MINC = 7+fieldBitOffset CCR3_MSIZE = 10+fieldBitOffset CCR3_PINC = 6+fieldBitOffset CCR3_PL = 12+fieldBitOffset CCR3_PSIZE = 8+fieldBitOffset CCR3_TCIE = 1+fieldBitOffset CCR3_TEIE = 3+fieldBitOffset CCR4_CCR4 = 0+fieldBitOffset CCR4_CIRC = 5+fieldBitOffset CCR4_DIR = 4+fieldBitOffset CCR4_EN = 0+fieldBitOffset CCR4_HTIE = 2+fieldBitOffset CCR4_MEM2MEM = 14+fieldBitOffset CCR4_MINC = 7+fieldBitOffset CCR4_MSIZE = 10+fieldBitOffset CCR4_PINC = 6+fieldBitOffset CCR4_PL = 12+fieldBitOffset CCR4_PSIZE = 8+fieldBitOffset CCR4_TCIE = 1+fieldBitOffset CCR4_TEIE = 3+fieldBitOffset CCR5_CIRC = 5+fieldBitOffset CCR5_DIR = 4+fieldBitOffset CCR5_EN = 0+fieldBitOffset CCR5_HTIE = 2+fieldBitOffset CCR5_MEM2MEM = 14+fieldBitOffset CCR5_MINC = 7+fieldBitOffset CCR5_MSIZE = 10+fieldBitOffset CCR5_PINC = 6+fieldBitOffset CCR5_PL = 12+fieldBitOffset CCR5_PSIZE = 8+fieldBitOffset CCR5_TCIE = 1+fieldBitOffset CCR5_TEIE = 3+fieldBitOffset CCR6_CIRC = 5+fieldBitOffset CCR6_DIR = 4+fieldBitOffset CCR6_EN = 0+fieldBitOffset CCR6_HTIE = 2+fieldBitOffset CCR6_MEM2MEM = 14+fieldBitOffset CCR6_MINC = 7+fieldBitOffset CCR6_MSIZE = 10+fieldBitOffset CCR6_PINC = 6+fieldBitOffset CCR6_PL = 12+fieldBitOffset CCR6_PSIZE = 8+fieldBitOffset CCR6_TCIE = 1+fieldBitOffset CCR6_TEIE = 3+fieldBitOffset CCR7_CIRC = 5+fieldBitOffset CCR7_DIR = 4+fieldBitOffset CCR7_EN = 0+fieldBitOffset CCR7_HTIE = 2+fieldBitOffset CCR7_MEM2MEM = 14+fieldBitOffset CCR7_MINC = 7+fieldBitOffset CCR7_MSIZE = 10+fieldBitOffset CCR7_PINC = 6+fieldBitOffset CCR7_PL = 12+fieldBitOffset CCR7_PSIZE = 8+fieldBitOffset CCR7_TCIE = 1+fieldBitOffset CCR7_TEIE = 3+fieldBitOffset CFGR_ADCPRE = 14+fieldBitOffset CFGR_HPRE = 4+fieldBitOffset CFGR_MCO = 24+fieldBitOffset CFGR_OTGFSPRE = 22+fieldBitOffset CFGR_PLLMUL = 18+fieldBitOffset CFGR_PLLSRC = 16+fieldBitOffset CFGR_PLLXTPRE = 17+fieldBitOffset CFGR_PPRE1 = 8+fieldBitOffset CFGR_PPRE2 = 11+fieldBitOffset CFGR_SW = 0+fieldBitOffset CFGR_SWS = 2+fieldBitOffset CFR_EWI = 9+fieldBitOffset CFR_W = 0+fieldBitOffset CFR_WDGTB = 7+fieldBitOffset CIR_CSSC = 23+fieldBitOffset CIR_CSSF = 7+fieldBitOffset CIR_HSERDYC = 19+fieldBitOffset CIR_HSERDYF = 3+fieldBitOffset CIR_HSERDYIE = 11+fieldBitOffset CIR_HSIRDYC = 18+fieldBitOffset CIR_HSIRDYF = 2+fieldBitOffset CIR_HSIRDYIE = 10+fieldBitOffset CIR_LSERDYC = 17+fieldBitOffset CIR_LSERDYF = 1+fieldBitOffset CIR_LSERDYIE = 9+fieldBitOffset CIR_LSIRDYC = 16+fieldBitOffset CIR_LSIRDYF = 0+fieldBitOffset CIR_LSIRDYIE = 8+fieldBitOffset CIR_PLLRDYC = 20+fieldBitOffset CIR_PLLRDYF = 4+fieldBitOffset CIR_PLLRDYIE = 12+fieldBitOffset CLKCR_BYPASS = 10+fieldBitOffset CLKCR_CLKDIV = 0+fieldBitOffset CLKCR_CLKEN = 8+fieldBitOffset CLKCR_HWFC_EN = 14+fieldBitOffset CLKCR_NEGEDGE = 13+fieldBitOffset CLKCR_PWRSAV = 9+fieldBitOffset CLKCR_WIDBUS = 11+fieldBitOffset CMAR1_MA = 0+fieldBitOffset CMAR2_MA = 0+fieldBitOffset CMAR3_MA = 0+fieldBitOffset CMAR4_MA = 0+fieldBitOffset CMAR5_MA = 0+fieldBitOffset CMAR6_MA = 0+fieldBitOffset CMAR7_MA = 0+fieldBitOffset CMD_CE_ATACMD = 14+fieldBitOffset CMD_CMDINDEX = 0+fieldBitOffset CMD_CPSMEN = 10+fieldBitOffset CMD_ENCMDcompl = 12+fieldBitOffset CMD_SDIOSuspend = 11+fieldBitOffset CMD_WAITINT = 8+fieldBitOffset CMD_WAITPEND = 9+fieldBitOffset CMD_WAITRESP = 6+fieldBitOffset CMD_nIEN = 13+fieldBitOffset CNDTR1_NDT = 0+fieldBitOffset CNDTR2_NDT = 0+fieldBitOffset CNDTR3_NDT = 0+fieldBitOffset CNDTR4_NDT = 0+fieldBitOffset CNDTR5_NDT = 0+fieldBitOffset CNDTR6_NDT = 0+fieldBitOffset CNDTR7_NDT = 0+fieldBitOffset CNT_CNT = 0+fieldBitOffset CNTH_CNTH = 0+fieldBitOffset CNTL_CNTL = 0+fieldBitOffset CNTR_CTRM = 15+fieldBitOffset CNTR_ERRM = 13+fieldBitOffset CNTR_ESOFM = 8+fieldBitOffset CNTR_FRES = 0+fieldBitOffset CNTR_FSUSP = 3+fieldBitOffset CNTR_LPMODE = 2+fieldBitOffset CNTR_PDWN = 1+fieldBitOffset CNTR_PMAOVRM = 14+fieldBitOffset CNTR_RESETM = 10+fieldBitOffset CNTR_RESUME = 4+fieldBitOffset CNTR_SOFM = 9+fieldBitOffset CNTR_SUSPM = 11+fieldBitOffset CNTR_WKUPM = 12+fieldBitOffset CPAR1_PA = 0+fieldBitOffset CPAR2_PA = 0+fieldBitOffset CPAR3_PA = 0+fieldBitOffset CPAR4_PA = 0+fieldBitOffset CPAR5_PA = 0+fieldBitOffset CPAR6_PA = 0+fieldBitOffset CPAR7_PA = 0+fieldBitOffset CR_BOFF1 = 1+fieldBitOffset CR_BOFF2 = 17+fieldBitOffset CR_CSBF = 3+fieldBitOffset CR_CSSON = 19+fieldBitOffset CR_CWUF = 2+fieldBitOffset CR_DBG_CAN1_STOP = 14+fieldBitOffset CR_DBG_CAN2_STOP = 21+fieldBitOffset CR_DBG_I2C1_SMBUS_TIMEOUT = 15+fieldBitOffset CR_DBG_I2C2_SMBUS_TIMEOUT = 16+fieldBitOffset CR_DBG_IWDG_STOP = 8+fieldBitOffset CR_DBG_SLEEP = 0+fieldBitOffset CR_DBG_STANDBY = 2+fieldBitOffset CR_DBG_STOP = 1+fieldBitOffset CR_DBG_TIM1_STOP = 10+fieldBitOffset CR_DBG_TIM2_STOP = 11+fieldBitOffset CR_DBG_TIM3_STOP = 12+fieldBitOffset CR_DBG_TIM4_STOP = 13+fieldBitOffset CR_DBG_TIM5_STOP = 18+fieldBitOffset CR_DBG_TIM6_STOP = 19+fieldBitOffset CR_DBG_TIM7_STOP = 20+fieldBitOffset CR_DBG_TIM8_STOP = 17+fieldBitOffset CR_DBG_WWDG_STOP = 9+fieldBitOffset CR_DBP = 8+fieldBitOffset CR_DMAEN1 = 12+fieldBitOffset CR_DMAEN2 = 28+fieldBitOffset CR_EN1 = 0+fieldBitOffset CR_EN2 = 16+fieldBitOffset CR_EOPIE = 12+fieldBitOffset CR_ERRIE = 10+fieldBitOffset CR_HSEBYP = 18+fieldBitOffset CR_HSEON = 16+fieldBitOffset CR_HSERDY = 17+fieldBitOffset CR_HSICAL = 8+fieldBitOffset CR_HSION = 0+fieldBitOffset CR_HSIRDY = 1+fieldBitOffset CR_HSITRIM = 3+fieldBitOffset CR_LOCK = 7+fieldBitOffset CR_LPDS = 0+fieldBitOffset CR_MAMP1 = 8+fieldBitOffset CR_MAMP2 = 24+fieldBitOffset CR_MER = 2+fieldBitOffset CR_OPTER = 5+fieldBitOffset CR_OPTPG = 4+fieldBitOffset CR_OPTWRE = 9+fieldBitOffset CR_PDDS = 1+fieldBitOffset CR_PER = 1+fieldBitOffset CR_PG = 0+fieldBitOffset CR_PLLON = 24+fieldBitOffset CR_PLLRDY = 25+fieldBitOffset CR_PLS = 5+fieldBitOffset CR_PVDE = 4+fieldBitOffset CR_RESET = 0+fieldBitOffset CR_STRT = 6+fieldBitOffset CR_T = 0+fieldBitOffset CR_TEN1 = 2+fieldBitOffset CR_TEN2 = 18+fieldBitOffset CR_TPAL = 1+fieldBitOffset CR_TPE = 0+fieldBitOffset CR_TRACE_IOEN = 5+fieldBitOffset CR_TRACE_MODE = 6+fieldBitOffset CR_TSEL1 = 3+fieldBitOffset CR_TSEL2 = 19+fieldBitOffset CR_WAVE1 = 6+fieldBitOffset CR_WAVE2 = 22+fieldBitOffset CR_WDGA = 7+fieldBitOffset CR1_ACK = 10+fieldBitOffset CR1_ALERT = 13+fieldBitOffset CR1_ARPE = 7+fieldBitOffset CR1_AWDCH = 0+fieldBitOffset CR1_AWDEN = 23+fieldBitOffset CR1_AWDIE = 6+fieldBitOffset CR1_AWDSGL = 9+fieldBitOffset CR1_BIDIMODE = 15+fieldBitOffset CR1_BIDIOE = 14+fieldBitOffset CR1_BR = 3+fieldBitOffset CR1_CEN = 0+fieldBitOffset CR1_CKD = 8+fieldBitOffset CR1_CMS = 5+fieldBitOffset CR1_CPHA = 0+fieldBitOffset CR1_CPOL = 1+fieldBitOffset CR1_CRCEN = 13+fieldBitOffset CR1_CRCNEXT = 12+fieldBitOffset CR1_DFF = 11+fieldBitOffset CR1_DIR = 4+fieldBitOffset CR1_DISCEN = 11+fieldBitOffset CR1_DISCNUM = 13+fieldBitOffset CR1_DUALMOD = 16+fieldBitOffset CR1_ENARP = 4+fieldBitOffset CR1_ENGC = 6+fieldBitOffset CR1_ENPEC = 5+fieldBitOffset CR1_EOCIE = 5+fieldBitOffset CR1_IDLEIE = 4+fieldBitOffset CR1_JAUTO = 10+fieldBitOffset CR1_JAWDEN = 22+fieldBitOffset CR1_JDISCEN = 12+fieldBitOffset CR1_JEOCIE = 7+fieldBitOffset CR1_LSBFIRST = 7+fieldBitOffset CR1_M = 12+fieldBitOffset CR1_MSTR = 2+fieldBitOffset CR1_NOSTRETCH = 7+fieldBitOffset CR1_OPM = 3+fieldBitOffset CR1_PCE = 10+fieldBitOffset CR1_PE = 0+fieldBitOffset CR1_PEC = 12+fieldBitOffset CR1_PEIE = 8+fieldBitOffset CR1_POS = 11+fieldBitOffset CR1_PS = 9+fieldBitOffset CR1_RE = 2+fieldBitOffset CR1_RWU = 1+fieldBitOffset CR1_RXNEIE = 5+fieldBitOffset CR1_RXONLY = 10+fieldBitOffset CR1_SBK = 0+fieldBitOffset CR1_SCAN = 8+fieldBitOffset CR1_SMBTYPE = 3+fieldBitOffset CR1_SMBUS = 1+fieldBitOffset CR1_SPE = 6+fieldBitOffset CR1_SSI = 8+fieldBitOffset CR1_SSM = 9+fieldBitOffset CR1_START = 8+fieldBitOffset CR1_STOP = 9+fieldBitOffset CR1_SWRST = 15+fieldBitOffset CR1_TCIE = 6+fieldBitOffset CR1_TE = 3+fieldBitOffset CR1_TXEIE = 7+fieldBitOffset CR1_UDIS = 1+fieldBitOffset CR1_UE = 13+fieldBitOffset CR1_URS = 2+fieldBitOffset CR1_WAKE = 11+fieldBitOffset CR2_ADD = 0+fieldBitOffset CR2_ADON = 0+fieldBitOffset CR2_ALIGN = 11+fieldBitOffset CR2_CAL = 2+fieldBitOffset CR2_CCDS = 3+fieldBitOffset CR2_CCPC = 0+fieldBitOffset CR2_CCUS = 2+fieldBitOffset CR2_CLKEN = 11+fieldBitOffset CR2_CONT = 1+fieldBitOffset CR2_CPHA = 9+fieldBitOffset CR2_CPOL = 10+fieldBitOffset CR2_DMA = 8+fieldBitOffset CR2_DMAEN = 11+fieldBitOffset CR2_ERRIE = 5+fieldBitOffset CR2_EXTSEL = 17+fieldBitOffset CR2_EXTTRIG = 20+fieldBitOffset CR2_FREQ = 0+fieldBitOffset CR2_ITBUFEN = 10+fieldBitOffset CR2_ITERREN = 8+fieldBitOffset CR2_ITEVTEN = 9+fieldBitOffset CR2_JEXTSEL = 12+fieldBitOffset CR2_JEXTTRIG = 15+fieldBitOffset CR2_JSWSTART = 21+fieldBitOffset CR2_LAST = 12+fieldBitOffset CR2_LBCL = 8+fieldBitOffset CR2_LBDIE = 6+fieldBitOffset CR2_LBDL = 5+fieldBitOffset CR2_LINEN = 14+fieldBitOffset CR2_MMS = 4+fieldBitOffset CR2_OIS1 = 8+fieldBitOffset CR2_OIS1N = 9+fieldBitOffset CR2_OIS2 = 10+fieldBitOffset CR2_OIS2N = 11+fieldBitOffset CR2_OIS3 = 12+fieldBitOffset CR2_OIS3N = 13+fieldBitOffset CR2_OIS4 = 14+fieldBitOffset CR2_RSTCAL = 3+fieldBitOffset CR2_RXDMAEN = 0+fieldBitOffset CR2_RXNEIE = 6+fieldBitOffset CR2_SSOE = 2+fieldBitOffset CR2_STOP = 12+fieldBitOffset CR2_SWSTART = 22+fieldBitOffset CR2_TI1S = 7+fieldBitOffset CR2_TSVREFE = 23+fieldBitOffset CR2_TXDMAEN = 1+fieldBitOffset CR2_TXEIE = 7+fieldBitOffset CR3_CTSE = 9+fieldBitOffset CR3_CTSIE = 10+fieldBitOffset CR3_DMAR = 6+fieldBitOffset CR3_DMAT = 7+fieldBitOffset CR3_EIE = 0+fieldBitOffset CR3_HDSEL = 3+fieldBitOffset CR3_IREN = 1+fieldBitOffset CR3_IRLP = 2+fieldBitOffset CR3_NACK = 4+fieldBitOffset CR3_RTSE = 8+fieldBitOffset CR3_SCEN = 5+fieldBitOffset CRCPR_CRCPOLY = 0+fieldBitOffset CRH_ALRIE = 1+fieldBitOffset CRH_CNF10 = 10+fieldBitOffset CRH_CNF11 = 14+fieldBitOffset CRH_CNF12 = 18+fieldBitOffset CRH_CNF13 = 22+fieldBitOffset CRH_CNF14 = 26+fieldBitOffset CRH_CNF15 = 30+fieldBitOffset CRH_CNF8 = 2+fieldBitOffset CRH_CNF9 = 6+fieldBitOffset CRH_MODE10 = 8+fieldBitOffset CRH_MODE11 = 12+fieldBitOffset CRH_MODE12 = 16+fieldBitOffset CRH_MODE13 = 20+fieldBitOffset CRH_MODE14 = 24+fieldBitOffset CRH_MODE15 = 28+fieldBitOffset CRH_MODE8 = 0+fieldBitOffset CRH_MODE9 = 4+fieldBitOffset CRH_OWIE = 2+fieldBitOffset CRH_SECIE = 0+fieldBitOffset CRL_ALRF = 1+fieldBitOffset CRL_CNF = 4+fieldBitOffset CRL_CNF0 = 2+fieldBitOffset CRL_CNF1 = 6+fieldBitOffset CRL_CNF2 = 10+fieldBitOffset CRL_CNF3 = 14+fieldBitOffset CRL_CNF4 = 18+fieldBitOffset CRL_CNF5 = 22+fieldBitOffset CRL_CNF6 = 26+fieldBitOffset CRL_CNF7 = 30+fieldBitOffset CRL_MODE0 = 0+fieldBitOffset CRL_MODE1 = 4+fieldBitOffset CRL_MODE2 = 8+fieldBitOffset CRL_MODE3 = 12+fieldBitOffset CRL_MODE4 = 16+fieldBitOffset CRL_MODE5 = 20+fieldBitOffset CRL_MODE6 = 24+fieldBitOffset CRL_MODE7 = 28+fieldBitOffset CRL_OWF = 2+fieldBitOffset CRL_RSF = 3+fieldBitOffset CRL_RTOFF = 5+fieldBitOffset CRL_SECF = 0+fieldBitOffset CSR_CTE = 0+fieldBitOffset CSR_CTI = 1+fieldBitOffset CSR_EWUP = 8+fieldBitOffset CSR_IWDGRSTF = 29+fieldBitOffset CSR_LPWRRSTF = 31+fieldBitOffset CSR_LSION = 0+fieldBitOffset CSR_LSIRDY = 1+fieldBitOffset CSR_PINRSTF = 26+fieldBitOffset CSR_PORRSTF = 27+fieldBitOffset CSR_PVDO = 2+fieldBitOffset CSR_RMVF = 24+fieldBitOffset CSR_SBF = 1+fieldBitOffset CSR_SFTRSTF = 28+fieldBitOffset CSR_TEF = 8+fieldBitOffset CSR_TIF = 9+fieldBitOffset CSR_TPIE = 2+fieldBitOffset CSR_WUF = 0+fieldBitOffset CSR_WWDGRSTF = 30+fieldBitOffset DADDR_ADD = 0+fieldBitOffset DADDR_EF = 7+fieldBitOffset DCOUNT_DATACOUNT = 0+fieldBitOffset DCR_DBA = 0+fieldBitOffset DCR_DBL = 8+fieldBitOffset DCTRL_DBLOCKSIZE = 4+fieldBitOffset DCTRL_DMAEN = 3+fieldBitOffset DCTRL_DTDIR = 1+fieldBitOffset DCTRL_DTEN = 0+fieldBitOffset DCTRL_DTMODE = 2+fieldBitOffset DCTRL_PWSTART = 8+fieldBitOffset DCTRL_PWSTOP = 9+fieldBitOffset DCTRL_RWMOD = 10+fieldBitOffset DCTRL_SDIOEN = 11+fieldBitOffset DHR12L1_DACC1DHR = 4+fieldBitOffset DHR12L2_DACC2DHR = 4+fieldBitOffset DHR12LD_DACC1DHR = 4+fieldBitOffset DHR12LD_DACC2DHR = 20+fieldBitOffset DHR12R1_DACC1DHR = 0+fieldBitOffset DHR12R2_DACC2DHR = 0+fieldBitOffset DHR12RD_DACC1DHR = 0+fieldBitOffset DHR12RD_DACC2DHR = 16+fieldBitOffset DHR8R1_DACC1DHR = 0+fieldBitOffset DHR8R2_DACC2DHR = 0+fieldBitOffset DHR8RD_DACC1DHR = 0+fieldBitOffset DHR8RD_DACC2DHR = 8+fieldBitOffset DIER_BIE = 7+fieldBitOffset DIER_CC1DE = 9+fieldBitOffset DIER_CC1IE = 1+fieldBitOffset DIER_CC2DE = 10+fieldBitOffset DIER_CC2IE = 2+fieldBitOffset DIER_CC3DE = 11+fieldBitOffset DIER_CC3IE = 3+fieldBitOffset DIER_CC4DE = 12+fieldBitOffset DIER_CC4IE = 4+fieldBitOffset DIER_COMDE = 13+fieldBitOffset DIER_COMIE = 5+fieldBitOffset DIER_TDE = 14+fieldBitOffset DIER_TIE = 6+fieldBitOffset DIER_UDE = 8+fieldBitOffset DIER_UIE = 0+fieldBitOffset DIVH_DIVH = 0+fieldBitOffset DIVL_DIVL = 0+fieldBitOffset DLEN_DATALENGTH = 0+fieldBitOffset DMAR_DMAB = 0+fieldBitOffset DOR1_DACC1DOR = 0+fieldBitOffset DOR2_DACC2DOR = 0+fieldBitOffset DR_ADC2DATA = 16+fieldBitOffset DR_DATA = 0+fieldBitOffset DR_DR = 0+fieldBitOffset DR1_D1 = 0+fieldBitOffset DR10_D10 = 0+fieldBitOffset DR11_DR11 = 0+fieldBitOffset DR12_DR12 = 0+fieldBitOffset DR13_DR13 = 0+fieldBitOffset DR14_D14 = 0+fieldBitOffset DR15_D15 = 0+fieldBitOffset DR16_D16 = 0+fieldBitOffset DR17_D17 = 0+fieldBitOffset DR18_D18 = 0+fieldBitOffset DR19_D19 = 0+fieldBitOffset DR2_D2 = 0+fieldBitOffset DR20_D20 = 0+fieldBitOffset DR21_D21 = 0+fieldBitOffset DR22_D22 = 0+fieldBitOffset DR23_D23 = 0+fieldBitOffset DR24_D24 = 0+fieldBitOffset DR25_D25 = 0+fieldBitOffset DR26_D26 = 0+fieldBitOffset DR27_D27 = 0+fieldBitOffset DR28_D28 = 0+fieldBitOffset DR29_D29 = 0+fieldBitOffset DR3_D3 = 0+fieldBitOffset DR30_D30 = 0+fieldBitOffset DR31_D31 = 0+fieldBitOffset DR32_D32 = 0+fieldBitOffset DR33_D33 = 0+fieldBitOffset DR34_D34 = 0+fieldBitOffset DR35_D35 = 0+fieldBitOffset DR36_D36 = 0+fieldBitOffset DR37_D37 = 0+fieldBitOffset DR38_D38 = 0+fieldBitOffset DR39_D39 = 0+fieldBitOffset DR4_D4 = 0+fieldBitOffset DR40_D40 = 0+fieldBitOffset DR41_D41 = 0+fieldBitOffset DR42_D42 = 0+fieldBitOffset DR5_D5 = 0+fieldBitOffset DR6_D6 = 0+fieldBitOffset DR7_D7 = 0+fieldBitOffset DR8_D8 = 0+fieldBitOffset DR9_D9 = 0+fieldBitOffset DTIMER_DATATIME = 0+fieldBitOffset ECCR2_ECCx = 0+fieldBitOffset ECCR3_ECCx = 0+fieldBitOffset EGR_BG = 7+fieldBitOffset EGR_CC1G = 1+fieldBitOffset EGR_CC2G = 2+fieldBitOffset EGR_CC3G = 3+fieldBitOffset EGR_CC4G = 4+fieldBitOffset EGR_COMG = 5+fieldBitOffset EGR_TG = 6+fieldBitOffset EGR_UG = 0+fieldBitOffset EMR_MR0 = 0+fieldBitOffset EMR_MR1 = 1+fieldBitOffset EMR_MR10 = 10+fieldBitOffset EMR_MR11 = 11+fieldBitOffset EMR_MR12 = 12+fieldBitOffset EMR_MR13 = 13+fieldBitOffset EMR_MR14 = 14+fieldBitOffset EMR_MR15 = 15+fieldBitOffset EMR_MR16 = 16+fieldBitOffset EMR_MR17 = 17+fieldBitOffset EMR_MR18 = 18+fieldBitOffset EMR_MR2 = 2+fieldBitOffset EMR_MR3 = 3+fieldBitOffset EMR_MR4 = 4+fieldBitOffset EMR_MR5 = 5+fieldBitOffset EMR_MR6 = 6+fieldBitOffset EMR_MR7 = 7+fieldBitOffset EMR_MR8 = 8+fieldBitOffset EMR_MR9 = 9+fieldBitOffset EP0R_CTR_RX = 15+fieldBitOffset EP0R_CTR_TX = 7+fieldBitOffset EP0R_DTOG_RX = 14+fieldBitOffset EP0R_DTOG_TX = 6+fieldBitOffset EP0R_EA = 0+fieldBitOffset EP0R_EP_KIND = 8+fieldBitOffset EP0R_EP_TYPE = 9+fieldBitOffset EP0R_SETUP = 11+fieldBitOffset EP0R_STAT_RX = 12+fieldBitOffset EP0R_STAT_TX = 4+fieldBitOffset EP1R_CTR_RX = 15+fieldBitOffset EP1R_CTR_TX = 7+fieldBitOffset EP1R_DTOG_RX = 14+fieldBitOffset EP1R_DTOG_TX = 6+fieldBitOffset EP1R_EA = 0+fieldBitOffset EP1R_EP_KIND = 8+fieldBitOffset EP1R_EP_TYPE = 9+fieldBitOffset EP1R_SETUP = 11+fieldBitOffset EP1R_STAT_RX = 12+fieldBitOffset EP1R_STAT_TX = 4+fieldBitOffset EP2R_CTR_RX = 15+fieldBitOffset EP2R_CTR_TX = 7+fieldBitOffset EP2R_DTOG_RX = 14+fieldBitOffset EP2R_DTOG_TX = 6+fieldBitOffset EP2R_EA = 0+fieldBitOffset EP2R_EP_KIND = 8+fieldBitOffset EP2R_EP_TYPE = 9+fieldBitOffset EP2R_SETUP = 11+fieldBitOffset EP2R_STAT_RX = 12+fieldBitOffset EP2R_STAT_TX = 4+fieldBitOffset EP3R_CTR_RX = 15+fieldBitOffset EP3R_CTR_TX = 7+fieldBitOffset EP3R_DTOG_RX = 14+fieldBitOffset EP3R_DTOG_TX = 6+fieldBitOffset EP3R_EA = 0+fieldBitOffset EP3R_EP_KIND = 8+fieldBitOffset EP3R_EP_TYPE = 9+fieldBitOffset EP3R_SETUP = 11+fieldBitOffset EP3R_STAT_RX = 12+fieldBitOffset EP3R_STAT_TX = 4+fieldBitOffset EP4R_CTR_RX = 15+fieldBitOffset EP4R_CTR_TX = 7+fieldBitOffset EP4R_DTOG_RX = 14+fieldBitOffset EP4R_DTOG_TX = 6+fieldBitOffset EP4R_EA = 0+fieldBitOffset EP4R_EP_KIND = 8+fieldBitOffset EP4R_EP_TYPE = 9+fieldBitOffset EP4R_SETUP = 11+fieldBitOffset EP4R_STAT_RX = 12+fieldBitOffset EP4R_STAT_TX = 4+fieldBitOffset EP5R_CTR_RX = 15+fieldBitOffset EP5R_CTR_TX = 7+fieldBitOffset EP5R_DTOG_RX = 14+fieldBitOffset EP5R_DTOG_TX = 6+fieldBitOffset EP5R_EA = 0+fieldBitOffset EP5R_EP_KIND = 8+fieldBitOffset EP5R_EP_TYPE = 9+fieldBitOffset EP5R_SETUP = 11+fieldBitOffset EP5R_STAT_RX = 12+fieldBitOffset EP5R_STAT_TX = 4+fieldBitOffset EP6R_CTR_RX = 15+fieldBitOffset EP6R_CTR_TX = 7+fieldBitOffset EP6R_DTOG_RX = 14+fieldBitOffset EP6R_DTOG_TX = 6+fieldBitOffset EP6R_EA = 0+fieldBitOffset EP6R_EP_KIND = 8+fieldBitOffset EP6R_EP_TYPE = 9+fieldBitOffset EP6R_SETUP = 11+fieldBitOffset EP6R_STAT_RX = 12+fieldBitOffset EP6R_STAT_TX = 4+fieldBitOffset EP7R_CTR_RX = 15+fieldBitOffset EP7R_CTR_TX = 7+fieldBitOffset EP7R_DTOG_RX = 14+fieldBitOffset EP7R_DTOG_TX = 6+fieldBitOffset EP7R_EA = 0+fieldBitOffset EP7R_EP_KIND = 8+fieldBitOffset EP7R_EP_TYPE = 9+fieldBitOffset EP7R_SETUP = 11+fieldBitOffset EP7R_STAT_RX = 12+fieldBitOffset EP7R_STAT_TX = 4+fieldBitOffset EVCR_EVOE = 7+fieldBitOffset EVCR_PIN = 0+fieldBitOffset EVCR_PORT = 4+fieldBitOffset EXTICR1_EXTI0 = 0+fieldBitOffset EXTICR1_EXTI1 = 4+fieldBitOffset EXTICR1_EXTI2 = 8+fieldBitOffset EXTICR1_EXTI3 = 12+fieldBitOffset EXTICR2_EXTI4 = 0+fieldBitOffset EXTICR2_EXTI5 = 4+fieldBitOffset EXTICR2_EXTI6 = 8+fieldBitOffset EXTICR2_EXTI7 = 12+fieldBitOffset EXTICR3_EXTI10 = 8+fieldBitOffset EXTICR3_EXTI11 = 12+fieldBitOffset EXTICR3_EXTI8 = 0+fieldBitOffset EXTICR3_EXTI9 = 4+fieldBitOffset EXTICR4_EXTI12 = 0+fieldBitOffset EXTICR4_EXTI13 = 4+fieldBitOffset EXTICR4_EXTI14 = 8+fieldBitOffset EXTICR4_EXTI15 = 12+fieldBitOffset F0R1_FB0 = 0+fieldBitOffset F0R1_FB1 = 1+fieldBitOffset F0R1_FB10 = 10+fieldBitOffset F0R1_FB11 = 11+fieldBitOffset F0R1_FB12 = 12+fieldBitOffset F0R1_FB13 = 13+fieldBitOffset F0R1_FB14 = 14+fieldBitOffset F0R1_FB15 = 15+fieldBitOffset F0R1_FB16 = 16+fieldBitOffset F0R1_FB17 = 17+fieldBitOffset F0R1_FB18 = 18+fieldBitOffset F0R1_FB19 = 19+fieldBitOffset F0R1_FB2 = 2+fieldBitOffset F0R1_FB20 = 20+fieldBitOffset F0R1_FB21 = 21+fieldBitOffset F0R1_FB22 = 22+fieldBitOffset F0R1_FB23 = 23+fieldBitOffset F0R1_FB24 = 24+fieldBitOffset F0R1_FB25 = 25+fieldBitOffset F0R1_FB26 = 26+fieldBitOffset F0R1_FB27 = 27+fieldBitOffset F0R1_FB28 = 28+fieldBitOffset F0R1_FB29 = 29+fieldBitOffset F0R1_FB3 = 3+fieldBitOffset F0R1_FB30 = 30+fieldBitOffset F0R1_FB31 = 31+fieldBitOffset F0R1_FB4 = 4+fieldBitOffset F0R1_FB5 = 5+fieldBitOffset F0R1_FB6 = 6+fieldBitOffset F0R1_FB7 = 7+fieldBitOffset F0R1_FB8 = 8+fieldBitOffset F0R1_FB9 = 9+fieldBitOffset F0R2_FB0 = 0+fieldBitOffset F0R2_FB1 = 1+fieldBitOffset F0R2_FB10 = 10+fieldBitOffset F0R2_FB11 = 11+fieldBitOffset F0R2_FB12 = 12+fieldBitOffset F0R2_FB13 = 13+fieldBitOffset F0R2_FB14 = 14+fieldBitOffset F0R2_FB15 = 15+fieldBitOffset F0R2_FB16 = 16+fieldBitOffset F0R2_FB17 = 17+fieldBitOffset F0R2_FB18 = 18+fieldBitOffset F0R2_FB19 = 19+fieldBitOffset F0R2_FB2 = 2+fieldBitOffset F0R2_FB20 = 20+fieldBitOffset F0R2_FB21 = 21+fieldBitOffset F0R2_FB22 = 22+fieldBitOffset F0R2_FB23 = 23+fieldBitOffset F0R2_FB24 = 24+fieldBitOffset F0R2_FB25 = 25+fieldBitOffset F0R2_FB26 = 26+fieldBitOffset F0R2_FB27 = 27+fieldBitOffset F0R2_FB28 = 28+fieldBitOffset F0R2_FB29 = 29+fieldBitOffset F0R2_FB3 = 3+fieldBitOffset F0R2_FB30 = 30+fieldBitOffset F0R2_FB31 = 31+fieldBitOffset F0R2_FB4 = 4+fieldBitOffset F0R2_FB5 = 5+fieldBitOffset F0R2_FB6 = 6+fieldBitOffset F0R2_FB7 = 7+fieldBitOffset F0R2_FB8 = 8+fieldBitOffset F0R2_FB9 = 9+fieldBitOffset F10R1_FB0 = 0+fieldBitOffset F10R1_FB1 = 1+fieldBitOffset F10R1_FB10 = 10+fieldBitOffset F10R1_FB11 = 11+fieldBitOffset F10R1_FB12 = 12+fieldBitOffset F10R1_FB13 = 13+fieldBitOffset F10R1_FB14 = 14+fieldBitOffset F10R1_FB15 = 15+fieldBitOffset F10R1_FB16 = 16+fieldBitOffset F10R1_FB17 = 17+fieldBitOffset F10R1_FB18 = 18+fieldBitOffset F10R1_FB19 = 19+fieldBitOffset F10R1_FB2 = 2+fieldBitOffset F10R1_FB20 = 20+fieldBitOffset F10R1_FB21 = 21+fieldBitOffset F10R1_FB22 = 22+fieldBitOffset F10R1_FB23 = 23+fieldBitOffset F10R1_FB24 = 24+fieldBitOffset F10R1_FB25 = 25+fieldBitOffset F10R1_FB26 = 26+fieldBitOffset F10R1_FB27 = 27+fieldBitOffset F10R1_FB28 = 28+fieldBitOffset F10R1_FB29 = 29+fieldBitOffset F10R1_FB3 = 3+fieldBitOffset F10R1_FB30 = 30+fieldBitOffset F10R1_FB31 = 31+fieldBitOffset F10R1_FB4 = 4+fieldBitOffset F10R1_FB5 = 5+fieldBitOffset F10R1_FB6 = 6+fieldBitOffset F10R1_FB7 = 7+fieldBitOffset F10R1_FB8 = 8+fieldBitOffset F10R1_FB9 = 9+fieldBitOffset F10R2_FB0 = 0+fieldBitOffset F10R2_FB1 = 1+fieldBitOffset F10R2_FB10 = 10+fieldBitOffset F10R2_FB11 = 11+fieldBitOffset F10R2_FB12 = 12+fieldBitOffset F10R2_FB13 = 13+fieldBitOffset F10R2_FB14 = 14+fieldBitOffset F10R2_FB15 = 15+fieldBitOffset F10R2_FB16 = 16+fieldBitOffset F10R2_FB17 = 17+fieldBitOffset F10R2_FB18 = 18+fieldBitOffset F10R2_FB19 = 19+fieldBitOffset F10R2_FB2 = 2+fieldBitOffset F10R2_FB20 = 20+fieldBitOffset F10R2_FB21 = 21+fieldBitOffset F10R2_FB22 = 22+fieldBitOffset F10R2_FB23 = 23+fieldBitOffset F10R2_FB24 = 24+fieldBitOffset F10R2_FB25 = 25+fieldBitOffset F10R2_FB26 = 26+fieldBitOffset F10R2_FB27 = 27+fieldBitOffset F10R2_FB28 = 28+fieldBitOffset F10R2_FB29 = 29+fieldBitOffset F10R2_FB3 = 3+fieldBitOffset F10R2_FB30 = 30+fieldBitOffset F10R2_FB31 = 31+fieldBitOffset F10R2_FB4 = 4+fieldBitOffset F10R2_FB5 = 5+fieldBitOffset F10R2_FB6 = 6+fieldBitOffset F10R2_FB7 = 7+fieldBitOffset F10R2_FB8 = 8+fieldBitOffset F10R2_FB9 = 9+fieldBitOffset F11R1_FB0 = 0+fieldBitOffset F11R1_FB1 = 1+fieldBitOffset F11R1_FB10 = 10+fieldBitOffset F11R1_FB11 = 11+fieldBitOffset F11R1_FB12 = 12+fieldBitOffset F11R1_FB13 = 13+fieldBitOffset F11R1_FB14 = 14+fieldBitOffset F11R1_FB15 = 15+fieldBitOffset F11R1_FB16 = 16+fieldBitOffset F11R1_FB17 = 17+fieldBitOffset F11R1_FB18 = 18+fieldBitOffset F11R1_FB19 = 19+fieldBitOffset F11R1_FB2 = 2+fieldBitOffset F11R1_FB20 = 20+fieldBitOffset F11R1_FB21 = 21+fieldBitOffset F11R1_FB22 = 22+fieldBitOffset F11R1_FB23 = 23+fieldBitOffset F11R1_FB24 = 24+fieldBitOffset F11R1_FB25 = 25+fieldBitOffset F11R1_FB26 = 26+fieldBitOffset F11R1_FB27 = 27+fieldBitOffset F11R1_FB28 = 28+fieldBitOffset F11R1_FB29 = 29+fieldBitOffset F11R1_FB3 = 3+fieldBitOffset F11R1_FB30 = 30+fieldBitOffset F11R1_FB31 = 31+fieldBitOffset F11R1_FB4 = 4+fieldBitOffset F11R1_FB5 = 5+fieldBitOffset F11R1_FB6 = 6+fieldBitOffset F11R1_FB7 = 7+fieldBitOffset F11R1_FB8 = 8+fieldBitOffset F11R1_FB9 = 9+fieldBitOffset F11R2_FB0 = 0+fieldBitOffset F11R2_FB1 = 1+fieldBitOffset F11R2_FB10 = 10+fieldBitOffset F11R2_FB11 = 11+fieldBitOffset F11R2_FB12 = 12+fieldBitOffset F11R2_FB13 = 13+fieldBitOffset F11R2_FB14 = 14+fieldBitOffset F11R2_FB15 = 15+fieldBitOffset F11R2_FB16 = 16+fieldBitOffset F11R2_FB17 = 17+fieldBitOffset F11R2_FB18 = 18+fieldBitOffset F11R2_FB19 = 19+fieldBitOffset F11R2_FB2 = 2+fieldBitOffset F11R2_FB20 = 20+fieldBitOffset F11R2_FB21 = 21+fieldBitOffset F11R2_FB22 = 22+fieldBitOffset F11R2_FB23 = 23+fieldBitOffset F11R2_FB24 = 24+fieldBitOffset F11R2_FB25 = 25+fieldBitOffset F11R2_FB26 = 26+fieldBitOffset F11R2_FB27 = 27+fieldBitOffset F11R2_FB28 = 28+fieldBitOffset F11R2_FB29 = 29+fieldBitOffset F11R2_FB3 = 3+fieldBitOffset F11R2_FB30 = 30+fieldBitOffset F11R2_FB31 = 31+fieldBitOffset F11R2_FB4 = 4+fieldBitOffset F11R2_FB5 = 5+fieldBitOffset F11R2_FB6 = 6+fieldBitOffset F11R2_FB7 = 7+fieldBitOffset F11R2_FB8 = 8+fieldBitOffset F11R2_FB9 = 9+fieldBitOffset F12R1_FB0 = 0+fieldBitOffset F12R1_FB1 = 1+fieldBitOffset F12R1_FB10 = 10+fieldBitOffset F12R1_FB11 = 11+fieldBitOffset F12R1_FB12 = 12+fieldBitOffset F12R1_FB13 = 13+fieldBitOffset F12R1_FB14 = 14+fieldBitOffset F12R1_FB15 = 15+fieldBitOffset F12R1_FB16 = 16+fieldBitOffset F12R1_FB17 = 17+fieldBitOffset F12R1_FB18 = 18+fieldBitOffset F12R1_FB19 = 19+fieldBitOffset F12R1_FB2 = 2+fieldBitOffset F12R1_FB20 = 20+fieldBitOffset F12R1_FB21 = 21+fieldBitOffset F12R1_FB22 = 22+fieldBitOffset F12R1_FB23 = 23+fieldBitOffset F12R1_FB24 = 24+fieldBitOffset F12R1_FB25 = 25+fieldBitOffset F12R1_FB26 = 26+fieldBitOffset F12R1_FB27 = 27+fieldBitOffset F12R1_FB28 = 28+fieldBitOffset F12R1_FB29 = 29+fieldBitOffset F12R1_FB3 = 3+fieldBitOffset F12R1_FB30 = 30+fieldBitOffset F12R1_FB31 = 31+fieldBitOffset F12R1_FB4 = 4+fieldBitOffset F12R1_FB5 = 5+fieldBitOffset F12R1_FB6 = 6+fieldBitOffset F12R1_FB7 = 7+fieldBitOffset F12R1_FB8 = 8+fieldBitOffset F12R1_FB9 = 9+fieldBitOffset F12R2_FB0 = 0+fieldBitOffset F12R2_FB1 = 1+fieldBitOffset F12R2_FB10 = 10+fieldBitOffset F12R2_FB11 = 11+fieldBitOffset F12R2_FB12 = 12+fieldBitOffset F12R2_FB13 = 13+fieldBitOffset F12R2_FB14 = 14+fieldBitOffset F12R2_FB15 = 15+fieldBitOffset F12R2_FB16 = 16+fieldBitOffset F12R2_FB17 = 17+fieldBitOffset F12R2_FB18 = 18+fieldBitOffset F12R2_FB19 = 19+fieldBitOffset F12R2_FB2 = 2+fieldBitOffset F12R2_FB20 = 20+fieldBitOffset F12R2_FB21 = 21+fieldBitOffset F12R2_FB22 = 22+fieldBitOffset F12R2_FB23 = 23+fieldBitOffset F12R2_FB24 = 24+fieldBitOffset F12R2_FB25 = 25+fieldBitOffset F12R2_FB26 = 26+fieldBitOffset F12R2_FB27 = 27+fieldBitOffset F12R2_FB28 = 28+fieldBitOffset F12R2_FB29 = 29+fieldBitOffset F12R2_FB3 = 3+fieldBitOffset F12R2_FB30 = 30+fieldBitOffset F12R2_FB31 = 31+fieldBitOffset F12R2_FB4 = 4+fieldBitOffset F12R2_FB5 = 5+fieldBitOffset F12R2_FB6 = 6+fieldBitOffset F12R2_FB7 = 7+fieldBitOffset F12R2_FB8 = 8+fieldBitOffset F12R2_FB9 = 9+fieldBitOffset F13R1_FB0 = 0+fieldBitOffset F13R1_FB1 = 1+fieldBitOffset F13R1_FB10 = 10+fieldBitOffset F13R1_FB11 = 11+fieldBitOffset F13R1_FB12 = 12+fieldBitOffset F13R1_FB13 = 13+fieldBitOffset F13R1_FB14 = 14+fieldBitOffset F13R1_FB15 = 15+fieldBitOffset F13R1_FB16 = 16+fieldBitOffset F13R1_FB17 = 17+fieldBitOffset F13R1_FB18 = 18+fieldBitOffset F13R1_FB19 = 19+fieldBitOffset F13R1_FB2 = 2+fieldBitOffset F13R1_FB20 = 20+fieldBitOffset F13R1_FB21 = 21+fieldBitOffset F13R1_FB22 = 22+fieldBitOffset F13R1_FB23 = 23+fieldBitOffset F13R1_FB24 = 24+fieldBitOffset F13R1_FB25 = 25+fieldBitOffset F13R1_FB26 = 26+fieldBitOffset F13R1_FB27 = 27+fieldBitOffset F13R1_FB28 = 28+fieldBitOffset F13R1_FB29 = 29+fieldBitOffset F13R1_FB3 = 3+fieldBitOffset F13R1_FB30 = 30+fieldBitOffset F13R1_FB31 = 31+fieldBitOffset F13R1_FB4 = 4+fieldBitOffset F13R1_FB5 = 5+fieldBitOffset F13R1_FB6 = 6+fieldBitOffset F13R1_FB7 = 7+fieldBitOffset F13R1_FB8 = 8+fieldBitOffset F13R1_FB9 = 9+fieldBitOffset F13R2_FB0 = 0+fieldBitOffset F13R2_FB1 = 1+fieldBitOffset F13R2_FB10 = 10+fieldBitOffset F13R2_FB11 = 11+fieldBitOffset F13R2_FB12 = 12+fieldBitOffset F13R2_FB13 = 13+fieldBitOffset F13R2_FB14 = 14+fieldBitOffset F13R2_FB15 = 15+fieldBitOffset F13R2_FB16 = 16+fieldBitOffset F13R2_FB17 = 17+fieldBitOffset F13R2_FB18 = 18+fieldBitOffset F13R2_FB19 = 19+fieldBitOffset F13R2_FB2 = 2+fieldBitOffset F13R2_FB20 = 20+fieldBitOffset F13R2_FB21 = 21+fieldBitOffset F13R2_FB22 = 22+fieldBitOffset F13R2_FB23 = 23+fieldBitOffset F13R2_FB24 = 24+fieldBitOffset F13R2_FB25 = 25+fieldBitOffset F13R2_FB26 = 26+fieldBitOffset F13R2_FB27 = 27+fieldBitOffset F13R2_FB28 = 28+fieldBitOffset F13R2_FB29 = 29+fieldBitOffset F13R2_FB3 = 3+fieldBitOffset F13R2_FB30 = 30+fieldBitOffset F13R2_FB31 = 31+fieldBitOffset F13R2_FB4 = 4+fieldBitOffset F13R2_FB5 = 5+fieldBitOffset F13R2_FB6 = 6+fieldBitOffset F13R2_FB7 = 7+fieldBitOffset F13R2_FB8 = 8+fieldBitOffset F13R2_FB9 = 9+fieldBitOffset F1R1_FB0 = 0+fieldBitOffset F1R1_FB1 = 1+fieldBitOffset F1R1_FB10 = 10+fieldBitOffset F1R1_FB11 = 11+fieldBitOffset F1R1_FB12 = 12+fieldBitOffset F1R1_FB13 = 13+fieldBitOffset F1R1_FB14 = 14+fieldBitOffset F1R1_FB15 = 15+fieldBitOffset F1R1_FB16 = 16+fieldBitOffset F1R1_FB17 = 17+fieldBitOffset F1R1_FB18 = 18+fieldBitOffset F1R1_FB19 = 19+fieldBitOffset F1R1_FB2 = 2+fieldBitOffset F1R1_FB20 = 20+fieldBitOffset F1R1_FB21 = 21+fieldBitOffset F1R1_FB22 = 22+fieldBitOffset F1R1_FB23 = 23+fieldBitOffset F1R1_FB24 = 24+fieldBitOffset F1R1_FB25 = 25+fieldBitOffset F1R1_FB26 = 26+fieldBitOffset F1R1_FB27 = 27+fieldBitOffset F1R1_FB28 = 28+fieldBitOffset F1R1_FB29 = 29+fieldBitOffset F1R1_FB3 = 3+fieldBitOffset F1R1_FB30 = 30+fieldBitOffset F1R1_FB31 = 31+fieldBitOffset F1R1_FB4 = 4+fieldBitOffset F1R1_FB5 = 5+fieldBitOffset F1R1_FB6 = 6+fieldBitOffset F1R1_FB7 = 7+fieldBitOffset F1R1_FB8 = 8+fieldBitOffset F1R1_FB9 = 9+fieldBitOffset F1R2_FB0 = 0+fieldBitOffset F1R2_FB1 = 1+fieldBitOffset F1R2_FB10 = 10+fieldBitOffset F1R2_FB11 = 11+fieldBitOffset F1R2_FB12 = 12+fieldBitOffset F1R2_FB13 = 13+fieldBitOffset F1R2_FB14 = 14+fieldBitOffset F1R2_FB15 = 15+fieldBitOffset F1R2_FB16 = 16+fieldBitOffset F1R2_FB17 = 17+fieldBitOffset F1R2_FB18 = 18+fieldBitOffset F1R2_FB19 = 19+fieldBitOffset F1R2_FB2 = 2+fieldBitOffset F1R2_FB20 = 20+fieldBitOffset F1R2_FB21 = 21+fieldBitOffset F1R2_FB22 = 22+fieldBitOffset F1R2_FB23 = 23+fieldBitOffset F1R2_FB24 = 24+fieldBitOffset F1R2_FB25 = 25+fieldBitOffset F1R2_FB26 = 26+fieldBitOffset F1R2_FB27 = 27+fieldBitOffset F1R2_FB28 = 28+fieldBitOffset F1R2_FB29 = 29+fieldBitOffset F1R2_FB3 = 3+fieldBitOffset F1R2_FB30 = 30+fieldBitOffset F1R2_FB31 = 31+fieldBitOffset F1R2_FB4 = 4+fieldBitOffset F1R2_FB5 = 5+fieldBitOffset F1R2_FB6 = 6+fieldBitOffset F1R2_FB7 = 7+fieldBitOffset F1R2_FB8 = 8+fieldBitOffset F1R2_FB9 = 9+fieldBitOffset F2R1_FB0 = 0+fieldBitOffset F2R1_FB1 = 1+fieldBitOffset F2R1_FB10 = 10+fieldBitOffset F2R1_FB11 = 11+fieldBitOffset F2R1_FB12 = 12+fieldBitOffset F2R1_FB13 = 13+fieldBitOffset F2R1_FB14 = 14+fieldBitOffset F2R1_FB15 = 15+fieldBitOffset F2R1_FB16 = 16+fieldBitOffset F2R1_FB17 = 17+fieldBitOffset F2R1_FB18 = 18+fieldBitOffset F2R1_FB19 = 19+fieldBitOffset F2R1_FB2 = 2+fieldBitOffset F2R1_FB20 = 20+fieldBitOffset F2R1_FB21 = 21+fieldBitOffset F2R1_FB22 = 22+fieldBitOffset F2R1_FB23 = 23+fieldBitOffset F2R1_FB24 = 24+fieldBitOffset F2R1_FB25 = 25+fieldBitOffset F2R1_FB26 = 26+fieldBitOffset F2R1_FB27 = 27+fieldBitOffset F2R1_FB28 = 28+fieldBitOffset F2R1_FB29 = 29+fieldBitOffset F2R1_FB3 = 3+fieldBitOffset F2R1_FB30 = 30+fieldBitOffset F2R1_FB31 = 31+fieldBitOffset F2R1_FB4 = 4+fieldBitOffset F2R1_FB5 = 5+fieldBitOffset F2R1_FB6 = 6+fieldBitOffset F2R1_FB7 = 7+fieldBitOffset F2R1_FB8 = 8+fieldBitOffset F2R1_FB9 = 9+fieldBitOffset F2R2_FB0 = 0+fieldBitOffset F2R2_FB1 = 1+fieldBitOffset F2R2_FB10 = 10+fieldBitOffset F2R2_FB11 = 11+fieldBitOffset F2R2_FB12 = 12+fieldBitOffset F2R2_FB13 = 13+fieldBitOffset F2R2_FB14 = 14+fieldBitOffset F2R2_FB15 = 15+fieldBitOffset F2R2_FB16 = 16+fieldBitOffset F2R2_FB17 = 17+fieldBitOffset F2R2_FB18 = 18+fieldBitOffset F2R2_FB19 = 19+fieldBitOffset F2R2_FB2 = 2+fieldBitOffset F2R2_FB20 = 20+fieldBitOffset F2R2_FB21 = 21+fieldBitOffset F2R2_FB22 = 22+fieldBitOffset F2R2_FB23 = 23+fieldBitOffset F2R2_FB24 = 24+fieldBitOffset F2R2_FB25 = 25+fieldBitOffset F2R2_FB26 = 26+fieldBitOffset F2R2_FB27 = 27+fieldBitOffset F2R2_FB28 = 28+fieldBitOffset F2R2_FB29 = 29+fieldBitOffset F2R2_FB3 = 3+fieldBitOffset F2R2_FB30 = 30+fieldBitOffset F2R2_FB31 = 31+fieldBitOffset F2R2_FB4 = 4+fieldBitOffset F2R2_FB5 = 5+fieldBitOffset F2R2_FB6 = 6+fieldBitOffset F2R2_FB7 = 7+fieldBitOffset F2R2_FB8 = 8+fieldBitOffset F2R2_FB9 = 9+fieldBitOffset F3R1_FB0 = 0+fieldBitOffset F3R1_FB1 = 1+fieldBitOffset F3R1_FB10 = 10+fieldBitOffset F3R1_FB11 = 11+fieldBitOffset F3R1_FB12 = 12+fieldBitOffset F3R1_FB13 = 13+fieldBitOffset F3R1_FB14 = 14+fieldBitOffset F3R1_FB15 = 15+fieldBitOffset F3R1_FB16 = 16+fieldBitOffset F3R1_FB17 = 17+fieldBitOffset F3R1_FB18 = 18+fieldBitOffset F3R1_FB19 = 19+fieldBitOffset F3R1_FB2 = 2+fieldBitOffset F3R1_FB20 = 20+fieldBitOffset F3R1_FB21 = 21+fieldBitOffset F3R1_FB22 = 22+fieldBitOffset F3R1_FB23 = 23+fieldBitOffset F3R1_FB24 = 24+fieldBitOffset F3R1_FB25 = 25+fieldBitOffset F3R1_FB26 = 26+fieldBitOffset F3R1_FB27 = 27+fieldBitOffset F3R1_FB28 = 28+fieldBitOffset F3R1_FB29 = 29+fieldBitOffset F3R1_FB3 = 3+fieldBitOffset F3R1_FB30 = 30+fieldBitOffset F3R1_FB31 = 31+fieldBitOffset F3R1_FB4 = 4+fieldBitOffset F3R1_FB5 = 5+fieldBitOffset F3R1_FB6 = 6+fieldBitOffset F3R1_FB7 = 7+fieldBitOffset F3R1_FB8 = 8+fieldBitOffset F3R1_FB9 = 9+fieldBitOffset F3R2_FB0 = 0+fieldBitOffset F3R2_FB1 = 1+fieldBitOffset F3R2_FB10 = 10+fieldBitOffset F3R2_FB11 = 11+fieldBitOffset F3R2_FB12 = 12+fieldBitOffset F3R2_FB13 = 13+fieldBitOffset F3R2_FB14 = 14+fieldBitOffset F3R2_FB15 = 15+fieldBitOffset F3R2_FB16 = 16+fieldBitOffset F3R2_FB17 = 17+fieldBitOffset F3R2_FB18 = 18+fieldBitOffset F3R2_FB19 = 19+fieldBitOffset F3R2_FB2 = 2+fieldBitOffset F3R2_FB20 = 20+fieldBitOffset F3R2_FB21 = 21+fieldBitOffset F3R2_FB22 = 22+fieldBitOffset F3R2_FB23 = 23+fieldBitOffset F3R2_FB24 = 24+fieldBitOffset F3R2_FB25 = 25+fieldBitOffset F3R2_FB26 = 26+fieldBitOffset F3R2_FB27 = 27+fieldBitOffset F3R2_FB28 = 28+fieldBitOffset F3R2_FB29 = 29+fieldBitOffset F3R2_FB3 = 3+fieldBitOffset F3R2_FB30 = 30+fieldBitOffset F3R2_FB31 = 31+fieldBitOffset F3R2_FB4 = 4+fieldBitOffset F3R2_FB5 = 5+fieldBitOffset F3R2_FB6 = 6+fieldBitOffset F3R2_FB7 = 7+fieldBitOffset F3R2_FB8 = 8+fieldBitOffset F3R2_FB9 = 9+fieldBitOffset F4R1_FB0 = 0+fieldBitOffset F4R1_FB1 = 1+fieldBitOffset F4R1_FB10 = 10+fieldBitOffset F4R1_FB11 = 11+fieldBitOffset F4R1_FB12 = 12+fieldBitOffset F4R1_FB13 = 13+fieldBitOffset F4R1_FB14 = 14+fieldBitOffset F4R1_FB15 = 15+fieldBitOffset F4R1_FB16 = 16+fieldBitOffset F4R1_FB17 = 17+fieldBitOffset F4R1_FB18 = 18+fieldBitOffset F4R1_FB19 = 19+fieldBitOffset F4R1_FB2 = 2+fieldBitOffset F4R1_FB20 = 20+fieldBitOffset F4R1_FB21 = 21+fieldBitOffset F4R1_FB22 = 22+fieldBitOffset F4R1_FB23 = 23+fieldBitOffset F4R1_FB24 = 24+fieldBitOffset F4R1_FB25 = 25+fieldBitOffset F4R1_FB26 = 26+fieldBitOffset F4R1_FB27 = 27+fieldBitOffset F4R1_FB28 = 28+fieldBitOffset F4R1_FB29 = 29+fieldBitOffset F4R1_FB3 = 3+fieldBitOffset F4R1_FB30 = 30+fieldBitOffset F4R1_FB31 = 31+fieldBitOffset F4R1_FB4 = 4+fieldBitOffset F4R1_FB5 = 5+fieldBitOffset F4R1_FB6 = 6+fieldBitOffset F4R1_FB7 = 7+fieldBitOffset F4R1_FB8 = 8+fieldBitOffset F4R1_FB9 = 9+fieldBitOffset F4R2_FB0 = 0+fieldBitOffset F4R2_FB1 = 1+fieldBitOffset F4R2_FB10 = 10+fieldBitOffset F4R2_FB11 = 11+fieldBitOffset F4R2_FB12 = 12+fieldBitOffset F4R2_FB13 = 13+fieldBitOffset F4R2_FB14 = 14+fieldBitOffset F4R2_FB15 = 15+fieldBitOffset F4R2_FB16 = 16+fieldBitOffset F4R2_FB17 = 17+fieldBitOffset F4R2_FB18 = 18+fieldBitOffset F4R2_FB19 = 19+fieldBitOffset F4R2_FB2 = 2+fieldBitOffset F4R2_FB20 = 20+fieldBitOffset F4R2_FB21 = 21+fieldBitOffset F4R2_FB22 = 22+fieldBitOffset F4R2_FB23 = 23+fieldBitOffset F4R2_FB24 = 24+fieldBitOffset F4R2_FB25 = 25+fieldBitOffset F4R2_FB26 = 26+fieldBitOffset F4R2_FB27 = 27+fieldBitOffset F4R2_FB28 = 28+fieldBitOffset F4R2_FB29 = 29+fieldBitOffset F4R2_FB3 = 3+fieldBitOffset F4R2_FB30 = 30+fieldBitOffset F4R2_FB31 = 31+fieldBitOffset F4R2_FB4 = 4+fieldBitOffset F4R2_FB5 = 5+fieldBitOffset F4R2_FB6 = 6+fieldBitOffset F4R2_FB7 = 7+fieldBitOffset F4R2_FB8 = 8+fieldBitOffset F4R2_FB9 = 9+fieldBitOffset F5R1_FB0 = 0+fieldBitOffset F5R1_FB1 = 1+fieldBitOffset F5R1_FB10 = 10+fieldBitOffset F5R1_FB11 = 11+fieldBitOffset F5R1_FB12 = 12+fieldBitOffset F5R1_FB13 = 13+fieldBitOffset F5R1_FB14 = 14+fieldBitOffset F5R1_FB15 = 15+fieldBitOffset F5R1_FB16 = 16+fieldBitOffset F5R1_FB17 = 17+fieldBitOffset F5R1_FB18 = 18+fieldBitOffset F5R1_FB19 = 19+fieldBitOffset F5R1_FB2 = 2+fieldBitOffset F5R1_FB20 = 20+fieldBitOffset F5R1_FB21 = 21+fieldBitOffset F5R1_FB22 = 22+fieldBitOffset F5R1_FB23 = 23+fieldBitOffset F5R1_FB24 = 24+fieldBitOffset F5R1_FB25 = 25+fieldBitOffset F5R1_FB26 = 26+fieldBitOffset F5R1_FB27 = 27+fieldBitOffset F5R1_FB28 = 28+fieldBitOffset F5R1_FB29 = 29+fieldBitOffset F5R1_FB3 = 3+fieldBitOffset F5R1_FB30 = 30+fieldBitOffset F5R1_FB31 = 31+fieldBitOffset F5R1_FB4 = 4+fieldBitOffset F5R1_FB5 = 5+fieldBitOffset F5R1_FB6 = 6+fieldBitOffset F5R1_FB7 = 7+fieldBitOffset F5R1_FB8 = 8+fieldBitOffset F5R1_FB9 = 9+fieldBitOffset F5R2_FB0 = 0+fieldBitOffset F5R2_FB1 = 1+fieldBitOffset F5R2_FB10 = 10+fieldBitOffset F5R2_FB11 = 11+fieldBitOffset F5R2_FB12 = 12+fieldBitOffset F5R2_FB13 = 13+fieldBitOffset F5R2_FB14 = 14+fieldBitOffset F5R2_FB15 = 15+fieldBitOffset F5R2_FB16 = 16+fieldBitOffset F5R2_FB17 = 17+fieldBitOffset F5R2_FB18 = 18+fieldBitOffset F5R2_FB19 = 19+fieldBitOffset F5R2_FB2 = 2+fieldBitOffset F5R2_FB20 = 20+fieldBitOffset F5R2_FB21 = 21+fieldBitOffset F5R2_FB22 = 22+fieldBitOffset F5R2_FB23 = 23+fieldBitOffset F5R2_FB24 = 24+fieldBitOffset F5R2_FB25 = 25+fieldBitOffset F5R2_FB26 = 26+fieldBitOffset F5R2_FB27 = 27+fieldBitOffset F5R2_FB28 = 28+fieldBitOffset F5R2_FB29 = 29+fieldBitOffset F5R2_FB3 = 3+fieldBitOffset F5R2_FB30 = 30+fieldBitOffset F5R2_FB31 = 31+fieldBitOffset F5R2_FB4 = 4+fieldBitOffset F5R2_FB5 = 5+fieldBitOffset F5R2_FB6 = 6+fieldBitOffset F5R2_FB7 = 7+fieldBitOffset F5R2_FB8 = 8+fieldBitOffset F5R2_FB9 = 9+fieldBitOffset F6R1_FB0 = 0+fieldBitOffset F6R1_FB1 = 1+fieldBitOffset F6R1_FB10 = 10+fieldBitOffset F6R1_FB11 = 11+fieldBitOffset F6R1_FB12 = 12+fieldBitOffset F6R1_FB13 = 13+fieldBitOffset F6R1_FB14 = 14+fieldBitOffset F6R1_FB15 = 15+fieldBitOffset F6R1_FB16 = 16+fieldBitOffset F6R1_FB17 = 17+fieldBitOffset F6R1_FB18 = 18+fieldBitOffset F6R1_FB19 = 19+fieldBitOffset F6R1_FB2 = 2+fieldBitOffset F6R1_FB20 = 20+fieldBitOffset F6R1_FB21 = 21+fieldBitOffset F6R1_FB22 = 22+fieldBitOffset F6R1_FB23 = 23+fieldBitOffset F6R1_FB24 = 24+fieldBitOffset F6R1_FB25 = 25+fieldBitOffset F6R1_FB26 = 26+fieldBitOffset F6R1_FB27 = 27+fieldBitOffset F6R1_FB28 = 28+fieldBitOffset F6R1_FB29 = 29+fieldBitOffset F6R1_FB3 = 3+fieldBitOffset F6R1_FB30 = 30+fieldBitOffset F6R1_FB31 = 31+fieldBitOffset F6R1_FB4 = 4+fieldBitOffset F6R1_FB5 = 5+fieldBitOffset F6R1_FB6 = 6+fieldBitOffset F6R1_FB7 = 7+fieldBitOffset F6R1_FB8 = 8+fieldBitOffset F6R1_FB9 = 9+fieldBitOffset F6R2_FB0 = 0+fieldBitOffset F6R2_FB1 = 1+fieldBitOffset F6R2_FB10 = 10+fieldBitOffset F6R2_FB11 = 11+fieldBitOffset F6R2_FB12 = 12+fieldBitOffset F6R2_FB13 = 13+fieldBitOffset F6R2_FB14 = 14+fieldBitOffset F6R2_FB15 = 15+fieldBitOffset F6R2_FB16 = 16+fieldBitOffset F6R2_FB17 = 17+fieldBitOffset F6R2_FB18 = 18+fieldBitOffset F6R2_FB19 = 19+fieldBitOffset F6R2_FB2 = 2+fieldBitOffset F6R2_FB20 = 20+fieldBitOffset F6R2_FB21 = 21+fieldBitOffset F6R2_FB22 = 22+fieldBitOffset F6R2_FB23 = 23+fieldBitOffset F6R2_FB24 = 24+fieldBitOffset F6R2_FB25 = 25+fieldBitOffset F6R2_FB26 = 26+fieldBitOffset F6R2_FB27 = 27+fieldBitOffset F6R2_FB28 = 28+fieldBitOffset F6R2_FB29 = 29+fieldBitOffset F6R2_FB3 = 3+fieldBitOffset F6R2_FB30 = 30+fieldBitOffset F6R2_FB31 = 31+fieldBitOffset F6R2_FB4 = 4+fieldBitOffset F6R2_FB5 = 5+fieldBitOffset F6R2_FB6 = 6+fieldBitOffset F6R2_FB7 = 7+fieldBitOffset F6R2_FB8 = 8+fieldBitOffset F6R2_FB9 = 9+fieldBitOffset F7R1_FB0 = 0+fieldBitOffset F7R1_FB1 = 1+fieldBitOffset F7R1_FB10 = 10+fieldBitOffset F7R1_FB11 = 11+fieldBitOffset F7R1_FB12 = 12+fieldBitOffset F7R1_FB13 = 13+fieldBitOffset F7R1_FB14 = 14+fieldBitOffset F7R1_FB15 = 15+fieldBitOffset F7R1_FB16 = 16+fieldBitOffset F7R1_FB17 = 17+fieldBitOffset F7R1_FB18 = 18+fieldBitOffset F7R1_FB19 = 19+fieldBitOffset F7R1_FB2 = 2+fieldBitOffset F7R1_FB20 = 20+fieldBitOffset F7R1_FB21 = 21+fieldBitOffset F7R1_FB22 = 22+fieldBitOffset F7R1_FB23 = 23+fieldBitOffset F7R1_FB24 = 24+fieldBitOffset F7R1_FB25 = 25+fieldBitOffset F7R1_FB26 = 26+fieldBitOffset F7R1_FB27 = 27+fieldBitOffset F7R1_FB28 = 28+fieldBitOffset F7R1_FB29 = 29+fieldBitOffset F7R1_FB3 = 3+fieldBitOffset F7R1_FB30 = 30+fieldBitOffset F7R1_FB31 = 31+fieldBitOffset F7R1_FB4 = 4+fieldBitOffset F7R1_FB5 = 5+fieldBitOffset F7R1_FB6 = 6+fieldBitOffset F7R1_FB7 = 7+fieldBitOffset F7R1_FB8 = 8+fieldBitOffset F7R1_FB9 = 9+fieldBitOffset F7R2_FB0 = 0+fieldBitOffset F7R2_FB1 = 1+fieldBitOffset F7R2_FB10 = 10+fieldBitOffset F7R2_FB11 = 11+fieldBitOffset F7R2_FB12 = 12+fieldBitOffset F7R2_FB13 = 13+fieldBitOffset F7R2_FB14 = 14+fieldBitOffset F7R2_FB15 = 15+fieldBitOffset F7R2_FB16 = 16+fieldBitOffset F7R2_FB17 = 17+fieldBitOffset F7R2_FB18 = 18+fieldBitOffset F7R2_FB19 = 19+fieldBitOffset F7R2_FB2 = 2+fieldBitOffset F7R2_FB20 = 20+fieldBitOffset F7R2_FB21 = 21+fieldBitOffset F7R2_FB22 = 22+fieldBitOffset F7R2_FB23 = 23+fieldBitOffset F7R2_FB24 = 24+fieldBitOffset F7R2_FB25 = 25+fieldBitOffset F7R2_FB26 = 26+fieldBitOffset F7R2_FB27 = 27+fieldBitOffset F7R2_FB28 = 28+fieldBitOffset F7R2_FB29 = 29+fieldBitOffset F7R2_FB3 = 3+fieldBitOffset F7R2_FB30 = 30+fieldBitOffset F7R2_FB31 = 31+fieldBitOffset F7R2_FB4 = 4+fieldBitOffset F7R2_FB5 = 5+fieldBitOffset F7R2_FB6 = 6+fieldBitOffset F7R2_FB7 = 7+fieldBitOffset F7R2_FB8 = 8+fieldBitOffset F7R2_FB9 = 9+fieldBitOffset F8R1_FB0 = 0+fieldBitOffset F8R1_FB1 = 1+fieldBitOffset F8R1_FB10 = 10+fieldBitOffset F8R1_FB11 = 11+fieldBitOffset F8R1_FB12 = 12+fieldBitOffset F8R1_FB13 = 13+fieldBitOffset F8R1_FB14 = 14+fieldBitOffset F8R1_FB15 = 15+fieldBitOffset F8R1_FB16 = 16+fieldBitOffset F8R1_FB17 = 17+fieldBitOffset F8R1_FB18 = 18+fieldBitOffset F8R1_FB19 = 19+fieldBitOffset F8R1_FB2 = 2+fieldBitOffset F8R1_FB20 = 20+fieldBitOffset F8R1_FB21 = 21+fieldBitOffset F8R1_FB22 = 22+fieldBitOffset F8R1_FB23 = 23+fieldBitOffset F8R1_FB24 = 24+fieldBitOffset F8R1_FB25 = 25+fieldBitOffset F8R1_FB26 = 26+fieldBitOffset F8R1_FB27 = 27+fieldBitOffset F8R1_FB28 = 28+fieldBitOffset F8R1_FB29 = 29+fieldBitOffset F8R1_FB3 = 3+fieldBitOffset F8R1_FB30 = 30+fieldBitOffset F8R1_FB31 = 31+fieldBitOffset F8R1_FB4 = 4+fieldBitOffset F8R1_FB5 = 5+fieldBitOffset F8R1_FB6 = 6+fieldBitOffset F8R1_FB7 = 7+fieldBitOffset F8R1_FB8 = 8+fieldBitOffset F8R1_FB9 = 9+fieldBitOffset F8R2_FB0 = 0+fieldBitOffset F8R2_FB1 = 1+fieldBitOffset F8R2_FB10 = 10+fieldBitOffset F8R2_FB11 = 11+fieldBitOffset F8R2_FB12 = 12+fieldBitOffset F8R2_FB13 = 13+fieldBitOffset F8R2_FB14 = 14+fieldBitOffset F8R2_FB15 = 15+fieldBitOffset F8R2_FB16 = 16+fieldBitOffset F8R2_FB17 = 17+fieldBitOffset F8R2_FB18 = 18+fieldBitOffset F8R2_FB19 = 19+fieldBitOffset F8R2_FB2 = 2+fieldBitOffset F8R2_FB20 = 20+fieldBitOffset F8R2_FB21 = 21+fieldBitOffset F8R2_FB22 = 22+fieldBitOffset F8R2_FB23 = 23+fieldBitOffset F8R2_FB24 = 24+fieldBitOffset F8R2_FB25 = 25+fieldBitOffset F8R2_FB26 = 26+fieldBitOffset F8R2_FB27 = 27+fieldBitOffset F8R2_FB28 = 28+fieldBitOffset F8R2_FB29 = 29+fieldBitOffset F8R2_FB3 = 3+fieldBitOffset F8R2_FB30 = 30+fieldBitOffset F8R2_FB31 = 31+fieldBitOffset F8R2_FB4 = 4+fieldBitOffset F8R2_FB5 = 5+fieldBitOffset F8R2_FB6 = 6+fieldBitOffset F8R2_FB7 = 7+fieldBitOffset F8R2_FB8 = 8+fieldBitOffset F8R2_FB9 = 9+fieldBitOffset F9R1_FB0 = 0+fieldBitOffset F9R1_FB1 = 1+fieldBitOffset F9R1_FB10 = 10+fieldBitOffset F9R1_FB11 = 11+fieldBitOffset F9R1_FB12 = 12+fieldBitOffset F9R1_FB13 = 13+fieldBitOffset F9R1_FB14 = 14+fieldBitOffset F9R1_FB15 = 15+fieldBitOffset F9R1_FB16 = 16+fieldBitOffset F9R1_FB17 = 17+fieldBitOffset F9R1_FB18 = 18+fieldBitOffset F9R1_FB19 = 19+fieldBitOffset F9R1_FB2 = 2+fieldBitOffset F9R1_FB20 = 20+fieldBitOffset F9R1_FB21 = 21+fieldBitOffset F9R1_FB22 = 22+fieldBitOffset F9R1_FB23 = 23+fieldBitOffset F9R1_FB24 = 24+fieldBitOffset F9R1_FB25 = 25+fieldBitOffset F9R1_FB26 = 26+fieldBitOffset F9R1_FB27 = 27+fieldBitOffset F9R1_FB28 = 28+fieldBitOffset F9R1_FB29 = 29+fieldBitOffset F9R1_FB3 = 3+fieldBitOffset F9R1_FB30 = 30+fieldBitOffset F9R1_FB31 = 31+fieldBitOffset F9R1_FB4 = 4+fieldBitOffset F9R1_FB5 = 5+fieldBitOffset F9R1_FB6 = 6+fieldBitOffset F9R1_FB7 = 7+fieldBitOffset F9R1_FB8 = 8+fieldBitOffset F9R1_FB9 = 9+fieldBitOffset F9R2_FB0 = 0+fieldBitOffset F9R2_FB1 = 1+fieldBitOffset F9R2_FB10 = 10+fieldBitOffset F9R2_FB11 = 11+fieldBitOffset F9R2_FB12 = 12+fieldBitOffset F9R2_FB13 = 13+fieldBitOffset F9R2_FB14 = 14+fieldBitOffset F9R2_FB15 = 15+fieldBitOffset F9R2_FB16 = 16+fieldBitOffset F9R2_FB17 = 17+fieldBitOffset F9R2_FB18 = 18+fieldBitOffset F9R2_FB19 = 19+fieldBitOffset F9R2_FB2 = 2+fieldBitOffset F9R2_FB20 = 20+fieldBitOffset F9R2_FB21 = 21+fieldBitOffset F9R2_FB22 = 22+fieldBitOffset F9R2_FB23 = 23+fieldBitOffset F9R2_FB24 = 24+fieldBitOffset F9R2_FB25 = 25+fieldBitOffset F9R2_FB26 = 26+fieldBitOffset F9R2_FB27 = 27+fieldBitOffset F9R2_FB28 = 28+fieldBitOffset F9R2_FB29 = 29+fieldBitOffset F9R2_FB3 = 3+fieldBitOffset F9R2_FB30 = 30+fieldBitOffset F9R2_FB31 = 31+fieldBitOffset F9R2_FB4 = 4+fieldBitOffset F9R2_FB5 = 5+fieldBitOffset F9R2_FB6 = 6+fieldBitOffset F9R2_FB7 = 7+fieldBitOffset F9R2_FB8 = 8+fieldBitOffset F9R2_FB9 = 9+fieldBitOffset FIFO_FIFOData = 0+fieldBitOffset FIFOCNT_FIF0COUNT = 0+fieldBitOffset FNR_FN = 0+fieldBitOffset FNR_LCK = 13+fieldBitOffset FNR_LSOF = 11+fieldBitOffset FNR_RXDM = 14+fieldBitOffset FNR_RXDP = 15+fieldBitOffset FTSR_TR0 = 0+fieldBitOffset FTSR_TR1 = 1+fieldBitOffset FTSR_TR10 = 10+fieldBitOffset FTSR_TR11 = 11+fieldBitOffset FTSR_TR12 = 12+fieldBitOffset FTSR_TR13 = 13+fieldBitOffset FTSR_TR14 = 14+fieldBitOffset FTSR_TR15 = 15+fieldBitOffset FTSR_TR16 = 16+fieldBitOffset FTSR_TR17 = 17+fieldBitOffset FTSR_TR18 = 18+fieldBitOffset FTSR_TR2 = 2+fieldBitOffset FTSR_TR3 = 3+fieldBitOffset FTSR_TR4 = 4+fieldBitOffset FTSR_TR5 = 5+fieldBitOffset FTSR_TR6 = 6+fieldBitOffset FTSR_TR7 = 7+fieldBitOffset FTSR_TR8 = 8+fieldBitOffset FTSR_TR9 = 9+fieldBitOffset GTPR_GT = 8+fieldBitOffset GTPR_PSC = 0+fieldBitOffset HTR_HT = 0+fieldBitOffset I2SCFGR_CHLEN = 0+fieldBitOffset I2SCFGR_CKPOL = 3+fieldBitOffset I2SCFGR_DATLEN = 1+fieldBitOffset I2SCFGR_I2SCFG = 8+fieldBitOffset I2SCFGR_I2SE = 10+fieldBitOffset I2SCFGR_I2SMOD = 11+fieldBitOffset I2SCFGR_I2SSTD = 4+fieldBitOffset I2SCFGR_PCMSYNC = 7+fieldBitOffset I2SPR_I2SDIV = 0+fieldBitOffset I2SPR_MCKOE = 9+fieldBitOffset I2SPR_ODD = 8+fieldBitOffset IABR0_ACTIVE = 0+fieldBitOffset IABR1_ACTIVE = 0+fieldBitOffset ICER0_CLRENA = 0+fieldBitOffset ICER1_CLRENA = 0+fieldBitOffset ICPR0_CLRPEND = 0+fieldBitOffset ICPR1_CLRPEND = 0+fieldBitOffset ICR_CCRCFAILC = 0+fieldBitOffset ICR_CEATAENDC = 23+fieldBitOffset ICR_CMDRENDC = 6+fieldBitOffset ICR_CMDSENTC = 7+fieldBitOffset ICR_CTIMEOUTC = 2+fieldBitOffset ICR_DATAENDC = 8+fieldBitOffset ICR_DBCKENDC = 10+fieldBitOffset ICR_DCRCFAILC = 1+fieldBitOffset ICR_DTIMEOUTC = 3+fieldBitOffset ICR_RXOVERRC = 5+fieldBitOffset ICR_SDIOITC = 22+fieldBitOffset ICR_STBITERRC = 9+fieldBitOffset ICR_TXUNDERRC = 4+fieldBitOffset ICTR_INTLINESNUM = 0+fieldBitOffset IDCODE_DEV_ID = 0+fieldBitOffset IDCODE_REV_ID = 16+fieldBitOffset IDR_IDR = 0+fieldBitOffset IDR_IDR0 = 0+fieldBitOffset IDR_IDR1 = 1+fieldBitOffset IDR_IDR10 = 10+fieldBitOffset IDR_IDR11 = 11+fieldBitOffset IDR_IDR12 = 12+fieldBitOffset IDR_IDR13 = 13+fieldBitOffset IDR_IDR14 = 14+fieldBitOffset IDR_IDR15 = 15+fieldBitOffset IDR_IDR2 = 2+fieldBitOffset IDR_IDR3 = 3+fieldBitOffset IDR_IDR4 = 4+fieldBitOffset IDR_IDR5 = 5+fieldBitOffset IDR_IDR6 = 6+fieldBitOffset IDR_IDR7 = 7+fieldBitOffset IDR_IDR8 = 8+fieldBitOffset IDR_IDR9 = 9+fieldBitOffset IFCR_CGIF1 = 0+fieldBitOffset IFCR_CGIF2 = 4+fieldBitOffset IFCR_CGIF3 = 8+fieldBitOffset IFCR_CGIF4 = 12+fieldBitOffset IFCR_CGIF5 = 16+fieldBitOffset IFCR_CGIF6 = 20+fieldBitOffset IFCR_CGIF7 = 24+fieldBitOffset IFCR_CHTIF1 = 2+fieldBitOffset IFCR_CHTIF2 = 6+fieldBitOffset IFCR_CHTIF3 = 10+fieldBitOffset IFCR_CHTIF4 = 14+fieldBitOffset IFCR_CHTIF5 = 18+fieldBitOffset IFCR_CHTIF6 = 22+fieldBitOffset IFCR_CHTIF7 = 26+fieldBitOffset IFCR_CTCIF1 = 1+fieldBitOffset IFCR_CTCIF2 = 5+fieldBitOffset IFCR_CTCIF3 = 9+fieldBitOffset IFCR_CTCIF4 = 13+fieldBitOffset IFCR_CTCIF5 = 17+fieldBitOffset IFCR_CTCIF6 = 21+fieldBitOffset IFCR_CTCIF7 = 25+fieldBitOffset IFCR_CTEIF1 = 3+fieldBitOffset IFCR_CTEIF2 = 7+fieldBitOffset IFCR_CTEIF3 = 11+fieldBitOffset IFCR_CTEIF4 = 15+fieldBitOffset IFCR_CTEIF5 = 19+fieldBitOffset IFCR_CTEIF6 = 23+fieldBitOffset IFCR_CTEIF7 = 27+fieldBitOffset IMR_MR0 = 0+fieldBitOffset IMR_MR1 = 1+fieldBitOffset IMR_MR10 = 10+fieldBitOffset IMR_MR11 = 11+fieldBitOffset IMR_MR12 = 12+fieldBitOffset IMR_MR13 = 13+fieldBitOffset IMR_MR14 = 14+fieldBitOffset IMR_MR15 = 15+fieldBitOffset IMR_MR16 = 16+fieldBitOffset IMR_MR17 = 17+fieldBitOffset IMR_MR18 = 18+fieldBitOffset IMR_MR2 = 2+fieldBitOffset IMR_MR3 = 3+fieldBitOffset IMR_MR4 = 4+fieldBitOffset IMR_MR5 = 5+fieldBitOffset IMR_MR6 = 6+fieldBitOffset IMR_MR7 = 7+fieldBitOffset IMR_MR8 = 8+fieldBitOffset IMR_MR9 = 9+fieldBitOffset IPR0_IPR_N0 = 0+fieldBitOffset IPR0_IPR_N1 = 8+fieldBitOffset IPR0_IPR_N2 = 16+fieldBitOffset IPR0_IPR_N3 = 24+fieldBitOffset IPR1_IPR_N0 = 0+fieldBitOffset IPR1_IPR_N1 = 8+fieldBitOffset IPR1_IPR_N2 = 16+fieldBitOffset IPR1_IPR_N3 = 24+fieldBitOffset IPR10_IPR_N0 = 0+fieldBitOffset IPR10_IPR_N1 = 8+fieldBitOffset IPR10_IPR_N2 = 16+fieldBitOffset IPR10_IPR_N3 = 24+fieldBitOffset IPR11_IPR_N0 = 0+fieldBitOffset IPR11_IPR_N1 = 8+fieldBitOffset IPR11_IPR_N2 = 16+fieldBitOffset IPR11_IPR_N3 = 24+fieldBitOffset IPR12_IPR_N0 = 0+fieldBitOffset IPR12_IPR_N1 = 8+fieldBitOffset IPR12_IPR_N2 = 16+fieldBitOffset IPR12_IPR_N3 = 24+fieldBitOffset IPR13_IPR_N0 = 0+fieldBitOffset IPR13_IPR_N1 = 8+fieldBitOffset IPR13_IPR_N2 = 16+fieldBitOffset IPR13_IPR_N3 = 24+fieldBitOffset IPR14_IPR_N0 = 0+fieldBitOffset IPR14_IPR_N1 = 8+fieldBitOffset IPR14_IPR_N2 = 16+fieldBitOffset IPR14_IPR_N3 = 24+fieldBitOffset IPR2_IPR_N0 = 0+fieldBitOffset IPR2_IPR_N1 = 8+fieldBitOffset IPR2_IPR_N2 = 16+fieldBitOffset IPR2_IPR_N3 = 24+fieldBitOffset IPR3_IPR_N0 = 0+fieldBitOffset IPR3_IPR_N1 = 8+fieldBitOffset IPR3_IPR_N2 = 16+fieldBitOffset IPR3_IPR_N3 = 24+fieldBitOffset IPR4_IPR_N0 = 0+fieldBitOffset IPR4_IPR_N1 = 8+fieldBitOffset IPR4_IPR_N2 = 16+fieldBitOffset IPR4_IPR_N3 = 24+fieldBitOffset IPR5_IPR_N0 = 0+fieldBitOffset IPR5_IPR_N1 = 8+fieldBitOffset IPR5_IPR_N2 = 16+fieldBitOffset IPR5_IPR_N3 = 24+fieldBitOffset IPR6_IPR_N0 = 0+fieldBitOffset IPR6_IPR_N1 = 8+fieldBitOffset IPR6_IPR_N2 = 16+fieldBitOffset IPR6_IPR_N3 = 24+fieldBitOffset IPR7_IPR_N0 = 0+fieldBitOffset IPR7_IPR_N1 = 8+fieldBitOffset IPR7_IPR_N2 = 16+fieldBitOffset IPR7_IPR_N3 = 24+fieldBitOffset IPR8_IPR_N0 = 0+fieldBitOffset IPR8_IPR_N1 = 8+fieldBitOffset IPR8_IPR_N2 = 16+fieldBitOffset IPR8_IPR_N3 = 24+fieldBitOffset IPR9_IPR_N0 = 0+fieldBitOffset IPR9_IPR_N1 = 8+fieldBitOffset IPR9_IPR_N2 = 16+fieldBitOffset IPR9_IPR_N3 = 24+fieldBitOffset ISER0_SETENA = 0+fieldBitOffset ISER1_SETENA = 0+fieldBitOffset ISPR0_SETPEND = 0+fieldBitOffset ISPR1_SETPEND = 0+fieldBitOffset ISR_GIF1 = 0+fieldBitOffset ISR_GIF2 = 4+fieldBitOffset ISR_GIF3 = 8+fieldBitOffset ISR_GIF4 = 12+fieldBitOffset ISR_GIF5 = 16+fieldBitOffset ISR_GIF6 = 20+fieldBitOffset ISR_GIF7 = 24+fieldBitOffset ISR_HTIF1 = 2+fieldBitOffset ISR_HTIF2 = 6+fieldBitOffset ISR_HTIF3 = 10+fieldBitOffset ISR_HTIF4 = 14+fieldBitOffset ISR_HTIF5 = 18+fieldBitOffset ISR_HTIF6 = 22+fieldBitOffset ISR_HTIF7 = 26+fieldBitOffset ISR_TCIF1 = 1+fieldBitOffset ISR_TCIF2 = 5+fieldBitOffset ISR_TCIF3 = 9+fieldBitOffset ISR_TCIF4 = 13+fieldBitOffset ISR_TCIF5 = 17+fieldBitOffset ISR_TCIF6 = 21+fieldBitOffset ISR_TCIF7 = 25+fieldBitOffset ISR_TEIF1 = 3+fieldBitOffset ISR_TEIF2 = 7+fieldBitOffset ISR_TEIF3 = 11+fieldBitOffset ISR_TEIF4 = 15+fieldBitOffset ISR_TEIF5 = 19+fieldBitOffset ISR_TEIF6 = 23+fieldBitOffset ISR_TEIF7 = 27+fieldBitOffset ISTR_CTR = 15+fieldBitOffset ISTR_DIR = 4+fieldBitOffset ISTR_EP_ID = 0+fieldBitOffset ISTR_ERR = 13+fieldBitOffset ISTR_ESOF = 8+fieldBitOffset ISTR_PMAOVR = 14+fieldBitOffset ISTR_RESET = 10+fieldBitOffset ISTR_SOF = 9+fieldBitOffset ISTR_SUSP = 11+fieldBitOffset ISTR_WKUP = 12+fieldBitOffset JDR1_JDATA = 0+fieldBitOffset JDR2_JDATA = 0+fieldBitOffset JDR3_JDATA = 0+fieldBitOffset JDR4_JDATA = 0+fieldBitOffset JOFR1_JOFFSET1 = 0+fieldBitOffset JOFR2_JOFFSET2 = 0+fieldBitOffset JOFR3_JOFFSET3 = 0+fieldBitOffset JOFR4_JOFFSET4 = 0+fieldBitOffset JSQR_JL = 20+fieldBitOffset JSQR_JSQ1 = 0+fieldBitOffset JSQR_JSQ2 = 5+fieldBitOffset JSQR_JSQ3 = 10+fieldBitOffset JSQR_JSQ4 = 15+fieldBitOffset KEYR_KEY = 0+fieldBitOffset KR_KEY = 0+fieldBitOffset LCKR_LCK0 = 0+fieldBitOffset LCKR_LCK1 = 1+fieldBitOffset LCKR_LCK10 = 10+fieldBitOffset LCKR_LCK11 = 11+fieldBitOffset LCKR_LCK12 = 12+fieldBitOffset LCKR_LCK13 = 13+fieldBitOffset LCKR_LCK14 = 14+fieldBitOffset LCKR_LCK15 = 15+fieldBitOffset LCKR_LCK2 = 2+fieldBitOffset LCKR_LCK3 = 3+fieldBitOffset LCKR_LCK4 = 4+fieldBitOffset LCKR_LCK5 = 5+fieldBitOffset LCKR_LCK6 = 6+fieldBitOffset LCKR_LCK7 = 7+fieldBitOffset LCKR_LCK8 = 8+fieldBitOffset LCKR_LCK9 = 9+fieldBitOffset LCKR_LCKK = 16+fieldBitOffset LTR_LT = 0+fieldBitOffset MAPR_ADC1_ETRGINJ_REMAP = 17+fieldBitOffset MAPR_ADC1_ETRGREG_REMAP = 18+fieldBitOffset MAPR_ADC2_ETRGINJ_REMAP = 19+fieldBitOffset MAPR_ADC2_ETRGREG_REMAP = 20+fieldBitOffset MAPR_CAN_REMAP = 13+fieldBitOffset MAPR_I2C1_REMAP = 1+fieldBitOffset MAPR_PD01_REMAP = 15+fieldBitOffset MAPR_SPI1_REMAP = 0+fieldBitOffset MAPR_SWJ_CFG = 24+fieldBitOffset MAPR_TIM1_REMAP = 6+fieldBitOffset MAPR_TIM2_REMAP = 8+fieldBitOffset MAPR_TIM3_REMAP = 10+fieldBitOffset MAPR_TIM4_REMAP = 12+fieldBitOffset MAPR_TIM5CH4_IREMAP = 16+fieldBitOffset MAPR_USART1_REMAP = 2+fieldBitOffset MAPR_USART2_REMAP = 3+fieldBitOffset MAPR_USART3_REMAP = 4+fieldBitOffset MAPR2_FSMC_NADV = 10+fieldBitOffset MAPR2_TIM10_REMAP = 6+fieldBitOffset MAPR2_TIM11_REMAP = 7+fieldBitOffset MAPR2_TIM13_REMAP = 8+fieldBitOffset MAPR2_TIM14_REMAP = 9+fieldBitOffset MAPR2_TIM9_REMAP = 5+fieldBitOffset MASK_CCRCFAILIE = 0+fieldBitOffset MASK_CEATENDIE = 23+fieldBitOffset MASK_CMDACTIE = 11+fieldBitOffset MASK_CMDRENDIE = 6+fieldBitOffset MASK_CMDSENTIE = 7+fieldBitOffset MASK_CTIMEOUTIE = 2+fieldBitOffset MASK_DATAENDIE = 8+fieldBitOffset MASK_DBACKENDIE = 10+fieldBitOffset MASK_DCRCFAILIE = 1+fieldBitOffset MASK_DTIMEOUTIE = 3+fieldBitOffset MASK_RXACTIE = 13+fieldBitOffset MASK_RXDAVLIE = 21+fieldBitOffset MASK_RXFIFOEIE = 19+fieldBitOffset MASK_RXFIFOFIE = 17+fieldBitOffset MASK_RXFIFOHFIE = 15+fieldBitOffset MASK_RXOVERRIE = 5+fieldBitOffset MASK_SDIOITIE = 22+fieldBitOffset MASK_STBITERRIE = 9+fieldBitOffset MASK_TXACTIE = 12+fieldBitOffset MASK_TXDAVLIE = 20+fieldBitOffset MASK_TXFIFOEIE = 18+fieldBitOffset MASK_TXFIFOFIE = 16+fieldBitOffset MASK_TXFIFOHEIE = 14+fieldBitOffset MASK_TXUNDERRIE = 4+fieldBitOffset OAR1_ADD0 = 0+fieldBitOffset OAR1_ADD10 = 8+fieldBitOffset OAR1_ADD7 = 1+fieldBitOffset OAR1_ADDMODE = 15+fieldBitOffset OAR2_ADD2 = 1+fieldBitOffset OAR2_ENDUAL = 0+fieldBitOffset OBR_Data0 = 10+fieldBitOffset OBR_Data1 = 18+fieldBitOffset OBR_OPTERR = 0+fieldBitOffset OBR_RDPRT = 1+fieldBitOffset OBR_WDG_SW = 2+fieldBitOffset OBR_nRST_STDBY = 4+fieldBitOffset OBR_nRST_STOP = 3+fieldBitOffset ODR_ODR0 = 0+fieldBitOffset ODR_ODR1 = 1+fieldBitOffset ODR_ODR10 = 10+fieldBitOffset ODR_ODR11 = 11+fieldBitOffset ODR_ODR12 = 12+fieldBitOffset ODR_ODR13 = 13+fieldBitOffset ODR_ODR14 = 14+fieldBitOffset ODR_ODR15 = 15+fieldBitOffset ODR_ODR2 = 2+fieldBitOffset ODR_ODR3 = 3+fieldBitOffset ODR_ODR4 = 4+fieldBitOffset ODR_ODR5 = 5+fieldBitOffset ODR_ODR6 = 6+fieldBitOffset ODR_ODR7 = 7+fieldBitOffset ODR_ODR8 = 8+fieldBitOffset ODR_ODR9 = 9+fieldBitOffset OPTKEYR_OPTKEY = 0+fieldBitOffset PATT2_ATTHIZx = 24+fieldBitOffset PATT2_ATTHOLDx = 16+fieldBitOffset PATT2_ATTSETx = 0+fieldBitOffset PATT2_ATTWAITx = 8+fieldBitOffset PATT3_ATTHIZx = 24+fieldBitOffset PATT3_ATTHOLDx = 16+fieldBitOffset PATT3_ATTSETx = 0+fieldBitOffset PATT3_ATTWAITx = 8+fieldBitOffset PATT4_ATTHIZx = 24+fieldBitOffset PATT4_ATTHOLDx = 16+fieldBitOffset PATT4_ATTSETx = 0+fieldBitOffset PATT4_ATTWAITx = 8+fieldBitOffset PCR2_ECCEN = 6+fieldBitOffset PCR2_ECCPS = 17+fieldBitOffset PCR2_PBKEN = 2+fieldBitOffset PCR2_PTYP = 3+fieldBitOffset PCR2_PWAITEN = 1+fieldBitOffset PCR2_PWID = 4+fieldBitOffset PCR2_TAR = 13+fieldBitOffset PCR2_TCLR = 9+fieldBitOffset PCR3_ECCEN = 6+fieldBitOffset PCR3_ECCPS = 17+fieldBitOffset PCR3_PBKEN = 2+fieldBitOffset PCR3_PTYP = 3+fieldBitOffset PCR3_PWAITEN = 1+fieldBitOffset PCR3_PWID = 4+fieldBitOffset PCR3_TAR = 13+fieldBitOffset PCR3_TCLR = 9+fieldBitOffset PCR4_ECCEN = 6+fieldBitOffset PCR4_ECCPS = 17+fieldBitOffset PCR4_PBKEN = 2+fieldBitOffset PCR4_PTYP = 3+fieldBitOffset PCR4_PWAITEN = 1+fieldBitOffset PCR4_PWID = 4+fieldBitOffset PCR4_TAR = 13+fieldBitOffset PCR4_TCLR = 9+fieldBitOffset PIO4_IOHIZx = 24+fieldBitOffset PIO4_IOHOLDx = 16+fieldBitOffset PIO4_IOSETx = 0+fieldBitOffset PIO4_IOWAITx = 8+fieldBitOffset PMEM2_MEMHIZx = 24+fieldBitOffset PMEM2_MEMHOLDx = 16+fieldBitOffset PMEM2_MEMSETx = 0+fieldBitOffset PMEM2_MEMWAITx = 8+fieldBitOffset PMEM3_MEMHIZx = 24+fieldBitOffset PMEM3_MEMHOLDx = 16+fieldBitOffset PMEM3_MEMSETx = 0+fieldBitOffset PMEM3_MEMWAITx = 8+fieldBitOffset PMEM4_MEMHIZx = 24+fieldBitOffset PMEM4_MEMHOLDx = 16+fieldBitOffset PMEM4_MEMSETx = 0+fieldBitOffset PMEM4_MEMWAITx = 8+fieldBitOffset POWER_PWRCTRL = 0+fieldBitOffset PR_PR = 0+fieldBitOffset PR_PR0 = 0+fieldBitOffset PR_PR1 = 1+fieldBitOffset PR_PR10 = 10+fieldBitOffset PR_PR11 = 11+fieldBitOffset PR_PR12 = 12+fieldBitOffset PR_PR13 = 13+fieldBitOffset PR_PR14 = 14+fieldBitOffset PR_PR15 = 15+fieldBitOffset PR_PR16 = 16+fieldBitOffset PR_PR17 = 17+fieldBitOffset PR_PR18 = 18+fieldBitOffset PR_PR2 = 2+fieldBitOffset PR_PR3 = 3+fieldBitOffset PR_PR4 = 4+fieldBitOffset PR_PR5 = 5+fieldBitOffset PR_PR6 = 6+fieldBitOffset PR_PR7 = 7+fieldBitOffset PR_PR8 = 8+fieldBitOffset PR_PR9 = 9+fieldBitOffset PRLH_PRLH = 0+fieldBitOffset PRLL_PRLL = 0+fieldBitOffset PSC_PSC = 0+fieldBitOffset RCR_REP = 0+fieldBitOffset RESP2_CARDSTATUS2 = 0+fieldBitOffset RESP3_CARDSTATUS3 = 0+fieldBitOffset RESP4_CARDSTATUS4 = 0+fieldBitOffset RESPCMD_RESPCMD = 0+fieldBitOffset RESPI1_CARDSTATUS1 = 0+fieldBitOffset RLR_RL = 0+fieldBitOffset RTCCR_ASOE = 8+fieldBitOffset RTCCR_ASOS = 9+fieldBitOffset RTCCR_CAL = 0+fieldBitOffset RTCCR_CCO = 7+fieldBitOffset RTSR_TR0 = 0+fieldBitOffset RTSR_TR1 = 1+fieldBitOffset RTSR_TR10 = 10+fieldBitOffset RTSR_TR11 = 11+fieldBitOffset RTSR_TR12 = 12+fieldBitOffset RTSR_TR13 = 13+fieldBitOffset RTSR_TR14 = 14+fieldBitOffset RTSR_TR15 = 15+fieldBitOffset RTSR_TR16 = 16+fieldBitOffset RTSR_TR17 = 17+fieldBitOffset RTSR_TR18 = 18+fieldBitOffset RTSR_TR2 = 2+fieldBitOffset RTSR_TR3 = 3+fieldBitOffset RTSR_TR4 = 4+fieldBitOffset RTSR_TR5 = 5+fieldBitOffset RTSR_TR6 = 6+fieldBitOffset RTSR_TR7 = 7+fieldBitOffset RTSR_TR8 = 8+fieldBitOffset RTSR_TR9 = 9+fieldBitOffset RXCRCR_RxCRC = 0+fieldBitOffset SMCR_ECE = 14+fieldBitOffset SMCR_ETF = 8+fieldBitOffset SMCR_ETP = 15+fieldBitOffset SMCR_ETPS = 12+fieldBitOffset SMCR_MSM = 7+fieldBitOffset SMCR_SMS = 0+fieldBitOffset SMCR_TS = 4+fieldBitOffset SMPR1_SMP10 = 0+fieldBitOffset SMPR1_SMP11 = 3+fieldBitOffset SMPR1_SMP12 = 6+fieldBitOffset SMPR1_SMP13 = 9+fieldBitOffset SMPR1_SMP14 = 12+fieldBitOffset SMPR1_SMP15 = 15+fieldBitOffset SMPR1_SMP16 = 18+fieldBitOffset SMPR1_SMP17 = 21+fieldBitOffset SMPR2_SMP0 = 0+fieldBitOffset SMPR2_SMP1 = 3+fieldBitOffset SMPR2_SMP2 = 6+fieldBitOffset SMPR2_SMP3 = 9+fieldBitOffset SMPR2_SMP4 = 12+fieldBitOffset SMPR2_SMP5 = 15+fieldBitOffset SMPR2_SMP6 = 18+fieldBitOffset SMPR2_SMP7 = 21+fieldBitOffset SMPR2_SMP8 = 24+fieldBitOffset SMPR2_SMP9 = 27+fieldBitOffset SQR1_L = 20+fieldBitOffset SQR1_SQ13 = 0+fieldBitOffset SQR1_SQ14 = 5+fieldBitOffset SQR1_SQ15 = 10+fieldBitOffset SQR1_SQ16 = 15+fieldBitOffset SQR2_SQ10 = 15+fieldBitOffset SQR2_SQ11 = 20+fieldBitOffset SQR2_SQ12 = 25+fieldBitOffset SQR2_SQ7 = 0+fieldBitOffset SQR2_SQ8 = 5+fieldBitOffset SQR2_SQ9 = 10+fieldBitOffset SQR3_SQ1 = 0+fieldBitOffset SQR3_SQ2 = 5+fieldBitOffset SQR3_SQ3 = 10+fieldBitOffset SQR3_SQ4 = 15+fieldBitOffset SQR3_SQ5 = 20+fieldBitOffset SQR3_SQ6 = 25+fieldBitOffset SR_AWD = 0+fieldBitOffset SR_BIF = 7+fieldBitOffset SR_BSY = 0+fieldBitOffset SR_CC1IF = 1+fieldBitOffset SR_CC1OF = 9+fieldBitOffset SR_CC2IF = 2+fieldBitOffset SR_CC2OF = 10+fieldBitOffset SR_CC3IF = 3+fieldBitOffset SR_CC3OF = 11+fieldBitOffset SR_CC4IF = 4+fieldBitOffset SR_CC4OF = 12+fieldBitOffset SR_CHSIDE = 2+fieldBitOffset SR_COMIF = 5+fieldBitOffset SR_CRCERR = 4+fieldBitOffset SR_CTS = 9+fieldBitOffset SR_EOC = 1+fieldBitOffset SR_EOP = 5+fieldBitOffset SR_EWI = 0+fieldBitOffset SR_FE = 1+fieldBitOffset SR_IDLE = 4+fieldBitOffset SR_JEOC = 2+fieldBitOffset SR_JSTRT = 3+fieldBitOffset SR_LBD = 8+fieldBitOffset SR_MODF = 5+fieldBitOffset SR_NE = 2+fieldBitOffset SR_ORE = 3+fieldBitOffset SR_OVR = 6+fieldBitOffset SR_PE = 0+fieldBitOffset SR_PGERR = 2+fieldBitOffset SR_PVU = 0+fieldBitOffset SR_RVU = 1+fieldBitOffset SR_RXNE = 5+fieldBitOffset SR_STRT = 4+fieldBitOffset SR_TC = 6+fieldBitOffset SR_TIF = 6+fieldBitOffset SR_TXE = 7+fieldBitOffset SR_UDR = 3+fieldBitOffset SR_UIF = 0+fieldBitOffset SR_WRPRTERR = 4+fieldBitOffset SR1_ADD10 = 3+fieldBitOffset SR1_ADDR = 1+fieldBitOffset SR1_AF = 10+fieldBitOffset SR1_ARLO = 9+fieldBitOffset SR1_BERR = 8+fieldBitOffset SR1_BTF = 2+fieldBitOffset SR1_OVR = 11+fieldBitOffset SR1_PECERR = 12+fieldBitOffset SR1_RxNE = 6+fieldBitOffset SR1_SB = 0+fieldBitOffset SR1_SMBALERT = 15+fieldBitOffset SR1_STOPF = 4+fieldBitOffset SR1_TIMEOUT = 14+fieldBitOffset SR1_TxE = 7+fieldBitOffset SR2_BUSY = 1+fieldBitOffset SR2_DUALF = 7+fieldBitOffset SR2_FEMPT = 6+fieldBitOffset SR2_GENCALL = 4+fieldBitOffset SR2_IFEN = 5+fieldBitOffset SR2_IFS = 2+fieldBitOffset SR2_ILEN = 4+fieldBitOffset SR2_ILS = 1+fieldBitOffset SR2_IREN = 3+fieldBitOffset SR2_IRS = 0+fieldBitOffset SR2_MSL = 0+fieldBitOffset SR2_PEC = 8+fieldBitOffset SR2_SMBDEFAULT = 5+fieldBitOffset SR2_SMBHOST = 6+fieldBitOffset SR2_TRA = 2+fieldBitOffset SR3_FEMPT = 6+fieldBitOffset SR3_IFEN = 5+fieldBitOffset SR3_IFS = 2+fieldBitOffset SR3_ILEN = 4+fieldBitOffset SR3_ILS = 1+fieldBitOffset SR3_IREN = 3+fieldBitOffset SR3_IRS = 0+fieldBitOffset SR4_FEMPT = 6+fieldBitOffset SR4_IFEN = 5+fieldBitOffset SR4_IFS = 2+fieldBitOffset SR4_ILEN = 4+fieldBitOffset SR4_ILS = 1+fieldBitOffset SR4_IREN = 3+fieldBitOffset SR4_IRS = 0+fieldBitOffset STA_CCRCFAIL = 0+fieldBitOffset STA_CEATAEND = 23+fieldBitOffset STA_CMDACT = 11+fieldBitOffset STA_CMDREND = 6+fieldBitOffset STA_CMDSENT = 7+fieldBitOffset STA_CTIMEOUT = 2+fieldBitOffset STA_DATAEND = 8+fieldBitOffset STA_DBCKEND = 10+fieldBitOffset STA_DCRCFAIL = 1+fieldBitOffset STA_DTIMEOUT = 3+fieldBitOffset STA_RXACT = 13+fieldBitOffset STA_RXDAVL = 21+fieldBitOffset STA_RXFIFOE = 19+fieldBitOffset STA_RXFIFOF = 17+fieldBitOffset STA_RXFIFOHF = 15+fieldBitOffset STA_RXOVERR = 5+fieldBitOffset STA_SDIOIT = 22+fieldBitOffset STA_STBITERR = 9+fieldBitOffset STA_TXACT = 12+fieldBitOffset STA_TXDAVL = 20+fieldBitOffset STA_TXFIFOE = 18+fieldBitOffset STA_TXFIFOF = 16+fieldBitOffset STA_TXFIFOHE = 14+fieldBitOffset STA_TXUNDERR = 4+fieldBitOffset STIR_INTID = 0+fieldBitOffset SWIER_SWIER0 = 0+fieldBitOffset SWIER_SWIER1 = 1+fieldBitOffset SWIER_SWIER10 = 10+fieldBitOffset SWIER_SWIER11 = 11+fieldBitOffset SWIER_SWIER12 = 12+fieldBitOffset SWIER_SWIER13 = 13+fieldBitOffset SWIER_SWIER14 = 14+fieldBitOffset SWIER_SWIER15 = 15+fieldBitOffset SWIER_SWIER16 = 16+fieldBitOffset SWIER_SWIER17 = 17+fieldBitOffset SWIER_SWIER18 = 18+fieldBitOffset SWIER_SWIER2 = 2+fieldBitOffset SWIER_SWIER3 = 3+fieldBitOffset SWIER_SWIER4 = 4+fieldBitOffset SWIER_SWIER5 = 5+fieldBitOffset SWIER_SWIER6 = 6+fieldBitOffset SWIER_SWIER7 = 7+fieldBitOffset SWIER_SWIER8 = 8+fieldBitOffset SWIER_SWIER9 = 9+fieldBitOffset SWTRIGR_SWTRIG1 = 0+fieldBitOffset SWTRIGR_SWTRIG2 = 1+fieldBitOffset TRISE_TRISE = 0+fieldBitOffset TXCRCR_TxCRC = 0+fieldBitOffset WRPR_WRP = 0++fieldBitWidth :: Field -> Int+fieldBitWidth ACR_HLFCYA = 1+fieldBitWidth ACR_LATENCY = 3+fieldBitWidth ACR_PRFTBE = 1+fieldBitWidth ACR_PRFTBS = 1+fieldBitWidth AHBENR_CRCEN = 1+fieldBitWidth AHBENR_DMA1EN = 1+fieldBitWidth AHBENR_DMA2EN = 1+fieldBitWidth AHBENR_FLITFEN = 1+fieldBitWidth AHBENR_FSMCEN = 1+fieldBitWidth AHBENR_SDIOEN = 1+fieldBitWidth AHBENR_SRAMEN = 1+fieldBitWidth ALRH_ALRH = 16+fieldBitWidth ALRL_ALRL = 16+fieldBitWidth APB1ENR_BKPEN = 1+fieldBitWidth APB1ENR_CANEN = 1+fieldBitWidth APB1ENR_DACEN = 1+fieldBitWidth APB1ENR_I2C1EN = 1+fieldBitWidth APB1ENR_I2C2EN = 1+fieldBitWidth APB1ENR_PWREN = 1+fieldBitWidth APB1ENR_SPI2EN = 1+fieldBitWidth APB1ENR_SPI3EN = 1+fieldBitWidth APB1ENR_TIM12EN = 1+fieldBitWidth APB1ENR_TIM13EN = 1+fieldBitWidth APB1ENR_TIM14EN = 1+fieldBitWidth APB1ENR_TIM2EN = 1+fieldBitWidth APB1ENR_TIM3EN = 1+fieldBitWidth APB1ENR_TIM4EN = 1+fieldBitWidth APB1ENR_TIM5EN = 1+fieldBitWidth APB1ENR_TIM6EN = 1+fieldBitWidth APB1ENR_TIM7EN = 1+fieldBitWidth APB1ENR_UART4EN = 1+fieldBitWidth APB1ENR_UART5EN = 1+fieldBitWidth APB1ENR_USART2EN = 1+fieldBitWidth APB1ENR_USART3EN = 1+fieldBitWidth APB1ENR_USBEN = 1+fieldBitWidth APB1ENR_WWDGEN = 1+fieldBitWidth APB1RSTR_BKPRST = 1+fieldBitWidth APB1RSTR_CANRST = 1+fieldBitWidth APB1RSTR_DACRST = 1+fieldBitWidth APB1RSTR_I2C1RST = 1+fieldBitWidth APB1RSTR_I2C2RST = 1+fieldBitWidth APB1RSTR_PWRRST = 1+fieldBitWidth APB1RSTR_SPI2RST = 1+fieldBitWidth APB1RSTR_SPI3RST = 1+fieldBitWidth APB1RSTR_TIM12RST = 1+fieldBitWidth APB1RSTR_TIM13RST = 1+fieldBitWidth APB1RSTR_TIM14RST = 1+fieldBitWidth APB1RSTR_TIM2RST = 1+fieldBitWidth APB1RSTR_TIM3RST = 1+fieldBitWidth APB1RSTR_TIM4RST = 1+fieldBitWidth APB1RSTR_TIM5RST = 1+fieldBitWidth APB1RSTR_TIM6RST = 1+fieldBitWidth APB1RSTR_TIM7RST = 1+fieldBitWidth APB1RSTR_UART4RST = 1+fieldBitWidth APB1RSTR_UART5RST = 1+fieldBitWidth APB1RSTR_USART2RST = 1+fieldBitWidth APB1RSTR_USART3RST = 1+fieldBitWidth APB1RSTR_USBRST = 1+fieldBitWidth APB1RSTR_WWDGRST = 1+fieldBitWidth APB2ENR_ADC1EN = 1+fieldBitWidth APB2ENR_ADC2EN = 1+fieldBitWidth APB2ENR_ADC3EN = 1+fieldBitWidth APB2ENR_AFIOEN = 1+fieldBitWidth APB2ENR_IOPAEN = 1+fieldBitWidth APB2ENR_IOPBEN = 1+fieldBitWidth APB2ENR_IOPCEN = 1+fieldBitWidth APB2ENR_IOPDEN = 1+fieldBitWidth APB2ENR_IOPEEN = 1+fieldBitWidth APB2ENR_IOPFEN = 1+fieldBitWidth APB2ENR_IOPGEN = 1+fieldBitWidth APB2ENR_SPI1EN = 1+fieldBitWidth APB2ENR_TIM10EN = 1+fieldBitWidth APB2ENR_TIM11EN = 1+fieldBitWidth APB2ENR_TIM1EN = 1+fieldBitWidth APB2ENR_TIM8EN = 1+fieldBitWidth APB2ENR_TIM9EN = 1+fieldBitWidth APB2ENR_USART1EN = 1+fieldBitWidth APB2RSTR_ADC1RST = 1+fieldBitWidth APB2RSTR_ADC2RST = 1+fieldBitWidth APB2RSTR_ADC3RST = 1+fieldBitWidth APB2RSTR_AFIORST = 1+fieldBitWidth APB2RSTR_IOPARST = 1+fieldBitWidth APB2RSTR_IOPBRST = 1+fieldBitWidth APB2RSTR_IOPCRST = 1+fieldBitWidth APB2RSTR_IOPDRST = 1+fieldBitWidth APB2RSTR_IOPERST = 1+fieldBitWidth APB2RSTR_IOPFRST = 1+fieldBitWidth APB2RSTR_IOPGRST = 1+fieldBitWidth APB2RSTR_SPI1RST = 1+fieldBitWidth APB2RSTR_TIM10RST = 1+fieldBitWidth APB2RSTR_TIM11RST = 1+fieldBitWidth APB2RSTR_TIM1RST = 1+fieldBitWidth APB2RSTR_TIM8RST = 1+fieldBitWidth APB2RSTR_TIM9RST = 1+fieldBitWidth APB2RSTR_USART1RST = 1+fieldBitWidth AR_FAR = 32+fieldBitWidth ARG_CMDARG = 32+fieldBitWidth ARR_ARR = 16+fieldBitWidth BCR1_ASYNCWAIT = 1+fieldBitWidth BCR1_BURSTEN = 1+fieldBitWidth BCR1_CBURSTRW = 1+fieldBitWidth BCR1_EXTMOD = 1+fieldBitWidth BCR1_FACCEN = 1+fieldBitWidth BCR1_MBKEN = 1+fieldBitWidth BCR1_MTYP = 2+fieldBitWidth BCR1_MUXEN = 1+fieldBitWidth BCR1_MWID = 2+fieldBitWidth BCR1_WAITCFG = 1+fieldBitWidth BCR1_WAITEN = 1+fieldBitWidth BCR1_WAITPOL = 1+fieldBitWidth BCR1_WREN = 1+fieldBitWidth BCR2_ASYNCWAIT = 1+fieldBitWidth BCR2_BURSTEN = 1+fieldBitWidth BCR2_CBURSTRW = 1+fieldBitWidth BCR2_EXTMOD = 1+fieldBitWidth BCR2_FACCEN = 1+fieldBitWidth BCR2_MBKEN = 1+fieldBitWidth BCR2_MTYP = 2+fieldBitWidth BCR2_MUXEN = 1+fieldBitWidth BCR2_MWID = 2+fieldBitWidth BCR2_WAITCFG = 1+fieldBitWidth BCR2_WAITEN = 1+fieldBitWidth BCR2_WAITPOL = 1+fieldBitWidth BCR2_WRAPMOD = 1+fieldBitWidth BCR2_WREN = 1+fieldBitWidth BCR3_ASYNCWAIT = 1+fieldBitWidth BCR3_BURSTEN = 1+fieldBitWidth BCR3_CBURSTRW = 1+fieldBitWidth BCR3_EXTMOD = 1+fieldBitWidth BCR3_FACCEN = 1+fieldBitWidth BCR3_MBKEN = 1+fieldBitWidth BCR3_MTYP = 2+fieldBitWidth BCR3_MUXEN = 1+fieldBitWidth BCR3_MWID = 2+fieldBitWidth BCR3_WAITCFG = 1+fieldBitWidth BCR3_WAITEN = 1+fieldBitWidth BCR3_WAITPOL = 1+fieldBitWidth BCR3_WRAPMOD = 1+fieldBitWidth BCR3_WREN = 1+fieldBitWidth BCR4_ASYNCWAIT = 1+fieldBitWidth BCR4_BURSTEN = 1+fieldBitWidth BCR4_CBURSTRW = 1+fieldBitWidth BCR4_EXTMOD = 1+fieldBitWidth BCR4_FACCEN = 1+fieldBitWidth BCR4_MBKEN = 1+fieldBitWidth BCR4_MTYP = 2+fieldBitWidth BCR4_MUXEN = 1+fieldBitWidth BCR4_MWID = 2+fieldBitWidth BCR4_WAITCFG = 1+fieldBitWidth BCR4_WAITEN = 1+fieldBitWidth BCR4_WAITPOL = 1+fieldBitWidth BCR4_WRAPMOD = 1+fieldBitWidth BCR4_WREN = 1+fieldBitWidth BDCR_BDRST = 1+fieldBitWidth BDCR_LSEBYP = 1+fieldBitWidth BDCR_LSEON = 1+fieldBitWidth BDCR_LSERDY = 1+fieldBitWidth BDCR_RTCEN = 1+fieldBitWidth BDCR_RTCSEL = 2+fieldBitWidth BDTR_AOE = 1+fieldBitWidth BDTR_BKE = 1+fieldBitWidth BDTR_BKP = 1+fieldBitWidth BDTR_DTG = 8+fieldBitWidth BDTR_LOCK = 2+fieldBitWidth BDTR_MOE = 1+fieldBitWidth BDTR_OSSI = 1+fieldBitWidth BDTR_OSSR = 1+fieldBitWidth BRR_BR0 = 1+fieldBitWidth BRR_BR1 = 1+fieldBitWidth BRR_BR10 = 1+fieldBitWidth BRR_BR11 = 1+fieldBitWidth BRR_BR12 = 1+fieldBitWidth BRR_BR13 = 1+fieldBitWidth BRR_BR14 = 1+fieldBitWidth BRR_BR15 = 1+fieldBitWidth BRR_BR2 = 1+fieldBitWidth BRR_BR3 = 1+fieldBitWidth BRR_BR4 = 1+fieldBitWidth BRR_BR5 = 1+fieldBitWidth BRR_BR6 = 1+fieldBitWidth BRR_BR7 = 1+fieldBitWidth BRR_BR8 = 1+fieldBitWidth BRR_BR9 = 1+fieldBitWidth BRR_DIV_Fraction = 4+fieldBitWidth BRR_DIV_Mantissa = 12+fieldBitWidth BSRR_BR0 = 1+fieldBitWidth BSRR_BR1 = 1+fieldBitWidth BSRR_BR10 = 1+fieldBitWidth BSRR_BR11 = 1+fieldBitWidth BSRR_BR12 = 1+fieldBitWidth BSRR_BR13 = 1+fieldBitWidth BSRR_BR14 = 1+fieldBitWidth BSRR_BR15 = 1+fieldBitWidth BSRR_BR2 = 1+fieldBitWidth BSRR_BR3 = 1+fieldBitWidth BSRR_BR4 = 1+fieldBitWidth BSRR_BR5 = 1+fieldBitWidth BSRR_BR6 = 1+fieldBitWidth BSRR_BR7 = 1+fieldBitWidth BSRR_BR8 = 1+fieldBitWidth BSRR_BR9 = 1+fieldBitWidth BSRR_BS0 = 1+fieldBitWidth BSRR_BS1 = 1+fieldBitWidth BSRR_BS10 = 1+fieldBitWidth BSRR_BS11 = 1+fieldBitWidth BSRR_BS12 = 1+fieldBitWidth BSRR_BS13 = 1+fieldBitWidth BSRR_BS14 = 1+fieldBitWidth BSRR_BS15 = 1+fieldBitWidth BSRR_BS2 = 1+fieldBitWidth BSRR_BS3 = 1+fieldBitWidth BSRR_BS4 = 1+fieldBitWidth BSRR_BS5 = 1+fieldBitWidth BSRR_BS6 = 1+fieldBitWidth BSRR_BS7 = 1+fieldBitWidth BSRR_BS8 = 1+fieldBitWidth BSRR_BS9 = 1+fieldBitWidth BTABLE_BTABLE = 13+fieldBitWidth BTR1_ACCMOD = 2+fieldBitWidth BTR1_ADDHLD = 4+fieldBitWidth BTR1_ADDSET = 4+fieldBitWidth BTR1_BUSTURN = 4+fieldBitWidth BTR1_CLKDIV = 4+fieldBitWidth BTR1_DATAST = 8+fieldBitWidth BTR1_DATLAT = 4+fieldBitWidth BTR2_ACCMOD = 2+fieldBitWidth BTR2_ADDHLD = 4+fieldBitWidth BTR2_ADDSET = 4+fieldBitWidth BTR2_BUSTURN = 4+fieldBitWidth BTR2_CLKDIV = 4+fieldBitWidth BTR2_DATAST = 8+fieldBitWidth BTR2_DATLAT = 4+fieldBitWidth BTR3_ACCMOD = 2+fieldBitWidth BTR3_ADDHLD = 4+fieldBitWidth BTR3_ADDSET = 4+fieldBitWidth BTR3_BUSTURN = 4+fieldBitWidth BTR3_CLKDIV = 4+fieldBitWidth BTR3_DATAST = 8+fieldBitWidth BTR3_DATLAT = 4+fieldBitWidth BTR4_ACCMOD = 2+fieldBitWidth BTR4_ADDHLD = 4+fieldBitWidth BTR4_ADDSET = 4+fieldBitWidth BTR4_BUSTURN = 4+fieldBitWidth BTR4_CLKDIV = 4+fieldBitWidth BTR4_DATAST = 8+fieldBitWidth BTR4_DATLAT = 4+fieldBitWidth BWTR1_ACCMOD = 2+fieldBitWidth BWTR1_ADDHLD = 4+fieldBitWidth BWTR1_ADDSET = 4+fieldBitWidth BWTR1_CLKDIV = 4+fieldBitWidth BWTR1_DATAST = 8+fieldBitWidth BWTR1_DATLAT = 4+fieldBitWidth BWTR2_ACCMOD = 2+fieldBitWidth BWTR2_ADDHLD = 4+fieldBitWidth BWTR2_ADDSET = 4+fieldBitWidth BWTR2_CLKDIV = 4+fieldBitWidth BWTR2_DATAST = 8+fieldBitWidth BWTR2_DATLAT = 4+fieldBitWidth BWTR3_ACCMOD = 2+fieldBitWidth BWTR3_ADDHLD = 4+fieldBitWidth BWTR3_ADDSET = 4+fieldBitWidth BWTR3_CLKDIV = 4+fieldBitWidth BWTR3_DATAST = 8+fieldBitWidth BWTR3_DATLAT = 4+fieldBitWidth BWTR4_ACCMOD = 2+fieldBitWidth BWTR4_ADDHLD = 4+fieldBitWidth BWTR4_ADDSET = 4+fieldBitWidth BWTR4_CLKDIV = 4+fieldBitWidth BWTR4_DATAST = 8+fieldBitWidth BWTR4_DATLAT = 4+fieldBitWidth CAN_BTR_BRP = 10+fieldBitWidth CAN_BTR_LBKM = 1+fieldBitWidth CAN_BTR_SILM = 1+fieldBitWidth CAN_BTR_SJW = 2+fieldBitWidth CAN_BTR_TS1 = 4+fieldBitWidth CAN_BTR_TS2 = 3+fieldBitWidth CAN_ESR_BOFF = 1+fieldBitWidth CAN_ESR_EPVF = 1+fieldBitWidth CAN_ESR_EWGF = 1+fieldBitWidth CAN_ESR_LEC = 3+fieldBitWidth CAN_ESR_REC = 8+fieldBitWidth CAN_ESR_TEC = 8+fieldBitWidth CAN_FA1R_FACT0 = 1+fieldBitWidth CAN_FA1R_FACT1 = 1+fieldBitWidth CAN_FA1R_FACT10 = 1+fieldBitWidth CAN_FA1R_FACT11 = 1+fieldBitWidth CAN_FA1R_FACT12 = 1+fieldBitWidth CAN_FA1R_FACT13 = 1+fieldBitWidth CAN_FA1R_FACT2 = 1+fieldBitWidth CAN_FA1R_FACT3 = 1+fieldBitWidth CAN_FA1R_FACT4 = 1+fieldBitWidth CAN_FA1R_FACT5 = 1+fieldBitWidth CAN_FA1R_FACT6 = 1+fieldBitWidth CAN_FA1R_FACT7 = 1+fieldBitWidth CAN_FA1R_FACT8 = 1+fieldBitWidth CAN_FA1R_FACT9 = 1+fieldBitWidth CAN_FFA1R_FFA0 = 1+fieldBitWidth CAN_FFA1R_FFA1 = 1+fieldBitWidth CAN_FFA1R_FFA10 = 1+fieldBitWidth CAN_FFA1R_FFA11 = 1+fieldBitWidth CAN_FFA1R_FFA12 = 1+fieldBitWidth CAN_FFA1R_FFA13 = 1+fieldBitWidth CAN_FFA1R_FFA2 = 1+fieldBitWidth CAN_FFA1R_FFA3 = 1+fieldBitWidth CAN_FFA1R_FFA4 = 1+fieldBitWidth CAN_FFA1R_FFA5 = 1+fieldBitWidth CAN_FFA1R_FFA6 = 1+fieldBitWidth CAN_FFA1R_FFA7 = 1+fieldBitWidth CAN_FFA1R_FFA8 = 1+fieldBitWidth CAN_FFA1R_FFA9 = 1+fieldBitWidth CAN_FM1R_FBM0 = 1+fieldBitWidth CAN_FM1R_FBM1 = 1+fieldBitWidth CAN_FM1R_FBM10 = 1+fieldBitWidth CAN_FM1R_FBM11 = 1+fieldBitWidth CAN_FM1R_FBM12 = 1+fieldBitWidth CAN_FM1R_FBM13 = 1+fieldBitWidth CAN_FM1R_FBM2 = 1+fieldBitWidth CAN_FM1R_FBM3 = 1+fieldBitWidth CAN_FM1R_FBM4 = 1+fieldBitWidth CAN_FM1R_FBM5 = 1+fieldBitWidth CAN_FM1R_FBM6 = 1+fieldBitWidth CAN_FM1R_FBM7 = 1+fieldBitWidth CAN_FM1R_FBM8 = 1+fieldBitWidth CAN_FM1R_FBM9 = 1+fieldBitWidth CAN_FMR_FINIT = 1+fieldBitWidth CAN_FS1R_FSC0 = 1+fieldBitWidth CAN_FS1R_FSC1 = 1+fieldBitWidth CAN_FS1R_FSC10 = 1+fieldBitWidth CAN_FS1R_FSC11 = 1+fieldBitWidth CAN_FS1R_FSC12 = 1+fieldBitWidth CAN_FS1R_FSC13 = 1+fieldBitWidth CAN_FS1R_FSC2 = 1+fieldBitWidth CAN_FS1R_FSC3 = 1+fieldBitWidth CAN_FS1R_FSC4 = 1+fieldBitWidth CAN_FS1R_FSC5 = 1+fieldBitWidth CAN_FS1R_FSC6 = 1+fieldBitWidth CAN_FS1R_FSC7 = 1+fieldBitWidth CAN_FS1R_FSC8 = 1+fieldBitWidth CAN_FS1R_FSC9 = 1+fieldBitWidth CAN_IER_BOFIE = 1+fieldBitWidth CAN_IER_EPVIE = 1+fieldBitWidth CAN_IER_ERRIE = 1+fieldBitWidth CAN_IER_EWGIE = 1+fieldBitWidth CAN_IER_FFIE0 = 1+fieldBitWidth CAN_IER_FFIE1 = 1+fieldBitWidth CAN_IER_FMPIE0 = 1+fieldBitWidth CAN_IER_FMPIE1 = 1+fieldBitWidth CAN_IER_FOVIE0 = 1+fieldBitWidth CAN_IER_FOVIE1 = 1+fieldBitWidth CAN_IER_LECIE = 1+fieldBitWidth CAN_IER_SLKIE = 1+fieldBitWidth CAN_IER_TMEIE = 1+fieldBitWidth CAN_IER_WKUIE = 1+fieldBitWidth CAN_MCR_ABOM = 1+fieldBitWidth CAN_MCR_AWUM = 1+fieldBitWidth CAN_MCR_DBF = 1+fieldBitWidth CAN_MCR_INRQ = 1+fieldBitWidth CAN_MCR_NART = 1+fieldBitWidth CAN_MCR_RESET = 1+fieldBitWidth CAN_MCR_RFLM = 1+fieldBitWidth CAN_MCR_SLEEP = 1+fieldBitWidth CAN_MCR_TTCM = 1+fieldBitWidth CAN_MCR_TXFP = 1+fieldBitWidth CAN_MSR_ERRI = 1+fieldBitWidth CAN_MSR_INAK = 1+fieldBitWidth CAN_MSR_RX = 1+fieldBitWidth CAN_MSR_RXM = 1+fieldBitWidth CAN_MSR_SAMP = 1+fieldBitWidth CAN_MSR_SLAK = 1+fieldBitWidth CAN_MSR_SLAKI = 1+fieldBitWidth CAN_MSR_TXM = 1+fieldBitWidth CAN_MSR_WKUI = 1+fieldBitWidth CAN_RDH0R_DATA4 = 8+fieldBitWidth CAN_RDH0R_DATA5 = 8+fieldBitWidth CAN_RDH0R_DATA6 = 8+fieldBitWidth CAN_RDH0R_DATA7 = 8+fieldBitWidth CAN_RDH1R_DATA4 = 8+fieldBitWidth CAN_RDH1R_DATA5 = 8+fieldBitWidth CAN_RDH1R_DATA6 = 8+fieldBitWidth CAN_RDH1R_DATA7 = 8+fieldBitWidth CAN_RDL0R_DATA0 = 8+fieldBitWidth CAN_RDL0R_DATA1 = 8+fieldBitWidth CAN_RDL0R_DATA2 = 8+fieldBitWidth CAN_RDL0R_DATA3 = 8+fieldBitWidth CAN_RDL1R_DATA0 = 8+fieldBitWidth CAN_RDL1R_DATA1 = 8+fieldBitWidth CAN_RDL1R_DATA2 = 8+fieldBitWidth CAN_RDL1R_DATA3 = 8+fieldBitWidth CAN_RDT0R_DLC = 4+fieldBitWidth CAN_RDT0R_FMI = 8+fieldBitWidth CAN_RDT0R_TIME = 16+fieldBitWidth CAN_RDT1R_DLC = 4+fieldBitWidth CAN_RDT1R_FMI = 8+fieldBitWidth CAN_RDT1R_TIME = 16+fieldBitWidth CAN_RF0R_FMP0 = 2+fieldBitWidth CAN_RF0R_FOVR0 = 1+fieldBitWidth CAN_RF0R_FULL0 = 1+fieldBitWidth CAN_RF0R_RFOM0 = 1+fieldBitWidth CAN_RF1R_FMP1 = 2+fieldBitWidth CAN_RF1R_FOVR1 = 1+fieldBitWidth CAN_RF1R_FULL1 = 1+fieldBitWidth CAN_RF1R_RFOM1 = 1+fieldBitWidth CAN_RI0R_EXID = 18+fieldBitWidth CAN_RI0R_IDE = 1+fieldBitWidth CAN_RI0R_RTR = 1+fieldBitWidth CAN_RI0R_STID = 11+fieldBitWidth CAN_RI1R_EXID = 18+fieldBitWidth CAN_RI1R_IDE = 1+fieldBitWidth CAN_RI1R_RTR = 1+fieldBitWidth CAN_RI1R_STID = 11+fieldBitWidth CAN_TDH0R_DATA4 = 8+fieldBitWidth CAN_TDH0R_DATA5 = 8+fieldBitWidth CAN_TDH0R_DATA6 = 8+fieldBitWidth CAN_TDH0R_DATA7 = 8+fieldBitWidth CAN_TDH1R_DATA4 = 8+fieldBitWidth CAN_TDH1R_DATA5 = 8+fieldBitWidth CAN_TDH1R_DATA6 = 8+fieldBitWidth CAN_TDH1R_DATA7 = 8+fieldBitWidth CAN_TDH2R_DATA4 = 8+fieldBitWidth CAN_TDH2R_DATA5 = 8+fieldBitWidth CAN_TDH2R_DATA6 = 8+fieldBitWidth CAN_TDH2R_DATA7 = 8+fieldBitWidth CAN_TDL0R_DATA0 = 8+fieldBitWidth CAN_TDL0R_DATA1 = 8+fieldBitWidth CAN_TDL0R_DATA2 = 8+fieldBitWidth CAN_TDL0R_DATA3 = 8+fieldBitWidth CAN_TDL1R_DATA0 = 8+fieldBitWidth CAN_TDL1R_DATA1 = 8+fieldBitWidth CAN_TDL1R_DATA2 = 8+fieldBitWidth CAN_TDL1R_DATA3 = 8+fieldBitWidth CAN_TDL2R_DATA0 = 8+fieldBitWidth CAN_TDL2R_DATA1 = 8+fieldBitWidth CAN_TDL2R_DATA2 = 8+fieldBitWidth CAN_TDL2R_DATA3 = 8+fieldBitWidth CAN_TDT0R_DLC = 4+fieldBitWidth CAN_TDT0R_TGT = 1+fieldBitWidth CAN_TDT0R_TIME = 16+fieldBitWidth CAN_TDT1R_DLC = 4+fieldBitWidth CAN_TDT1R_TGT = 1+fieldBitWidth CAN_TDT1R_TIME = 16+fieldBitWidth CAN_TDT2R_DLC = 4+fieldBitWidth CAN_TDT2R_TGT = 1+fieldBitWidth CAN_TDT2R_TIME = 16+fieldBitWidth CAN_TI0R_EXID = 18+fieldBitWidth CAN_TI0R_IDE = 1+fieldBitWidth CAN_TI0R_RTR = 1+fieldBitWidth CAN_TI0R_STID = 11+fieldBitWidth CAN_TI0R_TXRQ = 1+fieldBitWidth CAN_TI1R_EXID = 18+fieldBitWidth CAN_TI1R_IDE = 1+fieldBitWidth CAN_TI1R_RTR = 1+fieldBitWidth CAN_TI1R_STID = 11+fieldBitWidth CAN_TI1R_TXRQ = 1+fieldBitWidth CAN_TI2R_EXID = 18+fieldBitWidth CAN_TI2R_IDE = 1+fieldBitWidth CAN_TI2R_RTR = 1+fieldBitWidth CAN_TI2R_STID = 11+fieldBitWidth CAN_TI2R_TXRQ = 1+fieldBitWidth CAN_TSR_ABRQ0 = 1+fieldBitWidth CAN_TSR_ABRQ1 = 1+fieldBitWidth CAN_TSR_ABRQ2 = 1+fieldBitWidth CAN_TSR_ALST0 = 1+fieldBitWidth CAN_TSR_ALST1 = 1+fieldBitWidth CAN_TSR_ALST2 = 1+fieldBitWidth CAN_TSR_CODE = 2+fieldBitWidth CAN_TSR_LOW0 = 1+fieldBitWidth CAN_TSR_LOW1 = 1+fieldBitWidth CAN_TSR_LOW2 = 1+fieldBitWidth CAN_TSR_RQCP0 = 1+fieldBitWidth CAN_TSR_RQCP1 = 1+fieldBitWidth CAN_TSR_RQCP2 = 1+fieldBitWidth CAN_TSR_TERR0 = 1+fieldBitWidth CAN_TSR_TERR1 = 1+fieldBitWidth CAN_TSR_TERR2 = 1+fieldBitWidth CAN_TSR_TME0 = 1+fieldBitWidth CAN_TSR_TME1 = 1+fieldBitWidth CAN_TSR_TME2 = 1+fieldBitWidth CAN_TSR_TXOK0 = 1+fieldBitWidth CAN_TSR_TXOK1 = 1+fieldBitWidth CAN_TSR_TXOK2 = 1+fieldBitWidth CCER_CC1E = 1+fieldBitWidth CCER_CC1NE = 1+fieldBitWidth CCER_CC1NP = 1+fieldBitWidth CCER_CC1P = 1+fieldBitWidth CCER_CC2E = 1+fieldBitWidth CCER_CC2NE = 1+fieldBitWidth CCER_CC2NP = 1+fieldBitWidth CCER_CC2P = 1+fieldBitWidth CCER_CC3E = 1+fieldBitWidth CCER_CC3NE = 1+fieldBitWidth CCER_CC3NP = 1+fieldBitWidth CCER_CC3P = 1+fieldBitWidth CCER_CC4E = 1+fieldBitWidth CCER_CC4P = 1+fieldBitWidth CCMR1_Input_CC1S = 2+fieldBitWidth CCMR1_Input_CC2S = 2+fieldBitWidth CCMR1_Input_IC1F = 4+fieldBitWidth CCMR1_Input_IC1PSC = 2+fieldBitWidth CCMR1_Input_IC2F = 4+fieldBitWidth CCMR1_Input_IC2PCS = 2+fieldBitWidth CCMR1_Input_IC2PSC = 2+fieldBitWidth CCMR1_Input_ICPCS = 2+fieldBitWidth CCMR1_Output_CC1S = 2+fieldBitWidth CCMR1_Output_CC2S = 2+fieldBitWidth CCMR1_Output_OC1CE = 1+fieldBitWidth CCMR1_Output_OC1FE = 1+fieldBitWidth CCMR1_Output_OC1M = 3+fieldBitWidth CCMR1_Output_OC1PE = 1+fieldBitWidth CCMR1_Output_OC2CE = 1+fieldBitWidth CCMR1_Output_OC2FE = 1+fieldBitWidth CCMR1_Output_OC2M = 3+fieldBitWidth CCMR1_Output_OC2PE = 1+fieldBitWidth CCMR2_Input_CC3S = 2+fieldBitWidth CCMR2_Input_CC4S = 2+fieldBitWidth CCMR2_Input_IC3F = 4+fieldBitWidth CCMR2_Input_IC3PSC = 2+fieldBitWidth CCMR2_Input_IC4F = 4+fieldBitWidth CCMR2_Input_IC4PSC = 2+fieldBitWidth CCMR2_Output_CC3S = 2+fieldBitWidth CCMR2_Output_CC4S = 2+fieldBitWidth CCMR2_Output_O24CE = 1+fieldBitWidth CCMR2_Output_OC3CE = 1+fieldBitWidth CCMR2_Output_OC3FE = 1+fieldBitWidth CCMR2_Output_OC3M = 3+fieldBitWidth CCMR2_Output_OC3PE = 1+fieldBitWidth CCMR2_Output_OC4CE = 1+fieldBitWidth CCMR2_Output_OC4FE = 1+fieldBitWidth CCMR2_Output_OC4M = 3+fieldBitWidth CCMR2_Output_OC4PE = 1+fieldBitWidth CCR_CCR = 12+fieldBitWidth CCR_DUTY = 1+fieldBitWidth CCR_F_S = 1+fieldBitWidth CCR1_CCR1 = 16+fieldBitWidth CCR1_CIRC = 1+fieldBitWidth CCR1_DIR = 1+fieldBitWidth CCR1_EN = 1+fieldBitWidth CCR1_HTIE = 1+fieldBitWidth CCR1_MEM2MEM = 1+fieldBitWidth CCR1_MINC = 1+fieldBitWidth CCR1_MSIZE = 2+fieldBitWidth CCR1_PINC = 1+fieldBitWidth CCR1_PL = 2+fieldBitWidth CCR1_PSIZE = 2+fieldBitWidth CCR1_TCIE = 1+fieldBitWidth CCR1_TEIE = 1+fieldBitWidth CCR2_CCR2 = 16+fieldBitWidth CCR2_CIRC = 1+fieldBitWidth CCR2_DIR = 1+fieldBitWidth CCR2_EN = 1+fieldBitWidth CCR2_HTIE = 1+fieldBitWidth CCR2_MEM2MEM = 1+fieldBitWidth CCR2_MINC = 1+fieldBitWidth CCR2_MSIZE = 2+fieldBitWidth CCR2_PINC = 1+fieldBitWidth CCR2_PL = 2+fieldBitWidth CCR2_PSIZE = 2+fieldBitWidth CCR2_TCIE = 1+fieldBitWidth CCR2_TEIE = 1+fieldBitWidth CCR3_CCR3 = 16+fieldBitWidth CCR3_CIRC = 1+fieldBitWidth CCR3_DIR = 1+fieldBitWidth CCR3_EN = 1+fieldBitWidth CCR3_HTIE = 1+fieldBitWidth CCR3_MEM2MEM = 1+fieldBitWidth CCR3_MINC = 1+fieldBitWidth CCR3_MSIZE = 2+fieldBitWidth CCR3_PINC = 1+fieldBitWidth CCR3_PL = 2+fieldBitWidth CCR3_PSIZE = 2+fieldBitWidth CCR3_TCIE = 1+fieldBitWidth CCR3_TEIE = 1+fieldBitWidth CCR4_CCR4 = 16+fieldBitWidth CCR4_CIRC = 1+fieldBitWidth CCR4_DIR = 1+fieldBitWidth CCR4_EN = 1+fieldBitWidth CCR4_HTIE = 1+fieldBitWidth CCR4_MEM2MEM = 1+fieldBitWidth CCR4_MINC = 1+fieldBitWidth CCR4_MSIZE = 2+fieldBitWidth CCR4_PINC = 1+fieldBitWidth CCR4_PL = 2+fieldBitWidth CCR4_PSIZE = 2+fieldBitWidth CCR4_TCIE = 1+fieldBitWidth CCR4_TEIE = 1+fieldBitWidth CCR5_CIRC = 1+fieldBitWidth CCR5_DIR = 1+fieldBitWidth CCR5_EN = 1+fieldBitWidth CCR5_HTIE = 1+fieldBitWidth CCR5_MEM2MEM = 1+fieldBitWidth CCR5_MINC = 1+fieldBitWidth CCR5_MSIZE = 2+fieldBitWidth CCR5_PINC = 1+fieldBitWidth CCR5_PL = 2+fieldBitWidth CCR5_PSIZE = 2+fieldBitWidth CCR5_TCIE = 1+fieldBitWidth CCR5_TEIE = 1+fieldBitWidth CCR6_CIRC = 1+fieldBitWidth CCR6_DIR = 1+fieldBitWidth CCR6_EN = 1+fieldBitWidth CCR6_HTIE = 1+fieldBitWidth CCR6_MEM2MEM = 1+fieldBitWidth CCR6_MINC = 1+fieldBitWidth CCR6_MSIZE = 2+fieldBitWidth CCR6_PINC = 1+fieldBitWidth CCR6_PL = 2+fieldBitWidth CCR6_PSIZE = 2+fieldBitWidth CCR6_TCIE = 1+fieldBitWidth CCR6_TEIE = 1+fieldBitWidth CCR7_CIRC = 1+fieldBitWidth CCR7_DIR = 1+fieldBitWidth CCR7_EN = 1+fieldBitWidth CCR7_HTIE = 1+fieldBitWidth CCR7_MEM2MEM = 1+fieldBitWidth CCR7_MINC = 1+fieldBitWidth CCR7_MSIZE = 2+fieldBitWidth CCR7_PINC = 1+fieldBitWidth CCR7_PL = 2+fieldBitWidth CCR7_PSIZE = 2+fieldBitWidth CCR7_TCIE = 1+fieldBitWidth CCR7_TEIE = 1+fieldBitWidth CFGR_ADCPRE = 2+fieldBitWidth CFGR_HPRE = 4+fieldBitWidth CFGR_MCO = 3+fieldBitWidth CFGR_OTGFSPRE = 1+fieldBitWidth CFGR_PLLMUL = 4+fieldBitWidth CFGR_PLLSRC = 1+fieldBitWidth CFGR_PLLXTPRE = 1+fieldBitWidth CFGR_PPRE1 = 3+fieldBitWidth CFGR_PPRE2 = 3+fieldBitWidth CFGR_SW = 2+fieldBitWidth CFGR_SWS = 2+fieldBitWidth CFR_EWI = 1+fieldBitWidth CFR_W = 7+fieldBitWidth CFR_WDGTB = 2+fieldBitWidth CIR_CSSC = 1+fieldBitWidth CIR_CSSF = 1+fieldBitWidth CIR_HSERDYC = 1+fieldBitWidth CIR_HSERDYF = 1+fieldBitWidth CIR_HSERDYIE = 1+fieldBitWidth CIR_HSIRDYC = 1+fieldBitWidth CIR_HSIRDYF = 1+fieldBitWidth CIR_HSIRDYIE = 1+fieldBitWidth CIR_LSERDYC = 1+fieldBitWidth CIR_LSERDYF = 1+fieldBitWidth CIR_LSERDYIE = 1+fieldBitWidth CIR_LSIRDYC = 1+fieldBitWidth CIR_LSIRDYF = 1+fieldBitWidth CIR_LSIRDYIE = 1+fieldBitWidth CIR_PLLRDYC = 1+fieldBitWidth CIR_PLLRDYF = 1+fieldBitWidth CIR_PLLRDYIE = 1+fieldBitWidth CLKCR_BYPASS = 1+fieldBitWidth CLKCR_CLKDIV = 8+fieldBitWidth CLKCR_CLKEN = 1+fieldBitWidth CLKCR_HWFC_EN = 1+fieldBitWidth CLKCR_NEGEDGE = 1+fieldBitWidth CLKCR_PWRSAV = 1+fieldBitWidth CLKCR_WIDBUS = 2+fieldBitWidth CMAR1_MA = 32+fieldBitWidth CMAR2_MA = 32+fieldBitWidth CMAR3_MA = 32+fieldBitWidth CMAR4_MA = 32+fieldBitWidth CMAR5_MA = 32+fieldBitWidth CMAR6_MA = 32+fieldBitWidth CMAR7_MA = 32+fieldBitWidth CMD_CE_ATACMD = 1+fieldBitWidth CMD_CMDINDEX = 6+fieldBitWidth CMD_CPSMEN = 1+fieldBitWidth CMD_ENCMDcompl = 1+fieldBitWidth CMD_SDIOSuspend = 1+fieldBitWidth CMD_WAITINT = 1+fieldBitWidth CMD_WAITPEND = 1+fieldBitWidth CMD_WAITRESP = 2+fieldBitWidth CMD_nIEN = 1+fieldBitWidth CNDTR1_NDT = 16+fieldBitWidth CNDTR2_NDT = 16+fieldBitWidth CNDTR3_NDT = 16+fieldBitWidth CNDTR4_NDT = 16+fieldBitWidth CNDTR5_NDT = 16+fieldBitWidth CNDTR6_NDT = 16+fieldBitWidth CNDTR7_NDT = 16+fieldBitWidth CNT_CNT = 16+fieldBitWidth CNTH_CNTH = 16+fieldBitWidth CNTL_CNTL = 16+fieldBitWidth CNTR_CTRM = 1+fieldBitWidth CNTR_ERRM = 1+fieldBitWidth CNTR_ESOFM = 1+fieldBitWidth CNTR_FRES = 1+fieldBitWidth CNTR_FSUSP = 1+fieldBitWidth CNTR_LPMODE = 1+fieldBitWidth CNTR_PDWN = 1+fieldBitWidth CNTR_PMAOVRM = 1+fieldBitWidth CNTR_RESETM = 1+fieldBitWidth CNTR_RESUME = 1+fieldBitWidth CNTR_SOFM = 1+fieldBitWidth CNTR_SUSPM = 1+fieldBitWidth CNTR_WKUPM = 1+fieldBitWidth CPAR1_PA = 32+fieldBitWidth CPAR2_PA = 32+fieldBitWidth CPAR3_PA = 32+fieldBitWidth CPAR4_PA = 32+fieldBitWidth CPAR5_PA = 32+fieldBitWidth CPAR6_PA = 32+fieldBitWidth CPAR7_PA = 32+fieldBitWidth CR_BOFF1 = 1+fieldBitWidth CR_BOFF2 = 1+fieldBitWidth CR_CSBF = 1+fieldBitWidth CR_CSSON = 1+fieldBitWidth CR_CWUF = 1+fieldBitWidth CR_DBG_CAN1_STOP = 1+fieldBitWidth CR_DBG_CAN2_STOP = 1+fieldBitWidth CR_DBG_I2C1_SMBUS_TIMEOUT = 1+fieldBitWidth CR_DBG_I2C2_SMBUS_TIMEOUT = 1+fieldBitWidth CR_DBG_IWDG_STOP = 1+fieldBitWidth CR_DBG_SLEEP = 1+fieldBitWidth CR_DBG_STANDBY = 1+fieldBitWidth CR_DBG_STOP = 1+fieldBitWidth CR_DBG_TIM1_STOP = 1+fieldBitWidth CR_DBG_TIM2_STOP = 1+fieldBitWidth CR_DBG_TIM3_STOP = 1+fieldBitWidth CR_DBG_TIM4_STOP = 1+fieldBitWidth CR_DBG_TIM5_STOP = 1+fieldBitWidth CR_DBG_TIM6_STOP = 1+fieldBitWidth CR_DBG_TIM7_STOP = 1+fieldBitWidth CR_DBG_TIM8_STOP = 1+fieldBitWidth CR_DBG_WWDG_STOP = 1+fieldBitWidth CR_DBP = 1+fieldBitWidth CR_DMAEN1 = 1+fieldBitWidth CR_DMAEN2 = 1+fieldBitWidth CR_EN1 = 1+fieldBitWidth CR_EN2 = 1+fieldBitWidth CR_EOPIE = 1+fieldBitWidth CR_ERRIE = 1+fieldBitWidth CR_HSEBYP = 1+fieldBitWidth CR_HSEON = 1+fieldBitWidth CR_HSERDY = 1+fieldBitWidth CR_HSICAL = 8+fieldBitWidth CR_HSION = 1+fieldBitWidth CR_HSIRDY = 1+fieldBitWidth CR_HSITRIM = 5+fieldBitWidth CR_LOCK = 1+fieldBitWidth CR_LPDS = 1+fieldBitWidth CR_MAMP1 = 4+fieldBitWidth CR_MAMP2 = 4+fieldBitWidth CR_MER = 1+fieldBitWidth CR_OPTER = 1+fieldBitWidth CR_OPTPG = 1+fieldBitWidth CR_OPTWRE = 1+fieldBitWidth CR_PDDS = 1+fieldBitWidth CR_PER = 1+fieldBitWidth CR_PG = 1+fieldBitWidth CR_PLLON = 1+fieldBitWidth CR_PLLRDY = 1+fieldBitWidth CR_PLS = 3+fieldBitWidth CR_PVDE = 1+fieldBitWidth CR_RESET = 1+fieldBitWidth CR_STRT = 1+fieldBitWidth CR_T = 7+fieldBitWidth CR_TEN1 = 1+fieldBitWidth CR_TEN2 = 1+fieldBitWidth CR_TPAL = 1+fieldBitWidth CR_TPE = 1+fieldBitWidth CR_TRACE_IOEN = 1+fieldBitWidth CR_TRACE_MODE = 2+fieldBitWidth CR_TSEL1 = 3+fieldBitWidth CR_TSEL2 = 3+fieldBitWidth CR_WAVE1 = 2+fieldBitWidth CR_WAVE2 = 2+fieldBitWidth CR_WDGA = 1+fieldBitWidth CR1_ACK = 1+fieldBitWidth CR1_ALERT = 1+fieldBitWidth CR1_ARPE = 1+fieldBitWidth CR1_AWDCH = 5+fieldBitWidth CR1_AWDEN = 1+fieldBitWidth CR1_AWDIE = 1+fieldBitWidth CR1_AWDSGL = 1+fieldBitWidth CR1_BIDIMODE = 1+fieldBitWidth CR1_BIDIOE = 1+fieldBitWidth CR1_BR = 3+fieldBitWidth CR1_CEN = 1+fieldBitWidth CR1_CKD = 2+fieldBitWidth CR1_CMS = 2+fieldBitWidth CR1_CPHA = 1+fieldBitWidth CR1_CPOL = 1+fieldBitWidth CR1_CRCEN = 1+fieldBitWidth CR1_CRCNEXT = 1+fieldBitWidth CR1_DFF = 1+fieldBitWidth CR1_DIR = 1+fieldBitWidth CR1_DISCEN = 1+fieldBitWidth CR1_DISCNUM = 3+fieldBitWidth CR1_DUALMOD = 4+fieldBitWidth CR1_ENARP = 1+fieldBitWidth CR1_ENGC = 1+fieldBitWidth CR1_ENPEC = 1+fieldBitWidth CR1_EOCIE = 1+fieldBitWidth CR1_IDLEIE = 1+fieldBitWidth CR1_JAUTO = 1+fieldBitWidth CR1_JAWDEN = 1+fieldBitWidth CR1_JDISCEN = 1+fieldBitWidth CR1_JEOCIE = 1+fieldBitWidth CR1_LSBFIRST = 1+fieldBitWidth CR1_M = 1+fieldBitWidth CR1_MSTR = 1+fieldBitWidth CR1_NOSTRETCH = 1+fieldBitWidth CR1_OPM = 1+fieldBitWidth CR1_PCE = 1+fieldBitWidth CR1_PE = 1+fieldBitWidth CR1_PEC = 1+fieldBitWidth CR1_PEIE = 1+fieldBitWidth CR1_POS = 1+fieldBitWidth CR1_PS = 1+fieldBitWidth CR1_RE = 1+fieldBitWidth CR1_RWU = 1+fieldBitWidth CR1_RXNEIE = 1+fieldBitWidth CR1_RXONLY = 1+fieldBitWidth CR1_SBK = 1+fieldBitWidth CR1_SCAN = 1+fieldBitWidth CR1_SMBTYPE = 1+fieldBitWidth CR1_SMBUS = 1+fieldBitWidth CR1_SPE = 1+fieldBitWidth CR1_SSI = 1+fieldBitWidth CR1_SSM = 1+fieldBitWidth CR1_START = 1+fieldBitWidth CR1_STOP = 1+fieldBitWidth CR1_SWRST = 1+fieldBitWidth CR1_TCIE = 1+fieldBitWidth CR1_TE = 1+fieldBitWidth CR1_TXEIE = 1+fieldBitWidth CR1_UDIS = 1+fieldBitWidth CR1_UE = 1+fieldBitWidth CR1_URS = 1+fieldBitWidth CR1_WAKE = 1+fieldBitWidth CR2_ADD = 4+fieldBitWidth CR2_ADON = 1+fieldBitWidth CR2_ALIGN = 1+fieldBitWidth CR2_CAL = 1+fieldBitWidth CR2_CCDS = 1+fieldBitWidth CR2_CCPC = 1+fieldBitWidth CR2_CCUS = 1+fieldBitWidth CR2_CLKEN = 1+fieldBitWidth CR2_CONT = 1+fieldBitWidth CR2_CPHA = 1+fieldBitWidth CR2_CPOL = 1+fieldBitWidth CR2_DMA = 1+fieldBitWidth CR2_DMAEN = 1+fieldBitWidth CR2_ERRIE = 1+fieldBitWidth CR2_EXTSEL = 3+fieldBitWidth CR2_EXTTRIG = 1+fieldBitWidth CR2_FREQ = 6+fieldBitWidth CR2_ITBUFEN = 1+fieldBitWidth CR2_ITERREN = 1+fieldBitWidth CR2_ITEVTEN = 1+fieldBitWidth CR2_JEXTSEL = 3+fieldBitWidth CR2_JEXTTRIG = 1+fieldBitWidth CR2_JSWSTART = 1+fieldBitWidth CR2_LAST = 1+fieldBitWidth CR2_LBCL = 1+fieldBitWidth CR2_LBDIE = 1+fieldBitWidth CR2_LBDL = 1+fieldBitWidth CR2_LINEN = 1+fieldBitWidth CR2_MMS = 3+fieldBitWidth CR2_OIS1 = 1+fieldBitWidth CR2_OIS1N = 1+fieldBitWidth CR2_OIS2 = 1+fieldBitWidth CR2_OIS2N = 1+fieldBitWidth CR2_OIS3 = 1+fieldBitWidth CR2_OIS3N = 1+fieldBitWidth CR2_OIS4 = 1+fieldBitWidth CR2_RSTCAL = 1+fieldBitWidth CR2_RXDMAEN = 1+fieldBitWidth CR2_RXNEIE = 1+fieldBitWidth CR2_SSOE = 1+fieldBitWidth CR2_STOP = 2+fieldBitWidth CR2_SWSTART = 1+fieldBitWidth CR2_TI1S = 1+fieldBitWidth CR2_TSVREFE = 1+fieldBitWidth CR2_TXDMAEN = 1+fieldBitWidth CR2_TXEIE = 1+fieldBitWidth CR3_CTSE = 1+fieldBitWidth CR3_CTSIE = 1+fieldBitWidth CR3_DMAR = 1+fieldBitWidth CR3_DMAT = 1+fieldBitWidth CR3_EIE = 1+fieldBitWidth CR3_HDSEL = 1+fieldBitWidth CR3_IREN = 1+fieldBitWidth CR3_IRLP = 1+fieldBitWidth CR3_NACK = 1+fieldBitWidth CR3_RTSE = 1+fieldBitWidth CR3_SCEN = 1+fieldBitWidth CRCPR_CRCPOLY = 16+fieldBitWidth CRH_ALRIE = 1+fieldBitWidth CRH_CNF10 = 2+fieldBitWidth CRH_CNF11 = 2+fieldBitWidth CRH_CNF12 = 2+fieldBitWidth CRH_CNF13 = 2+fieldBitWidth CRH_CNF14 = 2+fieldBitWidth CRH_CNF15 = 2+fieldBitWidth CRH_CNF8 = 2+fieldBitWidth CRH_CNF9 = 2+fieldBitWidth CRH_MODE10 = 2+fieldBitWidth CRH_MODE11 = 2+fieldBitWidth CRH_MODE12 = 2+fieldBitWidth CRH_MODE13 = 2+fieldBitWidth CRH_MODE14 = 2+fieldBitWidth CRH_MODE15 = 2+fieldBitWidth CRH_MODE8 = 2+fieldBitWidth CRH_MODE9 = 2+fieldBitWidth CRH_OWIE = 1+fieldBitWidth CRH_SECIE = 1+fieldBitWidth CRL_ALRF = 1+fieldBitWidth CRL_CNF = 1+fieldBitWidth CRL_CNF0 = 2+fieldBitWidth CRL_CNF1 = 2+fieldBitWidth CRL_CNF2 = 2+fieldBitWidth CRL_CNF3 = 2+fieldBitWidth CRL_CNF4 = 2+fieldBitWidth CRL_CNF5 = 2+fieldBitWidth CRL_CNF6 = 2+fieldBitWidth CRL_CNF7 = 2+fieldBitWidth CRL_MODE0 = 2+fieldBitWidth CRL_MODE1 = 2+fieldBitWidth CRL_MODE2 = 2+fieldBitWidth CRL_MODE3 = 2+fieldBitWidth CRL_MODE4 = 2+fieldBitWidth CRL_MODE5 = 2+fieldBitWidth CRL_MODE6 = 2+fieldBitWidth CRL_MODE7 = 2+fieldBitWidth CRL_OWF = 1+fieldBitWidth CRL_RSF = 1+fieldBitWidth CRL_RTOFF = 1+fieldBitWidth CRL_SECF = 1+fieldBitWidth CSR_CTE = 1+fieldBitWidth CSR_CTI = 1+fieldBitWidth CSR_EWUP = 1+fieldBitWidth CSR_IWDGRSTF = 1+fieldBitWidth CSR_LPWRRSTF = 1+fieldBitWidth CSR_LSION = 1+fieldBitWidth CSR_LSIRDY = 1+fieldBitWidth CSR_PINRSTF = 1+fieldBitWidth CSR_PORRSTF = 1+fieldBitWidth CSR_PVDO = 1+fieldBitWidth CSR_RMVF = 1+fieldBitWidth CSR_SBF = 1+fieldBitWidth CSR_SFTRSTF = 1+fieldBitWidth CSR_TEF = 1+fieldBitWidth CSR_TIF = 1+fieldBitWidth CSR_TPIE = 1+fieldBitWidth CSR_WUF = 1+fieldBitWidth CSR_WWDGRSTF = 1+fieldBitWidth DADDR_ADD = 7+fieldBitWidth DADDR_EF = 1+fieldBitWidth DCOUNT_DATACOUNT = 25+fieldBitWidth DCR_DBA = 5+fieldBitWidth DCR_DBL = 5+fieldBitWidth DCTRL_DBLOCKSIZE = 4+fieldBitWidth DCTRL_DMAEN = 1+fieldBitWidth DCTRL_DTDIR = 1+fieldBitWidth DCTRL_DTEN = 1+fieldBitWidth DCTRL_DTMODE = 1+fieldBitWidth DCTRL_PWSTART = 1+fieldBitWidth DCTRL_PWSTOP = 1+fieldBitWidth DCTRL_RWMOD = 1+fieldBitWidth DCTRL_SDIOEN = 1+fieldBitWidth DHR12L1_DACC1DHR = 12+fieldBitWidth DHR12L2_DACC2DHR = 12+fieldBitWidth DHR12LD_DACC1DHR = 12+fieldBitWidth DHR12LD_DACC2DHR = 12+fieldBitWidth DHR12R1_DACC1DHR = 12+fieldBitWidth DHR12R2_DACC2DHR = 12+fieldBitWidth DHR12RD_DACC1DHR = 12+fieldBitWidth DHR12RD_DACC2DHR = 12+fieldBitWidth DHR8R1_DACC1DHR = 8+fieldBitWidth DHR8R2_DACC2DHR = 8+fieldBitWidth DHR8RD_DACC1DHR = 8+fieldBitWidth DHR8RD_DACC2DHR = 8+fieldBitWidth DIER_BIE = 1+fieldBitWidth DIER_CC1DE = 1+fieldBitWidth DIER_CC1IE = 1+fieldBitWidth DIER_CC2DE = 1+fieldBitWidth DIER_CC2IE = 1+fieldBitWidth DIER_CC3DE = 1+fieldBitWidth DIER_CC3IE = 1+fieldBitWidth DIER_CC4DE = 1+fieldBitWidth DIER_CC4IE = 1+fieldBitWidth DIER_COMDE = 1+fieldBitWidth DIER_COMIE = 1+fieldBitWidth DIER_TDE = 1+fieldBitWidth DIER_TIE = 1+fieldBitWidth DIER_UDE = 1+fieldBitWidth DIER_UIE = 1+fieldBitWidth DIVH_DIVH = 4+fieldBitWidth DIVL_DIVL = 16+fieldBitWidth DLEN_DATALENGTH = 25+fieldBitWidth DMAR_DMAB = 16+fieldBitWidth DOR1_DACC1DOR = 12+fieldBitWidth DOR2_DACC2DOR = 12+fieldBitWidth DR_ADC2DATA = 16+fieldBitWidth DR_DATA = 16+fieldBitWidth DR_DR = 32+fieldBitWidth DR1_D1 = 16+fieldBitWidth DR10_D10 = 16+fieldBitWidth DR11_DR11 = 16+fieldBitWidth DR12_DR12 = 16+fieldBitWidth DR13_DR13 = 16+fieldBitWidth DR14_D14 = 16+fieldBitWidth DR15_D15 = 16+fieldBitWidth DR16_D16 = 16+fieldBitWidth DR17_D17 = 16+fieldBitWidth DR18_D18 = 16+fieldBitWidth DR19_D19 = 16+fieldBitWidth DR2_D2 = 16+fieldBitWidth DR20_D20 = 16+fieldBitWidth DR21_D21 = 16+fieldBitWidth DR22_D22 = 16+fieldBitWidth DR23_D23 = 16+fieldBitWidth DR24_D24 = 16+fieldBitWidth DR25_D25 = 16+fieldBitWidth DR26_D26 = 16+fieldBitWidth DR27_D27 = 16+fieldBitWidth DR28_D28 = 16+fieldBitWidth DR29_D29 = 16+fieldBitWidth DR3_D3 = 16+fieldBitWidth DR30_D30 = 16+fieldBitWidth DR31_D31 = 16+fieldBitWidth DR32_D32 = 16+fieldBitWidth DR33_D33 = 16+fieldBitWidth DR34_D34 = 16+fieldBitWidth DR35_D35 = 16+fieldBitWidth DR36_D36 = 16+fieldBitWidth DR37_D37 = 16+fieldBitWidth DR38_D38 = 16+fieldBitWidth DR39_D39 = 16+fieldBitWidth DR4_D4 = 16+fieldBitWidth DR40_D40 = 16+fieldBitWidth DR41_D41 = 16+fieldBitWidth DR42_D42 = 16+fieldBitWidth DR5_D5 = 16+fieldBitWidth DR6_D6 = 16+fieldBitWidth DR7_D7 = 16+fieldBitWidth DR8_D8 = 16+fieldBitWidth DR9_D9 = 16+fieldBitWidth DTIMER_DATATIME = 32+fieldBitWidth ECCR2_ECCx = 32+fieldBitWidth ECCR3_ECCx = 32+fieldBitWidth EGR_BG = 1+fieldBitWidth EGR_CC1G = 1+fieldBitWidth EGR_CC2G = 1+fieldBitWidth EGR_CC3G = 1+fieldBitWidth EGR_CC4G = 1+fieldBitWidth EGR_COMG = 1+fieldBitWidth EGR_TG = 1+fieldBitWidth EGR_UG = 1+fieldBitWidth EMR_MR0 = 1+fieldBitWidth EMR_MR1 = 1+fieldBitWidth EMR_MR10 = 1+fieldBitWidth EMR_MR11 = 1+fieldBitWidth EMR_MR12 = 1+fieldBitWidth EMR_MR13 = 1+fieldBitWidth EMR_MR14 = 1+fieldBitWidth EMR_MR15 = 1+fieldBitWidth EMR_MR16 = 1+fieldBitWidth EMR_MR17 = 1+fieldBitWidth EMR_MR18 = 1+fieldBitWidth EMR_MR2 = 1+fieldBitWidth EMR_MR3 = 1+fieldBitWidth EMR_MR4 = 1+fieldBitWidth EMR_MR5 = 1+fieldBitWidth EMR_MR6 = 1+fieldBitWidth EMR_MR7 = 1+fieldBitWidth EMR_MR8 = 1+fieldBitWidth EMR_MR9 = 1+fieldBitWidth EP0R_CTR_RX = 1+fieldBitWidth EP0R_CTR_TX = 1+fieldBitWidth EP0R_DTOG_RX = 1+fieldBitWidth EP0R_DTOG_TX = 1+fieldBitWidth EP0R_EA = 4+fieldBitWidth EP0R_EP_KIND = 1+fieldBitWidth EP0R_EP_TYPE = 2+fieldBitWidth EP0R_SETUP = 1+fieldBitWidth EP0R_STAT_RX = 2+fieldBitWidth EP0R_STAT_TX = 2+fieldBitWidth EP1R_CTR_RX = 1+fieldBitWidth EP1R_CTR_TX = 1+fieldBitWidth EP1R_DTOG_RX = 1+fieldBitWidth EP1R_DTOG_TX = 1+fieldBitWidth EP1R_EA = 4+fieldBitWidth EP1R_EP_KIND = 1+fieldBitWidth EP1R_EP_TYPE = 2+fieldBitWidth EP1R_SETUP = 1+fieldBitWidth EP1R_STAT_RX = 2+fieldBitWidth EP1R_STAT_TX = 2+fieldBitWidth EP2R_CTR_RX = 1+fieldBitWidth EP2R_CTR_TX = 1+fieldBitWidth EP2R_DTOG_RX = 1+fieldBitWidth EP2R_DTOG_TX = 1+fieldBitWidth EP2R_EA = 4+fieldBitWidth EP2R_EP_KIND = 1+fieldBitWidth EP2R_EP_TYPE = 2+fieldBitWidth EP2R_SETUP = 1+fieldBitWidth EP2R_STAT_RX = 2+fieldBitWidth EP2R_STAT_TX = 2+fieldBitWidth EP3R_CTR_RX = 1+fieldBitWidth EP3R_CTR_TX = 1+fieldBitWidth EP3R_DTOG_RX = 1+fieldBitWidth EP3R_DTOG_TX = 1+fieldBitWidth EP3R_EA = 4+fieldBitWidth EP3R_EP_KIND = 1+fieldBitWidth EP3R_EP_TYPE = 2+fieldBitWidth EP3R_SETUP = 1+fieldBitWidth EP3R_STAT_RX = 2+fieldBitWidth EP3R_STAT_TX = 2+fieldBitWidth EP4R_CTR_RX = 1+fieldBitWidth EP4R_CTR_TX = 1+fieldBitWidth EP4R_DTOG_RX = 1+fieldBitWidth EP4R_DTOG_TX = 1+fieldBitWidth EP4R_EA = 4+fieldBitWidth EP4R_EP_KIND = 1+fieldBitWidth EP4R_EP_TYPE = 2+fieldBitWidth EP4R_SETUP = 1+fieldBitWidth EP4R_STAT_RX = 2+fieldBitWidth EP4R_STAT_TX = 2+fieldBitWidth EP5R_CTR_RX = 1+fieldBitWidth EP5R_CTR_TX = 1+fieldBitWidth EP5R_DTOG_RX = 1+fieldBitWidth EP5R_DTOG_TX = 1+fieldBitWidth EP5R_EA = 4+fieldBitWidth EP5R_EP_KIND = 1+fieldBitWidth EP5R_EP_TYPE = 2+fieldBitWidth EP5R_SETUP = 1+fieldBitWidth EP5R_STAT_RX = 2+fieldBitWidth EP5R_STAT_TX = 2+fieldBitWidth EP6R_CTR_RX = 1+fieldBitWidth EP6R_CTR_TX = 1+fieldBitWidth EP6R_DTOG_RX = 1+fieldBitWidth EP6R_DTOG_TX = 1+fieldBitWidth EP6R_EA = 4+fieldBitWidth EP6R_EP_KIND = 1+fieldBitWidth EP6R_EP_TYPE = 2+fieldBitWidth EP6R_SETUP = 1+fieldBitWidth EP6R_STAT_RX = 2+fieldBitWidth EP6R_STAT_TX = 2+fieldBitWidth EP7R_CTR_RX = 1+fieldBitWidth EP7R_CTR_TX = 1+fieldBitWidth EP7R_DTOG_RX = 1+fieldBitWidth EP7R_DTOG_TX = 1+fieldBitWidth EP7R_EA = 4+fieldBitWidth EP7R_EP_KIND = 1+fieldBitWidth EP7R_EP_TYPE = 2+fieldBitWidth EP7R_SETUP = 1+fieldBitWidth EP7R_STAT_RX = 2+fieldBitWidth EP7R_STAT_TX = 2+fieldBitWidth EVCR_EVOE = 1+fieldBitWidth EVCR_PIN = 4+fieldBitWidth EVCR_PORT = 3+fieldBitWidth EXTICR1_EXTI0 = 4+fieldBitWidth EXTICR1_EXTI1 = 4+fieldBitWidth EXTICR1_EXTI2 = 4+fieldBitWidth EXTICR1_EXTI3 = 4+fieldBitWidth EXTICR2_EXTI4 = 4+fieldBitWidth EXTICR2_EXTI5 = 4+fieldBitWidth EXTICR2_EXTI6 = 4+fieldBitWidth EXTICR2_EXTI7 = 4+fieldBitWidth EXTICR3_EXTI10 = 4+fieldBitWidth EXTICR3_EXTI11 = 4+fieldBitWidth EXTICR3_EXTI8 = 4+fieldBitWidth EXTICR3_EXTI9 = 4+fieldBitWidth EXTICR4_EXTI12 = 4+fieldBitWidth EXTICR4_EXTI13 = 4+fieldBitWidth EXTICR4_EXTI14 = 4+fieldBitWidth EXTICR4_EXTI15 = 4+fieldBitWidth F0R1_FB0 = 1+fieldBitWidth F0R1_FB1 = 1+fieldBitWidth F0R1_FB10 = 1+fieldBitWidth F0R1_FB11 = 1+fieldBitWidth F0R1_FB12 = 1+fieldBitWidth F0R1_FB13 = 1+fieldBitWidth F0R1_FB14 = 1+fieldBitWidth F0R1_FB15 = 1+fieldBitWidth F0R1_FB16 = 1+fieldBitWidth F0R1_FB17 = 1+fieldBitWidth F0R1_FB18 = 1+fieldBitWidth F0R1_FB19 = 1+fieldBitWidth F0R1_FB2 = 1+fieldBitWidth F0R1_FB20 = 1+fieldBitWidth F0R1_FB21 = 1+fieldBitWidth F0R1_FB22 = 1+fieldBitWidth F0R1_FB23 = 1+fieldBitWidth F0R1_FB24 = 1+fieldBitWidth F0R1_FB25 = 1+fieldBitWidth F0R1_FB26 = 1+fieldBitWidth F0R1_FB27 = 1+fieldBitWidth F0R1_FB28 = 1+fieldBitWidth F0R1_FB29 = 1+fieldBitWidth F0R1_FB3 = 1+fieldBitWidth F0R1_FB30 = 1+fieldBitWidth F0R1_FB31 = 1+fieldBitWidth F0R1_FB4 = 1+fieldBitWidth F0R1_FB5 = 1+fieldBitWidth F0R1_FB6 = 1+fieldBitWidth F0R1_FB7 = 1+fieldBitWidth F0R1_FB8 = 1+fieldBitWidth F0R1_FB9 = 1+fieldBitWidth F0R2_FB0 = 1+fieldBitWidth F0R2_FB1 = 1+fieldBitWidth F0R2_FB10 = 1+fieldBitWidth F0R2_FB11 = 1+fieldBitWidth F0R2_FB12 = 1+fieldBitWidth F0R2_FB13 = 1+fieldBitWidth F0R2_FB14 = 1+fieldBitWidth F0R2_FB15 = 1+fieldBitWidth F0R2_FB16 = 1+fieldBitWidth F0R2_FB17 = 1+fieldBitWidth F0R2_FB18 = 1+fieldBitWidth F0R2_FB19 = 1+fieldBitWidth F0R2_FB2 = 1+fieldBitWidth F0R2_FB20 = 1+fieldBitWidth F0R2_FB21 = 1+fieldBitWidth F0R2_FB22 = 1+fieldBitWidth F0R2_FB23 = 1+fieldBitWidth F0R2_FB24 = 1+fieldBitWidth F0R2_FB25 = 1+fieldBitWidth F0R2_FB26 = 1+fieldBitWidth F0R2_FB27 = 1+fieldBitWidth F0R2_FB28 = 1+fieldBitWidth F0R2_FB29 = 1+fieldBitWidth F0R2_FB3 = 1+fieldBitWidth F0R2_FB30 = 1+fieldBitWidth F0R2_FB31 = 1+fieldBitWidth F0R2_FB4 = 1+fieldBitWidth F0R2_FB5 = 1+fieldBitWidth F0R2_FB6 = 1+fieldBitWidth F0R2_FB7 = 1+fieldBitWidth F0R2_FB8 = 1+fieldBitWidth F0R2_FB9 = 1+fieldBitWidth F10R1_FB0 = 1+fieldBitWidth F10R1_FB1 = 1+fieldBitWidth F10R1_FB10 = 1+fieldBitWidth F10R1_FB11 = 1+fieldBitWidth F10R1_FB12 = 1+fieldBitWidth F10R1_FB13 = 1+fieldBitWidth F10R1_FB14 = 1+fieldBitWidth F10R1_FB15 = 1+fieldBitWidth F10R1_FB16 = 1+fieldBitWidth F10R1_FB17 = 1+fieldBitWidth F10R1_FB18 = 1+fieldBitWidth F10R1_FB19 = 1+fieldBitWidth F10R1_FB2 = 1+fieldBitWidth F10R1_FB20 = 1+fieldBitWidth F10R1_FB21 = 1+fieldBitWidth F10R1_FB22 = 1+fieldBitWidth F10R1_FB23 = 1+fieldBitWidth F10R1_FB24 = 1+fieldBitWidth F10R1_FB25 = 1+fieldBitWidth F10R1_FB26 = 1+fieldBitWidth F10R1_FB27 = 1+fieldBitWidth F10R1_FB28 = 1+fieldBitWidth F10R1_FB29 = 1+fieldBitWidth F10R1_FB3 = 1+fieldBitWidth F10R1_FB30 = 1+fieldBitWidth F10R1_FB31 = 1+fieldBitWidth F10R1_FB4 = 1+fieldBitWidth F10R1_FB5 = 1+fieldBitWidth F10R1_FB6 = 1+fieldBitWidth F10R1_FB7 = 1+fieldBitWidth F10R1_FB8 = 1+fieldBitWidth F10R1_FB9 = 1+fieldBitWidth F10R2_FB0 = 1+fieldBitWidth F10R2_FB1 = 1+fieldBitWidth F10R2_FB10 = 1+fieldBitWidth F10R2_FB11 = 1+fieldBitWidth F10R2_FB12 = 1+fieldBitWidth F10R2_FB13 = 1+fieldBitWidth F10R2_FB14 = 1+fieldBitWidth F10R2_FB15 = 1+fieldBitWidth F10R2_FB16 = 1+fieldBitWidth F10R2_FB17 = 1+fieldBitWidth F10R2_FB18 = 1+fieldBitWidth F10R2_FB19 = 1+fieldBitWidth F10R2_FB2 = 1+fieldBitWidth F10R2_FB20 = 1+fieldBitWidth F10R2_FB21 = 1+fieldBitWidth F10R2_FB22 = 1+fieldBitWidth F10R2_FB23 = 1+fieldBitWidth F10R2_FB24 = 1+fieldBitWidth F10R2_FB25 = 1+fieldBitWidth F10R2_FB26 = 1+fieldBitWidth F10R2_FB27 = 1+fieldBitWidth F10R2_FB28 = 1+fieldBitWidth F10R2_FB29 = 1+fieldBitWidth F10R2_FB3 = 1+fieldBitWidth F10R2_FB30 = 1+fieldBitWidth F10R2_FB31 = 1+fieldBitWidth F10R2_FB4 = 1+fieldBitWidth F10R2_FB5 = 1+fieldBitWidth F10R2_FB6 = 1+fieldBitWidth F10R2_FB7 = 1+fieldBitWidth F10R2_FB8 = 1+fieldBitWidth F10R2_FB9 = 1+fieldBitWidth F11R1_FB0 = 1+fieldBitWidth F11R1_FB1 = 1+fieldBitWidth F11R1_FB10 = 1+fieldBitWidth F11R1_FB11 = 1+fieldBitWidth F11R1_FB12 = 1+fieldBitWidth F11R1_FB13 = 1+fieldBitWidth F11R1_FB14 = 1+fieldBitWidth F11R1_FB15 = 1+fieldBitWidth F11R1_FB16 = 1+fieldBitWidth F11R1_FB17 = 1+fieldBitWidth F11R1_FB18 = 1+fieldBitWidth F11R1_FB19 = 1+fieldBitWidth F11R1_FB2 = 1+fieldBitWidth F11R1_FB20 = 1+fieldBitWidth F11R1_FB21 = 1+fieldBitWidth F11R1_FB22 = 1+fieldBitWidth F11R1_FB23 = 1+fieldBitWidth F11R1_FB24 = 1+fieldBitWidth F11R1_FB25 = 1+fieldBitWidth F11R1_FB26 = 1+fieldBitWidth F11R1_FB27 = 1+fieldBitWidth F11R1_FB28 = 1+fieldBitWidth F11R1_FB29 = 1+fieldBitWidth F11R1_FB3 = 1+fieldBitWidth F11R1_FB30 = 1+fieldBitWidth F11R1_FB31 = 1+fieldBitWidth F11R1_FB4 = 1+fieldBitWidth F11R1_FB5 = 1+fieldBitWidth F11R1_FB6 = 1+fieldBitWidth F11R1_FB7 = 1+fieldBitWidth F11R1_FB8 = 1+fieldBitWidth F11R1_FB9 = 1+fieldBitWidth F11R2_FB0 = 1+fieldBitWidth F11R2_FB1 = 1+fieldBitWidth F11R2_FB10 = 1+fieldBitWidth F11R2_FB11 = 1+fieldBitWidth F11R2_FB12 = 1+fieldBitWidth F11R2_FB13 = 1+fieldBitWidth F11R2_FB14 = 1+fieldBitWidth F11R2_FB15 = 1+fieldBitWidth F11R2_FB16 = 1+fieldBitWidth F11R2_FB17 = 1+fieldBitWidth F11R2_FB18 = 1+fieldBitWidth F11R2_FB19 = 1+fieldBitWidth F11R2_FB2 = 1+fieldBitWidth F11R2_FB20 = 1+fieldBitWidth F11R2_FB21 = 1+fieldBitWidth F11R2_FB22 = 1+fieldBitWidth F11R2_FB23 = 1+fieldBitWidth F11R2_FB24 = 1+fieldBitWidth F11R2_FB25 = 1+fieldBitWidth F11R2_FB26 = 1+fieldBitWidth F11R2_FB27 = 1+fieldBitWidth F11R2_FB28 = 1+fieldBitWidth F11R2_FB29 = 1+fieldBitWidth F11R2_FB3 = 1+fieldBitWidth F11R2_FB30 = 1+fieldBitWidth F11R2_FB31 = 1+fieldBitWidth F11R2_FB4 = 1+fieldBitWidth F11R2_FB5 = 1+fieldBitWidth F11R2_FB6 = 1+fieldBitWidth F11R2_FB7 = 1+fieldBitWidth F11R2_FB8 = 1+fieldBitWidth F11R2_FB9 = 1+fieldBitWidth F12R1_FB0 = 1+fieldBitWidth F12R1_FB1 = 1+fieldBitWidth F12R1_FB10 = 1+fieldBitWidth F12R1_FB11 = 1+fieldBitWidth F12R1_FB12 = 1+fieldBitWidth F12R1_FB13 = 1+fieldBitWidth F12R1_FB14 = 1+fieldBitWidth F12R1_FB15 = 1+fieldBitWidth F12R1_FB16 = 1+fieldBitWidth F12R1_FB17 = 1+fieldBitWidth F12R1_FB18 = 1+fieldBitWidth F12R1_FB19 = 1+fieldBitWidth F12R1_FB2 = 1+fieldBitWidth F12R1_FB20 = 1+fieldBitWidth F12R1_FB21 = 1+fieldBitWidth F12R1_FB22 = 1+fieldBitWidth F12R1_FB23 = 1+fieldBitWidth F12R1_FB24 = 1+fieldBitWidth F12R1_FB25 = 1+fieldBitWidth F12R1_FB26 = 1+fieldBitWidth F12R1_FB27 = 1+fieldBitWidth F12R1_FB28 = 1+fieldBitWidth F12R1_FB29 = 1+fieldBitWidth F12R1_FB3 = 1+fieldBitWidth F12R1_FB30 = 1+fieldBitWidth F12R1_FB31 = 1+fieldBitWidth F12R1_FB4 = 1+fieldBitWidth F12R1_FB5 = 1+fieldBitWidth F12R1_FB6 = 1+fieldBitWidth F12R1_FB7 = 1+fieldBitWidth F12R1_FB8 = 1+fieldBitWidth F12R1_FB9 = 1+fieldBitWidth F12R2_FB0 = 1+fieldBitWidth F12R2_FB1 = 1+fieldBitWidth F12R2_FB10 = 1+fieldBitWidth F12R2_FB11 = 1+fieldBitWidth F12R2_FB12 = 1+fieldBitWidth F12R2_FB13 = 1+fieldBitWidth F12R2_FB14 = 1+fieldBitWidth F12R2_FB15 = 1+fieldBitWidth F12R2_FB16 = 1+fieldBitWidth F12R2_FB17 = 1+fieldBitWidth F12R2_FB18 = 1+fieldBitWidth F12R2_FB19 = 1+fieldBitWidth F12R2_FB2 = 1+fieldBitWidth F12R2_FB20 = 1+fieldBitWidth F12R2_FB21 = 1+fieldBitWidth F12R2_FB22 = 1+fieldBitWidth F12R2_FB23 = 1+fieldBitWidth F12R2_FB24 = 1+fieldBitWidth F12R2_FB25 = 1+fieldBitWidth F12R2_FB26 = 1+fieldBitWidth F12R2_FB27 = 1+fieldBitWidth F12R2_FB28 = 1+fieldBitWidth F12R2_FB29 = 1+fieldBitWidth F12R2_FB3 = 1+fieldBitWidth F12R2_FB30 = 1+fieldBitWidth F12R2_FB31 = 1+fieldBitWidth F12R2_FB4 = 1+fieldBitWidth F12R2_FB5 = 1+fieldBitWidth F12R2_FB6 = 1+fieldBitWidth F12R2_FB7 = 1+fieldBitWidth F12R2_FB8 = 1+fieldBitWidth F12R2_FB9 = 1+fieldBitWidth F13R1_FB0 = 1+fieldBitWidth F13R1_FB1 = 1+fieldBitWidth F13R1_FB10 = 1+fieldBitWidth F13R1_FB11 = 1+fieldBitWidth F13R1_FB12 = 1+fieldBitWidth F13R1_FB13 = 1+fieldBitWidth F13R1_FB14 = 1+fieldBitWidth F13R1_FB15 = 1+fieldBitWidth F13R1_FB16 = 1+fieldBitWidth F13R1_FB17 = 1+fieldBitWidth F13R1_FB18 = 1+fieldBitWidth F13R1_FB19 = 1+fieldBitWidth F13R1_FB2 = 1+fieldBitWidth F13R1_FB20 = 1+fieldBitWidth F13R1_FB21 = 1+fieldBitWidth F13R1_FB22 = 1+fieldBitWidth F13R1_FB23 = 1+fieldBitWidth F13R1_FB24 = 1+fieldBitWidth F13R1_FB25 = 1+fieldBitWidth F13R1_FB26 = 1+fieldBitWidth F13R1_FB27 = 1+fieldBitWidth F13R1_FB28 = 1+fieldBitWidth F13R1_FB29 = 1+fieldBitWidth F13R1_FB3 = 1+fieldBitWidth F13R1_FB30 = 1+fieldBitWidth F13R1_FB31 = 1+fieldBitWidth F13R1_FB4 = 1+fieldBitWidth F13R1_FB5 = 1+fieldBitWidth F13R1_FB6 = 1+fieldBitWidth F13R1_FB7 = 1+fieldBitWidth F13R1_FB8 = 1+fieldBitWidth F13R1_FB9 = 1+fieldBitWidth F13R2_FB0 = 1+fieldBitWidth F13R2_FB1 = 1+fieldBitWidth F13R2_FB10 = 1+fieldBitWidth F13R2_FB11 = 1+fieldBitWidth F13R2_FB12 = 1+fieldBitWidth F13R2_FB13 = 1+fieldBitWidth F13R2_FB14 = 1+fieldBitWidth F13R2_FB15 = 1+fieldBitWidth F13R2_FB16 = 1+fieldBitWidth F13R2_FB17 = 1+fieldBitWidth F13R2_FB18 = 1+fieldBitWidth F13R2_FB19 = 1+fieldBitWidth F13R2_FB2 = 1+fieldBitWidth F13R2_FB20 = 1+fieldBitWidth F13R2_FB21 = 1+fieldBitWidth F13R2_FB22 = 1+fieldBitWidth F13R2_FB23 = 1+fieldBitWidth F13R2_FB24 = 1+fieldBitWidth F13R2_FB25 = 1+fieldBitWidth F13R2_FB26 = 1+fieldBitWidth F13R2_FB27 = 1+fieldBitWidth F13R2_FB28 = 1+fieldBitWidth F13R2_FB29 = 1+fieldBitWidth F13R2_FB3 = 1+fieldBitWidth F13R2_FB30 = 1+fieldBitWidth F13R2_FB31 = 1+fieldBitWidth F13R2_FB4 = 1+fieldBitWidth F13R2_FB5 = 1+fieldBitWidth F13R2_FB6 = 1+fieldBitWidth F13R2_FB7 = 1+fieldBitWidth F13R2_FB8 = 1+fieldBitWidth F13R2_FB9 = 1+fieldBitWidth F1R1_FB0 = 1+fieldBitWidth F1R1_FB1 = 1+fieldBitWidth F1R1_FB10 = 1+fieldBitWidth F1R1_FB11 = 1+fieldBitWidth F1R1_FB12 = 1+fieldBitWidth F1R1_FB13 = 1+fieldBitWidth F1R1_FB14 = 1+fieldBitWidth F1R1_FB15 = 1+fieldBitWidth F1R1_FB16 = 1+fieldBitWidth F1R1_FB17 = 1+fieldBitWidth F1R1_FB18 = 1+fieldBitWidth F1R1_FB19 = 1+fieldBitWidth F1R1_FB2 = 1+fieldBitWidth F1R1_FB20 = 1+fieldBitWidth F1R1_FB21 = 1+fieldBitWidth F1R1_FB22 = 1+fieldBitWidth F1R1_FB23 = 1+fieldBitWidth F1R1_FB24 = 1+fieldBitWidth F1R1_FB25 = 1+fieldBitWidth F1R1_FB26 = 1+fieldBitWidth F1R1_FB27 = 1+fieldBitWidth F1R1_FB28 = 1+fieldBitWidth F1R1_FB29 = 1+fieldBitWidth F1R1_FB3 = 1+fieldBitWidth F1R1_FB30 = 1+fieldBitWidth F1R1_FB31 = 1+fieldBitWidth F1R1_FB4 = 1+fieldBitWidth F1R1_FB5 = 1+fieldBitWidth F1R1_FB6 = 1+fieldBitWidth F1R1_FB7 = 1+fieldBitWidth F1R1_FB8 = 1+fieldBitWidth F1R1_FB9 = 1+fieldBitWidth F1R2_FB0 = 1+fieldBitWidth F1R2_FB1 = 1+fieldBitWidth F1R2_FB10 = 1+fieldBitWidth F1R2_FB11 = 1+fieldBitWidth F1R2_FB12 = 1+fieldBitWidth F1R2_FB13 = 1+fieldBitWidth F1R2_FB14 = 1+fieldBitWidth F1R2_FB15 = 1+fieldBitWidth F1R2_FB16 = 1+fieldBitWidth F1R2_FB17 = 1+fieldBitWidth F1R2_FB18 = 1+fieldBitWidth F1R2_FB19 = 1+fieldBitWidth F1R2_FB2 = 1+fieldBitWidth F1R2_FB20 = 1+fieldBitWidth F1R2_FB21 = 1+fieldBitWidth F1R2_FB22 = 1+fieldBitWidth F1R2_FB23 = 1+fieldBitWidth F1R2_FB24 = 1+fieldBitWidth F1R2_FB25 = 1+fieldBitWidth F1R2_FB26 = 1+fieldBitWidth F1R2_FB27 = 1+fieldBitWidth F1R2_FB28 = 1+fieldBitWidth F1R2_FB29 = 1+fieldBitWidth F1R2_FB3 = 1+fieldBitWidth F1R2_FB30 = 1+fieldBitWidth F1R2_FB31 = 1+fieldBitWidth F1R2_FB4 = 1+fieldBitWidth F1R2_FB5 = 1+fieldBitWidth F1R2_FB6 = 1+fieldBitWidth F1R2_FB7 = 1+fieldBitWidth F1R2_FB8 = 1+fieldBitWidth F1R2_FB9 = 1+fieldBitWidth F2R1_FB0 = 1+fieldBitWidth F2R1_FB1 = 1+fieldBitWidth F2R1_FB10 = 1+fieldBitWidth F2R1_FB11 = 1+fieldBitWidth F2R1_FB12 = 1+fieldBitWidth F2R1_FB13 = 1+fieldBitWidth F2R1_FB14 = 1+fieldBitWidth F2R1_FB15 = 1+fieldBitWidth F2R1_FB16 = 1+fieldBitWidth F2R1_FB17 = 1+fieldBitWidth F2R1_FB18 = 1+fieldBitWidth F2R1_FB19 = 1+fieldBitWidth F2R1_FB2 = 1+fieldBitWidth F2R1_FB20 = 1+fieldBitWidth F2R1_FB21 = 1+fieldBitWidth F2R1_FB22 = 1+fieldBitWidth F2R1_FB23 = 1+fieldBitWidth F2R1_FB24 = 1+fieldBitWidth F2R1_FB25 = 1+fieldBitWidth F2R1_FB26 = 1+fieldBitWidth F2R1_FB27 = 1+fieldBitWidth F2R1_FB28 = 1+fieldBitWidth F2R1_FB29 = 1+fieldBitWidth F2R1_FB3 = 1+fieldBitWidth F2R1_FB30 = 1+fieldBitWidth F2R1_FB31 = 1+fieldBitWidth F2R1_FB4 = 1+fieldBitWidth F2R1_FB5 = 1+fieldBitWidth F2R1_FB6 = 1+fieldBitWidth F2R1_FB7 = 1+fieldBitWidth F2R1_FB8 = 1+fieldBitWidth F2R1_FB9 = 1+fieldBitWidth F2R2_FB0 = 1+fieldBitWidth F2R2_FB1 = 1+fieldBitWidth F2R2_FB10 = 1+fieldBitWidth F2R2_FB11 = 1+fieldBitWidth F2R2_FB12 = 1+fieldBitWidth F2R2_FB13 = 1+fieldBitWidth F2R2_FB14 = 1+fieldBitWidth F2R2_FB15 = 1+fieldBitWidth F2R2_FB16 = 1+fieldBitWidth F2R2_FB17 = 1+fieldBitWidth F2R2_FB18 = 1+fieldBitWidth F2R2_FB19 = 1+fieldBitWidth F2R2_FB2 = 1+fieldBitWidth F2R2_FB20 = 1+fieldBitWidth F2R2_FB21 = 1+fieldBitWidth F2R2_FB22 = 1+fieldBitWidth F2R2_FB23 = 1+fieldBitWidth F2R2_FB24 = 1+fieldBitWidth F2R2_FB25 = 1+fieldBitWidth F2R2_FB26 = 1+fieldBitWidth F2R2_FB27 = 1+fieldBitWidth F2R2_FB28 = 1+fieldBitWidth F2R2_FB29 = 1+fieldBitWidth F2R2_FB3 = 1+fieldBitWidth F2R2_FB30 = 1+fieldBitWidth F2R2_FB31 = 1+fieldBitWidth F2R2_FB4 = 1+fieldBitWidth F2R2_FB5 = 1+fieldBitWidth F2R2_FB6 = 1+fieldBitWidth F2R2_FB7 = 1+fieldBitWidth F2R2_FB8 = 1+fieldBitWidth F2R2_FB9 = 1+fieldBitWidth F3R1_FB0 = 1+fieldBitWidth F3R1_FB1 = 1+fieldBitWidth F3R1_FB10 = 1+fieldBitWidth F3R1_FB11 = 1+fieldBitWidth F3R1_FB12 = 1+fieldBitWidth F3R1_FB13 = 1+fieldBitWidth F3R1_FB14 = 1+fieldBitWidth F3R1_FB15 = 1+fieldBitWidth F3R1_FB16 = 1+fieldBitWidth F3R1_FB17 = 1+fieldBitWidth F3R1_FB18 = 1+fieldBitWidth F3R1_FB19 = 1+fieldBitWidth F3R1_FB2 = 1+fieldBitWidth F3R1_FB20 = 1+fieldBitWidth F3R1_FB21 = 1+fieldBitWidth F3R1_FB22 = 1+fieldBitWidth F3R1_FB23 = 1+fieldBitWidth F3R1_FB24 = 1+fieldBitWidth F3R1_FB25 = 1+fieldBitWidth F3R1_FB26 = 1+fieldBitWidth F3R1_FB27 = 1+fieldBitWidth F3R1_FB28 = 1+fieldBitWidth F3R1_FB29 = 1+fieldBitWidth F3R1_FB3 = 1+fieldBitWidth F3R1_FB30 = 1+fieldBitWidth F3R1_FB31 = 1+fieldBitWidth F3R1_FB4 = 1+fieldBitWidth F3R1_FB5 = 1+fieldBitWidth F3R1_FB6 = 1+fieldBitWidth F3R1_FB7 = 1+fieldBitWidth F3R1_FB8 = 1+fieldBitWidth F3R1_FB9 = 1+fieldBitWidth F3R2_FB0 = 1+fieldBitWidth F3R2_FB1 = 1+fieldBitWidth F3R2_FB10 = 1+fieldBitWidth F3R2_FB11 = 1+fieldBitWidth F3R2_FB12 = 1+fieldBitWidth F3R2_FB13 = 1+fieldBitWidth F3R2_FB14 = 1+fieldBitWidth F3R2_FB15 = 1+fieldBitWidth F3R2_FB16 = 1+fieldBitWidth F3R2_FB17 = 1+fieldBitWidth F3R2_FB18 = 1+fieldBitWidth F3R2_FB19 = 1+fieldBitWidth F3R2_FB2 = 1+fieldBitWidth F3R2_FB20 = 1+fieldBitWidth F3R2_FB21 = 1+fieldBitWidth F3R2_FB22 = 1+fieldBitWidth F3R2_FB23 = 1+fieldBitWidth F3R2_FB24 = 1+fieldBitWidth F3R2_FB25 = 1+fieldBitWidth F3R2_FB26 = 1+fieldBitWidth F3R2_FB27 = 1+fieldBitWidth F3R2_FB28 = 1+fieldBitWidth F3R2_FB29 = 1+fieldBitWidth F3R2_FB3 = 1+fieldBitWidth F3R2_FB30 = 1+fieldBitWidth F3R2_FB31 = 1+fieldBitWidth F3R2_FB4 = 1+fieldBitWidth F3R2_FB5 = 1+fieldBitWidth F3R2_FB6 = 1+fieldBitWidth F3R2_FB7 = 1+fieldBitWidth F3R2_FB8 = 1+fieldBitWidth F3R2_FB9 = 1+fieldBitWidth F4R1_FB0 = 1+fieldBitWidth F4R1_FB1 = 1+fieldBitWidth F4R1_FB10 = 1+fieldBitWidth F4R1_FB11 = 1+fieldBitWidth F4R1_FB12 = 1+fieldBitWidth F4R1_FB13 = 1+fieldBitWidth F4R1_FB14 = 1+fieldBitWidth F4R1_FB15 = 1+fieldBitWidth F4R1_FB16 = 1+fieldBitWidth F4R1_FB17 = 1+fieldBitWidth F4R1_FB18 = 1+fieldBitWidth F4R1_FB19 = 1+fieldBitWidth F4R1_FB2 = 1+fieldBitWidth F4R1_FB20 = 1+fieldBitWidth F4R1_FB21 = 1+fieldBitWidth F4R1_FB22 = 1+fieldBitWidth F4R1_FB23 = 1+fieldBitWidth F4R1_FB24 = 1+fieldBitWidth F4R1_FB25 = 1+fieldBitWidth F4R1_FB26 = 1+fieldBitWidth F4R1_FB27 = 1+fieldBitWidth F4R1_FB28 = 1+fieldBitWidth F4R1_FB29 = 1+fieldBitWidth F4R1_FB3 = 1+fieldBitWidth F4R1_FB30 = 1+fieldBitWidth F4R1_FB31 = 1+fieldBitWidth F4R1_FB4 = 1+fieldBitWidth F4R1_FB5 = 1+fieldBitWidth F4R1_FB6 = 1+fieldBitWidth F4R1_FB7 = 1+fieldBitWidth F4R1_FB8 = 1+fieldBitWidth F4R1_FB9 = 1+fieldBitWidth F4R2_FB0 = 1+fieldBitWidth F4R2_FB1 = 1+fieldBitWidth F4R2_FB10 = 1+fieldBitWidth F4R2_FB11 = 1+fieldBitWidth F4R2_FB12 = 1+fieldBitWidth F4R2_FB13 = 1+fieldBitWidth F4R2_FB14 = 1+fieldBitWidth F4R2_FB15 = 1+fieldBitWidth F4R2_FB16 = 1+fieldBitWidth F4R2_FB17 = 1+fieldBitWidth F4R2_FB18 = 1+fieldBitWidth F4R2_FB19 = 1+fieldBitWidth F4R2_FB2 = 1+fieldBitWidth F4R2_FB20 = 1+fieldBitWidth F4R2_FB21 = 1+fieldBitWidth F4R2_FB22 = 1+fieldBitWidth F4R2_FB23 = 1+fieldBitWidth F4R2_FB24 = 1+fieldBitWidth F4R2_FB25 = 1+fieldBitWidth F4R2_FB26 = 1+fieldBitWidth F4R2_FB27 = 1+fieldBitWidth F4R2_FB28 = 1+fieldBitWidth F4R2_FB29 = 1+fieldBitWidth F4R2_FB3 = 1+fieldBitWidth F4R2_FB30 = 1+fieldBitWidth F4R2_FB31 = 1+fieldBitWidth F4R2_FB4 = 1+fieldBitWidth F4R2_FB5 = 1+fieldBitWidth F4R2_FB6 = 1+fieldBitWidth F4R2_FB7 = 1+fieldBitWidth F4R2_FB8 = 1+fieldBitWidth F4R2_FB9 = 1+fieldBitWidth F5R1_FB0 = 1+fieldBitWidth F5R1_FB1 = 1+fieldBitWidth F5R1_FB10 = 1+fieldBitWidth F5R1_FB11 = 1+fieldBitWidth F5R1_FB12 = 1+fieldBitWidth F5R1_FB13 = 1+fieldBitWidth F5R1_FB14 = 1+fieldBitWidth F5R1_FB15 = 1+fieldBitWidth F5R1_FB16 = 1+fieldBitWidth F5R1_FB17 = 1+fieldBitWidth F5R1_FB18 = 1+fieldBitWidth F5R1_FB19 = 1+fieldBitWidth F5R1_FB2 = 1+fieldBitWidth F5R1_FB20 = 1+fieldBitWidth F5R1_FB21 = 1+fieldBitWidth F5R1_FB22 = 1+fieldBitWidth F5R1_FB23 = 1+fieldBitWidth F5R1_FB24 = 1+fieldBitWidth F5R1_FB25 = 1+fieldBitWidth F5R1_FB26 = 1+fieldBitWidth F5R1_FB27 = 1+fieldBitWidth F5R1_FB28 = 1+fieldBitWidth F5R1_FB29 = 1+fieldBitWidth F5R1_FB3 = 1+fieldBitWidth F5R1_FB30 = 1+fieldBitWidth F5R1_FB31 = 1+fieldBitWidth F5R1_FB4 = 1+fieldBitWidth F5R1_FB5 = 1+fieldBitWidth F5R1_FB6 = 1+fieldBitWidth F5R1_FB7 = 1+fieldBitWidth F5R1_FB8 = 1+fieldBitWidth F5R1_FB9 = 1+fieldBitWidth F5R2_FB0 = 1+fieldBitWidth F5R2_FB1 = 1+fieldBitWidth F5R2_FB10 = 1+fieldBitWidth F5R2_FB11 = 1+fieldBitWidth F5R2_FB12 = 1+fieldBitWidth F5R2_FB13 = 1+fieldBitWidth F5R2_FB14 = 1+fieldBitWidth F5R2_FB15 = 1+fieldBitWidth F5R2_FB16 = 1+fieldBitWidth F5R2_FB17 = 1+fieldBitWidth F5R2_FB18 = 1+fieldBitWidth F5R2_FB19 = 1+fieldBitWidth F5R2_FB2 = 1+fieldBitWidth F5R2_FB20 = 1+fieldBitWidth F5R2_FB21 = 1+fieldBitWidth F5R2_FB22 = 1+fieldBitWidth F5R2_FB23 = 1+fieldBitWidth F5R2_FB24 = 1+fieldBitWidth F5R2_FB25 = 1+fieldBitWidth F5R2_FB26 = 1+fieldBitWidth F5R2_FB27 = 1+fieldBitWidth F5R2_FB28 = 1+fieldBitWidth F5R2_FB29 = 1+fieldBitWidth F5R2_FB3 = 1+fieldBitWidth F5R2_FB30 = 1+fieldBitWidth F5R2_FB31 = 1+fieldBitWidth F5R2_FB4 = 1+fieldBitWidth F5R2_FB5 = 1+fieldBitWidth F5R2_FB6 = 1+fieldBitWidth F5R2_FB7 = 1+fieldBitWidth F5R2_FB8 = 1+fieldBitWidth F5R2_FB9 = 1+fieldBitWidth F6R1_FB0 = 1+fieldBitWidth F6R1_FB1 = 1+fieldBitWidth F6R1_FB10 = 1+fieldBitWidth F6R1_FB11 = 1+fieldBitWidth F6R1_FB12 = 1+fieldBitWidth F6R1_FB13 = 1+fieldBitWidth F6R1_FB14 = 1+fieldBitWidth F6R1_FB15 = 1+fieldBitWidth F6R1_FB16 = 1+fieldBitWidth F6R1_FB17 = 1+fieldBitWidth F6R1_FB18 = 1+fieldBitWidth F6R1_FB19 = 1+fieldBitWidth F6R1_FB2 = 1+fieldBitWidth F6R1_FB20 = 1+fieldBitWidth F6R1_FB21 = 1+fieldBitWidth F6R1_FB22 = 1+fieldBitWidth F6R1_FB23 = 1+fieldBitWidth F6R1_FB24 = 1+fieldBitWidth F6R1_FB25 = 1+fieldBitWidth F6R1_FB26 = 1+fieldBitWidth F6R1_FB27 = 1+fieldBitWidth F6R1_FB28 = 1+fieldBitWidth F6R1_FB29 = 1+fieldBitWidth F6R1_FB3 = 1+fieldBitWidth F6R1_FB30 = 1+fieldBitWidth F6R1_FB31 = 1+fieldBitWidth F6R1_FB4 = 1+fieldBitWidth F6R1_FB5 = 1+fieldBitWidth F6R1_FB6 = 1+fieldBitWidth F6R1_FB7 = 1+fieldBitWidth F6R1_FB8 = 1+fieldBitWidth F6R1_FB9 = 1+fieldBitWidth F6R2_FB0 = 1+fieldBitWidth F6R2_FB1 = 1+fieldBitWidth F6R2_FB10 = 1+fieldBitWidth F6R2_FB11 = 1+fieldBitWidth F6R2_FB12 = 1+fieldBitWidth F6R2_FB13 = 1+fieldBitWidth F6R2_FB14 = 1+fieldBitWidth F6R2_FB15 = 1+fieldBitWidth F6R2_FB16 = 1+fieldBitWidth F6R2_FB17 = 1+fieldBitWidth F6R2_FB18 = 1+fieldBitWidth F6R2_FB19 = 1+fieldBitWidth F6R2_FB2 = 1+fieldBitWidth F6R2_FB20 = 1+fieldBitWidth F6R2_FB21 = 1+fieldBitWidth F6R2_FB22 = 1+fieldBitWidth F6R2_FB23 = 1+fieldBitWidth F6R2_FB24 = 1+fieldBitWidth F6R2_FB25 = 1+fieldBitWidth F6R2_FB26 = 1+fieldBitWidth F6R2_FB27 = 1+fieldBitWidth F6R2_FB28 = 1+fieldBitWidth F6R2_FB29 = 1+fieldBitWidth F6R2_FB3 = 1+fieldBitWidth F6R2_FB30 = 1+fieldBitWidth F6R2_FB31 = 1+fieldBitWidth F6R2_FB4 = 1+fieldBitWidth F6R2_FB5 = 1+fieldBitWidth F6R2_FB6 = 1+fieldBitWidth F6R2_FB7 = 1+fieldBitWidth F6R2_FB8 = 1+fieldBitWidth F6R2_FB9 = 1+fieldBitWidth F7R1_FB0 = 1+fieldBitWidth F7R1_FB1 = 1+fieldBitWidth F7R1_FB10 = 1+fieldBitWidth F7R1_FB11 = 1+fieldBitWidth F7R1_FB12 = 1+fieldBitWidth F7R1_FB13 = 1+fieldBitWidth F7R1_FB14 = 1+fieldBitWidth F7R1_FB15 = 1+fieldBitWidth F7R1_FB16 = 1+fieldBitWidth F7R1_FB17 = 1+fieldBitWidth F7R1_FB18 = 1+fieldBitWidth F7R1_FB19 = 1+fieldBitWidth F7R1_FB2 = 1+fieldBitWidth F7R1_FB20 = 1+fieldBitWidth F7R1_FB21 = 1+fieldBitWidth F7R1_FB22 = 1+fieldBitWidth F7R1_FB23 = 1+fieldBitWidth F7R1_FB24 = 1+fieldBitWidth F7R1_FB25 = 1+fieldBitWidth F7R1_FB26 = 1+fieldBitWidth F7R1_FB27 = 1+fieldBitWidth F7R1_FB28 = 1+fieldBitWidth F7R1_FB29 = 1+fieldBitWidth F7R1_FB3 = 1+fieldBitWidth F7R1_FB30 = 1+fieldBitWidth F7R1_FB31 = 1+fieldBitWidth F7R1_FB4 = 1+fieldBitWidth F7R1_FB5 = 1+fieldBitWidth F7R1_FB6 = 1+fieldBitWidth F7R1_FB7 = 1+fieldBitWidth F7R1_FB8 = 1+fieldBitWidth F7R1_FB9 = 1+fieldBitWidth F7R2_FB0 = 1+fieldBitWidth F7R2_FB1 = 1+fieldBitWidth F7R2_FB10 = 1+fieldBitWidth F7R2_FB11 = 1+fieldBitWidth F7R2_FB12 = 1+fieldBitWidth F7R2_FB13 = 1+fieldBitWidth F7R2_FB14 = 1+fieldBitWidth F7R2_FB15 = 1+fieldBitWidth F7R2_FB16 = 1+fieldBitWidth F7R2_FB17 = 1+fieldBitWidth F7R2_FB18 = 1+fieldBitWidth F7R2_FB19 = 1+fieldBitWidth F7R2_FB2 = 1+fieldBitWidth F7R2_FB20 = 1+fieldBitWidth F7R2_FB21 = 1+fieldBitWidth F7R2_FB22 = 1+fieldBitWidth F7R2_FB23 = 1+fieldBitWidth F7R2_FB24 = 1+fieldBitWidth F7R2_FB25 = 1+fieldBitWidth F7R2_FB26 = 1+fieldBitWidth F7R2_FB27 = 1+fieldBitWidth F7R2_FB28 = 1+fieldBitWidth F7R2_FB29 = 1+fieldBitWidth F7R2_FB3 = 1+fieldBitWidth F7R2_FB30 = 1+fieldBitWidth F7R2_FB31 = 1+fieldBitWidth F7R2_FB4 = 1+fieldBitWidth F7R2_FB5 = 1+fieldBitWidth F7R2_FB6 = 1+fieldBitWidth F7R2_FB7 = 1+fieldBitWidth F7R2_FB8 = 1+fieldBitWidth F7R2_FB9 = 1+fieldBitWidth F8R1_FB0 = 1+fieldBitWidth F8R1_FB1 = 1+fieldBitWidth F8R1_FB10 = 1+fieldBitWidth F8R1_FB11 = 1+fieldBitWidth F8R1_FB12 = 1+fieldBitWidth F8R1_FB13 = 1+fieldBitWidth F8R1_FB14 = 1+fieldBitWidth F8R1_FB15 = 1+fieldBitWidth F8R1_FB16 = 1+fieldBitWidth F8R1_FB17 = 1+fieldBitWidth F8R1_FB18 = 1+fieldBitWidth F8R1_FB19 = 1+fieldBitWidth F8R1_FB2 = 1+fieldBitWidth F8R1_FB20 = 1+fieldBitWidth F8R1_FB21 = 1+fieldBitWidth F8R1_FB22 = 1+fieldBitWidth F8R1_FB23 = 1+fieldBitWidth F8R1_FB24 = 1+fieldBitWidth F8R1_FB25 = 1+fieldBitWidth F8R1_FB26 = 1+fieldBitWidth F8R1_FB27 = 1+fieldBitWidth F8R1_FB28 = 1+fieldBitWidth F8R1_FB29 = 1+fieldBitWidth F8R1_FB3 = 1+fieldBitWidth F8R1_FB30 = 1+fieldBitWidth F8R1_FB31 = 1+fieldBitWidth F8R1_FB4 = 1+fieldBitWidth F8R1_FB5 = 1+fieldBitWidth F8R1_FB6 = 1+fieldBitWidth F8R1_FB7 = 1+fieldBitWidth F8R1_FB8 = 1+fieldBitWidth F8R1_FB9 = 1+fieldBitWidth F8R2_FB0 = 1+fieldBitWidth F8R2_FB1 = 1+fieldBitWidth F8R2_FB10 = 1+fieldBitWidth F8R2_FB11 = 1+fieldBitWidth F8R2_FB12 = 1+fieldBitWidth F8R2_FB13 = 1+fieldBitWidth F8R2_FB14 = 1+fieldBitWidth F8R2_FB15 = 1+fieldBitWidth F8R2_FB16 = 1+fieldBitWidth F8R2_FB17 = 1+fieldBitWidth F8R2_FB18 = 1+fieldBitWidth F8R2_FB19 = 1+fieldBitWidth F8R2_FB2 = 1+fieldBitWidth F8R2_FB20 = 1+fieldBitWidth F8R2_FB21 = 1+fieldBitWidth F8R2_FB22 = 1+fieldBitWidth F8R2_FB23 = 1+fieldBitWidth F8R2_FB24 = 1+fieldBitWidth F8R2_FB25 = 1+fieldBitWidth F8R2_FB26 = 1+fieldBitWidth F8R2_FB27 = 1+fieldBitWidth F8R2_FB28 = 1+fieldBitWidth F8R2_FB29 = 1+fieldBitWidth F8R2_FB3 = 1+fieldBitWidth F8R2_FB30 = 1+fieldBitWidth F8R2_FB31 = 1+fieldBitWidth F8R2_FB4 = 1+fieldBitWidth F8R2_FB5 = 1+fieldBitWidth F8R2_FB6 = 1+fieldBitWidth F8R2_FB7 = 1+fieldBitWidth F8R2_FB8 = 1+fieldBitWidth F8R2_FB9 = 1+fieldBitWidth F9R1_FB0 = 1+fieldBitWidth F9R1_FB1 = 1+fieldBitWidth F9R1_FB10 = 1+fieldBitWidth F9R1_FB11 = 1+fieldBitWidth F9R1_FB12 = 1+fieldBitWidth F9R1_FB13 = 1+fieldBitWidth F9R1_FB14 = 1+fieldBitWidth F9R1_FB15 = 1+fieldBitWidth F9R1_FB16 = 1+fieldBitWidth F9R1_FB17 = 1+fieldBitWidth F9R1_FB18 = 1+fieldBitWidth F9R1_FB19 = 1+fieldBitWidth F9R1_FB2 = 1+fieldBitWidth F9R1_FB20 = 1+fieldBitWidth F9R1_FB21 = 1+fieldBitWidth F9R1_FB22 = 1+fieldBitWidth F9R1_FB23 = 1+fieldBitWidth F9R1_FB24 = 1+fieldBitWidth F9R1_FB25 = 1+fieldBitWidth F9R1_FB26 = 1+fieldBitWidth F9R1_FB27 = 1+fieldBitWidth F9R1_FB28 = 1+fieldBitWidth F9R1_FB29 = 1+fieldBitWidth F9R1_FB3 = 1+fieldBitWidth F9R1_FB30 = 1+fieldBitWidth F9R1_FB31 = 1+fieldBitWidth F9R1_FB4 = 1+fieldBitWidth F9R1_FB5 = 1+fieldBitWidth F9R1_FB6 = 1+fieldBitWidth F9R1_FB7 = 1+fieldBitWidth F9R1_FB8 = 1+fieldBitWidth F9R1_FB9 = 1+fieldBitWidth F9R2_FB0 = 1+fieldBitWidth F9R2_FB1 = 1+fieldBitWidth F9R2_FB10 = 1+fieldBitWidth F9R2_FB11 = 1+fieldBitWidth F9R2_FB12 = 1+fieldBitWidth F9R2_FB13 = 1+fieldBitWidth F9R2_FB14 = 1+fieldBitWidth F9R2_FB15 = 1+fieldBitWidth F9R2_FB16 = 1+fieldBitWidth F9R2_FB17 = 1+fieldBitWidth F9R2_FB18 = 1+fieldBitWidth F9R2_FB19 = 1+fieldBitWidth F9R2_FB2 = 1+fieldBitWidth F9R2_FB20 = 1+fieldBitWidth F9R2_FB21 = 1+fieldBitWidth F9R2_FB22 = 1+fieldBitWidth F9R2_FB23 = 1+fieldBitWidth F9R2_FB24 = 1+fieldBitWidth F9R2_FB25 = 1+fieldBitWidth F9R2_FB26 = 1+fieldBitWidth F9R2_FB27 = 1+fieldBitWidth F9R2_FB28 = 1+fieldBitWidth F9R2_FB29 = 1+fieldBitWidth F9R2_FB3 = 1+fieldBitWidth F9R2_FB30 = 1+fieldBitWidth F9R2_FB31 = 1+fieldBitWidth F9R2_FB4 = 1+fieldBitWidth F9R2_FB5 = 1+fieldBitWidth F9R2_FB6 = 1+fieldBitWidth F9R2_FB7 = 1+fieldBitWidth F9R2_FB8 = 1+fieldBitWidth F9R2_FB9 = 1+fieldBitWidth FIFO_FIFOData = 32+fieldBitWidth FIFOCNT_FIF0COUNT = 24+fieldBitWidth FNR_FN = 11+fieldBitWidth FNR_LCK = 1+fieldBitWidth FNR_LSOF = 2+fieldBitWidth FNR_RXDM = 1+fieldBitWidth FNR_RXDP = 1+fieldBitWidth FTSR_TR0 = 1+fieldBitWidth FTSR_TR1 = 1+fieldBitWidth FTSR_TR10 = 1+fieldBitWidth FTSR_TR11 = 1+fieldBitWidth FTSR_TR12 = 1+fieldBitWidth FTSR_TR13 = 1+fieldBitWidth FTSR_TR14 = 1+fieldBitWidth FTSR_TR15 = 1+fieldBitWidth FTSR_TR16 = 1+fieldBitWidth FTSR_TR17 = 1+fieldBitWidth FTSR_TR18 = 1+fieldBitWidth FTSR_TR2 = 1+fieldBitWidth FTSR_TR3 = 1+fieldBitWidth FTSR_TR4 = 1+fieldBitWidth FTSR_TR5 = 1+fieldBitWidth FTSR_TR6 = 1+fieldBitWidth FTSR_TR7 = 1+fieldBitWidth FTSR_TR8 = 1+fieldBitWidth FTSR_TR9 = 1+fieldBitWidth GTPR_GT = 8+fieldBitWidth GTPR_PSC = 8+fieldBitWidth HTR_HT = 12+fieldBitWidth I2SCFGR_CHLEN = 1+fieldBitWidth I2SCFGR_CKPOL = 1+fieldBitWidth I2SCFGR_DATLEN = 2+fieldBitWidth I2SCFGR_I2SCFG = 2+fieldBitWidth I2SCFGR_I2SE = 1+fieldBitWidth I2SCFGR_I2SMOD = 1+fieldBitWidth I2SCFGR_I2SSTD = 2+fieldBitWidth I2SCFGR_PCMSYNC = 1+fieldBitWidth I2SPR_I2SDIV = 8+fieldBitWidth I2SPR_MCKOE = 1+fieldBitWidth I2SPR_ODD = 1+fieldBitWidth IABR0_ACTIVE = 32+fieldBitWidth IABR1_ACTIVE = 32+fieldBitWidth ICER0_CLRENA = 32+fieldBitWidth ICER1_CLRENA = 32+fieldBitWidth ICPR0_CLRPEND = 32+fieldBitWidth ICPR1_CLRPEND = 32+fieldBitWidth ICR_CCRCFAILC = 1+fieldBitWidth ICR_CEATAENDC = 1+fieldBitWidth ICR_CMDRENDC = 1+fieldBitWidth ICR_CMDSENTC = 1+fieldBitWidth ICR_CTIMEOUTC = 1+fieldBitWidth ICR_DATAENDC = 1+fieldBitWidth ICR_DBCKENDC = 1+fieldBitWidth ICR_DCRCFAILC = 1+fieldBitWidth ICR_DTIMEOUTC = 1+fieldBitWidth ICR_RXOVERRC = 1+fieldBitWidth ICR_SDIOITC = 1+fieldBitWidth ICR_STBITERRC = 1+fieldBitWidth ICR_TXUNDERRC = 1+fieldBitWidth ICTR_INTLINESNUM = 4+fieldBitWidth IDCODE_DEV_ID = 12+fieldBitWidth IDCODE_REV_ID = 16+fieldBitWidth IDR_IDR = 8+fieldBitWidth IDR_IDR0 = 1+fieldBitWidth IDR_IDR1 = 1+fieldBitWidth IDR_IDR10 = 1+fieldBitWidth IDR_IDR11 = 1+fieldBitWidth IDR_IDR12 = 1+fieldBitWidth IDR_IDR13 = 1+fieldBitWidth IDR_IDR14 = 1+fieldBitWidth IDR_IDR15 = 1+fieldBitWidth IDR_IDR2 = 1+fieldBitWidth IDR_IDR3 = 1+fieldBitWidth IDR_IDR4 = 1+fieldBitWidth IDR_IDR5 = 1+fieldBitWidth IDR_IDR6 = 1+fieldBitWidth IDR_IDR7 = 1+fieldBitWidth IDR_IDR8 = 1+fieldBitWidth IDR_IDR9 = 1+fieldBitWidth IFCR_CGIF1 = 1+fieldBitWidth IFCR_CGIF2 = 1+fieldBitWidth IFCR_CGIF3 = 1+fieldBitWidth IFCR_CGIF4 = 1+fieldBitWidth IFCR_CGIF5 = 1+fieldBitWidth IFCR_CGIF6 = 1+fieldBitWidth IFCR_CGIF7 = 1+fieldBitWidth IFCR_CHTIF1 = 1+fieldBitWidth IFCR_CHTIF2 = 1+fieldBitWidth IFCR_CHTIF3 = 1+fieldBitWidth IFCR_CHTIF4 = 1+fieldBitWidth IFCR_CHTIF5 = 1+fieldBitWidth IFCR_CHTIF6 = 1+fieldBitWidth IFCR_CHTIF7 = 1+fieldBitWidth IFCR_CTCIF1 = 1+fieldBitWidth IFCR_CTCIF2 = 1+fieldBitWidth IFCR_CTCIF3 = 1+fieldBitWidth IFCR_CTCIF4 = 1+fieldBitWidth IFCR_CTCIF5 = 1+fieldBitWidth IFCR_CTCIF6 = 1+fieldBitWidth IFCR_CTCIF7 = 1+fieldBitWidth IFCR_CTEIF1 = 1+fieldBitWidth IFCR_CTEIF2 = 1+fieldBitWidth IFCR_CTEIF3 = 1+fieldBitWidth IFCR_CTEIF4 = 1+fieldBitWidth IFCR_CTEIF5 = 1+fieldBitWidth IFCR_CTEIF6 = 1+fieldBitWidth IFCR_CTEIF7 = 1+fieldBitWidth IMR_MR0 = 1+fieldBitWidth IMR_MR1 = 1+fieldBitWidth IMR_MR10 = 1+fieldBitWidth IMR_MR11 = 1+fieldBitWidth IMR_MR12 = 1+fieldBitWidth IMR_MR13 = 1+fieldBitWidth IMR_MR14 = 1+fieldBitWidth IMR_MR15 = 1+fieldBitWidth IMR_MR16 = 1+fieldBitWidth IMR_MR17 = 1+fieldBitWidth IMR_MR18 = 1+fieldBitWidth IMR_MR2 = 1+fieldBitWidth IMR_MR3 = 1+fieldBitWidth IMR_MR4 = 1+fieldBitWidth IMR_MR5 = 1+fieldBitWidth IMR_MR6 = 1+fieldBitWidth IMR_MR7 = 1+fieldBitWidth IMR_MR8 = 1+fieldBitWidth IMR_MR9 = 1+fieldBitWidth IPR0_IPR_N0 = 8+fieldBitWidth IPR0_IPR_N1 = 8+fieldBitWidth IPR0_IPR_N2 = 8+fieldBitWidth IPR0_IPR_N3 = 8+fieldBitWidth IPR1_IPR_N0 = 8+fieldBitWidth IPR1_IPR_N1 = 8+fieldBitWidth IPR1_IPR_N2 = 8+fieldBitWidth IPR1_IPR_N3 = 8+fieldBitWidth IPR10_IPR_N0 = 8+fieldBitWidth IPR10_IPR_N1 = 8+fieldBitWidth IPR10_IPR_N2 = 8+fieldBitWidth IPR10_IPR_N3 = 8+fieldBitWidth IPR11_IPR_N0 = 8+fieldBitWidth IPR11_IPR_N1 = 8+fieldBitWidth IPR11_IPR_N2 = 8+fieldBitWidth IPR11_IPR_N3 = 8+fieldBitWidth IPR12_IPR_N0 = 8+fieldBitWidth IPR12_IPR_N1 = 8+fieldBitWidth IPR12_IPR_N2 = 8+fieldBitWidth IPR12_IPR_N3 = 8+fieldBitWidth IPR13_IPR_N0 = 8+fieldBitWidth IPR13_IPR_N1 = 8+fieldBitWidth IPR13_IPR_N2 = 8+fieldBitWidth IPR13_IPR_N3 = 8+fieldBitWidth IPR14_IPR_N0 = 8+fieldBitWidth IPR14_IPR_N1 = 8+fieldBitWidth IPR14_IPR_N2 = 8+fieldBitWidth IPR14_IPR_N3 = 8+fieldBitWidth IPR2_IPR_N0 = 8+fieldBitWidth IPR2_IPR_N1 = 8+fieldBitWidth IPR2_IPR_N2 = 8+fieldBitWidth IPR2_IPR_N3 = 8+fieldBitWidth IPR3_IPR_N0 = 8+fieldBitWidth IPR3_IPR_N1 = 8+fieldBitWidth IPR3_IPR_N2 = 8+fieldBitWidth IPR3_IPR_N3 = 8+fieldBitWidth IPR4_IPR_N0 = 8+fieldBitWidth IPR4_IPR_N1 = 8+fieldBitWidth IPR4_IPR_N2 = 8+fieldBitWidth IPR4_IPR_N3 = 8+fieldBitWidth IPR5_IPR_N0 = 8+fieldBitWidth IPR5_IPR_N1 = 8+fieldBitWidth IPR5_IPR_N2 = 8+fieldBitWidth IPR5_IPR_N3 = 8+fieldBitWidth IPR6_IPR_N0 = 8+fieldBitWidth IPR6_IPR_N1 = 8+fieldBitWidth IPR6_IPR_N2 = 8+fieldBitWidth IPR6_IPR_N3 = 8+fieldBitWidth IPR7_IPR_N0 = 8+fieldBitWidth IPR7_IPR_N1 = 8+fieldBitWidth IPR7_IPR_N2 = 8+fieldBitWidth IPR7_IPR_N3 = 8+fieldBitWidth IPR8_IPR_N0 = 8+fieldBitWidth IPR8_IPR_N1 = 8+fieldBitWidth IPR8_IPR_N2 = 8+fieldBitWidth IPR8_IPR_N3 = 8+fieldBitWidth IPR9_IPR_N0 = 8+fieldBitWidth IPR9_IPR_N1 = 8+fieldBitWidth IPR9_IPR_N2 = 8+fieldBitWidth IPR9_IPR_N3 = 8+fieldBitWidth ISER0_SETENA = 32+fieldBitWidth ISER1_SETENA = 32+fieldBitWidth ISPR0_SETPEND = 32+fieldBitWidth ISPR1_SETPEND = 32+fieldBitWidth ISR_GIF1 = 1+fieldBitWidth ISR_GIF2 = 1+fieldBitWidth ISR_GIF3 = 1+fieldBitWidth ISR_GIF4 = 1+fieldBitWidth ISR_GIF5 = 1+fieldBitWidth ISR_GIF6 = 1+fieldBitWidth ISR_GIF7 = 1+fieldBitWidth ISR_HTIF1 = 1+fieldBitWidth ISR_HTIF2 = 1+fieldBitWidth ISR_HTIF3 = 1+fieldBitWidth ISR_HTIF4 = 1+fieldBitWidth ISR_HTIF5 = 1+fieldBitWidth ISR_HTIF6 = 1+fieldBitWidth ISR_HTIF7 = 1+fieldBitWidth ISR_TCIF1 = 1+fieldBitWidth ISR_TCIF2 = 1+fieldBitWidth ISR_TCIF3 = 1+fieldBitWidth ISR_TCIF4 = 1+fieldBitWidth ISR_TCIF5 = 1+fieldBitWidth ISR_TCIF6 = 1+fieldBitWidth ISR_TCIF7 = 1+fieldBitWidth ISR_TEIF1 = 1+fieldBitWidth ISR_TEIF2 = 1+fieldBitWidth ISR_TEIF3 = 1+fieldBitWidth ISR_TEIF4 = 1+fieldBitWidth ISR_TEIF5 = 1+fieldBitWidth ISR_TEIF6 = 1+fieldBitWidth ISR_TEIF7 = 1+fieldBitWidth ISTR_CTR = 1+fieldBitWidth ISTR_DIR = 1+fieldBitWidth ISTR_EP_ID = 4+fieldBitWidth ISTR_ERR = 1+fieldBitWidth ISTR_ESOF = 1+fieldBitWidth ISTR_PMAOVR = 1+fieldBitWidth ISTR_RESET = 1+fieldBitWidth ISTR_SOF = 1+fieldBitWidth ISTR_SUSP = 1+fieldBitWidth ISTR_WKUP = 1+fieldBitWidth JDR1_JDATA = 16+fieldBitWidth JDR2_JDATA = 16+fieldBitWidth JDR3_JDATA = 16+fieldBitWidth JDR4_JDATA = 16+fieldBitWidth JOFR1_JOFFSET1 = 12+fieldBitWidth JOFR2_JOFFSET2 = 12+fieldBitWidth JOFR3_JOFFSET3 = 12+fieldBitWidth JOFR4_JOFFSET4 = 12+fieldBitWidth JSQR_JL = 2+fieldBitWidth JSQR_JSQ1 = 5+fieldBitWidth JSQR_JSQ2 = 5+fieldBitWidth JSQR_JSQ3 = 5+fieldBitWidth JSQR_JSQ4 = 5+fieldBitWidth KEYR_KEY = 32+fieldBitWidth KR_KEY = 16+fieldBitWidth LCKR_LCK0 = 1+fieldBitWidth LCKR_LCK1 = 1+fieldBitWidth LCKR_LCK10 = 1+fieldBitWidth LCKR_LCK11 = 1+fieldBitWidth LCKR_LCK12 = 1+fieldBitWidth LCKR_LCK13 = 1+fieldBitWidth LCKR_LCK14 = 1+fieldBitWidth LCKR_LCK15 = 1+fieldBitWidth LCKR_LCK2 = 1+fieldBitWidth LCKR_LCK3 = 1+fieldBitWidth LCKR_LCK4 = 1+fieldBitWidth LCKR_LCK5 = 1+fieldBitWidth LCKR_LCK6 = 1+fieldBitWidth LCKR_LCK7 = 1+fieldBitWidth LCKR_LCK8 = 1+fieldBitWidth LCKR_LCK9 = 1+fieldBitWidth LCKR_LCKK = 1+fieldBitWidth LTR_LT = 12+fieldBitWidth MAPR_ADC1_ETRGINJ_REMAP = 1+fieldBitWidth MAPR_ADC1_ETRGREG_REMAP = 1+fieldBitWidth MAPR_ADC2_ETRGINJ_REMAP = 1+fieldBitWidth MAPR_ADC2_ETRGREG_REMAP = 1+fieldBitWidth MAPR_CAN_REMAP = 2+fieldBitWidth MAPR_I2C1_REMAP = 1+fieldBitWidth MAPR_PD01_REMAP = 1+fieldBitWidth MAPR_SPI1_REMAP = 1+fieldBitWidth MAPR_SWJ_CFG = 3+fieldBitWidth MAPR_TIM1_REMAP = 2+fieldBitWidth MAPR_TIM2_REMAP = 2+fieldBitWidth MAPR_TIM3_REMAP = 2+fieldBitWidth MAPR_TIM4_REMAP = 1+fieldBitWidth MAPR_TIM5CH4_IREMAP = 1+fieldBitWidth MAPR_USART1_REMAP = 1+fieldBitWidth MAPR_USART2_REMAP = 1+fieldBitWidth MAPR_USART3_REMAP = 2+fieldBitWidth MAPR2_FSMC_NADV = 1+fieldBitWidth MAPR2_TIM10_REMAP = 1+fieldBitWidth MAPR2_TIM11_REMAP = 1+fieldBitWidth MAPR2_TIM13_REMAP = 1+fieldBitWidth MAPR2_TIM14_REMAP = 1+fieldBitWidth MAPR2_TIM9_REMAP = 1+fieldBitWidth MASK_CCRCFAILIE = 1+fieldBitWidth MASK_CEATENDIE = 1+fieldBitWidth MASK_CMDACTIE = 1+fieldBitWidth MASK_CMDRENDIE = 1+fieldBitWidth MASK_CMDSENTIE = 1+fieldBitWidth MASK_CTIMEOUTIE = 1+fieldBitWidth MASK_DATAENDIE = 1+fieldBitWidth MASK_DBACKENDIE = 1+fieldBitWidth MASK_DCRCFAILIE = 1+fieldBitWidth MASK_DTIMEOUTIE = 1+fieldBitWidth MASK_RXACTIE = 1+fieldBitWidth MASK_RXDAVLIE = 1+fieldBitWidth MASK_RXFIFOEIE = 1+fieldBitWidth MASK_RXFIFOFIE = 1+fieldBitWidth MASK_RXFIFOHFIE = 1+fieldBitWidth MASK_RXOVERRIE = 1+fieldBitWidth MASK_SDIOITIE = 1+fieldBitWidth MASK_STBITERRIE = 1+fieldBitWidth MASK_TXACTIE = 1+fieldBitWidth MASK_TXDAVLIE = 1+fieldBitWidth MASK_TXFIFOEIE = 1+fieldBitWidth MASK_TXFIFOFIE = 1+fieldBitWidth MASK_TXFIFOHEIE = 1+fieldBitWidth MASK_TXUNDERRIE = 1+fieldBitWidth OAR1_ADD0 = 1+fieldBitWidth OAR1_ADD10 = 2+fieldBitWidth OAR1_ADD7 = 7+fieldBitWidth OAR1_ADDMODE = 1+fieldBitWidth OAR2_ADD2 = 7+fieldBitWidth OAR2_ENDUAL = 1+fieldBitWidth OBR_Data0 = 8+fieldBitWidth OBR_Data1 = 8+fieldBitWidth OBR_OPTERR = 1+fieldBitWidth OBR_RDPRT = 1+fieldBitWidth OBR_WDG_SW = 1+fieldBitWidth OBR_nRST_STDBY = 1+fieldBitWidth OBR_nRST_STOP = 1+fieldBitWidth ODR_ODR0 = 1+fieldBitWidth ODR_ODR1 = 1+fieldBitWidth ODR_ODR10 = 1+fieldBitWidth ODR_ODR11 = 1+fieldBitWidth ODR_ODR12 = 1+fieldBitWidth ODR_ODR13 = 1+fieldBitWidth ODR_ODR14 = 1+fieldBitWidth ODR_ODR15 = 1+fieldBitWidth ODR_ODR2 = 1+fieldBitWidth ODR_ODR3 = 1+fieldBitWidth ODR_ODR4 = 1+fieldBitWidth ODR_ODR5 = 1+fieldBitWidth ODR_ODR6 = 1+fieldBitWidth ODR_ODR7 = 1+fieldBitWidth ODR_ODR8 = 1+fieldBitWidth ODR_ODR9 = 1+fieldBitWidth OPTKEYR_OPTKEY = 32+fieldBitWidth PATT2_ATTHIZx = 8+fieldBitWidth PATT2_ATTHOLDx = 8+fieldBitWidth PATT2_ATTSETx = 8+fieldBitWidth PATT2_ATTWAITx = 8+fieldBitWidth PATT3_ATTHIZx = 8+fieldBitWidth PATT3_ATTHOLDx = 8+fieldBitWidth PATT3_ATTSETx = 8+fieldBitWidth PATT3_ATTWAITx = 8+fieldBitWidth PATT4_ATTHIZx = 8+fieldBitWidth PATT4_ATTHOLDx = 8+fieldBitWidth PATT4_ATTSETx = 8+fieldBitWidth PATT4_ATTWAITx = 8+fieldBitWidth PCR2_ECCEN = 1+fieldBitWidth PCR2_ECCPS = 3+fieldBitWidth PCR2_PBKEN = 1+fieldBitWidth PCR2_PTYP = 1+fieldBitWidth PCR2_PWAITEN = 1+fieldBitWidth PCR2_PWID = 2+fieldBitWidth PCR2_TAR = 4+fieldBitWidth PCR2_TCLR = 4+fieldBitWidth PCR3_ECCEN = 1+fieldBitWidth PCR3_ECCPS = 3+fieldBitWidth PCR3_PBKEN = 1+fieldBitWidth PCR3_PTYP = 1+fieldBitWidth PCR3_PWAITEN = 1+fieldBitWidth PCR3_PWID = 2+fieldBitWidth PCR3_TAR = 4+fieldBitWidth PCR3_TCLR = 4+fieldBitWidth PCR4_ECCEN = 1+fieldBitWidth PCR4_ECCPS = 3+fieldBitWidth PCR4_PBKEN = 1+fieldBitWidth PCR4_PTYP = 1+fieldBitWidth PCR4_PWAITEN = 1+fieldBitWidth PCR4_PWID = 2+fieldBitWidth PCR4_TAR = 4+fieldBitWidth PCR4_TCLR = 4+fieldBitWidth PIO4_IOHIZx = 8+fieldBitWidth PIO4_IOHOLDx = 8+fieldBitWidth PIO4_IOSETx = 8+fieldBitWidth PIO4_IOWAITx = 8+fieldBitWidth PMEM2_MEMHIZx = 8+fieldBitWidth PMEM2_MEMHOLDx = 8+fieldBitWidth PMEM2_MEMSETx = 8+fieldBitWidth PMEM2_MEMWAITx = 8+fieldBitWidth PMEM3_MEMHIZx = 8+fieldBitWidth PMEM3_MEMHOLDx = 8+fieldBitWidth PMEM3_MEMSETx = 8+fieldBitWidth PMEM3_MEMWAITx = 8+fieldBitWidth PMEM4_MEMHIZx = 8+fieldBitWidth PMEM4_MEMHOLDx = 8+fieldBitWidth PMEM4_MEMSETx = 8+fieldBitWidth PMEM4_MEMWAITx = 8+fieldBitWidth POWER_PWRCTRL = 2+fieldBitWidth PR_PR = 3+fieldBitWidth PR_PR0 = 1+fieldBitWidth PR_PR1 = 1+fieldBitWidth PR_PR10 = 1+fieldBitWidth PR_PR11 = 1+fieldBitWidth PR_PR12 = 1+fieldBitWidth PR_PR13 = 1+fieldBitWidth PR_PR14 = 1+fieldBitWidth PR_PR15 = 1+fieldBitWidth PR_PR16 = 1+fieldBitWidth PR_PR17 = 1+fieldBitWidth PR_PR18 = 1+fieldBitWidth PR_PR2 = 1+fieldBitWidth PR_PR3 = 1+fieldBitWidth PR_PR4 = 1+fieldBitWidth PR_PR5 = 1+fieldBitWidth PR_PR6 = 1+fieldBitWidth PR_PR7 = 1+fieldBitWidth PR_PR8 = 1+fieldBitWidth PR_PR9 = 1+fieldBitWidth PRLH_PRLH = 4+fieldBitWidth PRLL_PRLL = 16+fieldBitWidth PSC_PSC = 16+fieldBitWidth RCR_REP = 8+fieldBitWidth RESP2_CARDSTATUS2 = 32+fieldBitWidth RESP3_CARDSTATUS3 = 32+fieldBitWidth RESP4_CARDSTATUS4 = 32+fieldBitWidth RESPCMD_RESPCMD = 6+fieldBitWidth RESPI1_CARDSTATUS1 = 32+fieldBitWidth RLR_RL = 12+fieldBitWidth RTCCR_ASOE = 1+fieldBitWidth RTCCR_ASOS = 1+fieldBitWidth RTCCR_CAL = 7+fieldBitWidth RTCCR_CCO = 1+fieldBitWidth RTSR_TR0 = 1+fieldBitWidth RTSR_TR1 = 1+fieldBitWidth RTSR_TR10 = 1+fieldBitWidth RTSR_TR11 = 1+fieldBitWidth RTSR_TR12 = 1+fieldBitWidth RTSR_TR13 = 1+fieldBitWidth RTSR_TR14 = 1+fieldBitWidth RTSR_TR15 = 1+fieldBitWidth RTSR_TR16 = 1+fieldBitWidth RTSR_TR17 = 1+fieldBitWidth RTSR_TR18 = 1+fieldBitWidth RTSR_TR2 = 1+fieldBitWidth RTSR_TR3 = 1+fieldBitWidth RTSR_TR4 = 1+fieldBitWidth RTSR_TR5 = 1+fieldBitWidth RTSR_TR6 = 1+fieldBitWidth RTSR_TR7 = 1+fieldBitWidth RTSR_TR8 = 1+fieldBitWidth RTSR_TR9 = 1+fieldBitWidth RXCRCR_RxCRC = 16+fieldBitWidth SMCR_ECE = 1+fieldBitWidth SMCR_ETF = 4+fieldBitWidth SMCR_ETP = 1+fieldBitWidth SMCR_ETPS = 2+fieldBitWidth SMCR_MSM = 1+fieldBitWidth SMCR_SMS = 3+fieldBitWidth SMCR_TS = 3+fieldBitWidth SMPR1_SMP10 = 3+fieldBitWidth SMPR1_SMP11 = 3+fieldBitWidth SMPR1_SMP12 = 3+fieldBitWidth SMPR1_SMP13 = 3+fieldBitWidth SMPR1_SMP14 = 3+fieldBitWidth SMPR1_SMP15 = 3+fieldBitWidth SMPR1_SMP16 = 3+fieldBitWidth SMPR1_SMP17 = 3+fieldBitWidth SMPR2_SMP0 = 3+fieldBitWidth SMPR2_SMP1 = 3+fieldBitWidth SMPR2_SMP2 = 3+fieldBitWidth SMPR2_SMP3 = 3+fieldBitWidth SMPR2_SMP4 = 3+fieldBitWidth SMPR2_SMP5 = 3+fieldBitWidth SMPR2_SMP6 = 3+fieldBitWidth SMPR2_SMP7 = 3+fieldBitWidth SMPR2_SMP8 = 3+fieldBitWidth SMPR2_SMP9 = 3+fieldBitWidth SQR1_L = 4+fieldBitWidth SQR1_SQ13 = 5+fieldBitWidth SQR1_SQ14 = 5+fieldBitWidth SQR1_SQ15 = 5+fieldBitWidth SQR1_SQ16 = 5+fieldBitWidth SQR2_SQ10 = 5+fieldBitWidth SQR2_SQ11 = 5+fieldBitWidth SQR2_SQ12 = 5+fieldBitWidth SQR2_SQ7 = 5+fieldBitWidth SQR2_SQ8 = 5+fieldBitWidth SQR2_SQ9 = 5+fieldBitWidth SQR3_SQ1 = 5+fieldBitWidth SQR3_SQ2 = 5+fieldBitWidth SQR3_SQ3 = 5+fieldBitWidth SQR3_SQ4 = 5+fieldBitWidth SQR3_SQ5 = 5+fieldBitWidth SQR3_SQ6 = 5+fieldBitWidth SR_AWD = 1+fieldBitWidth SR_BIF = 1+fieldBitWidth SR_BSY = 1+fieldBitWidth SR_CC1IF = 1+fieldBitWidth SR_CC1OF = 1+fieldBitWidth SR_CC2IF = 1+fieldBitWidth SR_CC2OF = 1+fieldBitWidth SR_CC3IF = 1+fieldBitWidth SR_CC3OF = 1+fieldBitWidth SR_CC4IF = 1+fieldBitWidth SR_CC4OF = 1+fieldBitWidth SR_CHSIDE = 1+fieldBitWidth SR_COMIF = 1+fieldBitWidth SR_CRCERR = 1+fieldBitWidth SR_CTS = 1+fieldBitWidth SR_EOC = 1+fieldBitWidth SR_EOP = 1+fieldBitWidth SR_EWI = 1+fieldBitWidth SR_FE = 1+fieldBitWidth SR_IDLE = 1+fieldBitWidth SR_JEOC = 1+fieldBitWidth SR_JSTRT = 1+fieldBitWidth SR_LBD = 1+fieldBitWidth SR_MODF = 1+fieldBitWidth SR_NE = 1+fieldBitWidth SR_ORE = 1+fieldBitWidth SR_OVR = 1+fieldBitWidth SR_PE = 1+fieldBitWidth SR_PGERR = 1+fieldBitWidth SR_PVU = 1+fieldBitWidth SR_RVU = 1+fieldBitWidth SR_RXNE = 1+fieldBitWidth SR_STRT = 1+fieldBitWidth SR_TC = 1+fieldBitWidth SR_TIF = 1+fieldBitWidth SR_TXE = 1+fieldBitWidth SR_UDR = 1+fieldBitWidth SR_UIF = 1+fieldBitWidth SR_WRPRTERR = 1+fieldBitWidth SR1_ADD10 = 1+fieldBitWidth SR1_ADDR = 1+fieldBitWidth SR1_AF = 1+fieldBitWidth SR1_ARLO = 1+fieldBitWidth SR1_BERR = 1+fieldBitWidth SR1_BTF = 1+fieldBitWidth SR1_OVR = 1+fieldBitWidth SR1_PECERR = 1+fieldBitWidth SR1_RxNE = 1+fieldBitWidth SR1_SB = 1+fieldBitWidth SR1_SMBALERT = 1+fieldBitWidth SR1_STOPF = 1+fieldBitWidth SR1_TIMEOUT = 1+fieldBitWidth SR1_TxE = 1+fieldBitWidth SR2_BUSY = 1+fieldBitWidth SR2_DUALF = 1+fieldBitWidth SR2_FEMPT = 1+fieldBitWidth SR2_GENCALL = 1+fieldBitWidth SR2_IFEN = 1+fieldBitWidth SR2_IFS = 1+fieldBitWidth SR2_ILEN = 1+fieldBitWidth SR2_ILS = 1+fieldBitWidth SR2_IREN = 1+fieldBitWidth SR2_IRS = 1+fieldBitWidth SR2_MSL = 1+fieldBitWidth SR2_PEC = 8+fieldBitWidth SR2_SMBDEFAULT = 1+fieldBitWidth SR2_SMBHOST = 1+fieldBitWidth SR2_TRA = 1+fieldBitWidth SR3_FEMPT = 1+fieldBitWidth SR3_IFEN = 1+fieldBitWidth SR3_IFS = 1+fieldBitWidth SR3_ILEN = 1+fieldBitWidth SR3_ILS = 1+fieldBitWidth SR3_IREN = 1+fieldBitWidth SR3_IRS = 1+fieldBitWidth SR4_FEMPT = 1+fieldBitWidth SR4_IFEN = 1+fieldBitWidth SR4_IFS = 1+fieldBitWidth SR4_ILEN = 1+fieldBitWidth SR4_ILS = 1+fieldBitWidth SR4_IREN = 1+fieldBitWidth SR4_IRS = 1+fieldBitWidth STA_CCRCFAIL = 1+fieldBitWidth STA_CEATAEND = 1+fieldBitWidth STA_CMDACT = 1+fieldBitWidth STA_CMDREND = 1+fieldBitWidth STA_CMDSENT = 1+fieldBitWidth STA_CTIMEOUT = 1+fieldBitWidth STA_DATAEND = 1+fieldBitWidth STA_DBCKEND = 1+fieldBitWidth STA_DCRCFAIL = 1+fieldBitWidth STA_DTIMEOUT = 1+fieldBitWidth STA_RXACT = 1+fieldBitWidth STA_RXDAVL = 1+fieldBitWidth STA_RXFIFOE = 1+fieldBitWidth STA_RXFIFOF = 1+fieldBitWidth STA_RXFIFOHF = 1+fieldBitWidth STA_RXOVERR = 1+fieldBitWidth STA_SDIOIT = 1+fieldBitWidth STA_STBITERR = 1+fieldBitWidth STA_TXACT = 1+fieldBitWidth STA_TXDAVL = 1+fieldBitWidth STA_TXFIFOE = 1+fieldBitWidth STA_TXFIFOF = 1+fieldBitWidth STA_TXFIFOHE = 1+fieldBitWidth STA_TXUNDERR = 1+fieldBitWidth STIR_INTID = 9+fieldBitWidth SWIER_SWIER0 = 1+fieldBitWidth SWIER_SWIER1 = 1+fieldBitWidth SWIER_SWIER10 = 1+fieldBitWidth SWIER_SWIER11 = 1+fieldBitWidth SWIER_SWIER12 = 1+fieldBitWidth SWIER_SWIER13 = 1+fieldBitWidth SWIER_SWIER14 = 1+fieldBitWidth SWIER_SWIER15 = 1+fieldBitWidth SWIER_SWIER16 = 1+fieldBitWidth SWIER_SWIER17 = 1+fieldBitWidth SWIER_SWIER18 = 1+fieldBitWidth SWIER_SWIER2 = 1+fieldBitWidth SWIER_SWIER3 = 1+fieldBitWidth SWIER_SWIER4 = 1+fieldBitWidth SWIER_SWIER5 = 1+fieldBitWidth SWIER_SWIER6 = 1+fieldBitWidth SWIER_SWIER7 = 1+fieldBitWidth SWIER_SWIER8 = 1+fieldBitWidth SWIER_SWIER9 = 1+fieldBitWidth SWTRIGR_SWTRIG1 = 1+fieldBitWidth SWTRIGR_SWTRIG2 = 1+fieldBitWidth TRISE_TRISE = 6+fieldBitWidth TXCRCR_TxCRC = 16+fieldBitWidth WRPR_WRP = 32