packages feed

ForSyDe (empty) → 3.0

raw patch · 138 files changed

+33170/−0 lines, 138 filesdep +basedep +containersdep +directorybuild-type:Customsetup-changedbinary-added

Dependencies added: base, containers, directory, filepath, mtl, old-time, packedstring, parameterized-data, pretty, process, random, regex-posix, template-haskell, type-level

Files

+ ForSyDe.cabal view
@@ -0,0 +1,182 @@+name:           ForSyDe+version:        3.0+cabal-version:  >= 1.2+build-type:     Custom+license:        BSD3+license-file:   LICENSE+author:         SAM group, KTH/ICT/ECS+copyright:      Copyright (c) 2003-2008 SAM group, KTH/ICT/ECS+maintainer:     forsyde-dev@ict.kth.se+homepage:       http://www.ict.kth.se/org/ict/ecs/sam/projects/forsyde/www/+stability:      alpha+synopsis:       + ForSyDe's Haskell-embedded Domain Specific Language.+description: + The ForSyDe (Formal System Design) methodology has been developed with the objective to move system design to a higher level of abstraction and to bridge the abstraction gap by transformational design refinement. + + This library provides ForSyDe's implementation as a Haskell-embedded Domain Specific Language (DSL). For more information, please see ForSyDe's website: <http://www.ict.kth.se/org/ict/ecs/sam/projects/forsyde/www/>.+category:       Language+tested-with:    GHC==6.8.1, GHC==6.8.2+data-files:     lib/forsyde.vhd+-- In order to include all this files with sdist+extra-source-files: LICENSE,+                    README,+                    INSTALL,+                    doc/www/files/tutorial/tutorial.pdf,+                    doc/www/files/tutorial/tutorial.html,+                    doc/www/files/tutorial/fptools.css,+                    doc/www/files/tutorial/figures/SeqAddFour.svg+                    doc/www/files/tutorial/figures/VHDLTree.svg,+                    doc/www/files/tutorial/figures/compflow.svg,+                    doc/www/files/tutorial/figures/delaySY.svg,+                    doc/www/files/tutorial/figures/encoder.svg,+                    doc/www/files/tutorial/figures/fullAdderMealy.svg,+                    doc/www/files/tutorial/figures/fullAdderMoore.svg,+                    doc/www/files/tutorial/figures/layout.png,+                    doc/www/files/tutorial/figures/mapSY.svg,+                    doc/www/files/tutorial/figures/piecewise_sin.svg,+                    doc/www/files/tutorial/figures/portConstraints1.png,+                    doc/www/files/tutorial/figures/portConstraints2.png,+                    doc/www/files/tutorial/figures/processbox.svg,+                    doc/www/files/tutorial/figures/processcons.svg,+                    doc/www/files/tutorial/figures/processfun.svg,+                    doc/www/files/tutorial/figures/sourceSY.svg,+                    doc/www/files/tutorial/figures/sourceSY_counterProc1.svg,+                    doc/www/files/tutorial/figures/sourceSY_counterProc2.svg,+                    examples/ALU.hs,+                    examples/ALU_Shallow.hs,+                    examples/BitVector.hs,+                    examples/ButtonEncoder.hs,+                    examples/CarrySelectAdder.hs,+                    examples/Counter.hs,+                    examples/DeepShallow.hs,+                    examples/LFSR.hs,+                    examples/Multiplexer.hs,+                    examples/Multiplexer_FSVector.hs,+                    examples/Null.hs,+                    examples/ParAddFour.hs,+                    examples/SeqAddFour.hs,+                    examples/ZipTwist.hs,+                    examples/Equalizer_Shallow/README,+                    examples/Equalizer_Shallow/AudioAnalyzer.lhs,+                    examples/Equalizer_Shallow/AudioFilter.lhs,+                    examples/Equalizer_Shallow/ButtonControl.lhs,+                    examples/Equalizer_Shallow/DistortionControl.lhs,+                    examples/Equalizer_Shallow/Equalizer.lhs,+                    examples/Equalizer_Shallow/EqualizerTypes.lhs,+                    examples/Equalizer_Shallow/Test/AudioIn.mat,+                    examples/Equalizer_Shallow/TestAnalyzer.lhs,+                    examples/Equalizer_Shallow/TestButtonControl.lhs,+                    examples/Equalizer_Shallow/TestDFT.lhs,+                    examples/Equalizer_Shallow/TestDistortionControl.lhs,+                    examples/Equalizer_Shallow/TestEqualizer.lhs,+                    examples/Equalizer_Shallow/TestFilter.lhs,+                    examples/Equalizer_Shallow/TestFIR.lhs,+                    tests/Main.hs,+                    tests/Install.hs,+                    tests/properties/Main.hs,+                    tests/properties/Shallow/SynchronousMoC.hs,+                    tests/properties/Shallow.hs,+                    tests/properties/VHDLBackend.hs,+-- due to a bug in cabal 1.2, sdist does not include hs-boot files+                    src/ForSyDe/Backend/VHDL/GlobalNameTable.hs-boot,+                    src/ForSyDe/System/SysDef.hs-boot+++Library+  build-depends:   type-level,+                   parameterized-data,+                   containers,+                   packedstring,+                   base, +                   regex-posix, +                   mtl, +                   pretty, +                   template-haskell > 2.0,+                   process,+                   directory,+                   filepath,+                   old-time,+                   random++  hs-source-dirs:  src, dist/build/autogen+  exposed-modules: Language.Haskell.TH.Lift,+                   Language.Haskell.TH.LiftInstances,+                   ForSyDe,+                   ForSyDe.Ids,+                   ForSyDe.System,+                   ForSyDe.AbsentExt,+                   ForSyDe.Bit,+                   ForSyDe.DFT,+                   ForSyDe.FIR,+                   ForSyDe.Signal,+                   ForSyDe.Process,+                   ForSyDe.Process.SynchProc,+                   ForSyDe.Backend,+                   ForSyDe.Backend.Simulate,+                   ForSyDe.Backend.VHDL,+                   ForSyDe.Backend.GraphML,+                   ForSyDe.Shallow,+                   ForSyDe.Shallow.AbsentExt,+                   ForSyDe.Shallow.MoCLib,+                   ForSyDe.Shallow.AdaptivityLib,+                   ForSyDe.Shallow.PolyArith,+                   ForSyDe.Shallow.BitVector,+                   ForSyDe.Shallow.Queue,+                   ForSyDe.Shallow.CTLib,+                   ForSyDe.Shallow.Signal,+                   ForSyDe.Shallow.CoreLib,+                   ForSyDe.Shallow.StochasticLib,+                   ForSyDe.Shallow.DFT,+                   ForSyDe.Shallow.SynchronousLib,+                   ForSyDe.Shallow.DomainInterfaces,+                   ForSyDe.Shallow.SynchronousProcessLib,+                   ForSyDe.Shallow.FIR,+                   ForSyDe.Shallow.UntimedLib,+                   ForSyDe.Shallow.FilterLib,+                   ForSyDe.Shallow.UtilityLib,+                   ForSyDe.Shallow.Gaussian,+                   ForSyDe.Shallow.Vector,+                   ForSyDe.Shallow.Memory++ +  other-modules:   Paths_ForSyDe,+                   Language.Haskell.TH.TypeLib,+                   Data.Typeable.TypeRepLib,+                   Data.Traversable.GenericZipWith,+                   ForSyDe.Config,+                   ForSyDe.ForSyDeErr,+                   ForSyDe.Netlist,+                   ForSyDe.Netlist.Traverse,+                   ForSyDe.OSharing,+                   ForSyDe.OSharing.UDynamic,+                   ForSyDe.System.SysFun,+                   ForSyDe.System.SysFun.Instances,+                   ForSyDe.System.SysDef,+                   ForSyDe.System.Instantiate,+                   ForSyDe.Process.ProcFun,+                   ForSyDe.Process.ProcVal, +                   ForSyDe.Process.ProcType,+                   ForSyDe.Process.ProcType.Instances,+                   ForSyDe.Backend.Ppr,+                   ForSyDe.Backend.VHDL.GlobalNameTable,+                   ForSyDe.Backend.VHDL.AST,+                   ForSyDe.Backend.VHDL.Ppr,+                   ForSyDe.Backend.VHDL.Constants,+                   ForSyDe.Backend.VHDL.FileIO,+                   ForSyDe.Backend.VHDL.Traverse,+                   ForSyDe.Backend.VHDL.Traverse.VHDLM,+                   ForSyDe.Backend.VHDL.Translate,+                   ForSyDe.Backend.VHDL.Generate,+                   ForSyDe.Backend.VHDL.TestBench,+                   ForSyDe.Backend.VHDL.Quartus,+                   ForSyDe.Backend.VHDL.Modelsim,+                   ForSyDe.Backend.GraphML.AST,+                   ForSyDe.Backend.GraphML.Ppr,+                   ForSyDe.Backend.GraphML.FileIO,+                   ForSyDe.Backend.GraphML.Traverse,+                   ForSyDe.Backend.GraphML.Traverse.GraphMLM+                     +++  ghc-options:	-Wall -fno-warn-name-shadowing -fno-warn-orphans
+ INSTALL view
@@ -0,0 +1,29 @@+DEPENDENCIES+ + ForSyDe depends on GHC >= 6.8.2 due to the use of numerous extensions,+ namely Template Haskell (TH).++ It depends on the type-level and parameterized-data packages and some+ others normally bundled with GHC distributions.++INSTALLATION++See http://www.haskell.org/haskellwiki/Cabal/How_to_install_a_Cabal_package++Here is a summary on how to install ForSyDe manually:++To install globally, for the whole system (requires admin permissions):++$ ./Setup.hs configure+$ ./Setup.hs build+$ ./Setup.hs haddock # generate documentation, optional, +                     # requires Haddock > 2.0 due to the use of TH+$ sudo ./Setup.hs install++To install locally and just for your own user:++$ ./Setup.hs configure --user --prefix=The/selected/local/directory+$ ./Setup.hs build+$ ./Setup.hs haddock  # generate documentation, optional, +                      # requires Haddock > 2.0 due to the use of TH+$ ./Setup.hs install
+ LICENSE view
@@ -0,0 +1,26 @@+ Copyright (c) 2003-2008, SAM Group at the School of Information and + Communication Technology, (Royal Institute of Technology, Stockholm, Sweden)++ All rights reserved.++ Redistribution and use in source and binary forms, with or without+ modification, are permitted provided that the following conditions are met:+     * Redistributions of source code must retain the above copyright+       notice, this list of conditions and the following disclaimer.+     * Redistributions in binary form must reproduce the above copyright+       notice, this list of conditions and the following disclaimer in the+       documentation and/or other materials provided with the distribution.+     * Neither the name of the SAM Group nor the+       names of its contributors may be used to endorse or promote products+       derived from this software without specific prior written permission.++ THIS SOFTWARE IS PROVIDED BY THE SAM GROUP ``AS IS'' AND ANY+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE+ DISCLAIMED. IN NO EVENT SHALL The ForSyDe TEAM BE LIABLE FOR ANY+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ README view
@@ -0,0 +1,20 @@+ ForSyDe's Haskell-embedded Domain Specific Language.+ ====================================================++DESCRIPTION++ The ForSyDe (Formal System Design) methodology has been developed+ with the objective to move system design to a higher level of+ abstraction and to bridge the abstraction gap by transformational+ design refinement.+ + This library provides ForSyDe's implementation as a Haskell-embedded+ Domain Specific Language (DSL). ++ For more information, please see ForSyDe's website:+ <http://www.ict.kth.se/org/ict/ecs/sam/projects/forsyde/www/>.+++INSTALLATION++ For information on how to install ForSyDe see the INSTALL file.
+ Setup.hs view
@@ -0,0 +1,115 @@+#! /usr/bin/env runhaskell+module Main (main) where++import Control.Monad (liftM, when)+import Data.List (intersperse)+import Distribution.Simple+import Distribution.Simple.Setup+import Distribution.Simple.LocalBuildInfo+import Distribution.PackageDescription+import System.Process+import System.Exit+import System.Directory+import System.FilePath++main :: IO ()+main = defaultMainWithHooks simpleUserHooks{runTests=forsydeTests,+                                            postInst=forsydePostInst,+                                            postCopy=forsydePostCopy}++forsydeTests :: Args -> Bool -> PackageDescription -> LocalBuildInfo -> IO ()+forsydeTests _ _ _ _ = do +  e <- runCommandMsg "runghc" +              ["-itests/properties", "-iexamples", "tests/properties/Main.hs"] +  when (not e) exitFailure++forsydePostInst :: Args -> InstallFlags -> PackageDescription -> +                   LocalBuildInfo -> IO () +forsydePostInst _ _  = compile_forsyde_vhd NoCopyDest++forsydePostCopy :: Args -> CopyFlags -> PackageDescription -> +                   LocalBuildInfo -> IO ()+forsydePostCopy _ cf  = compile_forsyde_vhd (copyDest cf)+++-- NOTE: Most of this code is duplicated from ForSyDe.Backend.VHDL.Modelsim,+--       however, it allows Setup.hs to be selfcontained++-- Compile forsyde.vhd if possible, showing what's going on to the end user+compile_forsyde_vhd :: CopyDest -> PackageDescription -> LocalBuildInfo +                    -> IO ()+compile_forsyde_vhd cd pd lbi = do+    putStrLn "Compiling ForSyDe's VHDL library with Modelsim ..." +    (ifNot isModelsimInstalled  +           (modelsimError "Modelsim executables could not be found.")) <&&>+     (ifNot (do_compile_forsyde_vhd forsyde_vhd_dir)+            ( modelsimError "Compilation failed.")) <&&>+     (putStrLn "Compilation succeded." >> return True)                        +    return ()+ where +   forsyde_vhd_dir = (datadir $ absoluteInstallDirs pd lbi cd) </> +                     "lib"+   modelsimError err = putStrLn $ +    "Error: " ++ err ++ "\n" +++    "       ForSyDe will work, but you will not be able to automatically\n" +++    "       simulate the ForSyDe-generated VHDL models with Modelsim\n" +++    "       (see function ForSyDe.Backend.VHDL.writeAndSimulateVHDL).\n\n" +++    "       In order to fix this, make sure that the Modelsim executables " ++ +    "       can be found in PATH and reinstall ForSyDe"++-- Look for modelsim executables+isModelsimInstalled :: IO Bool+isModelsimInstalled =  executablePresent "vlib" <&&> +                       executablePresent "vmap" <&&> +                       executablePresent "vcom"+ where executablePresent = (liftM (maybe False (\_-> True))) .findExecutable+ +-- Create a modelsim library for forsyde.vhd +-- in the same directory in which forsyde.vhd was copied+do_compile_forsyde_vhd :: FilePath -- ^ absolute directory  which +                                   --   forsyde.vhd was copied into +                      -> IO Bool+do_compile_forsyde_vhd dir = + (runCommandMsg "vlib" [dir </> "modelsim"])            <&&> + (runCommandMsg+         "vcom" ["-93", "-quiet", "-nologo", "-work", dir </> "modelsim", +                 dir </> "forsyde.vhd"])+ where runWait :: String -> FilePath -> [String] -> IO Bool+       runWait msg proc args = do+           putStrLn msg +           h <- runProcess proc args (Just dir) Nothing Nothing Nothing Nothing+           code <- waitForProcess h+           return $ code == ExitSuccess ++-- | run a command showing what's being run+runCommandMsg :: String -- ^ Command to execute +              -> [String] -- ^ Command arguments+              -> IO Bool+runCommandMsg command args = runWait msg command args+ where msg = "Running: " ++ command ++ " " ++ (concat $ intersperse " " args)+++-- | Run a process, previously announcing a message and waiting for it+--   to finnish its execution.+runWait :: String -- ^ message to show+        -> FilePath -- ^ command to execute +        -> [String] -- ^ command arguments+        -> IO Bool -- ^ Did the execution end succesfully?+runWait msg proc args = do+           putStrLn msg +           h <- runProcess proc args Nothing Nothing Nothing Nothing Nothing+           code <- waitForProcess h+           return $ code == ExitSuccess +++-- | short-circuit and for monads+(<&&>) :: Monad m => m Bool -> m Bool -> m Bool+x <&&> y = do p <- x+              if p then y else return False++-- | execute an action when the argument is False+--   and return the boolean value+ifNot :: Monad m => m Bool -> m () -> m Bool+ifNot x a = do p <- x+               when (not p) a+               return p
+ dist/build/autogen/Paths_ForSyDe.hs view
@@ -0,0 +1,3 @@+-- Phony file to hush HackageDB, see http://groups.google.com/group/fa.haskell/browse_thread/thread/58994ec169aba9d0/ebcaf29a3b56c0dc?lnk=raot+-- The solution is simply to require Cabal >= 1.4 once it is included with GHC+-- and which allows to remove Paths_ForSyDe from ForSyDe.cabal
+ doc/www/files/tutorial/figures/SeqAddFour.svg view
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kEnFToWYScQoGpCR8SISb9m0ROo0AEGTVgTMutuBC1A4Yi9ZEDiiQsEcc7L9+nAlhr+a3f+i1+53d+B+89xhj27NkzJlB1tl0zdDX5cjeBv5d1LwscGENGqQyWn2uhG3Wvk8mExjWEELh+/RpvvP46L774PC88/xyvvvodLt/YYLr7QR49+3E+/jf/K/7BL3yeJ3/qYQ7thRaJnfMZzDbgVg8hQApyMa01dJMGYzUxNVmEUkKYARtFaawBTCbFhTsPSWJ3TCLUGPW8fSamQPBF4IkYGZM/aw1NY3HGYqzFObDG0rqMdw6SvGdD8TYRNMwJG+yIvucSK3zz9edFh7gHKtg5xxe/+EW+/OUvj0na8lEXf4oQ62z/vdx57fKLYsAiYSsuvI7dyy69Jn/6+ZzrN27yndde4avPfoUXX3yRV7/zOldvbLLrwHE+9LHP8jOf/VU+9Yu/xJnHYL/mTB7YTDDbgvlck+nq4mTNxcoFy1kuco6QE0QktS7CijGRM6PlxpiIauXRJ2JKhJCIIeHVvYecCDFjKoFbawTzG7BOHgskNBmygc5BSIZrecI85ZI/4mMEs7MzanvDc3H9AH/4eYEfP9IDGGP45Cc/ye/93u/teL7G/jHGMRwU6FcXgu5m3ctWX1fA3qsMXPPrk8lEk9AZ598W/P3881/jpZe+xfffvsjteeDAw+f46Cc/zxf/zi/xM3/tGR57FPYrbJoB28CNHoIXC0eSbSYt5HYh9DFGS8glG/UGGrcx4JK69JwJUUJDiJmYIjGIlXsfCCERQiTERIxJEkUyJgv0W2ksGItrVNAqA6veJlF5dFPCfcbT0CNJnishIrlF9qdHtJFhvvj5RyqAtZYvfelLOwRfFAOkqWF7e3tMAmsFWLb8OgcAdljzcgyvM/jCCwBsbW7y9ltv8vUXnuerz36Fl771Km+98w7R7ebkR3+epz/3n/Gbn/oFPv4zhzm5G3arNcyBrQyXAT9ASmhAFi/pGvm5CBykjpKz/G3OQFKBK57KSTxAVGHnGPFJ4vcQI3GIhCAx3PtAiAmSYHdMxmJxnVo6FdmjiWHJ5UooN8bgsiSK0WRsNqKUOeNzBNPhUhhpfxq0IKBaECOta5iv3IcC7N27l8997nOj8GuOv+97tre3x47UYvUF/xeXXmPsUhGriR5jjJAfVqxAUENDSomNrS1ef+01nvvan/DVZ5/l1e98h+9+703SZDePPfUL/Pxv/3f8w8/+dT7+sYbjQKPCmwHbGa4gtLiiISyS1JWs3FS/y3Eh8JhEECmDTeBVAWIS6w9eYroPYskhJsKg1h0Sgy/Kr32AGFprsY2RHMGpwBPkHZ9iEZWTunmriCHlkmvoe5eiVswkZ8ltJBsRd1axJ6tqFCEZi7eZvQ/chwKANH4UDSxsX9/3zOdz+r5nNpsxm81GS/fej8Iurrxm2JpGhFsqY9Y1NI0jhsTt27d45bVX+eY3X+Yr/+L/5ZVXX+H6xpzcPMC5T/5bfO53/wFPP/NJPvOpvZxg5EsIGbYQSy+Eh3pnuur7ctQoqVz6WEwuLR5D0BgfRDFCkO+HEPE+asIWReA+qLcQoTfOQitu3NrRX498DxFSowLGKPYXDqAkljGp8FMi5kyKiRwSQ86kIeFTxuVEnlrcZEIMdjwvR2S0fwchgUsN3x/uUwHKUQvde898Ph8HMgrDNplMRosvyVlRnpqFs9ayvbXFjRs3+cFbb/P888/x7LPP8torr3H+4gX2PXSOj/3S3+B3fue/5+c+92Ge3Av7qnQ1q8D7Soh6nuNJFYEXZYjVz1UEGMm3FFXISYQ+DPI+wwDRw+AzPsXR0oeYyEFgHEDbNMLll/d3Ep9NssICpqwJZNakriiLvI8ApQUkTCnjQ4SMepWoz5dQnDHG0jWW3DRsZkt0JX5Bto6WyFgj6jN2V8e7L74PBdja2qLv+xGaGWPGmjssunCKsIvrL14g58zm5ibvnH+bb7/8LZ79kz/mT5/9Y86/e40+NRw49lN86Jm/xt/97X/Cp37uYzx9GPZWAk9ZkrZS5Sx5jtWTqC18GdYUgTfs9A5Bn4+psu4E3kueEAL4AGFIEtNDIo2JG7TWQleUO49vlg3q+g0Z4QuabMTDpGLtmT5mbMpK6GRC1LatCN4nUo7EmAlBPIp1hpwMTQvWOpw1OGdpHQTb0AQI5SJYUSinRYFsIeXIFTuB19+HAixj7VEwivWLcpQwUDj+N9/8Ac/+8Vf4ylf+Jc999TnePn+BrXlg70OP8cu/+SX+48//TZ759GGeXIHJksA3VUC+ErBjkdgWj73s2uv4Xqy7KIEm7wRVhhhU0F6tfIAhQRgEyqUk8A2Ev0/WYjotyCCCF+sVT5ABYpZELkFKBlImKGmUciYGhOVLiXmQ5HGIieCFBIoxapHHYJyhmwgUtNYoFDRS1dPKYNcZcjT0NROoFyM6oabkumT8Jrzx5cUVu2cFKO1UtfBzzju8QoF80+mUS5cu8fu//3v8r//0f2E7dpz5qV/mY7/2D/n7v/wrfPwzj/L4CqxWAh8y3FbBlDSofLgVfc5WilB7gCL48nJF4FG/L49hSfCDF8GHAbwSN1H/2drSp2cXULC8V0qSEOakVg7GZmwywuoZKdSklIm5QMIi3MLsRaISPoUYwijJ1DY4Z6Txw1pVBPU0mskWVtGhSapFTqLmaZzCVSlBMA9gl2ZH7psKXkYC3vsdRaCu6/je977H3/2P/kO+/Z3v8at/73/kv/nyf8nHmgW8AugrgY8ngrBwTSXs8lj+taifY6EERejl5/Kavghbvw/q5r3G9BC1LJrkddsWOnMn/tdwS8yaJxhLtoIJBR4mTdQyIWuYCIoQQmbwgvtDFISQvGD/TBG4xU0Aa3FG2D0cwg2MCcXiXHOp9+dMMoaQErhMNs2Yj5TDtYyNoNbEOwR+XwpQ1/6992P2v7m5Sd/35JzZ3t7m7/+nX+Lb3/kev/d/3+ZLvySTQNtZMvRaaCV+F+Fb3tu92+p/aw9QLLy49SL8QZ8PaGz3IsDoNTw4aC1MzAJuGaMZfxG8fp80KSzeJ+fC32tDbJT4Gnxm8AILB0UIPkgZmADZZpyx2Ck0Bfo2Rs9P29cwYPPo0rJldGFZw01CE8cAKQesyfjcYFpwmiSVhHekASKEZElLrWL3XQ0sJeAi/PK1vb3N6uoq/9f/+X/w3Avf4B/9z/+aL/3S+gjNagGb6rE8X8fxZaGPrnfpq1h3yROKpSc98aDakY0It7HQNSpofaMUK6ZPtcomvYCV68nKAcSU5StKZh5ixIeI70XoMWb82LcIzhk605A7iyVLG5dxaD6otXsE9o1vZoRksorflQHESy4RvUJCL/QxMcCuiSR6pQuoZuwD8ve2IT24U573pQAhhBEGzudztre32draGuFgzpk//MP/nSOPfZz/4u99erTG6Q8R8vIM7w5ihkXytmzxYyyvvjKM9KxxMHVAu3iv8tq1heM0WYsLxcgoy6chY0QIJX4PgSEkvCZtYYiiqFk6d1ZXOglrpSl16RxLHcFlDQWuFIoUPWCkJOyz1g+0buATIWdCDEJdZ8kbOjJuLE6wUKpy2EwKkJqGLb/zs9yzAnjvR1dfWL8y41Y6cy+8e5GXX3mNf/K/Pct+/QxdOWnujNt12XpZ6OP7FqGxEHz5eTlEWBhr7+Wow0W5JiWu5tKLUdy+eo0UoA/iRZKHPiRiiAwhamyPQhOnrM0ejSSNRoKEtYVqzqNilFqC9G9lLGLNJBV6gpCFE/RevEpQ2FnYRgUjWGPoWrA4ms4wdY6+sVr4CYyUZ3XkFMl2hee/svP5e1IA7/1I+Rb8P5lMdnTrrK2t8c2vvwDA5//GJ8b/LbRkTb7ULpyl7+usHUQBqP6/xOHlRPFux7Iy1XlEXdwZEUAU3D8MkiD6QecDQiblpBpn6LpGK4NC64qWWYxEe1LOGCuuyKrUamEnkwQK5kzwiaQFJKGRIz5Ip0828j9jGdg5RQcWawyNIgNnYGgMOVTmZIzSwEAAHwJmT0u3tvMa3ZMCtG3L7t27WVlZ0bGlOOYCpQ7QdR3vnH+H/YfPclahxg6Wrbr4dVyvsXmx6vpvayG31fflsRbw3bzIssKlrJadlfDRSqDvpYEiRoghjf+LtXQdGNNILpEAI5aajFq6tn6F7DApjQllYe28YsgcIj6hdHlmCIEUpQ8gpETOaTTexjmhyRtorMU5dVulFFxINyShTLSEBKY2h6AZoINkpa/hjX+1U7b3HAJKbR4Yufx6EULwnrffeZt9+w8x0f8pCVn9NbJv3OkRDDstvFg5LJLGGhKWCwA7Far8fEeiqEWcGKFXK09ePEDS0NE04FrtvS+hoiCBChbm4o9NJllFSIrpx6GXJHE8pAXRE/qAL/0BMY3xqHMWnMM6i8PQtAUd2EVyyCK+ZYCUMc4QsjB9yv9WV0czrBAZgqHLwD+rA+T7bAotjRx1TSAEz/e++10OHz9LGUwZ9KsWfPkqgqzdeQ0DCzTU095xLAt92WuMSADwhdVTijcmhYJC0GEddK18hqxJSkZgoYZxYpYOH3HvWhiyhqxkT0KInhQX7Vt+SAoJI2GI+JzIGuuNMbhWS+A61eMMUg3N5fpYjeVZQo3mEVpMGPsL4yBnbw046wgxY5ezThzJRHGhS8f7goHDMLC5uTkigO3tbXKGS5cu89hn/m0CsIEIv2Tr5TNZdgq7fqzjeVGQWp+XY/oyzbsDCnq1dhVY+T9nwa2ootXkSgUFS2udQSBhAuX3GTuAslp7ULw/aN1/CJHYRyJJ47u8T4vFTg0GJ4JWgduC9XP1GfXkskmL6qIWigIZgnQa+ZzIIWJDJO0TvmXkDYBkFyNC87lh/S7J0n0pQOH9NzY2mM/nowLM5zO2t2Zcv3mdAwePMEcKN+Xta+xfK0Bx6e/F9tWQkOqxuPQaEgYWiVyZhk7ILFwzrWCoWnnSC1Us3Kjl4+R7r/EjwFgl9B4tzgjB0/fayuWjKoM2u1iDM6X8rX3/ijEtjEMZ5RjbwTOLOYjxswlEGWIiR4WAKUv/YMgYIiZBty9AbmkzhFHQMiEagUljFk2i1XHPCpBzHiuCs9lsbAaZzWaE4Lm1cZvtrZ5HTp8TWpVF0lZ/wU7h18/fzbXX7j2z8Chj8lhYOgPGCrtnSxICd4SPqBZnI+QGTFSBK/WbgkLBtKgN9D34mIkhMO+1HJyi8v3SyNJYaCaNNHxobNYRF6IyTIWmdUk9SpSQkICkY9xBWoUZguYMIWkTSiDkjA/CEhirq22alqYxWBzbem0jjGEgW0fOMG+BvXfK9Z4UoJRyNzc3x5hfOICu61hZWeH69Rv0w8DpJ84yASbsxPy1QIpQEotMflnoI5XJzgQyZ7l4VgwNKy1079kDUCeaCUnsIuoqFf9HJYJCrKCgVgd7nxj6MHbwppjBGVrXYBpDbvQccvXOWYicmDMmgbPSumXygvAhaqEoC+5PMSuruGgUDak0mQpj5ZxhtXW4zmCtwzpDZw2uhY0silXnV+j18iGz1k54/cqd8rhnHiDGOPbulfp+af9unOP177xBNg1HTqzsEMRy1r4cx4sLL78rbn1UhCouOEToDWLxJaTckfOw8Ba1QpSkrnD7Pixcu9fiUN8vWL8QhOFzFoxzOAtkO87sSTPnYngjJ3k+Kh1pIkTUyrMojwgkEmImhcg8JOKQyCnRR3mMUYZDrTF0ExF048oOAiiVg9I/aK3DOIPPmZLr9fW5p8jQWc5//87rdE8KUGr7BfqVxs8SApyzXLx4nunabg7uWeD6WuCjAJZ+Vws/poVXMFaxfxF49WHrEFILfJkDqHmIqK8fg5I8XhSg9AOEqLSvZp4NlrYTJ17IHqv8QUYFGgzZGAwJF2HQNq6kLKE0dEhc9zETNGcYCtOno12oJ3DO4roy6GJxSmsanKDFUgO2eTz7xmiTqXMknQeMCAPboylPgj0rju6DooAyE+Cc27HXDxrOn3+btfX97GIBwwr0oxJEQluuVCNiLhYm2lznDqVaCAt4eDf/h7AqAAAgAElEQVRIWGN/2EkoFRg6zEXgXhPFwvGjOUGTFwOTpf8/GsZEMSdJrmwURTIYrM34BDkI2ZODFopCZMiZ2AsqSD7Re20h0+kfkZnB2UaIngaMszisKJWySaY6sVG51YthpHnFGVEo06oCBw0FVq+NhcFC2LxTpu8LBtY9APP5DGMaLrzzDg8cPMIEqf6V0u/o4tXKSu3dWTAtTDVjbdmJEspREMRC56vPwk7FqpPEgFj5ECENktXn8v4GWu0MxuqjsnwR1GWrsK1avQEblJpOogShWHEUS/ZDpA+ygCENKvyYR47fGYNtLa5pcFm7NBotC5dmUIX/DiPhT5UlIV4lAwTpO4gxY7NSxu0KkUaKQl0cXWtE8ptZgG9/+0553rcClKLQzj6AxNtvvcmuAx/Bs2jWTOpeHZJxt06E3thF82ax9GXSx7FT4Mu5xN2gYEIsIqml5yRe01iZnjGSS4kHdeo9FOJlxBOk8j8onFLcH+MCYg4pE+aBvkBALxn7PASil6HObME6S9PAxFqhdY0UckouogFGT9DpPGGWUJWR+kMqP2eSFoWGKHmDDxmTA6Z1rKxAixJEUYpChT7fxjIJ3MEC3rcCbG9vs729zebm5kgAee/p53OuXb3ORz92Eq/Cz0kGLppmJ9mz3PRRHn9YTC8/11ZeQkxABF4Su2Q0d2iF5TOg83klC1eL1hdPTn6f9HVM0tdMigr0MQzgh0QfCvEjhM+QdJwrZ5yzTJwhGZ3bsxU6qNy4VbpRPrMhGe0XTFp0isI35CwDJlIdTIRB5wmzFJ2sNaw4Q2cbjHOEAHZcCdeQCKQAg0LJux33rAB937O5uTkmfvUGkGEYuHbjCuvrh+gQCIi9E+9TPda/q4Vcx3RYxPMaLYz4X8/VNmCanR5FjXz0FIYqmUMtP4s38Jq4hSDP+9IoGrVIFBLDPOCTWHjU2rt10r83NbKzJyOPgGD/KP2Bpc5vgJwTMelGlYTARW3YyF4mi7zXqqBP0hGM8NDZSh7WNR2tk/fqOujalk0iNuu1y2i8laudXMO+ihu5bwUo7N9sNhv3+dTrXN7te2azOac+/DQraP8dd7rw+lhWyKIItcBHSFgJ2zjNH9SdlIQR7uwvKM+V1y6KEOKC9PGpQgHaDj546D0EneWLWs2ztsFNFH6BupadmDuZTA5gnNEkLo9l2jBOA2supS3gIQbmc7HsGFToGvub1uByi+sMjXNYB41R32kMkzYT2kYKWzjJSFF8CIIMWkOshkHq454UoKyCKyig8ALee5qm4d2LFwghc/TRU2jifAc+XyYoynM1RPQa1EtrVjZC3LhGzudubWR1k0lNLNWvj36mnNWyFQ4OWi8oxE8pDecoBR5rHd1UIZiVhUrRgIl5LAZl9QZJewFMECUQpKOdOElInlL2jSEx7wM+ROkY1uESayUhbDvdCm4trtFScAaMtIYLZpTzcgbdFyBdtyk3SA/Y4hqQDbuO3l2299wPUC9OLj0AMUbapuHiu+9imgmPnN6zQ9B3w/+JRQxOirvrVmxjtGDT7oSDy7WD5bBRHmteoeQLAUgehgChFwUY1Np99Q/OyVeZVaxfP+ZFUhmNESrZGlWsNBaKhpBJJLJP9FE2e2z7SOwDPms/X4ikwnk4FXixbmuxjRI91pCywY77gvSjGqvKlwg2E7Ml2bzoeLFFCQRShABvv4ds31c5eMccQIxcu3aVECOtXbj/Ha48a0WuECl60QsSshaaVhLGUkdY5gGKYtUXonxfh44aGchUz0LghfRBE0HX6FQw4x4FUNSQYsUcRskVkpHagdPvQxILD2TSIO3fQyy4PxH6yLzkDVpxssbQto2UgDG4xtI0Wga2BlM4aj0fme00Y1UwaQv62D+YAqEVSjqFDNbobgM5sZAS07UJ/bW7y/K+FaAshSqdwMF7Ll+6wgOHjrDngZ0Dmr6Xi1dgFEjYbJ1k6M6J4LV3U36vj8W117G8juNF6LCz6WPQpo/C9tXNHMZAuY9EPT9hDNrjx0g/2yzWXlrSknIDSZGB9AVmBsX7fi6NosIoRuIQ1HsYJq2DKVgjsNAYN6KTbMFmQ5AIDiZjotE6QSZrFimeKgoyUa4h+ATB41a1ABYNyaQdJxd9pusc//Llu8vzvhSgQL/SDby1tUWcTrl4/m2wDh9hw8LmNuPwQnHdk06FbqFR6FWPedXZf+3Sl8MILCw8AUFdXAji5qNat9GQIi69uiYKDUa3nlXgVj5zUdRxl17QVjGtDPohitB9pPeJ1AcGnfjJ2rzROku7NpXzNaIEMs1jxjJdSWozhmwzttDQCQa06BQhxciQ5T1jiPgY8X0mk4jAmpFQUEitUuXKBfsWyMvGB1OAGgkU4fd9T06J25ubPHT0NE0rrrY1QKexHCF/ai6gfNY6KSzxvUYHdZyP1Vcp2QYlBDIi5KzDHlYVrEzgpliFjSykVEiC+ZMBUxRHFWCsClbIwPtAPwjb52OZ0s2yEawxTKz0+mdjR7e9eM+04B0QZCCGnUlJ6gVkCRNBWcUhSDgJQ8THTA5l1NtiGsO0aYQHmLY0rWMTMQZJF+xIdCQHkwQh3XmrnntWgJQSGxsbOwRfGkNN47h86RLTtWOsAb6F2C4WFZVYfjdIWLJ2WMTwohQj5s8LUiYs9bS3rQpZhz2W2cPyHqZhpHczamlZmb28aCYpnmReEEGfGYZAHyMmZr3AmaZraLSlyOw4MStjYRpuci6j3JYckyaSOiCa0oj/UxAK2WsZOPVRF1KICtnG4FY6WmNpJlIldMZhGlhpMnPTklIhnuR/yo6j5Bv8Lug+SA6wvb1N3/fjOri2bcd9gCsrq8QUefTUh9mFTPSWNKYIH+7E57WA6kQuKQFTmL0suROmUXbPisDrPsJl6FfnCSMHoFl8mf+PGsvjIJg/DtBr3jB43ctnEtkYJo2DiWHFaJOHLmxOMWGMlSFRhXPGWlxeMG8yICrQ0utmsBAyYQj4lBiGslWNkes3VvKGxtZlYAsuY9Al0Vo3cDbjGifeK+SdLhZIVtrc71IGuHcF2LVrF03TjE0gMcbRCwQfuH17g737H6SrBFE3epQYjgoBjbdkxmpaccGZRUY+ooNW+QB+dLNoZjEYk1kIOyOIYFAOwOsoeHHzZS0MQNsa6JoFjVy9fqGSUwaLGxm+pH+QY5JlUUG6ejKZ+SwScmaYBWKWMBJ131+ICecsXWtpWsH5jXO4RjyHsRXxRInnwpFIgmsgJEkhuyCVwJIdWwg5cKAF/vGddQC4jxyg3HyhcAClL31rtsnm5gYHj5zaMb1Tu/kcFzBwjLVp9HBj+bVtJGa3jfAANfFTJ4s1tVwUrBBQNfaPWhTySvgMVf1fp7FB3xcYL3b5TCUhLFNXUfMGMyaK6sp1qKMsc5BETWJ3Pw/jVLBk9VnKvs7STHTJQ+MkYbVunCoa5xfLsWPXoCIgH7EOBmehkSQYWFh/lM+6+R4sILwPGFgvgvTDwI3rt5jNPQ8eOjJe+EK8xAxpWNTeo/rnEredUQvXopFxkkDWXqy29pryLaGjxv0ZydhLs0dZ/OBDqeHLezctTNyCdBJh7oSMMcpnKoMkaIIVSpIYBJL5EAhDpk+RYSbIIAxi6SHkUbmb1tE1BhrZ2dE0riJ7NG4nMYAyB1A2giaAkLXbWZLG6D1DzmQ/0K7tgj0LL2T0/4yF1DXY9ygE3bcClEbQAgdDCFy7comN2zcwXcsmsDVI1py9FlkUrzVOY3dTCd3Jh2ydkh7stPCa5q2TxeLhCulUpoDnw4LOjQmZ8rXS928qStmaymuowAmMxaIY5W/G5FCVNwwQYmbuJTvvveB9EXrcMb/XuoaVFcA4bXgxmGRwJpNcBc9SYUAlgIWweI2gNYMwyH6BxWKqIHlSSExNxqwknPYcjG6jgbgt3+65OwC4PwXw3o8wsEBBaw3Xbt6iXV1n38GHuBVhe0sEYBBI1k7U0jV4twWiKUYvuUIRfmIxTxir5+o2M8+iVBsV/w9xQfa0Tt63QMHCAxT3Pi581De2CWKjuYgqVGkdi1GLQ0NmmA8yCu4leYspSwnWJGzbyPq5VgRusWSbR9o+lJNEmMRI0nMTfz6kKLxDzMSc6OdR8oe5dPsI+SP3F7DG4hrHdM2x1hnMdCINOEYo4JzkIqUOwiyPivC+FSDnPMLAYv2z2Yymabh04QIbt2/JsIOSPE0HnUrUWunNp3AgKgTndiZxRdg1n1+eLx1FfVzEuZFZVFax0wmfO+BmxfiBunizE2EM2iaWku4IUgq599D3QTiAfrGePVlp52o6x6rRVS7GSteQFfwvFcwsHH3OMmCSNYanRET7ASP0OZNLN9GgiyV8lBwjqqFYx9qawzUNbaM7g7RLOFqY5YRJ2mJSLkKUH4Zd7y3be1KAgv/LWHgpB6+vr2MM7N33IA8dWaEzYNYY72JRLHmM3/qNQays2o2ANYuiUE6yMyirUEZhs8gfuqkolnE7PQkskUkl2cwaKvKiNa2PAv8G3RPUB50B8Bk/SJ2jzOfLYkv5AHXPf85pJ7uo72lMJluZEYgJiLINLKQk7WIx4wfPECJ9n8k56pIoBPo5S+sstpUmE+taRQZl8aa0m1uT6RsnHiZFguyWAaS8bCcTHjz0ARWgbP0CuYt2uUvI3r17uXnzJu3qOgcf0jVsunChsGwLKrJIRC6+QRYb5UEvWlw0ZtR/21glfJzyAM2iSFRzCzXsHLF/ldDFokhJ8oSZWvkwLKw+BkmwcsqYFl3WZCnrW8rURSIrq5dIyZGRQY0hI+1gSTt3QmbIELUL2IdIPxdLj0MmRekHwEmO0K00NMbhOktrHa7RBVRON4oqs1qup2FxjccnNENKyUoTsYPtH3JX+XtSgD179rC+vj4uhSq3h2mahqGfYZWcKMIoY1b1bp1YKoBxYeFo1l1KqSVDbyxYrQ62jeYLdoEK6rpAOe+CCKK+b2ncTFkrgl7eM/Qw79XyS9lcc4euczIRrHnKKPCCuT2kBvGxKWOieACBtjK65YEwJGIMzIeEnyeG4KVSOEhmk9HbvrUN7arDtWX9m6PR0q+xSGtZOUkHprxXEiU0WRZNzFpInSP0Qe5NBBirOwhU2T+QAgDjitf6/rfDMHDhnYscPnmWdYQFLBi7JCJBL1yZzh2JjLyAYdZBu6I8QCP5g+vu3gq+jGiKMhTXm4IIOqlrT0HWo3ktB5cE0LjFvqAxH9E3NBGi0ZpDo9g/6XP6/zFCJOqeHhkdG3rPMETm8zDuC04hkozBOeimDR0NthHrNs7SINs+kzU4l0lVHG9jJhqk0JT03GOqlldEGAbcAxNsI9YeghjOkMHbzOp6w5rjPY/7goF1O3jpCXz7nbeYrJ8hoBx6v+i6yQWSaQpfRrjEvaqFK7XrGonpVum+u/H6tcAL/s+xaulS7D/0mnWr1TuNEZ32DjoV9g5vkhbCLTODWSFI2SISNDz4mAizQJ+hn3tCiPRDFIYv5lFJu9ZiOpkXbJ2VtnALyYjw0amisTCWHUlpZZNhnkXgPsh2Uh8jvSak0cusojORPXs8hqkwkw6CjzSNXoMI19/5MShASmksA89mM+bzOdY6pTxnbAC3t8DPJNkq2bqzigTUnTdWGzFcBQVdVTAq7drLQtd4rrmO4H31KqX9vJR3Sys4HewyIvRSLEoO6ffPi3xhXAePCH1cFxMXcNAPmX7whJjp+8g8RvI80qc0ZrK2a2W+wckKV2PEuo0mg1DlKxnAavKbNNmV+D1EvaFEH5mHSOilAhn84jZ7xlm6qWO1a7GmJWTxUBigc6QgHUkksGVR0wdRgI2NDTY2Nqrt4NsY4xhS4sDDx+l72J6BCXLBJxMlXpQDcAoJneJxoyZulbnKVi1OM/6yqLEgAK9Ucu8ZFzmXJY+oknWtvl5F+CzXJEjiKgt1WEikWGhqr+ggFPwf8X1gPsRxFXwMkuXTGFZdS6MWbY2R+O7KIojF55dJ7aSKnEeFG3wgR00WB4GBvQ/SCu61OTQnHBbXOlZsg5s4WtvQtoaug9TqDuVCUVuwOWEtbAf44+9+QAXY2NjY0Q6+vb2tlPDA1Xff5cynH6KbwOoKuIiuNV1w/HK3SsbW7LHHMSpq0A9vqwtWGDixvp00bVGQ1unsfycbPo1lx5YP8iK5lKxd/j9oIhoHcfseiL0khb2HYcj080iMnr6P8lrGClc/FWTQGKn8ZQy5bOgOQnbkkEhWbkePybKkUlu7Q9KNXynLUoleGMVB2T7K8mhkN7F1Hc4ZJl1D07pxqMVag02wYmB76kg9i0HaqAmxh8lUcqAPpAClDazg4dXVVZqmIfiBRKTp1lkF+o5xyuZuHH5E4rEv6brCwMLDB3W945BmFkWo+/ZcK4J3OmXUKTSwWTyxVQuvCZ+osXCIi8dYSr9K+Awehj6SYiDGhNG58+mKwzjZ1+tcwho3ruGR3QRapLFJEELQRtEUCdGQQpJm0CRVwKEXFlGWSsZxtQzIYigmjt2Nwxpx8RlonZFEMSf1ajKDYJtEbKzMJuo1Tppn+QDZZtYncP7WB1SA1dVVuq5jGAbqu3/evr1B061x8uxHpZGzQDXLuIIdzahR1s1XvEBOmqnDuLuHXJWDG1hZU3jYaXuVq6hl1LoL6xiRca4K8w9q6T7uXAHX95KwxixrXrJW45p2Qmlls50qFIXkceJdoipZTIIMNG9IIeOz3hyqT8y1o2fuI3FIDL020+oFMEamgVdH0kd6ANCBB5sW9DUIBQzgtZRsgDQE+tVOClXIOQcfZHFVgj7B6f3wxgdRgLU1WS5XMv9yd7Dee4aUmervS+PkWF+PSlwU60v6uyxWWdy9MYviUNtVI2UqbNS9G1WKEkqsCj5F+YrqUcqwxxAWTF/fa/6gyV3xTG1j6KaNVCFdlR+giWgSq8pRBIIRTx+9uvGUSIPu+veyNsYHEbqfByF9vN7VvEBBJ0SPbeSewVhp87IFG4u4ZSE1koALQsl63ZLeuyBicmBlbUVKyCwINkrC3IN/j26ge1aAchTrL1zAzetXuX31MhjHnMXoNXkxex/LZG5fkS4of9/tLAcXRFBKtEYTw7JIyVotFqlQSCp4JE8IWrgZBlG0+cDYzJmyNqR2UnJutfxsnYSlrPlHQiw6sYCC2WtNIouXSlEKQvMQiX2mD15Wx/hI6BMeWetKI+RSO+mwraWxBtNYGmPGPka51a8dIScIIkhWXiNrH1tZQiV9BpIk5pxobMI9wNgj0Og1hoaQPA5484fI9L52BJU9wRsbGxhjuHH1Gs10lUNHHmUrwdaWjmMrREvanWIBNGnr2sUMQFPgWVfV/o0KG8ZdvoXuDFHCSG+BYUHv9v2i8cMHxoGTkVk0UixCm1MbI3CwdI+kVtBL48RrlPpBKsgDEXwYIoP3zIdM33tCH5kNeoNLxa22caw4h12V7Z7GOimGWav8uF5PRANM0lvBJWH5vAeIWqAKDPOkiEB6BnNMRCvj46sTx9p0gm0sKMmWfRhzoJAye6a8ZzfQfSnA1tbWCAPn8znGwLXbmyTTkE3m+k24eZsxAxf3usD+rZN369zCjReLrxECsCBlCmsnT41TPCWBK0JPecEbOAOTVc1HSugwO/sA9C3E0jpk7bqSPaVu4IPQxkOUwdD5EOn7oD0AMp8vN3U0NJMGZxxta/U8HE1ThUBKl5Qkc1E3U4y4f0CVSMfGBgkfPgnTGEFWw7aWdm3CrknLZNKytu5YaRpuGscwzzQWBidiNTaQ8g9HAPesAEX4pTlUVsO2XLt0kc3b19me9fgkF7ttJY5jql0+ZUS8uPYsSiA9dBp30e9ZwL3C6Ye0EH5BCrAIJa1+lTbwokejsE1VFdZ4Ps7ga+NK9Lo9VNvAZ3PP0HshYkJW6KZs5dSx6hrh762hNZakRbBS4YREhyWYpD16SZpkiORQFkDLYEmMge0+4Qcv4TMKhreuYbresTpp6DrH6kpLO2noWkPjGiYtuKnl5pWIs4Y8eLnYJpA8ZJ/JP6QQdF8KUCaByl0/27YDEo1r2b1nD7umYNdZzOIXN44m6XX2r0IoQoyKFnJeWB8oJPQLurZxQvK0DUx1pUghmLJjsec/M45xleSocEZ4vSdQUOwftZNoDjPvmc+FeZO/TxgskxWDk2CNNXLvP6MbQoHFrKaFZDIuwJAsXpcehSTdQvMQdEZRyCUfM75PWlKWewK3U8felYZp45iqwNvW0Wrfn8lgkuwa98HiZonOZRKBWPBfygwp4PuE2/1jUIBS/9+1a9d4x5A9e/YwWVnlwSPHOHJcihG2XVhaTvK9L8IvHR9IXmDywgqLoHX6aazAOW0D75zE8q70DWp3Uc3yRRWAQXMABcYlk/dogUihYD/IPYJ9SAxDYPABo0Md05VWSrDOjjdnKodBYmuJOePdvJMUhWQXcSLp7eX6GPA+E+by/XyI2JhIyN2+1tYcbTtlOrV0k5aVlVbzIxGNMRaTRNVKMgryWUNOWj9JuCGzPQTdb5yxITPf2uLBlX0fXAEOHjw4wr+UEn3fs7a2xtUrVxh8oJ3oxa9MLaMdPHERo7MKIaBJlRZadDm31AkcNBNY6cSbtJ32ARgovQ7LrdrF9Y4Fm0IqobDPQz8Xa+/nsvtPuAzRmqZ1TFYaLJZGHJtQ1XHBHhbvlHVT2pAz5DBOKeUcmc/ldeczEXrvg2wS0VHg1jpW25bJXse0a+gmLdOpo2kbJo2VOobi99IYGlEFMxJjTZAkkBAkIXaJXTmx3kZu3vYkA53JzPuMTYm1H9IMcs8KUO76Wd8IOsbIrRvXiN6TTemULSVLdvTrhajZdGAkaYzWAVwnyKBtNWFsNWfQApF1mkBXEh/xOYwrXROMu/78XN8rLBo/pEAl83uNM7RNS+MkHDkNWaiwy2RV0AaMEFkMZyaIunLF+yxbPHrPVi93Pw/zRI9gU2cNE+doViSOT1YczbRlpbU0ttFzNCRkWsgYkA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kEnFToWYScQoGpCR8SISb9m0ROo0AEGTVgTMutuBC1A4Yi9ZEDiiQsEcc7L9+nAlhr+a3f+i1+53d+B+89xhj27NkzJlB1tl0zdDX5cjeBv5d1LwscGENGqQyWn2uhG3Wvk8mExjWEELh+/RpvvP46L774PC88/xyvvvodLt/YYLr7QR49+3E+/jf/K/7BL3yeJ3/qYQ7thRaJnfMZzDbgVg8hQApyMa01dJMGYzUxNVmEUkKYARtFaawBTCbFhTsPSWJ3TCLUGPW8fSamQPBF4IkYGZM/aw1NY3HGYqzFObDG0rqMdw6SvGdD8TYRNMwJG+yIvucSK3zz9edFh7gHKtg5xxe/+EW+/OUvj0na8lEXf4oQ62z/vdx57fKLYsAiYSsuvI7dyy69Jn/6+ZzrN27yndde4avPfoUXX3yRV7/zOldvbLLrwHE+9LHP8jOf/VU+9Yu/xJnHYL/mTB7YTDDbgvlck+nq4mTNxcoFy1kuco6QE0QktS7CijGRM6PlxpiIauXRJ2JKhJCIIeHVvYecCDFjKoFbawTzG7BOHgskNBmygc5BSIZrecI85ZI/4mMEs7MzanvDc3H9AH/4eYEfP9IDGGP45Cc/ye/93u/teL7G/jHGMRwU6FcXgu5m3ctWX1fA3qsMXPPrk8lEk9AZ598W/P3881/jpZe+xfffvsjteeDAw+f46Cc/zxf/zi/xM3/tGR57FPYrbJoB28CNHoIXC0eSbSYt5HYh9DFGS8glG/UGGrcx4JK69JwJUUJDiJmYIjGIlXsfCCERQiTERIxJEkUyJgv0W2ksGItrVNAqA6veJlF5dFPCfcbT0CNJnishIrlF9qdHtJFhvvj5RyqAtZYvfelLOwRfFAOkqWF7e3tMAmsFWLb8OgcAdljzcgyvM/jCCwBsbW7y9ltv8vUXnuerz36Fl771Km+98w7R7ebkR3+epz/3n/Gbn/oFPv4zhzm5G3arNcyBrQyXAT9ASmhAFi/pGvm5CBykjpKz/G3OQFKBK57KSTxAVGHnGPFJ4vcQI3GIhCAx3PtAiAmSYHdMxmJxnVo6FdmjiWHJ5UooN8bgsiSK0WRsNqKUOeNzBNPhUhhpfxq0IKBaECOta5iv3IcC7N27l8997nOj8GuOv+97tre3x47UYvUF/xeXXmPsUhGriR5jjJAfVqxAUENDSomNrS1ef+01nvvan/DVZ5/l1e98h+9+703SZDePPfUL/Pxv/3f8w8/+dT7+sYbjQKPCmwHbGa4gtLiiISyS1JWs3FS/y3Eh8JhEECmDTeBVAWIS6w9eYroPYskhJsKg1h0Sgy/Kr32AGFprsY2RHMGpwBPkHZ9iEZWTunmriCHlkmvoe5eiVswkZ8ltJBsRd1axJ6tqFCEZi7eZvQ/chwKANH4UDSxsX9/3zOdz+r5nNpsxm81GS/fej8Iurrxm2JpGhFsqY9Y1NI0jhsTt27d45bVX+eY3X+Yr/+L/5ZVXX+H6xpzcPMC5T/5bfO53/wFPP/NJPvOpvZxg5EsIGbYQSy+Eh3pnuur7ctQoqVz6WEwuLR5D0BgfRDFCkO+HEPE+asIWReA+qLcQoTfOQitu3NrRX498DxFSowLGKPYXDqAkljGp8FMi5kyKiRwSQ86kIeFTxuVEnlrcZEIMdjwvR2S0fwchgUsN3x/uUwHKUQvde898Ph8HMgrDNplMRosvyVlRnpqFs9ayvbXFjRs3+cFbb/P888/x7LPP8torr3H+4gX2PXSOj/3S3+B3fue/5+c+92Ge3Av7qnQ1q8D7Soh6nuNJFYEXZYjVz1UEGMm3FFXISYQ+DPI+wwDRw+AzPsXR0oeYyEFgHEDbNMLll/d3Ep9NssICpqwJZNakriiLvI8ApQUkTCnjQ4SMepWoz5dQnDHG0jWW3DRsZkt0JX5Bto6WyFgj6jN2V8e7L74PBdja2qLv+xGaGWPGmjssunCKsIvrL14g58zm5ibvnH+bb7/8LZ79kz/mT5/9Y86/e40+NRw49lN86Jm/xt/97X/Cp37uYzx9GPZWAk9ZkrZS5Sx5jtWTqC18GdYUgTfs9A5Bn4+psu4E3kueEAL4AGFIEtNDIo2JG7TWQleUO49vlg3q+g0Z4QuabMTDpGLtmT5mbMpK6GRC1LatCN4nUo7EmAlBPIp1hpwMTQvWOpw1OGdpHQTb0AQI5SJYUSinRYFsIeXIFTuB19+HAixj7VEwivWLcpQwUDj+N9/8Ac/+8Vf4ylf+Jc999TnePn+BrXlg70OP8cu/+SX+48//TZ759GGeXIHJksA3VUC+ErBjkdgWj73s2uv4Xqy7KIEm7wRVhhhU0F6tfIAhQRgEyqUk8A2Ev0/WYjotyCCCF+sVT5ABYpZELkFKBlImKGmUciYGhOVLiXmQ5HGIieCFBIoxapHHYJyhmwgUtNYoFDRS1dPKYNcZcjT0NROoFyM6oabkumT8Jrzx5cUVu2cFKO1UtfBzzju8QoF80+mUS5cu8fu//3v8r//0f2E7dpz5qV/mY7/2D/n7v/wrfPwzj/L4CqxWAh8y3FbBlDSofLgVfc5WilB7gCL48nJF4FG/L49hSfCDF8GHAbwSN1H/2drSp2cXULC8V0qSEOakVg7GZmwywuoZKdSklIm5QMIi3MLsRaISPoUYwijJ1DY4Z6Txw1pVBPU0mskWVtGhSapFTqLmaZzCVSlBMA9gl2ZH7psKXkYC3vsdRaCu6/je977H3/2P/kO+/Z3v8at/73/kv/nyf8nHmgW8AugrgY8ngrBwTSXs8lj+taifY6EERejl5/Kavghbvw/q5r3G9BC1LJrkddsWOnMn/tdwS8yaJxhLtoIJBR4mTdQyIWuYCIoQQmbwgvtDFISQvGD/TBG4xU0Aa3FG2D0cwg2MCcXiXHOp9+dMMoaQErhMNs2Yj5TDtYyNoNbEOwR+XwpQ1/6992P2v7m5Sd/35JzZ3t7m7/+nX+Lb3/kev/d/3+ZLvySTQNtZMvRaaCV+F+Fb3tu92+p/aw9QLLy49SL8QZ8PaGz3IsDoNTw4aC1MzAJuGaMZfxG8fp80KSzeJ+fC32tDbJT4Gnxm8AILB0UIPkgZmADZZpyx2Ck0Bfo2Rs9P29cwYPPo0rJldGFZw01CE8cAKQesyfjcYFpwmiSVhHekASKEZElLrWL3XQ0sJeAi/PK1vb3N6uoq/9f/+X/w3Avf4B/9z/+aL/3S+gjNagGb6rE8X8fxZaGPrnfpq1h3yROKpSc98aDakY0It7HQNSpofaMUK6ZPtcomvYCV68nKAcSU5StKZh5ixIeI70XoMWb82LcIzhk605A7iyVLG5dxaD6otXsE9o1vZoRksorflQHESy4RvUJCL/QxMcCuiSR6pQuoZuwD8ve2IT24U573pQAhhBEGzudztre32draGuFgzpk//MP/nSOPfZz/4u99erTG6Q8R8vIM7w5ihkXytmzxYyyvvjKM9KxxMHVAu3iv8tq1heM0WYsLxcgoy6chY0QIJX4PgSEkvCZtYYiiqFk6d1ZXOglrpSl16RxLHcFlDQWuFIoUPWCkJOyz1g+0buATIWdCDEJdZ8kbOjJuLE6wUKpy2EwKkJqGLb/zs9yzAnjvR1dfWL8y41Y6cy+8e5GXX3mNf/K/Pct+/QxdOWnujNt12XpZ6OP7FqGxEHz5eTlEWBhr7+Wow0W5JiWu5tKLUdy+eo0UoA/iRZKHPiRiiAwhamyPQhOnrM0ejSSNRoKEtYVqzqNilFqC9G9lLGLNJBV6gpCFE/RevEpQ2FnYRgUjWGPoWrA4ms4wdY6+sVr4CYyUZ3XkFMl2hee/svP5e1IA7/1I+Rb8P5lMdnTrrK2t8c2vvwDA5//GJ8b/LbRkTb7ULpyl7+usHUQBqP6/xOHlRPFux7Iy1XlEXdwZEUAU3D8MkiD6QecDQiblpBpn6LpGK4NC64qWWYxEe1LOGCuuyKrUamEnkwQK5kzwiaQFJKGRIz5Ip0828j9jGdg5RQcWawyNIgNnYGgMOVTmZIzSwEAAHwJmT0u3tvMa3ZMCtG3L7t27WVlZ0bGlOOYCpQ7QdR3vnH+H/YfPclahxg6Wrbr4dVyvsXmx6vpvayG31fflsRbw3bzIssKlrJadlfDRSqDvpYEiRoghjf+LtXQdGNNILpEAI5aajFq6tn6F7DApjQllYe28YsgcIj6hdHlmCIEUpQ8gpETOaTTexjmhyRtorMU5dVulFFxINyShTLSEBKY2h6AZoINkpa/hjX+1U7b3HAJKbR4Yufx6EULwnrffeZt9+w8x0f8pCVn9NbJv3OkRDDstvFg5LJLGGhKWCwA7Far8fEeiqEWcGKFXK09ePEDS0NE04FrtvS+hoiCBChbm4o9NJllFSIrpx6GXJHE8pAXRE/qAL/0BMY3xqHMWnMM6i8PQtAUd2EVyyCK+ZYCUMc4QsjB9yv9WV0czrBAZgqHLwD+rA+T7bAotjRx1TSAEz/e++10OHz9LGUwZ9KsWfPkqgqzdeQ0DCzTU095xLAt92WuMSADwhdVTijcmhYJC0GEddK18hqxJSkZgoYZxYpYOH3HvWhiyhqxkT0KInhQX7Vt+SAoJI2GI+JzIGuuNMbhWS+A61eMMUg3N5fpYjeVZQo3mEVpMGPsL4yBnbw046wgxY5ezThzJRHGhS8f7goHDMLC5uTkigO3tbXKGS5cu89hn/m0CsIEIv2Tr5TNZdgq7fqzjeVGQWp+XY/oyzbsDCnq1dhVY+T9nwa2ootXkSgUFS2udQSBhAuX3GTuAslp7ULw/aN1/CJHYRyJJ47u8T4vFTg0GJ4JWgduC9XP1GfXkskmL6qIWigIZgnQa+ZzIIWJDJO0TvmXkDYBkFyNC87lh/S7J0n0pQOH9NzY2mM/nowLM5zO2t2Zcv3mdAwePMEcKN+Xta+xfK0Bx6e/F9tWQkOqxuPQaEgYWiVyZhk7ILFwzrWCoWnnSC1Us3Kjl4+R7r/EjwFgl9B4tzgjB0/fayuWjKoM2u1iDM6X8rX3/ijEtjEMZ5RjbwTOLOYjxswlEGWIiR4WAKUv/YMgYIiZBty9AbmkzhFHQMiEagUljFk2i1XHPCpBzHiuCs9lsbAaZzWaE4Lm1cZvtrZ5HTp8TWpVF0lZ/wU7h18/fzbXX7j2z8Chj8lhYOgPGCrtnSxICd4SPqBZnI+QGTFSBK/WbgkLBtKgN9D34mIkhMO+1HJyi8v3SyNJYaCaNNHxobNYRF6IyTIWmdUk9SpSQkICkY9xBWoUZguYMIWkTSiDkjA/CEhirq22alqYxWBzbem0jjGEgW0fOMG+BvXfK9Z4UoJRyNzc3x5hfOICu61hZWeH69Rv0w8DpJ84yASbsxPy1QIpQEotMflnoI5XJzgQyZ7l4VgwNKy1079kDUCeaCUnsIuoqFf9HJYJCrKCgVgd7nxj6MHbwppjBGVrXYBpDbvQccvXOWYicmDMmgbPSumXygvAhaqEoC+5PMSuruGgUDak0mQpj5ZxhtXW4zmCtwzpDZw2uhY0silXnV+j18iGz1k54/cqd8rhnHiDGOPbulfp+af9unOP177xBNg1HTqzsEMRy1r4cx4sLL78rbn1UhCouOEToDWLxJaTckfOw8Ba1QpSkrnD7Pixcu9fiUN8vWL8QhOFzFoxzOAtkO87sSTPnYngjJ3k+Kh1pIkTUyrMojwgkEmImhcg8JOKQyCnRR3mMUYZDrTF0ExF048oOAiiVg9I/aK3DOIPPmZLr9fW5p8jQWc5//87rdE8KUGr7BfqVxs8SApyzXLx4nunabg7uWeD6WuCjAJZ+Vws/poVXMFaxfxF49WHrEFILfJkDqHmIqK8fg5I8XhSg9AOEqLSvZp4NlrYTJ17IHqv8QUYFGgzZGAwJF2HQNq6kLKE0dEhc9zETNGcYCtOno12oJ3DO4roy6GJxSmsanKDFUgO2eTz7xmiTqXMknQeMCAPboylPgj0rju6DooAyE+Cc27HXDxrOn3+btfX97GIBwwr0oxJEQluuVCNiLhYm2lznDqVaCAt4eDf/h7AqAAAgAElEQVRIWGN/2EkoFRg6zEXgXhPFwvGjOUGTFwOTpf8/GsZEMSdJrmwURTIYrM34BDkI2ZODFopCZMiZ2AsqSD7Re20h0+kfkZnB2UaIngaMszisKJWySaY6sVG51YthpHnFGVEo06oCBw0FVq+NhcFC2LxTpu8LBtY9APP5DGMaLrzzDg8cPMIEqf6V0u/o4tXKSu3dWTAtTDVjbdmJEspREMRC56vPwk7FqpPEgFj5ECENktXn8v4GWu0MxuqjsnwR1GWrsK1avQEblJpOogShWHEUS/ZDpA+ygCENKvyYR47fGYNtLa5pcFm7NBotC5dmUIX/DiPhT5UlIV4lAwTpO4gxY7NSxu0KkUaKQl0cXWtE8ptZgG9/+0553rcClKLQzj6AxNtvvcmuAx/Bs2jWTOpeHZJxt06E3thF82ax9GXSx7FT4Mu5xN2gYEIsIqml5yRe01iZnjGSS4kHdeo9FOJlxBOk8j8onFLcH+MCYg4pE+aBvkBALxn7PASil6HObME6S9PAxFqhdY0UckouogFGT9DpPGGWUJWR+kMqP2eSFoWGKHmDDxmTA6Z1rKxAixJEUYpChT7fxjIJ3MEC3rcCbG9vs729zebm5kgAee/p53OuXb3ORz92Eq/Cz0kGLppmJ9mz3PRRHn9YTC8/11ZeQkxABF4Su2Q0d2iF5TOg83klC1eL1hdPTn6f9HVM0tdMigr0MQzgh0QfCvEjhM+QdJwrZ5yzTJwhGZ3bsxU6qNy4VbpRPrMhGe0XTFp0isI35CwDJlIdTIRB5wmzFJ2sNaw4Q2cbjHOEAHZcCdeQCKQAg0LJux33rAB937O5uTkmfvUGkGEYuHbjCuvrh+gQCIi9E+9TPda/q4Vcx3RYxPMaLYz4X8/VNmCanR5FjXz0FIYqmUMtP4s38Jq4hSDP+9IoGrVIFBLDPOCTWHjU2rt10r83NbKzJyOPgGD/KP2Bpc5vgJwTMelGlYTARW3YyF4mi7zXqqBP0hGM8NDZSh7WNR2tk/fqOujalk0iNuu1y2i8laudXMO+ihu5bwUo7N9sNhv3+dTrXN7te2azOac+/DQraP8dd7rw+lhWyKIItcBHSFgJ2zjNH9SdlIQR7uwvKM+V1y6KEOKC9PGpQgHaDj546D0EneWLWs2ztsFNFH6BupadmDuZTA5gnNEkLo9l2jBOA2supS3gIQbmc7HsGFToGvub1uByi+sMjXNYB41R32kMkzYT2kYKWzjJSFF8CIIMWkOshkHq454UoKyCKyig8ALee5qm4d2LFwghc/TRU2jifAc+XyYoynM1RPQa1EtrVjZC3LhGzudubWR1k0lNLNWvj36mnNWyFQ4OWi8oxE8pDecoBR5rHd1UIZiVhUrRgIl5LAZl9QZJewFMECUQpKOdOElInlL2jSEx7wM+ROkY1uESayUhbDvdCm4trtFScAaMtIYLZpTzcgbdFyBdtyk3SA/Y4hqQDbuO3l2299wPUC9OLj0AMUbapuHiu+9imgmPnN6zQ9B3w/+JRQxOirvrVmxjtGDT7oSDy7WD5bBRHmteoeQLAUgehgChFwUY1Np99Q/OyVeZVaxfP+ZFUhmNESrZGlWsNBaKhpBJJLJP9FE2e2z7SOwDPms/X4ikwnk4FXixbmuxjRI91pCywY77gvSjGqvKlwg2E7Ml2bzoeLFFCQRShABvv4ds31c5eMccQIxcu3aVECOtXbj/Ha48a0WuECl60QsSshaaVhLGUkdY5gGKYtUXonxfh44aGchUz0LghfRBE0HX6FQw4x4FUNSQYsUcRskVkpHagdPvQxILD2TSIO3fQyy4PxH6yLzkDVpxssbQto2UgDG4xtI0Wga2BlM4aj0fme00Y1UwaQv62D+YAqEVSjqFDNbobgM5sZAS07UJ/bW7y/K+FaAshSqdwMF7Ll+6wgOHjrDngZ0Dmr6Xi1dgFEjYbJ1k6M6J4LV3U36vj8W117G8juNF6LCz6WPQpo/C9tXNHMZAuY9EPT9hDNrjx0g/2yzWXlrSknIDSZGB9AVmBsX7fi6NosIoRuIQ1HsYJq2DKVgjsNAYN6KTbMFmQ5AIDiZjotE6QSZrFimeKgoyUa4h+ATB41a1ABYNyaQdJxd9pusc//Llu8vzvhSgQL/SDby1tUWcTrl4/m2wDh9hw8LmNuPwQnHdk06FbqFR6FWPedXZf+3Sl8MILCw8AUFdXAji5qNat9GQIi69uiYKDUa3nlXgVj5zUdRxl17QVjGtDPohitB9pPeJ1AcGnfjJ2rzROku7NpXzNaIEMs1jxjJdSWozhmwzttDQCQa06BQhxciQ5T1jiPgY8X0mk4jAmpFQUEitUuXKBfsWyMvGB1OAGgkU4fd9T06J25ubPHT0NE0rrrY1QKexHCF/ai6gfNY6KSzxvUYHdZyP1Vcp2QYlBDIi5KzDHlYVrEzgpliFjSykVEiC+ZMBUxRHFWCsClbIwPtAPwjb52OZ0s2yEawxTKz0+mdjR7e9eM+04B0QZCCGnUlJ6gVkCRNBWcUhSDgJQ8THTA5l1NtiGsO0aYQHmLY0rWMTMQZJF+xIdCQHkwQh3XmrnntWgJQSGxsbOwRfGkNN47h86RLTtWOsAb6F2C4WFZVYfjdIWLJ2WMTwohQj5s8LUiYs9bS3rQpZhz2W2cPyHqZhpHczamlZmb28aCYpnmReEEGfGYZAHyMmZr3AmaZraLSlyOw4MStjYRpuci6j3JYckyaSOiCa0oj/UxAK2WsZOPVRF1KICtnG4FY6WmNpJlIldMZhGlhpMnPTklIhnuR/yo6j5Bv8Lug+SA6wvb1N3/fjOri2bcd9gCsrq8QUefTUh9mFTPSWNKYIH+7E57WA6kQuKQFTmL0suROmUXbPisDrPsJl6FfnCSMHoFl8mf+PGsvjIJg/DtBr3jB43ctnEtkYJo2DiWHFaJOHLmxOMWGMlSFRhXPGWlxeMG8yICrQ0utmsBAyYQj4lBiGslWNkes3VvKGxtZlYAsuY9Al0Vo3cDbjGifeK+SdLhZIVtrc71IGuHcF2LVrF03TjE0gMcbRCwQfuH17g737H6SrBFE3epQYjgoBjbdkxmpaccGZRUY+ooNW+QB+dLNoZjEYk1kIOyOIYFAOwOsoeHHzZS0MQNsa6JoFjVy9fqGSUwaLGxm+pH+QY5JlUUG6ejKZ+SwScmaYBWKWMBJ131+ICecsXWtpWsH5jXO4RjyHsRXxRInnwpFIgmsgJEkhuyCVwJIdWwg5cKAF/vGddQC4jxyg3HyhcAClL31rtsnm5gYHj5zaMb1Tu/kcFzBwjLVp9HBj+bVtJGa3jfAANfFTJ4s1tVwUrBBQNfaPWhTySvgMVf1fp7FB3xcYL3b5TCUhLFNXUfMGMyaK6sp1qKMsc5BETWJ3Pw/jVLBk9VnKvs7STHTJQ+MkYbVunCoa5xfLsWPXoCIgH7EOBmehkSQYWFh/lM+6+R4sILwPGFgvgvTDwI3rt5jNPQ8eOjJe+EK8xAxpWNTeo/rnEredUQvXopFxkkDWXqy29pryLaGjxv0ZydhLs0dZ/OBDqeHLezctTNyCdBJh7oSMMcpnKoMkaIIVSpIYBJL5EAhDpk+RYSbIIAxi6SHkUbmb1tE1BhrZ2dE0riJ7NG4nMYAyB1A2giaAkLXbWZLG6D1DzmQ/0K7tgj0LL2T0/4yF1DXY9ygE3bcClEbQAgdDCFy7comN2zcwXcsmsDVI1py9FlkUrzVOY3dTCd3Jh2ydkh7stPCa5q2TxeLhCulUpoDnw4LOjQmZ8rXS928qStmaymuowAmMxaIY5W/G5FCVNwwQYmbuJTvvveB9EXrcMb/XuoaVFcA4bXgxmGRwJpNcBc9SYUAlgIWweI2gNYMwyH6BxWKqIHlSSExNxqwknPYcjG6jgbgt3+65OwC4PwXw3o8wsEBBaw3Xbt6iXV1n38GHuBVhe0sEYBBI1k7U0jV4twWiKUYvuUIRfmIxTxir5+o2M8+iVBsV/w9xQfa0Tt63QMHCAxT3Pi581De2CWKjuYgqVGkdi1GLQ0NmmA8yCu4leYspSwnWJGzbyPq5VgRusWSbR9o+lJNEmMRI0nMTfz6kKLxDzMSc6OdR8oe5dPsI+SP3F7DG4hrHdM2x1hnMdCINOEYo4JzkIqUOwiyPivC+FSDnPMLAYv2z2Yymabh04QIbt2/JsIOSPE0HnUrUWunNp3AgKgTndiZxRdg1n1+eLx1FfVzEuZFZVFax0wmfO+BmxfiBunizE2EM2iaWku4IUgq599D3QTiAfrGePVlp52o6x6rRVS7GSteQFfwvFcwsHH3OMmCSNYanRET7ASP0OZNLN9GgiyV8lBwjqqFYx9qawzUNbaM7g7RLOFqY5YRJ2mJSLkKUH4Zd7y3be1KAgv/LWHgpB6+vr2MM7N33IA8dWaEzYNYY72JRLHmM3/qNQays2o2ANYuiUE6yMyirUEZhs8gfuqkolnE7PQkskUkl2cwaKvKiNa2PAv8G3RPUB50B8Bk/SJ2jzOfLYkv5AHXPf85pJ7uo72lMJluZEYgJiLINLKQk7WIx4wfPECJ9n8k56pIoBPo5S+sstpUmE+taRQZl8aa0m1uT6RsnHiZFguyWAaS8bCcTHjz0ARWgbP0CuYt2uUvI3r17uXnzJu3qOgcf0jVsunChsGwLKrJIRC6+QRYb5UEvWlw0ZtR/21glfJzyAM2iSFRzCzXsHLF/ldDFokhJ8oSZWvkwLKw+BkmwcsqYFl3WZCnrW8rURSIrq5dIyZGRQY0hI+1gSTt3QmbIELUL2IdIPxdLj0MmRekHwEmO0K00NMbhOktrHa7RBVRON4oqs1qup2FxjccnNENKyUoTsYPtH3JX+XtSgD179rC+vj4uhSq3h2mahqGfYZWcKMIoY1b1bp1YKoBxYeFo1l1KqSVDbyxYrQ62jeYLdoEK6rpAOe+CCKK+b2ncTFkrgl7eM/Qw79XyS9lcc4euczIRrHnKKPCCuT2kBvGxKWOieACBtjK65YEwJGIMzIeEnyeG4KVSOEhmk9HbvrUN7arDtWX9m6PR0q+xSGtZOUkHprxXEiU0WRZNzFpInSP0Qe5NBBirOwhU2T+QAgDjitf6/rfDMHDhnYscPnmWdYQFLBi7JCJBL1yZzh2JjLyAYdZBu6I8QCP5g+vu3gq+jGiKMhTXm4IIOqlrT0HWo3ktB5cE0LjFvqAxH9E3NBGi0ZpDo9g/6XP6/zFCJOqeHhkdG3rPMETm8zDuC04hkozBOeimDR0NthHrNs7SINs+kzU4l0lVHG9jJhqk0JT03GOqlldEGAbcAxNsI9YeghjOkMHbzOp6w5rjPY/7goF1O3jpCXz7nbeYrJ8hoBx6v+i6yQWSaQpfRrjEvaqFK7XrGonpVum+u/H6tcAL/s+xaulS7D/0mnWr1TuNEZ32DjoV9g5vkhbCLTODWSFI2SISNDz4mAizQJ+hn3tCiPRDFIYv5lFJu9ZiOpkXbJ2VtnALyYjw0amisTCWHUlpZZNhnkXgPsh2Uh8jvSak0cusojORPXs8hqkwkw6CjzSNXoMI19/5MShASmksA89mM+bzOdY6pTxnbAC3t8DPJNkq2bqzigTUnTdWGzFcBQVdVTAq7drLQtd4rrmO4H31KqX9vJR3Sys4HewyIvRSLEoO6ffPi3xhXAePCH1cFxMXcNAPmX7whJjp+8g8RvI80qc0ZrK2a2W+wckKV2PEuo0mg1DlKxnAavKbNNmV+D1EvaFEH5mHSOilAhn84jZ7xlm6qWO1a7GmJWTxUBigc6QgHUkksGVR0wdRgI2NDTY2Nqrt4NsY4xhS4sDDx+l72J6BCXLBJxMlXpQDcAoJneJxoyZulbnKVi1OM/6yqLEgAK9Ucu8ZFzmXJY+oknWtvl5F+CzXJEjiKgt1WEikWGhqr+ggFPwf8X1gPsRxFXwMkuXTGFZdS6MWbY2R+O7KIojF55dJ7aSKnEeFG3wgR00WB4GBvQ/SCu61OTQnHBbXOlZsg5s4WtvQtoaug9TqDuVCUVuwOWEtbAf44+9+QAXY2NjY0Q6+vb2tlPDA1Xff5cynH6KbwOoKuIiuNV1w/HK3SsbW7LHHMSpq0A9vqwtWGDixvp00bVGQ1unsfycbPo1lx5YP8iK5lKxd/j9oIhoHcfseiL0khb2HYcj080iMnr6P8lrGClc/FWTQGKn8ZQy5bOgOQnbkkEhWbkePybKkUlu7Q9KNXynLUoleGMVB2T7K8mhkN7F1Hc4ZJl1D07pxqMVag02wYmB76kg9i0HaqAmxh8lUcqAPpAClDazg4dXVVZqmIfiBRKTp1lkF+o5xyuZuHH5E4rEv6brCwMLDB3W945BmFkWo+/ZcK4J3OmXUKTSwWTyxVQuvCZ+osXCIi8dYSr9K+Awehj6SYiDGhNG58+mKwzjZ1+tcwho3ruGR3QRapLFJEELQRtEUCdGQQpJm0CRVwKEXFlGWSsZxtQzIYigmjt2Nwxpx8RlonZFEMSf1ajKDYJtEbKzMJuo1Tppn+QDZZtYncP7WB1SA1dVVuq5jGAbqu3/evr1B061x8uxHpZGzQDXLuIIdzahR1s1XvEBOmqnDuLuHXJWDG1hZU3jYaXuVq6hl1LoL6xiRca4K8w9q6T7uXAHX95KwxixrXrJW45p2Qmlls50qFIXkceJdoipZTIIMNG9IIeOz3hyqT8y1o2fuI3FIDL020+oFMEamgVdH0kd6ANCBB5sW9DUIBQzgtZRsgDQE+tVOClXIOQcfZHFVgj7B6f3wxgdRgLU1WS5XMv9yd7Dee4aUmervS+PkWF+PSlwU60v6uyxWWdy9MYviUNtVI2UqbNS9G1WKEkqsCj5F+YrqUcqwxxAWTF/fa/6gyV3xTG1j6KaNVCFdlR+giWgSq8pRBIIRTx+9uvGUSIPu+veyNsYHEbqfByF9vN7VvEBBJ0SPbeSewVhp87IFG4u4ZSE1koALQsl63ZLeuyBicmBlbUVKyCwINkrC3IN/j26ge1aAchTrL1zAzetXuX31MhjHnMXoNXkxex/LZG5fkS4of9/tLAcXRFBKtEYTw7JIyVotFqlQSCp4JE8IWrgZBlG0+cDYzJmyNqR2UnJutfxsnYSlrPlHQiw6sYCC2WtNIouXSlEKQvMQiX2mD15Wx/hI6BMeWetKI+RSO+mwraWxBtNYGmPGPka51a8dIScIIkhWXiNrH1tZQiV9BpIk5pxobMI9wNgj0Og1hoaQPA5484fI9L52BJU9wRsbGxhjuHH1Gs10lUNHHmUrwdaWjmMrREvanWIBNGnr2sUMQFPgWVfV/o0KG8ZdvoXuDFHCSG+BYUHv9v2i8cMHxoGTkVk0UixCm1MbI3CwdI+kVtBL48RrlPpBKsgDEXwYIoP3zIdM33tCH5kNeoNLxa22caw4h12V7Z7GOimGWav8uF5PRANM0lvBJWH5vAeIWqAKDPOkiEB6BnNMRCvj46sTx9p0gm0sKMmWfRhzoJAye6a8ZzfQfSnA1tbWCAPn8znGwLXbmyTTkE3m+k24eZsxAxf3usD+rZN369zCjReLrxECsCBlCmsnT41TPCWBK0JPecEbOAOTVc1HSugwO/sA9C3E0jpk7bqSPaVu4IPQxkOUwdD5EOn7oD0AMp8vN3U0NJMGZxxta/U8HE1ThUBKl5Qkc1E3U4y4f0CVSMfGBgkfPgnTGEFWw7aWdm3CrknLZNKytu5YaRpuGscwzzQWBidiNTaQ8g9HAPesAEX4pTlUVsO2XLt0kc3b19me9fgkF7ttJY5jql0+ZUS8uPYsSiA9dBp30e9ZwL3C6Ye0EH5BCrAIJa1+lTbwokejsE1VFdZ4Ps7ga+NK9Lo9VNvAZ3PP0HshYkJW6KZs5dSx6hrh762hNZakRbBS4YREhyWYpD16SZpkiORQFkDLYEmMge0+4Qcv4TMKhreuYbresTpp6DrH6kpLO2noWkPjGiYtuKnl5pWIs4Y8eLnYJpA8ZJ/JP6QQdF8KUCaByl0/27YDEo1r2b1nD7umYNdZzOIXN44m6XX2r0IoQoyKFnJeWB8oJPQLurZxQvK0DUx1pUghmLJjsec/M45xleSocEZ4vSdQUOwftZNoDjPvmc+FeZO/TxgskxWDk2CNNXLvP6MbQoHFrKaFZDIuwJAsXpcehSTdQvMQdEZRyCUfM75PWlKWewK3U8felYZp45iqwNvW0Wrfn8lgkuwa98HiZonOZRKBWPBfygwp4PuE2/1jUIBS/9+1a9d4x5A9e/YwWVnlwSPHOHJcihG2XVhaTvK9L8IvHR9IXmDywgqLoHX6aazAOW0D75zE8q70DWp3Uc3yRRWAQXMABcYlk/dogUihYD/IPYJ9SAxDYPABo0Md05VWSrDOjjdnKodBYmuJOePdvJMUhWQXcSLp7eX6GPA+E+by/XyI2JhIyN2+1tYcbTtlOrV0k5aVlVbzIxGNMRaTRNVKMgryWUNOWj9JuCGzPQTdb5yxITPf2uLBlX0fXAEOHjw4wr+UEn3fs7a2xtUrVxh8oJ3oxa9MLaMdPHERo7MKIaBJlRZadDm31AkcNBNY6cSbtJ32ARgovQ7LrdrF9Y4Fm0IqobDPQz8Xa+/nsvtPuAzRmqZ1TFYaLJZGHJtQ1XHBHhbvlHVT2pAz5DBOKeUcmc/ldeczEXrvg2wS0VHg1jpW25bJXse0a+gmLdOpo2kbJo2VOobi99IYGlEFMxJjTZAkkBAkIXaJXTmx3kZu3vYkA53JzPuMTYm1H9IMcs8KUO76Wd8IOsbIrRvXiN6TTemULSVLdvTrhajZdGAkaYzWAVwnyKBtNWFsNWfQApF1mkBXEh/xOYwrXROMu/78XN8rLBo/pEAl83uNM7RNS+MkHDkNWaiwy2RV0AaMEFkMZyaIunLF+yxbPHrPVi93Pw/zRI9gU2cNE+doViSOT1YczbRlpbU0ttFzNCRkWsgYkA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kEnFToWYScQoGpCR8SISb9m0ROo0AEGTVgTMutuBC1A4Yi9ZEDiiQsEcc7L9+nAlhr+a3f+i1+53d+B+89xhj27NkzJlB1tl0zdDX5cjeBv5d1LwscGENGqQyWn2uhG3Wvk8mExjWEELh+/RpvvP46L774PC88/xyvvvodLt/YYLr7QR49+3E+/jf/K/7BL3yeJ3/qYQ7thRaJnfMZzDbgVg8hQApyMa01dJMGYzUxNVmEUkKYARtFaawBTCbFhTsPSWJ3TCLUGPW8fSamQPBF4IkYGZM/aw1NY3HGYqzFObDG0rqMdw6SvGdD8TYRNMwJG+yIvucSK3zz9edFh7gHKtg5xxe/+EW+/OUvj0na8lEXf4oQ62z/vdx57fKLYsAiYSsuvI7dyy69Jn/6+ZzrN27yndde4avPfoUXX3yRV7/zOldvbLLrwHE+9LHP8jOf/VU+9Yu/xJnHYL/mTB7YTDDbgvlck+nq4mTNxcoFy1kuco6QE0QktS7CijGRM6PlxpiIauXRJ2JKhJCIIeHVvYecCDFjKoFbawTzG7BOHgskNBmygc5BSIZrecI85ZI/4mMEs7MzanvDc3H9AH/4eYEfP9IDGGP45Cc/ye/93u/teL7G/jHGMRwU6FcXgu5m3ctWX1fA3qsMXPPrk8lEk9AZ598W/P3881/jpZe+xfffvsjteeDAw+f46Cc/zxf/zi/xM3/tGR57FPYrbJoB28CNHoIXC0eSbSYt5HYh9DFGS8glG/UGGrcx4JK69JwJUUJDiJmYIjGIlXsfCCERQiTERIxJEkUyJgv0W2ksGItrVNAqA6veJlF5dFPCfcbT0CNJnishIrlF9qdHtJFhvvj5RyqAtZYvfelLOwRfFAOkqWF7e3tMAmsFWLb8OgcAdljzcgyvM/jCCwBsbW7y9ltv8vUXnuerz36Fl771Km+98w7R7ebkR3+epz/3n/Gbn/oFPv4zhzm5G3arNcyBrQyXAT9ASmhAFi/pGvm5CBykjpKz/G3OQFKBK57KSTxAVGHnGPFJ4vcQI3GIhCAx3PtAiAmSYHdMxmJxnVo6FdmjiWHJ5UooN8bgsiSK0WRsNqKUOeNzBNPhUhhpfxq0IKBaECOta5iv3IcC7N27l8997nOj8GuOv+97tre3x47UYvUF/xeXXmPsUhGriR5jjJAfVqxAUENDSomNrS1ef+01nvvan/DVZ5/l1e98h+9+703SZDePPfUL/Pxv/3f8w8/+dT7+sYbjQKPCmwHbGa4gtLiiISyS1JWs3FS/y3Eh8JhEECmDTeBVAWIS6w9eYroPYskhJsKg1h0Sgy/Kr32AGFprsY2RHMGpwBPkHZ9iEZWTunmriCHlkmvoe5eiVswkZ8ltJBsRd1axJ6tqFCEZi7eZvQ/chwKANH4UDSxsX9/3zOdz+r5nNpsxm81GS/fej8Iurrxm2JpGhFsqY9Y1NI0jhsTt27d45bVX+eY3X+Yr/+L/5ZVXX+H6xpzcPMC5T/5bfO53/wFPP/NJPvOpvZxg5EsIGbYQSy+Eh3pnuur7ctQoqVz6WEwuLR5D0BgfRDFCkO+HEPE+asIWReA+qLcQoTfOQitu3NrRX498DxFSowLGKPYXDqAkljGp8FMi5kyKiRwSQ86kIeFTxuVEnlrcZEIMdjwvR2S0fwchgUsN3x/uUwHKUQvde898Ph8HMgrDNplMRosvyVlRnpqFs9ayvbXFjRs3+cFbb/P888/x7LPP8torr3H+4gX2PXSOj/3S3+B3fue/5+c+92Ge3Av7qnQ1q8D7Soh6nuNJFYEXZYjVz1UEGMm3FFXISYQ+DPI+wwDRw+AzPsXR0oeYyEFgHEDbNMLll/d3Ep9NssICpqwJZNakriiLvI8ApQUkTCnjQ4SMepWoz5dQnDHG0jWW3DRsZkt0JX5Bto6WyFgj6jN2V8e7L74PBdja2qLv+xGaGWPGmjssunCKsIvrL14g58zm5ibvnH+bb7/8LZ79kz/mT5/9Y86/e40+NRw49lN86Jm/xt/97X/Cp37uYzx9GPZWAk9ZkrZS5Sx5jtWTqC18GdYUgTfs9A5Bn4+psu4E3kueEAL4AGFIEtNDIo2JG7TWQleUO49vlg3q+g0Z4QuabMTDpGLtmT5mbMpK6GRC1LatCN4nUo7EmAlBPIp1hpwMTQvWOpw1OGdpHQTb0AQI5SJYUSinRYFsIeXIFTuB19+HAixj7VEwivWLcpQwUDj+N9/8Ac/+8Vf4ylf+Jc999TnePn+BrXlg70OP8cu/+SX+48//TZ759GGeXIHJksA3VUC+ErBjkdgWj73s2uv4Xqy7KIEm7wRVhhhU0F6tfIAhQRgEyqUk8A2Ev0/WYjotyCCCF+sVT5ABYpZELkFKBlImKGmUciYGhOVLiXmQ5HGIieCFBIoxapHHYJyhmwgUtNYoFDRS1dPKYNcZcjT0NROoFyM6oabkumT8Jrzx5cUVu2cFKO1UtfBzzju8QoF80+mUS5cu8fu//3v8r//0f2E7dpz5qV/mY7/2D/n7v/wrfPwzj/L4CqxWAh8y3FbBlDSofLgVfc5WilB7gCL48nJF4FG/L49hSfCDF8GHAbwSN1H/2drSp2cXULC8V0qSEOakVg7GZmwywuoZKdSklIm5QMIi3MLsRaISPoUYwijJ1DY4Z6Txw1pVBPU0mskWVtGhSapFTqLmaZzCVSlBMA9gl2ZH7psKXkYC3vsdRaCu6/je977H3/2P/kO+/Z3v8at/73/kv/nyf8nHmgW8AugrgY8ngrBwTSXs8lj+taifY6EERejl5/Kavghbvw/q5r3G9BC1LJrkddsWOnMn/tdwS8yaJxhLtoIJBR4mTdQyIWuYCIoQQmbwgvtDFISQvGD/TBG4xU0Aa3FG2D0cwg2MCcXiXHOp9+dMMoaQErhMNs2Yj5TDtYyNoNbEOwR+XwpQ1/6992P2v7m5Sd/35JzZ3t7m7/+nX+Lb3/kev/d/3+ZLvySTQNtZMvRaaCV+F+Fb3tu92+p/aw9QLLy49SL8QZ8PaGz3IsDoNTw4aC1MzAJuGaMZfxG8fp80KSzeJ+fC32tDbJT4Gnxm8AILB0UIPkgZmADZZpyx2Ck0Bfo2Rs9P29cwYPPo0rJldGFZw01CE8cAKQesyfjcYFpwmiSVhHekASKEZElLrWL3XQ0sJeAi/PK1vb3N6uoq/9f/+X/w3Avf4B/9z/+aL/3S+gjNagGb6rE8X8fxZaGPrnfpq1h3yROKpSc98aDakY0It7HQNSpofaMUK6ZPtcomvYCV68nKAcSU5StKZh5ixIeI70XoMWb82LcIzhk605A7iyVLG5dxaD6otXsE9o1vZoRksorflQHESy4RvUJCL/QxMcCuiSR6pQuoZuwD8ve2IT24U573pQAhhBEGzudztre32draGuFgzpk//MP/nSOPfZz/4u99erTG6Q8R8vIM7w5ihkXytmzxYyyvvjKM9KxxMHVAu3iv8tq1heM0WYsLxcgoy6chY0QIJX4PgSEkvCZtYYiiqFk6d1ZXOglrpSl16RxLHcFlDQWuFIoUPWCkJOyz1g+0buATIWdCDEJdZ8kbOjJuLE6wUKpy2EwKkJqGLb/zs9yzAnjvR1dfWL8y41Y6cy+8e5GXX3mNf/K/Pct+/QxdOWnujNt12XpZ6OP7FqGxEHz5eTlEWBhr7+Wow0W5JiWu5tKLUdy+eo0UoA/iRZKHPiRiiAwhamyPQhOnrM0ejSSNRoKEtYVqzqNilFqC9G9lLGLNJBV6gpCFE/RevEpQ2FnYRgUjWGPoWrA4ms4wdY6+sVr4CYyUZ3XkFMl2hee/svP5e1IA7/1I+Rb8P5lMdnTrrK2t8c2vvwDA5//GJ8b/LbRkTb7ULpyl7+usHUQBqP6/xOHlRPFux7Iy1XlEXdwZEUAU3D8MkiD6QecDQiblpBpn6LpGK4NC64qWWYxEe1LOGCuuyKrUamEnkwQK5kzwiaQFJKGRIz5Ip0828j9jGdg5RQcWawyNIgNnYGgMOVTmZIzSwEAAHwJmT0u3tvMa3ZMCtG3L7t27WVlZ0bGlOOYCpQ7QdR3vnH+H/YfPclahxg6Wrbr4dVyvsXmx6vpvayG31fflsRbw3bzIssKlrJadlfDRSqDvpYEiRoghjf+LtXQdGNNILpEAI5aajFq6tn6F7DApjQllYe28YsgcIj6hdHlmCIEUpQ8gpETOaTTexjmhyRtorMU5dVulFFxINyShTLSEBKY2h6AZoINkpa/hjX+1U7b3HAJKbR4Yufx6EULwnrffeZt9+w8x0f8pCVn9NbJv3OkRDDstvFg5LJLGGhKWCwA7Far8fEeiqEWcGKFXK09ePEDS0NE04FrtvS+hoiCBChbm4o9NJllFSIrpx6GXJHE8pAXRE/qAL/0BMY3xqHMWnMM6i8PQtAUd2EVyyCK+ZYCUMc4QsjB9yv9WV0czrBAZgqHLwD+rA+T7bAotjRx1TSAEz/e++10OHz9LGUwZ9KsWfPkqgqzdeQ0DCzTU095xLAt92WuMSADwhdVTijcmhYJC0GEddK18hqxJSkZgoYZxYpYOH3HvWhiyhqxkT0KInhQX7Vt+SAoJI2GI+JzIGuuNMbhWS+A61eMMUg3N5fpYjeVZQo3mEVpMGPsL4yBnbw046wgxY5ezThzJRHGhS8f7goHDMLC5uTkigO3tbXKGS5cu89hn/m0CsIEIv2Tr5TNZdgq7fqzjeVGQWp+XY/oyzbsDCnq1dhVY+T9nwa2ootXkSgUFS2udQSBhAuX3GTuAslp7ULw/aN1/CJHYRyJJ47u8T4vFTg0GJ4JWgduC9XP1GfXkskmL6qIWigIZgnQa+ZzIIWJDJO0TvmXkDYBkFyNC87lh/S7J0n0pQOH9NzY2mM/nowLM5zO2t2Zcv3mdAwePMEcKN+Xta+xfK0Bx6e/F9tWQkOqxuPQaEgYWiVyZhk7ILFwzrWCoWnnSC1Us3Kjl4+R7r/EjwFgl9B4tzgjB0/fayuWjKoM2u1iDM6X8rX3/ijEtjEMZ5RjbwTOLOYjxswlEGWIiR4WAKUv/YMgYIiZBty9AbmkzhFHQMiEagUljFk2i1XHPCpBzHiuCs9lsbAaZzWaE4Lm1cZvtrZ5HTp8TWpVF0lZ/wU7h18/fzbXX7j2z8Chj8lhYOgPGCrtnSxICd4SPqBZnI+QGTFSBK/WbgkLBtKgN9D34mIkhMO+1HJyi8v3SyNJYaCaNNHxobNYRF6IyTIWmdUk9SpSQkICkY9xBWoUZguYMIWkTSiDkjA/CEhirq22alqYxWBzbem0jjGEgW0fOMG+BvXfK9Z4UoJRyNzc3x5hfOICu61hZWeH69Rv0w8DpJ84yASbsxPy1QIpQEotMflnoI5XJzgQyZ7l4VgwNKy1079kDUCeaCUnsIuoqFf9HJYJCrKCgVgd7nxj6MHbwppjBGVrXYBpDbvQccvXOWYicmDMmgbPSumXygvAhaqEoC+5PMSuruGgUDak0mQpj5ZxhtXW4zmCtwzpDZw2uhY0silXnV+j18iGz1k54/cqd8rhnHiDGOPbulfp+af9unOP177xBNg1HTqzsEMRy1r4cx4sLL78rbn1UhCouOEToDWLxJaTckfOw8Ba1QpSkrnD7Pixcu9fiUN8vWL8QhOFzFoxzOAtkO87sSTPnYngjJ3k+Kh1pIkTUyrMojwgkEmImhcg8JOKQyCnRR3mMUYZDrTF0ExF048oOAiiVg9I/aK3DOIPPmZLr9fW5p8jQWc5//87rdE8KUGr7BfqVxs8SApyzXLx4nunabg7uWeD6WuCjAJZ+Vws/poVXMFaxfxF49WHrEFILfJkDqHmIqK8fg5I8XhSg9AOEqLSvZp4NlrYTJ17IHqv8QUYFGgzZGAwJF2HQNq6kLKE0dEhc9zETNGcYCtOno12oJ3DO4roy6GJxSmsanKDFUgO2eTz7xmiTqXMknQeMCAPboylPgj0rju6DooAyE+Cc27HXDxrOn3+btfX97GIBwwr0oxJEQluuVCNiLhYm2lznDqVaCAt4eDf/h7AqAAAgAElEQVRIWGN/2EkoFRg6zEXgXhPFwvGjOUGTFwOTpf8/GsZEMSdJrmwURTIYrM34BDkI2ZODFopCZMiZ2AsqSD7Re20h0+kfkZnB2UaIngaMszisKJWySaY6sVG51YthpHnFGVEo06oCBw0FVq+NhcFC2LxTpu8LBtY9APP5DGMaLrzzDg8cPMIEqf6V0u/o4tXKSu3dWTAtTDVjbdmJEspREMRC56vPwk7FqpPEgFj5ECENktXn8v4GWu0MxuqjsnwR1GWrsK1avQEblJpOogShWHEUS/ZDpA+ygCENKvyYR47fGYNtLa5pcFm7NBotC5dmUIX/DiPhT5UlIV4lAwTpO4gxY7NSxu0KkUaKQl0cXWtE8ptZgG9/+0553rcClKLQzj6AxNtvvcmuAx/Bs2jWTOpeHZJxt06E3thF82ax9GXSx7FT4Mu5xN2gYEIsIqml5yRe01iZnjGSS4kHdeo9FOJlxBOk8j8onFLcH+MCYg4pE+aBvkBALxn7PASil6HObME6S9PAxFqhdY0UckouogFGT9DpPGGWUJWR+kMqP2eSFoWGKHmDDxmTA6Z1rKxAixJEUYpChT7fxjIJ3MEC3rcCbG9vs729zebm5kgAee/p53OuXb3ORz92Eq/Cz0kGLppmJ9mz3PRRHn9YTC8/11ZeQkxABF4Su2Q0d2iF5TOg83klC1eL1hdPTn6f9HVM0tdMigr0MQzgh0QfCvEjhM+QdJwrZ5yzTJwhGZ3bsxU6qNy4VbpRPrMhGe0XTFp0isI35CwDJlIdTIRB5wmzFJ2sNaw4Q2cbjHOEAHZcCdeQCKQAg0LJux33rAB937O5uTkmfvUGkGEYuHbjCuvrh+gQCIi9E+9TPda/q4Vcx3RYxPMaLYz4X8/VNmCanR5FjXz0FIYqmUMtP4s38Jq4hSDP+9IoGrVIFBLDPOCTWHjU2rt10r83NbKzJyOPgGD/KP2Bpc5vgJwTMelGlYTARW3YyF4mi7zXqqBP0hGM8NDZSh7WNR2tk/fqOujalk0iNuu1y2i8laudXMO+ihu5bwUo7N9sNhv3+dTrXN7te2azOac+/DQraP8dd7rw+lhWyKIItcBHSFgJ2zjNH9SdlIQR7uwvKM+V1y6KEOKC9PGpQgHaDj546D0EneWLWs2ztsFNFH6BupadmDuZTA5gnNEkLo9l2jBOA2supS3gIQbmc7HsGFToGvub1uByi+sMjXNYB41R32kMkzYT2kYKWzjJSFF8CIIMWkOshkHq454UoKyCKyig8ALee5qm4d2LFwghc/TRU2jifAc+XyYoynM1RPQa1EtrVjZC3LhGzudubWR1k0lNLNWvj36mnNWyFQ4OWi8oxE8pDecoBR5rHd1UIZiVhUrRgIl5LAZl9QZJewFMECUQpKOdOElInlL2jSEx7wM+ROkY1uESayUhbDvdCm4trtFScAaMtIYLZpTzcgbdFyBdtyk3SA/Y4hqQDbuO3l2299wPUC9OLj0AMUbapuHiu+9imgmPnN6zQ9B3w/+JRQxOirvrVmxjtGDT7oSDy7WD5bBRHmteoeQLAUgehgChFwUY1Np99Q/OyVeZVaxfP+ZFUhmNESrZGlWsNBaKhpBJJLJP9FE2e2z7SOwDPms/X4ikwnk4FXixbmuxjRI91pCywY77gvSjGqvKlwg2E7Ml2bzoeLFFCQRShABvv4ds31c5eMccQIxcu3aVECOtXbj/Ha48a0WuECl60QsSshaaVhLGUkdY5gGKYtUXonxfh44aGchUz0LghfRBE0HX6FQw4x4FUNSQYsUcRskVkpHagdPvQxILD2TSIO3fQyy4PxH6yLzkDVpxssbQto2UgDG4xtI0Wga2BlM4aj0fme00Y1UwaQv62D+YAqEVSjqFDNbobgM5sZAS07UJ/bW7y/K+FaAshSqdwMF7Ll+6wgOHjrDngZ0Dmr6Xi1dgFEjYbJ1k6M6J4LV3U36vj8W117G8juNF6LCz6WPQpo/C9tXNHMZAuY9EPT9hDNrjx0g/2yzWXlrSknIDSZGB9AVmBsX7fi6NosIoRuIQ1HsYJq2DKVgjsNAYN6KTbMFmQ5AIDiZjotE6QSZrFimeKgoyUa4h+ATB41a1ABYNyaQdJxd9pusc//Llu8vzvhSgQL/SDby1tUWcTrl4/m2wDh9hw8LmNuPwQnHdk06FbqFR6FWPedXZf+3Sl8MILCw8AUFdXAji5qNat9GQIi69uiYKDUa3nlXgVj5zUdRxl17QVjGtDPohitB9pPeJ1AcGnfjJ2rzROku7NpXzNaIEMs1jxjJdSWozhmwzttDQCQa06BQhxciQ5T1jiPgY8X0mk4jAmpFQUEitUuXKBfsWyMvGB1OAGgkU4fd9T06J25ubPHT0NE0rrrY1QKexHCF/ai6gfNY6KSzxvUYHdZyP1Vcp2QYlBDIi5KzDHlYVrEzgpliFjSykVEiC+ZMBUxRHFWCsClbIwPtAPwjb52OZ0s2yEawxTKz0+mdjR7e9eM+04B0QZCCGnUlJ6gVkCRNBWcUhSDgJQ8THTA5l1NtiGsO0aYQHmLY0rWMTMQZJF+xIdCQHkwQh3XmrnntWgJQSGxsbOwRfGkNN47h86RLTtWOsAb6F2C4WFZVYfjdIWLJ2WMTwohQj5s8LUiYs9bS3rQpZhz2W2cPyHqZhpHczamlZmb28aCYpnmReEEGfGYZAHyMmZr3AmaZraLSlyOw4MStjYRpuci6j3JYckyaSOiCa0oj/UxAK2WsZOPVRF1KICtnG4FY6WmNpJlIldMZhGlhpMnPTklIhnuR/yo6j5Bv8Lug+SA6wvb1N3/fjOri2bcd9gCsrq8QUefTUh9mFTPSWNKYIH+7E57WA6kQuKQFTmL0suROmUXbPisDrPsJl6FfnCSMHoFl8mf+PGsvjIJg/DtBr3jB43ctnEtkYJo2DiWHFaJOHLmxOMWGMlSFRhXPGWlxeMG8yICrQ0utmsBAyYQj4lBiGslWNkes3VvKGxtZlYAsuY9Al0Vo3cDbjGifeK+SdLhZIVtrc71IGuHcF2LVrF03TjE0gMcbRCwQfuH17g737H6SrBFE3epQYjgoBjbdkxmpaccGZRUY+ooNW+QB+dLNoZjEYk1kIOyOIYFAOwOsoeHHzZS0MQNsa6JoFjVy9fqGSUwaLGxm+pH+QY5JlUUG6ejKZ+SwScmaYBWKWMBJ131+ICecsXWtpWsH5jXO4RjyHsRXxRInnwpFIgmsgJEkhuyCVwJIdWwg5cKAF/vGddQC4jxyg3HyhcAClL31rtsnm5gYHj5zaMb1Tu/kcFzBwjLVp9HBj+bVtJGa3jfAANfFTJ4s1tVwUrBBQNfaPWhTySvgMVf1fp7FB3xcYL3b5TCUhLFNXUfMGMyaK6sp1qKMsc5BETWJ3Pw/jVLBk9VnKvs7STHTJQ+MkYbVunCoa5xfLsWPXoCIgH7EOBmehkSQYWFh/lM+6+R4sILwPGFgvgvTDwI3rt5jNPQ8eOjJe+EK8xAxpWNTeo/rnEredUQvXopFxkkDWXqy29pryLaGjxv0ZydhLs0dZ/OBDqeHLezctTNyCdBJh7oSMMcpnKoMkaIIVSpIYBJL5EAhDpk+RYSbIIAxi6SHkUbmb1tE1BhrZ2dE0riJ7NG4nMYAyB1A2giaAkLXbWZLG6D1DzmQ/0K7tgj0LL2T0/4yF1DXY9ygE3bcClEbQAgdDCFy7comN2zcwXcsmsDVI1py9FlkUrzVOY3dTCd3Jh2ydkh7stPCa5q2TxeLhCulUpoDnw4LOjQmZ8rXS928qStmaymuowAmMxaIY5W/G5FCVNwwQYmbuJTvvveB9EXrcMb/XuoaVFcA4bXgxmGRwJpNcBc9SYUAlgIWweI2gNYMwyH6BxWKqIHlSSExNxqwknPYcjG6jgbgt3+65OwC4PwXw3o8wsEBBaw3Xbt6iXV1n38GHuBVhe0sEYBBI1k7U0jV4twWiKUYvuUIRfmIxTxir5+o2M8+iVBsV/w9xQfa0Tt63QMHCAxT3Pi581De2CWKjuYgqVGkdi1GLQ0NmmA8yCu4leYspSwnWJGzbyPq5VgRusWSbR9o+lJNEmMRI0nMTfz6kKLxDzMSc6OdR8oe5dPsI+SP3F7DG4hrHdM2x1hnMdCINOEYo4JzkIqUOwiyPivC+FSDnPMLAYv2z2Yymabh04QIbt2/JsIOSPE0HnUrUWunNp3AgKgTndiZxRdg1n1+eLx1FfVzEuZFZVFax0wmfO+BmxfiBunizE2EM2iaWku4IUgq599D3QTiAfrGePVlp52o6x6rRVS7GSteQFfwvFcwsHH3OMmCSNYanRET7ASP0OZNLN9GgiyV8lBwjqqFYx9qawzUNbaM7g7RLOFqY5YRJ2mJSLkKUH4Zd7y3be1KAgv/LWHgpB6+vr2MM7N33IA8dWaEzYNYY72JRLHmM3/qNQays2o2ANYuiUE6yMyirUEZhs8gfuqkolnE7PQkskUkl2cwaKvKiNa2PAv8G3RPUB50B8Bk/SJ2jzOfLYkv5AHXPf85pJ7uo72lMJluZEYgJiLINLKQk7WIx4wfPECJ9n8k56pIoBPo5S+sstpUmE+taRQZl8aa0m1uT6RsnHiZFguyWAaS8bCcTHjz0ARWgbP0CuYt2uUvI3r17uXnzJu3qOgcf0jVsunChsGwLKrJIRC6+QRYb5UEvWlw0ZtR/21glfJzyAM2iSFRzCzXsHLF/ldDFokhJ8oSZWvkwLKw+BkmwcsqYFl3WZCnrW8rURSIrq5dIyZGRQY0hI+1gSTt3QmbIELUL2IdIPxdLj0MmRekHwEmO0K00NMbhOktrHa7RBVRON4oqs1qup2FxjccnNENKyUoTsYPtH3JX+XtSgD179rC+vj4uhSq3h2mahqGfYZWcKMIoY1b1bp1YKoBxYeFo1l1KqSVDbyxYrQ62jeYLdoEK6rpAOe+CCKK+b2ncTFkrgl7eM/Qw79XyS9lcc4euczIRrHnKKPCCuT2kBvGxKWOieACBtjK65YEwJGIMzIeEnyeG4KVSOEhmk9HbvrUN7arDtWX9m6PR0q+xSGtZOUkHprxXEiU0WRZNzFpInSP0Qe5NBBirOwhU2T+QAgDjitf6/rfDMHDhnYscPnmWdYQFLBi7JCJBL1yZzh2JjLyAYdZBu6I8QCP5g+vu3gq+jGiKMhTXm4IIOqlrT0HWo3ktB5cE0LjFvqAxH9E3NBGi0ZpDo9g/6XP6/zFCJOqeHhkdG3rPMETm8zDuC04hkozBOeimDR0NthHrNs7SINs+kzU4l0lVHG9jJhqk0JT03GOqlldEGAbcAxNsI9YeghjOkMHbzOp6w5rjPY/7goF1O3jpCXz7nbeYrJ8hoBx6v+i6yQWSaQpfRrjEvaqFK7XrGonpVum+u/H6tcAL/s+xaulS7D/0mnWr1TuNEZ32DjoV9g5vkhbCLTODWSFI2SISNDz4mAizQJ+hn3tCiPRDFIYv5lFJu9ZiOpkXbJ2VtnALyYjw0amisTCWHUlpZZNhnkXgPsh2Uh8jvSak0cusojORPXs8hqkwkw6CjzSNXoMI19/5MShASmksA89mM+bzOdY6pTxnbAC3t8DPJNkq2bqzigTUnTdWGzFcBQVdVTAq7drLQtd4rrmO4H31KqX9vJR3Sys4HewyIvRSLEoO6ffPi3xhXAePCH1cFxMXcNAPmX7whJjp+8g8RvI80qc0ZrK2a2W+wckKV2PEuo0mg1DlKxnAavKbNNmV+D1EvaFEH5mHSOilAhn84jZ7xlm6qWO1a7GmJWTxUBigc6QgHUkksGVR0wdRgI2NDTY2Nqrt4NsY4xhS4sDDx+l72J6BCXLBJxMlXpQDcAoJneJxoyZulbnKVi1OM/6yqLEgAK9Ucu8ZFzmXJY+oknWtvl5F+CzXJEjiKgt1WEikWGhqr+ggFPwf8X1gPsRxFXwMkuXTGFZdS6MWbY2R+O7KIojF55dJ7aSKnEeFG3wgR00WB4GBvQ/SCu61OTQnHBbXOlZsg5s4WtvQtoaug9TqDuVCUVuwOWEtbAf44+9+QAXY2NjY0Q6+vb2tlPDA1Xff5cynH6KbwOoKuIiuNV1w/HK3SsbW7LHHMSpq0A9vqwtWGDixvp00bVGQ1unsfycbPo1lx5YP8iK5lKxd/j9oIhoHcfseiL0khb2HYcj080iMnr6P8lrGClc/FWTQGKn8ZQy5bOgOQnbkkEhWbkePybKkUlu7Q9KNXynLUoleGMVB2T7K8mhkN7F1Hc4ZJl1D07pxqMVag02wYmB76kg9i0HaqAmxh8lUcqAPpAClDazg4dXVVZqmIfiBRKTp1lkF+o5xyuZuHH5E4rEv6brCwMLDB3W945BmFkWo+/ZcK4J3OmXUKTSwWTyxVQuvCZ+osXCIi8dYSr9K+Awehj6SYiDGhNG58+mKwzjZ1+tcwho3ruGR3QRapLFJEELQRtEUCdGQQpJm0CRVwKEXFlGWSsZxtQzIYigmjt2Nwxpx8RlonZFEMSf1ajKDYJtEbKzMJuo1Tppn+QDZZtYncP7WB1SA1dVVuq5jGAbqu3/evr1B061x8uxHpZGzQDXLuIIdzahR1s1XvEBOmqnDuLuHXJWDG1hZU3jYaXuVq6hl1LoL6xiRca4K8w9q6T7uXAHX95KwxixrXrJW45p2Qmlls50qFIXkceJdoipZTIIMNG9IIeOz3hyqT8y1o2fuI3FIDL020+oFMEamgVdH0kd6ANCBB5sW9DUIBQzgtZRsgDQE+tVOClXIOQcfZHFVgj7B6f3wxgdRgLU1WS5XMv9yd7Dee4aUmervS+PkWF+PSlwU60v6uyxWWdy9MYviUNtVI2UqbNS9G1WKEkqsCj5F+YrqUcqwxxAWTF/fa/6gyV3xTG1j6KaNVCFdlR+giWgSq8pRBIIRTx+9uvGUSIPu+veyNsYHEbqfByF9vN7VvEBBJ0SPbeSewVhp87IFG4u4ZSE1koALQsl63ZLeuyBicmBlbUVKyCwINkrC3IN/j26ge1aAchTrL1zAzetXuX31MhjHnMXoNXkxex/LZG5fkS4of9/tLAcXRFBKtEYTw7JIyVotFqlQSCp4JE8IWrgZBlG0+cDYzJmyNqR2UnJutfxsnYSlrPlHQiw6sYCC2WtNIouXSlEKQvMQiX2mD15Wx/hI6BMeWetKI+RSO+mwraWxBtNYGmPGPka51a8dIScIIkhWXiNrH1tZQiV9BpIk5pxobMI9wNgj0Og1hoaQPA5484fI9L52BJU9wRsbGxhjuHH1Gs10lUNHHmUrwdaWjmMrREvanWIBNGnr2sUMQFPgWVfV/o0KG8ZdvoXuDFHCSG+BYUHv9v2i8cMHxoGTkVk0UixCm1MbI3CwdI+kVtBL48RrlPpBKsgDEXwYIoP3zIdM33tCH5kNeoNLxa22caw4h12V7Z7GOimGWav8uF5PRANM0lvBJWH5vAeIWqAKDPOkiEB6BnNMRCvj46sTx9p0gm0sKMmWfRhzoJAye6a8ZzfQfSnA1tbWCAPn8znGwLXbmyTTkE3m+k24eZsxAxf3usD+rZN369zCjReLrxECsCBlCmsnT41TPCWBK0JPecEbOAOTVc1HSugwO/sA9C3E0jpk7bqSPaVu4IPQxkOUwdD5EOn7oD0AMp8vN3U0NJMGZxxta/U8HE1ThUBKl5Qkc1E3U4y4f0CVSMfGBgkfPgnTGEFWw7aWdm3CrknLZNKytu5YaRpuGscwzzQWBidiNTaQ8g9HAPesAEX4pTlUVsO2XLt0kc3b19me9fgkF7ttJY5jql0+ZUS8uPYsSiA9dBp30e9ZwL3C6Ye0EH5BCrAIJa1+lTbwokejsE1VFdZ4Ps7ga+NK9Lo9VNvAZ3PP0HshYkJW6KZs5dSx6hrh762hNZakRbBS4YREhyWYpD16SZpkiORQFkDLYEmMge0+4Qcv4TMKhreuYbresTpp6DrH6kpLO2noWkPjGiYtuKnl5pWIs4Y8eLnYJpA8ZJ/JP6QQdF8KUCaByl0/27YDEo1r2b1nD7umYNdZzOIXN44m6XX2r0IoQoyKFnJeWB8oJPQLurZxQvK0DUx1pUghmLJjsec/M45xleSocEZ4vSdQUOwftZNoDjPvmc+FeZO/TxgskxWDk2CNNXLvP6MbQoHFrKaFZDIuwJAsXpcehSTdQvMQdEZRyCUfM75PWlKWewK3U8felYZp45iqwNvW0Wrfn8lgkuwa98HiZonOZRKBWPBfygwp4PuE2/1jUIBS/9+1a9d4x5A9e/YwWVnlwSPHOHJcihG2XVhaTvK9L8IvHR9IXmDywgqLoHX6aazAOW0D75zE8q70DWp3Uc3yRRWAQXMABcYlk/dogUihYD/IPYJ9SAxDYPABo0Md05VWSrDOjjdnKodBYmuJOePdvJMUhWQXcSLp7eX6GPA+E+by/XyI2JhIyN2+1tYcbTtlOrV0k5aVlVbzIxGNMRaTRNVKMgryWUNOWj9JuCGzPQTdb5yxITPf2uLBlX0fXAEOHjw4wr+UEn3fs7a2xtUrVxh8oJ3oxa9MLaMdPHERo7MKIaBJlRZadDm31AkcNBNY6cSbtJ32ARgovQ7LrdrF9Y4Fm0IqobDPQz8Xa+/nsvtPuAzRmqZ1TFYaLJZGHJtQ1XHBHhbvlHVT2pAz5DBOKeUcmc/ldeczEXrvg2wS0VHg1jpW25bJXse0a+gmLdOpo2kbJo2VOobi99IYGlEFMxJjTZAkkBAkIXaJXTmx3kZu3vYkA53JzPuMTYm1H9IMcs8KUO76Wd8IOsbIrRvXiN6TTemULSVLdvTrhajZdGAkaYzWAVwnyKBtNWFsNWfQApF1mkBXEh/xOYwrXROMu/78XN8rLBo/pEAl83uNM7RNS+MkHDkNWaiwy2RV0AaMEFkMZyaIunLF+yxbPHrPVi93Pw/zRI9gU2cNE+doViSOT1YczbRlpbU0ttFzNCRkWsgYkA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kEnFToWYScQoGpCR8SISb9m0ROo0AEGTVgTMutuBC1A4Yi9ZEDiiQsEcc7L9+nAlhr+a3f+i1+53d+B+89xhj27NkzJlB1tl0zdDX5cjeBv5d1LwscGENGqQyWn2uhG3Wvk8mExjWEELh+/RpvvP46L774PC88/xyvvvodLt/YYLr7QR49+3E+/jf/K/7BL3yeJ3/qYQ7thRaJnfMZzDbgVg8hQApyMa01dJMGYzUxNVmEUkKYARtFaawBTCbFhTsPSWJ3TCLUGPW8fSamQPBF4IkYGZM/aw1NY3HGYqzFObDG0rqMdw6SvGdD8TYRNMwJG+yIvucSK3zz9edFh7gHKtg5xxe/+EW+/OUvj0na8lEXf4oQ62z/vdx57fKLYsAiYSsuvI7dyy69Jn/6+ZzrN27yndde4avPfoUXX3yRV7/zOldvbLLrwHE+9LHP8jOf/VU+9Yu/xJnHYL/mTB7YTDDbgvlck+nq4mTNxcoFy1kuco6QE0QktS7CijGRM6PlxpiIauXRJ2JKhJCIIeHVvYecCDFjKoFbawTzG7BOHgskNBmygc5BSIZrecI85ZI/4mMEs7MzanvDc3H9AH/4eYEfP9IDGGP45Cc/ye/93u/teL7G/jHGMRwU6FcXgu5m3ctWX1fA3qsMXPPrk8lEk9AZ598W/P3881/jpZe+xfffvsjteeDAw+f46Cc/zxf/zi/xM3/tGR57FPYrbJoB28CNHoIXC0eSbSYt5HYh9DFGS8glG/UGGrcx4JK69JwJUUJDiJmYIjGIlXsfCCERQiTERIxJEkUyJgv0W2ksGItrVNAqA6veJlF5dFPCfcbT0CNJnishIrlF9qdHtJFhvvj5RyqAtZYvfelLOwRfFAOkqWF7e3tMAmsFWLb8OgcAdljzcgyvM/jCCwBsbW7y9ltv8vUXnuerz36Fl771Km+98w7R7ebkR3+epz/3n/Gbn/oFPv4zhzm5G3arNcyBrQyXAT9ASmhAFi/pGvm5CBykjpKz/G3OQFKBK57KSTxAVGHnGPFJ4vcQI3GIhCAx3PtAiAmSYHdMxmJxnVo6FdmjiWHJ5UooN8bgsiSK0WRsNqKUOeNzBNPhUhhpfxq0IKBaECOta5iv3IcC7N27l8997nOj8GuOv+97tre3x47UYvUF/xeXXmPsUhGriR5jjJAfVqxAUENDSomNrS1ef+01nvvan/DVZ5/l1e98h+9+703SZDePPfUL/Pxv/3f8w8/+dT7+sYbjQKPCmwHbGa4gtLiiISyS1JWs3FS/y3Eh8JhEECmDTeBVAWIS6w9eYroPYskhJsKg1h0Sgy/Kr32AGFprsY2RHMGpwBPkHZ9iEZWTunmriCHlkmvoe5eiVswkZ8ltJBsRd1axJ6tqFCEZi7eZvQ/chwKANH4UDSxsX9/3zOdz+r5nNpsxm81GS/fej8Iurrxm2JpGhFsqY9Y1NI0jhsTt27d45bVX+eY3X+Yr/+L/5ZVXX+H6xpzcPMC5T/5bfO53/wFPP/NJPvOpvZxg5EsIGbYQSy+Eh3pnuur7ctQoqVz6WEwuLR5D0BgfRDFCkO+HEPE+asIWReA+qLcQoTfOQitu3NrRX498DxFSowLGKPYXDqAkljGp8FMi5kyKiRwSQ86kIeFTxuVEnlrcZEIMdjwvR2S0fwchgUsN3x/uUwHKUQvde898Ph8HMgrDNplMRosvyVlRnpqFs9ayvbXFjRs3+cFbb/P888/x7LPP8torr3H+4gX2PXSOj/3S3+B3fue/5+c+92Ge3Av7qnQ1q8D7Soh6nuNJFYEXZYjVz1UEGMm3FFXISYQ+DPI+wwDRw+AzPsXR0oeYyEFgHEDbNMLll/d3Ep9NssICpqwJZNakriiLvI8ApQUkTCnjQ4SMepWoz5dQnDHG0jWW3DRsZkt0JX5Bto6WyFgj6jN2V8e7L74PBdja2qLv+xGaGWPGmjssunCKsIvrL14g58zm5ibvnH+bb7/8LZ79kz/mT5/9Y86/e40+NRw49lN86Jm/xt/97X/Cp37uYzx9GPZWAk9ZkrZS5Sx5jtWTqC18GdYUgTfs9A5Bn4+psu4E3kueEAL4AGFIEtNDIo2JG7TWQleUO49vlg3q+g0Z4QuabMTDpGLtmT5mbMpK6GRC1LatCN4nUo7EmAlBPIp1hpwMTQvWOpw1OGdpHQTb0AQI5SJYUSinRYFsIeXIFTuB19+HAixj7VEwivWLcpQwUDj+N9/8Ac/+8Vf4ylf+Jc999TnePn+BrXlg70OP8cu/+SX+48//TZ759GGeXIHJksA3VUC+ErBjkdgWj73s2uv4Xqy7KIEm7wRVhhhU0F6tfIAhQRgEyqUk8A2Ev0/WYjotyCCCF+sVT5ABYpZELkFKBlImKGmUciYGhOVLiXmQ5HGIieCFBIoxapHHYJyhmwgUtNYoFDRS1dPKYNcZcjT0NROoFyM6oabkumT8Jrzx5cUVu2cFKO1UtfBzzju8QoF80+mUS5cu8fu//3v8r//0f2E7dpz5qV/mY7/2D/n7v/wrfPwzj/L4CqxWAh8y3FbBlDSofLgVfc5WilB7gCL48nJF4FG/L49hSfCDF8GHAbwSN1H/2drSp2cXULC8V0qSEOakVg7GZmwywuoZKdSklIm5QMIi3MLsRaISPoUYwijJ1DY4Z6Txw1pVBPU0mskWVtGhSapFTqLmaZzCVSlBMA9gl2ZH7psKXkYC3vsdRaCu6/je977H3/2P/kO+/Z3v8at/73/kv/nyf8nHmgW8AugrgY8ngrBwTSXs8lj+taifY6EERejl5/Kavghbvw/q5r3G9BC1LJrkddsWOnMn/tdwS8yaJxhLtoIJBR4mTdQyIWuYCIoQQmbwgvtDFISQvGD/TBG4xU0Aa3FG2D0cwg2MCcXiXHOp9+dMMoaQErhMNs2Yj5TDtYyNoNbEOwR+XwpQ1/6992P2v7m5Sd/35JzZ3t7m7/+nX+Lb3/kev/d/3+ZLvySTQNtZMvRaaCV+F+Fb3tu92+p/aw9QLLy49SL8QZ8PaGz3IsDoNTw4aC1MzAJuGaMZfxG8fp80KSzeJ+fC32tDbJT4Gnxm8AILB0UIPkgZmADZZpyx2Ck0Bfo2Rs9P29cwYPPo0rJldGFZw01CE8cAKQesyfjcYFpwmiSVhHekASKEZElLrWL3XQ0sJeAi/PK1vb3N6uoq/9f/+X/w3Avf4B/9z/+aL/3S+gjNagGb6rE8X8fxZaGPrnfpq1h3yROKpSc98aDakY0It7HQNSpofaMUK6ZPtcomvYCV68nKAcSU5StKZh5ixIeI70XoMWb82LcIzhk605A7iyVLG5dxaD6otXsE9o1vZoRksorflQHESy4RvUJCL/QxMcCuiSR6pQuoZuwD8ve2IT24U573pQAhhBEGzudztre32draGuFgzpk//MP/nSOPfZz/4u99erTG6Q8R8vIM7w5ihkXytmzxYyyvvjKM9KxxMHVAu3iv8tq1heM0WYsLxcgoy6chY0QIJX4PgSEkvCZtYYiiqFk6d1ZXOglrpSl16RxLHcFlDQWuFIoUPWCkJOyz1g+0buATIWdCDEJdZ8kbOjJuLE6wUKpy2EwKkJqGLb/zs9yzAnjvR1dfWL8y41Y6cy+8e5GXX3mNf/K/Pct+/QxdOWnujNt12XpZ6OP7FqGxEHz5eTlEWBhr7+Wow0W5JiWu5tKLUdy+eo0UoA/iRZKHPiRiiAwhamyPQhOnrM0ejSSNRoKEtYVqzqNilFqC9G9lLGLNJBV6gpCFE/RevEpQ2FnYRgUjWGPoWrA4ms4wdY6+sVr4CYyUZ3XkFMl2hee/svP5e1IA7/1I+Rb8P5lMdnTrrK2t8c2vvwDA5//GJ8b/LbRkTb7ULpyl7+usHUQBqP6/xOHlRPFux7Iy1XlEXdwZEUAU3D8MkiD6QecDQiblpBpn6LpGK4NC64qWWYxEe1LOGCuuyKrUamEnkwQK5kzwiaQFJKGRIz5Ip0828j9jGdg5RQcWawyNIgNnYGgMOVTmZIzSwEAAHwJmT0u3tvMa3ZMCtG3L7t27WVlZ0bGlOOYCpQ7QdR3vnH+H/YfPclahxg6Wrbr4dVyvsXmx6vpvayG31fflsRbw3bzIssKlrJadlfDRSqDvpYEiRoghjf+LtXQdGNNILpEAI5aajFq6tn6F7DApjQllYe28YsgcIj6hdHlmCIEUpQ8gpETOaTTexjmhyRtorMU5dVulFFxINyShTLSEBKY2h6AZoINkpa/hjX+1U7b3HAJKbR4Yufx6EULwnrffeZt9+w8x0f8pCVn9NbJv3OkRDDstvFg5LJLGGhKWCwA7Far8fEeiqEWcGKFXK09ePEDS0NE04FrtvS+hoiCBChbm4o9NJllFSIrpx6GXJHE8pAXRE/qAL/0BMY3xqHMWnMM6i8PQtAUd2EVyyCK+ZYCUMc4QsjB9yv9WV0czrBAZgqHLwD+rA+T7bAotjRx1TSAEz/e++10OHz9LGUwZ9KsWfPkqgqzdeQ0DCzTU095xLAt92WuMSADwhdVTijcmhYJC0GEddK18hqxJSkZgoYZxYpYOH3HvWhiyhqxkT0KInhQX7Vt+SAoJI2GI+JzIGuuNMbhWS+A61eMMUg3N5fpYjeVZQo3mEVpMGPsL4yBnbw046wgxY5ezThzJRHGhS8f7goHDMLC5uTkigO3tbXKGS5cu89hn/m0CsIEIv2Tr5TNZdgq7fqzjeVGQWp+XY/oyzbsDCnq1dhVY+T9nwa2ootXkSgUFS2udQSBhAuX3GTuAslp7ULw/aN1/CJHYRyJJ47u8T4vFTg0GJ4JWgduC9XP1GfXkskmL6qIWigIZgnQa+ZzIIWJDJO0TvmXkDYBkFyNC87lh/S7J0n0pQOH9NzY2mM/nowLM5zO2t2Zcv3mdAwePMEcKN+Xta+xfK0Bx6e/F9tWQkOqxuPQaEgYWiVyZhk7ILFwzrWCoWnnSC1Us3Kjl4+R7r/EjwFgl9B4tzgjB0/fayuWjKoM2u1iDM6X8rX3/ijEtjEMZ5RjbwTOLOYjxswlEGWIiR4WAKUv/YMgYIiZBty9AbmkzhFHQMiEagUljFk2i1XHPCpBzHiuCs9lsbAaZzWaE4Lm1cZvtrZ5HTp8TWpVF0lZ/wU7h18/fzbXX7j2z8Chj8lhYOgPGCrtnSxICd4SPqBZnI+QGTFSBK/WbgkLBtKgN9D34mIkhMO+1HJyi8v3SyNJYaCaNNHxobNYRF6IyTIWmdUk9SpSQkICkY9xBWoUZguYMIWkTSiDkjA/CEhirq22alqYxWBzbem0jjGEgW0fOMG+BvXfK9Z4UoJRyNzc3x5hfOICu61hZWeH69Rv0w8DpJ84yASbsxPy1QIpQEotMflnoI5XJzgQyZ7l4VgwNKy1079kDUCeaCUnsIuoqFf9HJYJCrKCgVgd7nxj6MHbwppjBGVrXYBpDbvQccvXOWYicmDMmgbPSumXygvAhaqEoC+5PMSuruGgUDak0mQpj5ZxhtXW4zmCtwzpDZw2uhY0silXnV+j18iGz1k54/cqd8rhnHiDGOPbulfp+af9unOP177xBNg1HTqzsEMRy1r4cx4sLL78rbn1UhCouOEToDWLxJaTckfOw8Ba1QpSkrnD7Pixcu9fiUN8vWL8QhOFzFoxzOAtkO87sSTPnYngjJ3k+Kh1pIkTUyrMojwgkEmImhcg8JOKQyCnRR3mMUYZDrTF0ExF048oOAiiVg9I/aK3DOIPPmZLr9fW5p8jQWc5//87rdE8KUGr7BfqVxs8SApyzXLx4nunabg7uWeD6WuCjAJZ+Vws/poVXMFaxfxF49WHrEFILfJkDqHmIqK8fg5I8XhSg9AOEqLSvZp4NlrYTJ17IHqv8QUYFGgzZGAwJF2HQNq6kLKE0dEhc9zETNGcYCtOno12oJ3DO4roy6GJxSmsanKDFUgO2eTz7xmiTqXMknQeMCAPboylPgj0rju6DooAyE+Cc27HXDxrOn3+btfX97GIBwwr0oxJEQluuVCNiLhYm2lznDqVaCAt4eDf/h7AqAAAgAElEQVRIWGN/2EkoFRg6zEXgXhPFwvGjOUGTFwOTpf8/GsZEMSdJrmwURTIYrM34BDkI2ZODFopCZMiZ2AsqSD7Re20h0+kfkZnB2UaIngaMszisKJWySaY6sVG51YthpHnFGVEo06oCBw0FVq+NhcFC2LxTpu8LBtY9APP5DGMaLrzzDg8cPMIEqf6V0u/o4tXKSu3dWTAtTDVjbdmJEspREMRC56vPwk7FqpPEgFj5ECENktXn8v4GWu0MxuqjsnwR1GWrsK1avQEblJpOogShWHEUS/ZDpA+ygCENKvyYR47fGYNtLa5pcFm7NBotC5dmUIX/DiPhT5UlIV4lAwTpO4gxY7NSxu0KkUaKQl0cXWtE8ptZgG9/+0553rcClKLQzj6AxNtvvcmuAx/Bs2jWTOpeHZJxt06E3thF82ax9GXSx7FT4Mu5xN2gYEIsIqml5yRe01iZnjGSS4kHdeo9FOJlxBOk8j8onFLcH+MCYg4pE+aBvkBALxn7PASil6HObME6S9PAxFqhdY0UckouogFGT9DpPGGWUJWR+kMqP2eSFoWGKHmDDxmTA6Z1rKxAixJEUYpChT7fxjIJ3MEC3rcCbG9vs729zebm5kgAee/p53OuXb3ORz92Eq/Cz0kGLppmJ9mz3PRRHn9YTC8/11ZeQkxABF4Su2Q0d2iF5TOg83klC1eL1hdPTn6f9HVM0tdMigr0MQzgh0QfCvEjhM+QdJwrZ5yzTJwhGZ3bsxU6qNy4VbpRPrMhGe0XTFp0isI35CwDJlIdTIRB5wmzFJ2sNaw4Q2cbjHOEAHZcCdeQCKQAg0LJux33rAB937O5uTkmfvUGkGEYuHbjCuvrh+gQCIi9E+9TPda/q4Vcx3RYxPMaLYz4X8/VNmCanR5FjXz0FIYqmUMtP4s38Jq4hSDP+9IoGrVIFBLDPOCTWHjU2rt10r83NbKzJyOPgGD/KP2Bpc5vgJwTMelGlYTARW3YyF4mi7zXqqBP0hGM8NDZSh7WNR2tk/fqOujalk0iNuu1y2i8laudXMO+ihu5bwUo7N9sNhv3+dTrXN7te2azOac+/DQraP8dd7rw+lhWyKIItcBHSFgJ2zjNH9SdlIQR7uwvKM+V1y6KEOKC9PGpQgHaDj546D0EneWLWs2ztsFNFH6BupadmDuZTA5gnNEkLo9l2jBOA2supS3gIQbmc7HsGFToGvub1uByi+sMjXNYB41R32kMkzYT2kYKWzjJSFF8CIIMWkOshkHq454UoKyCKyig8ALee5qm4d2LFwghc/TRU2jifAc+XyYoynM1RPQa1EtrVjZC3LhGzudubWR1k0lNLNWvj36mnNWyFQ4OWi8oxE8pDecoBR5rHd1UIZiVhUrRgIl5LAZl9QZJewFMECUQpKOdOElInlL2jSEx7wM+ROkY1uESayUhbDvdCm4trtFScAaMtIYLZpTzcgbdFyBdtyk3SA/Y4hqQDbuO3l2299wPUC9OLj0AMUbapuHiu+9imgmPnN6zQ9B3w/+JRQxOirvrVmxjtGDT7oSDy7WD5bBRHmteoeQLAUgehgChFwUY1Np99Q/OyVeZVaxfP+ZFUhmNESrZGlWsNBaKhpBJJLJP9FE2e2z7SOwDPms/X4ikwnk4FXixbmuxjRI91pCywY77gvSjGqvKlwg2E7Ml2bzoeLFFCQRShABvv4ds31c5eMccQIxcu3aVECOtXbj/Ha48a0WuECl60QsSshaaVhLGUkdY5gGKYtUXonxfh44aGchUz0LghfRBE0HX6FQw4x4FUNSQYsUcRskVkpHagdPvQxILD2TSIO3fQyy4PxH6yLzkDVpxssbQto2UgDG4xtI0Wga2BlM4aj0fme00Y1UwaQv62D+YAqEVSjqFDNbobgM5sZAS07UJ/bW7y/K+FaAshSqdwMF7Ll+6wgOHjrDngZ0Dmr6Xi1dgFEjYbJ1k6M6J4LV3U36vj8W117G8juNF6LCz6WPQpo/C9tXNHMZAuY9EPT9hDNrjx0g/2yzWXlrSknIDSZGB9AVmBsX7fi6NosIoRuIQ1HsYJq2DKVgjsNAYN6KTbMFmQ5AIDiZjotE6QSZrFimeKgoyUa4h+ATB41a1ABYNyaQdJxd9pusc//Llu8vzvhSgQL/SDby1tUWcTrl4/m2wDh9hw8LmNuPwQnHdk06FbqFR6FWPedXZf+3Sl8MILCw8AUFdXAji5qNat9GQIi69uiYKDUa3nlXgVj5zUdRxl17QVjGtDPohitB9pPeJ1AcGnfjJ2rzROku7NpXzNaIEMs1jxjJdSWozhmwzttDQCQa06BQhxciQ5T1jiPgY8X0mk4jAmpFQUEitUuXKBfsWyMvGB1OAGgkU4fd9T06J25ubPHT0NE0rrrY1QKexHCF/ai6gfNY6KSzxvUYHdZyP1Vcp2QYlBDIi5KzDHlYVrEzgpliFjSykVEiC+ZMBUxRHFWCsClbIwPtAPwjb52OZ0s2yEawxTKz0+mdjR7e9eM+04B0QZCCGnUlJ6gVkCRNBWcUhSDgJQ8THTA5l1NtiGsO0aYQHmLY0rWMTMQZJF+xIdCQHkwQh3XmrnntWgJQSGxsbOwRfGkNN47h86RLTtWOsAb6F2C4WFZVYfjdIWLJ2WMTwohQj5s8LUiYs9bS3rQpZhz2W2cPyHqZhpHczamlZmb28aCYpnmReEEGfGYZAHyMmZr3AmaZraLSlyOw4MStjYRpuci6j3JYckyaSOiCa0oj/UxAK2WsZOPVRF1KICtnG4FY6WmNpJlIldMZhGlhpMnPTklIhnuR/yo6j5Bv8Lug+SA6wvb1N3/fjOri2bcd9gCsrq8QUefTUh9mFTPSWNKYIH+7E57WA6kQuKQFTmL0suROmUXbPisDrPsJl6FfnCSMHoFl8mf+PGsvjIJg/DtBr3jB43ctnEtkYJo2DiWHFaJOHLmxOMWGMlSFRhXPGWlxeMG8yICrQ0utmsBAyYQj4lBiGslWNkes3VvKGxtZlYAsuY9Al0Vo3cDbjGifeK+SdLhZIVtrc71IGuHcF2LVrF03TjE0gMcbRCwQfuH17g737H6SrBFE3epQYjgoBjbdkxmpaccGZRUY+ooNW+QB+dLNoZjEYk1kIOyOIYFAOwOsoeHHzZS0MQNsa6JoFjVy9fqGSUwaLGxm+pH+QY5JlUUG6ejKZ+SwScmaYBWKWMBJ131+ICecsXWtpWsH5jXO4RjyHsRXxRInnwpFIgmsgJEkhuyCVwJIdWwg5cKAF/vGddQC4jxyg3HyhcAClL31rtsnm5gYHj5zaMb1Tu/kcFzBwjLVp9HBj+bVtJGa3jfAANfFTJ4s1tVwUrBBQNfaPWhTySvgMVf1fp7FB3xcYL3b5TCUhLFNXUfMGMyaK6sp1qKMsc5BETWJ3Pw/jVLBk9VnKvs7STHTJQ+MkYbVunCoa5xfLsWPXoCIgH7EOBmehkSQYWFh/lM+6+R4sILwPGFgvgvTDwI3rt5jNPQ8eOjJe+EK8xAxpWNTeo/rnEredUQvXopFxkkDWXqy29pryLaGjxv0ZydhLs0dZ/OBDqeHLezctTNyCdBJh7oSMMcpnKoMkaIIVSpIYBJL5EAhDpk+RYSbIIAxi6SHkUbmb1tE1BhrZ2dE0riJ7NG4nMYAyB1A2giaAkLXbWZLG6D1DzmQ/0K7tgj0LL2T0/4yF1DXY9ygE3bcClEbQAgdDCFy7comN2zcwXcsmsDVI1py9FlkUrzVOY3dTCd3Jh2ydkh7stPCa5q2TxeLhCulUpoDnw4LOjQmZ8rXS928qStmaymuowAmMxaIY5W/G5FCVNwwQYmbuJTvvveB9EXrcMb/XuoaVFcA4bXgxmGRwJpNcBc9SYUAlgIWweI2gNYMwyH6BxWKqIHlSSExNxqwknPYcjG6jgbgt3+65OwC4PwXw3o8wsEBBaw3Xbt6iXV1n38GHuBVhe0sEYBBI1k7U0jV4twWiKUYvuUIRfmIxTxir5+o2M8+iVBsV/w9xQfa0Tt63QMHCAxT3Pi581De2CWKjuYgqVGkdi1GLQ0NmmA8yCu4leYspSwnWJGzbyPq5VgRusWSbR9o+lJNEmMRI0nMTfz6kKLxDzMSc6OdR8oe5dPsI+SP3F7DG4hrHdM2x1hnMdCINOEYo4JzkIqUOwiyPivC+FSDnPMLAYv2z2Yymabh04QIbt2/JsIOSPE0HnUrUWunNp3AgKgTndiZxRdg1n1+eLx1FfVzEuZFZVFax0wmfO+BmxfiBunizE2EM2iaWku4IUgq599D3QTiAfrGePVlp52o6x6rRVS7GSteQFfwvFcwsHH3OMmCSNYanRET7ASP0OZNLN9GgiyV8lBwjqqFYx9qawzUNbaM7g7RLOFqY5YRJ2mJSLkKUH4Zd7y3be1KAgv/LWHgpB6+vr2MM7N33IA8dWaEzYNYY72JRLHmM3/qNQays2o2ANYuiUE6yMyirUEZhs8gfuqkolnE7PQkskUkl2cwaKvKiNa2PAv8G3RPUB50B8Bk/SJ2jzOfLYkv5AHXPf85pJ7uo72lMJluZEYgJiLINLKQk7WIx4wfPECJ9n8k56pIoBPo5S+sstpUmE+taRQZl8aa0m1uT6RsnHiZFguyWAaS8bCcTHjz0ARWgbP0CuYt2uUvI3r17uXnzJu3qOgcf0jVsunChsGwLKrJIRC6+QRYb5UEvWlw0ZtR/21glfJzyAM2iSFRzCzXsHLF/ldDFokhJ8oSZWvkwLKw+BkmwcsqYFl3WZCnrW8rURSIrq5dIyZGRQY0hI+1gSTt3QmbIELUL2IdIPxdLj0MmRekHwEmO0K00NMbhOktrHa7RBVRON4oqs1qup2FxjccnNENKyUoTsYPtH3JX+XtSgD179rC+vj4uhSq3h2mahqGfYZWcKMIoY1b1bp1YKoBxYeFo1l1KqSVDbyxYrQ62jeYLdoEK6rpAOe+CCKK+b2ncTFkrgl7eM/Qw79XyS9lcc4euczIRrHnKKPCCuT2kBvGxKWOieACBtjK65YEwJGIMzIeEnyeG4KVSOEhmk9HbvrUN7arDtWX9m6PR0q+xSGtZOUkHprxXEiU0WRZNzFpInSP0Qe5NBBirOwhU2T+QAgDjitf6/rfDMHDhnYscPnmWdYQFLBi7JCJBL1yZzh2JjLyAYdZBu6I8QCP5g+vu3gq+jGiKMhTXm4IIOqlrT0HWo3ktB5cE0LjFvqAxH9E3NBGi0ZpDo9g/6XP6/zFCJOqeHhkdG3rPMETm8zDuC04hkozBOeimDR0NthHrNs7SINs+kzU4l0lVHG9jJhqk0JT03GOqlldEGAbcAxNsI9YeghjOkMHbzOp6w5rjPY/7goF1O3jpCXz7nbeYrJ8hoBx6v+i6yQWSaQpfRrjEvaqFK7XrGonpVum+u/H6tcAL/s+xaulS7D/0mnWr1TuNEZ32DjoV9g5vkhbCLTODWSFI2SISNDz4mAizQJ+hn3tCiPRDFIYv5lFJu9ZiOpkXbJ2VtnALyYjw0amisTCWHUlpZZNhnkXgPsh2Uh8jvSak0cusojORPXs8hqkwkw6CjzSNXoMI19/5MShASmksA89mM+bzOdY6pTxnbAC3t8DPJNkq2bqzigTUnTdWGzFcBQVdVTAq7drLQtd4rrmO4H31KqX9vJR3Sys4HewyIvRSLEoO6ffPi3xhXAePCH1cFxMXcNAPmX7whJjp+8g8RvI80qc0ZrK2a2W+wckKV2PEuo0mg1DlKxnAavKbNNmV+D1EvaFEH5mHSOilAhn84jZ7xlm6qWO1a7GmJWTxUBigc6QgHUkksGVR0wdRgI2NDTY2Nqrt4NsY4xhS4sDDx+l72J6BCXLBJxMlXpQDcAoJneJxoyZulbnKVi1OM/6yqLEgAK9Ucu8ZFzmXJY+oknWtvl5F+CzXJEjiKgt1WEikWGhqr+ggFPwf8X1gPsRxFXwMkuXTGFZdS6MWbY2R+O7KIojF55dJ7aSKnEeFG3wgR00WB4GBvQ/SCu61OTQnHBbXOlZsg5s4WtvQtoaug9TqDuVCUVuwOWEtbAf44+9+QAXY2NjY0Q6+vb2tlPDA1Xff5cynH6KbwOoKuIiuNV1w/HK3SsbW7LHHMSpq0A9vqwtWGDixvp00bVGQ1unsfycbPo1lx5YP8iK5lKxd/j9oIhoHcfseiL0khb2HYcj080iMnr6P8lrGClc/FWTQGKn8ZQy5bOgOQnbkkEhWbkePybKkUlu7Q9KNXynLUoleGMVB2T7K8mhkN7F1Hc4ZJl1D07pxqMVag02wYmB76kg9i0HaqAmxh8lUcqAPpAClDazg4dXVVZqmIfiBRKTp1lkF+o5xyuZuHH5E4rEv6brCwMLDB3W945BmFkWo+/ZcK4J3OmXUKTSwWTyxVQuvCZ+osXCIi8dYSr9K+Awehj6SYiDGhNG58+mKwzjZ1+tcwho3ruGR3QRapLFJEELQRtEUCdGQQpJm0CRVwKEXFlGWSsZxtQzIYigmjt2Nwxpx8RlonZFEMSf1ajKDYJtEbKzMJuo1Tppn+QDZZtYncP7WB1SA1dVVuq5jGAbqu3/evr1B061x8uxHpZGzQDXLuIIdzahR1s1XvEBOmqnDuLuHXJWDG1hZU3jYaXuVq6hl1LoL6xiRca4K8w9q6T7uXAHX95KwxixrXrJW45p2Qmlls50qFIXkceJdoipZTIIMNG9IIeOz3hyqT8y1o2fuI3FIDL020+oFMEamgVdH0kd6ANCBB5sW9DUIBQzgtZRsgDQE+tVOClXIOQcfZHFVgj7B6f3wxgdRgLU1WS5XMv9yd7Dee4aUmervS+PkWF+PSlwU60v6uyxWWdy9MYviUNtVI2UqbNS9G1WKEkqsCj5F+YrqUcqwxxAWTF/fa/6gyV3xTG1j6KaNVCFdlR+giWgSq8pRBIIRTx+9uvGUSIPu+veyNsYHEbqfByF9vN7VvEBBJ0SPbeSewVhp87IFG4u4ZSE1koALQsl63ZLeuyBicmBlbUVKyCwINkrC3IN/j26ge1aAchTrL1zAzetXuX31MhjHnMXoNXkxex/LZG5fkS4of9/tLAcXRFBKtEYTw7JIyVotFqlQSCp4JE8IWrgZBlG0+cDYzJmyNqR2UnJutfxsnYSlrPlHQiw6sYCC2WtNIouXSlEKQvMQiX2mD15Wx/hI6BMeWetKI+RSO+mwraWxBtNYGmPGPka51a8dIScIIkhWXiNrH1tZQiV9BpIk5pxobMI9wNgj0Og1hoaQPA5484fI9L52BJU9wRsbGxhjuHH1Gs10lUNHHmUrwdaWjmMrREvanWIBNGnr2sUMQFPgWVfV/o0KG8ZdvoXuDFHCSG+BYUHv9v2i8cMHxoGTkVk0UixCm1MbI3CwdI+kVtBL48RrlPpBKsgDEXwYIoP3zIdM33tCH5kNeoNLxa22caw4h12V7Z7GOimGWav8uF5PRANM0lvBJWH5vAeIWqAKDPOkiEB6BnNMRCvj46sTx9p0gm0sKMmWfRhzoJAye6a8ZzfQfSnA1tbWCAPn8znGwLXbmyTTkE3m+k24eZsxAxf3usD+rZN369zCjReLrxECsCBlCmsnT41TPCWBK0JPecEbOAOTVc1HSugwO/sA9C3E0jpk7bqSPaVu4IPQxkOUwdD5EOn7oD0AMp8vN3U0NJMGZxxta/U8HE1ThUBKl5Qkc1E3U4y4f0CVSMfGBgkfPgnTGEFWw7aWdm3CrknLZNKytu5YaRpuGscwzzQWBidiNTaQ8g9HAPesAEX4pTlUVsO2XLt0kc3b19me9fgkF7ttJY5jql0+ZUS8uPYsSiA9dBp30e9ZwL3C6Ye0EH5BCrAIJa1+lTbwokejsE1VFdZ4Ps7ga+NK9Lo9VNvAZ3PP0HshYkJW6KZs5dSx6hrh762hNZakRbBS4YREhyWYpD16SZpkiORQFkDLYEmMge0+4Qcv4TMKhreuYbresTpp6DrH6kpLO2noWkPjGiYtuKnl5pWIs4Y8eLnYJpA8ZJ/JP6QQdF8KUCaByl0/27YDEo1r2b1nD7umYNdZzOIXN44m6XX2r0IoQoyKFnJeWB8oJPQLurZxQvK0DUx1pUghmLJjsec/M45xleSocEZ4vSdQUOwftZNoDjPvmc+FeZO/TxgskxWDk2CNNXLvP6MbQoHFrKaFZDIuwJAsXpcehSTdQvMQdEZRyCUfM75PWlKWewK3U8felYZp45iqwNvW0Wrfn8lgkuwa98HiZonOZRKBWPBfygwp4PuE2/1jUIBS/9+1a9d4x5A9e/YwWVnlwSPHOHJcihG2XVhaTvK9L8IvHR9IXmDywgqLoHX6aazAOW0D75zE8q70DWp3Uc3yRRWAQXMABcYlk/dogUihYD/IPYJ9SAxDYPABo0Md05VWSrDOjjdnKodBYmuJOePdvJMUhWQXcSLp7eX6GPA+E+by/XyI2JhIyN2+1tYcbTtlOrV0k5aVlVbzIxGNMRaTRNVKMgryWUNOWj9JuCGzPQTdb5yxITPf2uLBlX0fXAEOHjw4wr+UEn3fs7a2xtUrVxh8oJ3oxa9MLaMdPHERo7MKIaBJlRZadDm31AkcNBNY6cSbtJ32ARgovQ7LrdrF9Y4Fm0IqobDPQz8Xa+/nsvtPuAzRmqZ1TFYaLJZGHJtQ1XHBHhbvlHVT2pAz5DBOKeUcmc/ldeczEXrvg2wS0VHg1jpW25bJXse0a+gmLdOpo2kbJo2VOobi99IYGlEFMxJjTZAkkBAkIXaJXTmx3kZu3vYkA53JzPuMTYm1H9IMcs8KUO76Wd8IOsbIrRvXiN6TTemULSVLdvTrhajZdGAkaYzWAVwnyKBtNWFsNWfQApF1mkBXEh/xOYwrXROMu/78XN8rLBo/pEAl83uNM7RNS+MkHDkNWaiwy2RV0AaMEFkMZyaIunLF+yxbPHrPVi93Pw/zRI9gU2cNE+doViSOT1YczbRlpbU0ttFzNCRkWsgYkA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kEnFToWYScQoGpCR8SISb9m0ROo0AEGTVgTMutuBC1A4Yi9ZEDiiQsEcc7L9+nAlhr+a3f+i1+53d+B+89xhj27NkzJlB1tl0zdDX5cjeBv5d1LwscGENGqQyWn2uhG3Wvk8mExjWEELh+/RpvvP46L774PC88/xyvvvodLt/YYLr7QR49+3E+/jf/K/7BL3yeJ3/qYQ7thRaJnfMZzDbgVg8hQApyMa01dJMGYzUxNVmEUkKYARtFaawBTCbFhTsPSWJ3TCLUGPW8fSamQPBF4IkYGZM/aw1NY3HGYqzFObDG0rqMdw6SvGdD8TYRNMwJG+yIvucSK3zz9edFh7gHKtg5xxe/+EW+/OUvj0na8lEXf4oQ62z/vdx57fKLYsAiYSsuvI7dyy69Jn/6+ZzrN27yndde4avPfoUXX3yRV7/zOldvbLLrwHE+9LHP8jOf/VU+9Yu/xJnHYL/mTB7YTDDbgvlck+nq4mTNxcoFy1kuco6QE0QktS7CijGRM6PlxpiIauXRJ2JKhJCIIeHVvYecCDFjKoFbawTzG7BOHgskNBmygc5BSIZrecI85ZI/4mMEs7MzanvDc3H9AH/4eYEfP9IDGGP45Cc/ye/93u/teL7G/jHGMRwU6FcXgu5m3ctWX1fA3qsMXPPrk8lEk9AZ598W/P3881/jpZe+xfffvsjteeDAw+f46Cc/zxf/zi/xM3/tGR57FPYrbJoB28CNHoIXC0eSbSYt5HYh9DFGS8glG/UGGrcx4JK69JwJUUJDiJmYIjGIlXsfCCERQiTERIxJEkUyJgv0W2ksGItrVNAqA6veJlF5dFPCfcbT0CNJnishIrlF9qdHtJFhvvj5RyqAtZYvfelLOwRfFAOkqWF7e3tMAmsFWLb8OgcAdljzcgyvM/jCCwBsbW7y9ltv8vUXnuerz36Fl771Km+98w7R7ebkR3+epz/3n/Gbn/oFPv4zhzm5G3arNcyBrQyXAT9ASmhAFi/pGvm5CBykjpKz/G3OQFKBK57KSTxAVGHnGPFJ4vcQI3GIhCAx3PtAiAmSYHdMxmJxnVo6FdmjiWHJ5UooN8bgsiSK0WRsNqKUOeNzBNPhUhhpfxq0IKBaECOta5iv3IcC7N27l8997nOj8GuOv+97tre3x47UYvUF/xeXXmPsUhGriR5jjJAfVqxAUENDSomNrS1ef+01nvvan/DVZ5/l1e98h+9+703SZDePPfUL/Pxv/3f8w8/+dT7+sYbjQKPCmwHbGa4gtLiiISyS1JWs3FS/y3Eh8JhEECmDTeBVAWIS6w9eYroPYskhJsKg1h0Sgy/Kr32AGFprsY2RHMGpwBPkHZ9iEZWTunmriCHlkmvoe5eiVswkZ8ltJBsRd1axJ6tqFCEZi7eZvQ/chwKANH4UDSxsX9/3zOdz+r5nNpsxm81GS/fej8Iurrxm2JpGhFsqY9Y1NI0jhsTt27d45bVX+eY3X+Yr/+L/5ZVXX+H6xpzcPMC5T/5bfO53/wFPP/NJPvOpvZxg5EsIGbYQSy+Eh3pnuur7ctQoqVz6WEwuLR5D0BgfRDFCkO+HEPE+asIWReA+qLcQoTfOQitu3NrRX498DxFSowLGKPYXDqAkljGp8FMi5kyKiRwSQ86kIeFTxuVEnlrcZEIMdjwvR2S0fwchgUsN3x/uUwHKUQvde898Ph8HMgrDNplMRosvyVlRnpqFs9ayvbXFjRs3+cFbb/P888/x7LPP8torr3H+4gX2PXSOj/3S3+B3fue/5+c+92Ge3Av7qnQ1q8D7Soh6nuNJFYEXZYjVz1UEGMm3FFXISYQ+DPI+wwDRw+AzPsXR0oeYyEFgHEDbNMLll/d3Ep9NssICpqwJZNakriiLvI8ApQUkTCnjQ4SMepWoz5dQnDHG0jWW3DRsZkt0JX5Bto6WyFgj6jN2V8e7L74PBdja2qLv+xGaGWPGmjssunCKsIvrL14g58zm5ibvnH+bb7/8LZ79kz/mT5/9Y86/e40+NRw49lN86Jm/xt/97X/Cp37uYzx9GPZWAk9ZkrZS5Sx5jtWTqC18GdYUgTfs9A5Bn4+psu4E3kueEAL4AGFIEtNDIo2JG7TWQleUO49vlg3q+g0Z4QuabMTDpGLtmT5mbMpK6GRC1LatCN4nUo7EmAlBPIp1hpwMTQvWOpw1OGdpHQTb0AQI5SJYUSinRYFsIeXIFTuB19+HAixj7VEwivWLcpQwUDj+N9/8Ac/+8Vf4ylf+Jc999TnePn+BrXlg70OP8cu/+SX+48//TZ759GGeXIHJksA3VUC+ErBjkdgWj73s2uv4Xqy7KIEm7wRVhhhU0F6tfIAhQRgEyqUk8A2Ev0/WYjotyCCCF+sVT5ABYpZELkFKBlImKGmUciYGhOVLiXmQ5HGIieCFBIoxapHHYJyhmwgUtNYoFDRS1dPKYNcZcjT0NROoFyM6oabkumT8Jrzx5cUVu2cFKO1UtfBzzju8QoF80+mUS5cu8fu//3v8r//0f2E7dpz5qV/mY7/2D/n7v/wrfPwzj/L4CqxWAh8y3FbBlDSofLgVfc5WilB7gCL48nJF4FG/L49hSfCDF8GHAbwSN1H/2drSp2cXULC8V0qSEOakVg7GZmwywuoZKdSklIm5QMIi3MLsRaISPoUYwijJ1DY4Z6Txw1pVBPU0mskWVtGhSapFTqLmaZzCVSlBMA9gl2ZH7psKXkYC3vsdRaCu6/je977H3/2P/kO+/Z3v8at/73/kv/nyf8nHmgW8AugrgY8ngrBwTSXs8lj+taifY6EERejl5/Kavghbvw/q5r3G9BC1LJrkddsWOnMn/tdwS8yaJxhLtoIJBR4mTdQyIWuYCIoQQmbwgvtDFISQvGD/TBG4xU0Aa3FG2D0cwg2MCcXiXHOp9+dMMoaQErhMNs2Yj5TDtYyNoNbEOwR+XwpQ1/6992P2v7m5Sd/35JzZ3t7m7/+nX+Lb3/kev/d/3+ZLvySTQNtZMvRaaCV+F+Fb3tu92+p/aw9QLLy49SL8QZ8PaGz3IsDoNTw4aC1MzAJuGaMZfxG8fp80KSzeJ+fC32tDbJT4Gnxm8AILB0UIPkgZmADZZpyx2Ck0Bfo2Rs9P29cwYPPo0rJldGFZw01CE8cAKQesyfjcYFpwmiSVhHekASKEZElLrWL3XQ0sJeAi/PK1vb3N6uoq/9f/+X/w3Avf4B/9z/+aL/3S+gjNagGb6rE8X8fxZaGPrnfpq1h3yROKpSc98aDakY0It7HQNSpofaMUK6ZPtcomvYCV68nKAcSU5StKZh5ixIeI70XoMWb82LcIzhk605A7iyVLG5dxaD6otXsE9o1vZoRksorflQHESy4RvUJCL/QxMcCuiSR6pQuoZuwD8ve2IT24U573pQAhhBEGzudztre32draGuFgzpk//MP/nSOPfZz/4u99erTG6Q8R8vIM7w5ihkXytmzxYyyvvjKM9KxxMHVAu3iv8tq1heM0WYsLxcgoy6chY0QIJX4PgSEkvCZtYYiiqFk6d1ZXOglrpSl16RxLHcFlDQWuFIoUPWCkJOyz1g+0buATIWdCDEJdZ8kbOjJuLE6wUKpy2EwKkJqGLb/zs9yzAnjvR1dfWL8y41Y6cy+8e5GXX3mNf/K/Pct+/QxdOWnujNt12XpZ6OP7FqGxEHz5eTlEWBhr7+Wow0W5JiWu5tKLUdy+eo0UoA/iRZKHPiRiiAwhamyPQhOnrM0ejSSNRoKEtYVqzqNilFqC9G9lLGLNJBV6gpCFE/RevEpQ2FnYRgUjWGPoWrA4ms4wdY6+sVr4CYyUZ3XkFMl2hee/svP5e1IA7/1I+Rb8P5lMdnTrrK2t8c2vvwDA5//GJ8b/LbRkTb7ULpyl7+usHUQBqP6/xOHlRPFux7Iy1XlEXdwZEUAU3D8MkiD6QecDQiblpBpn6LpGK4NC64qWWYxEe1LOGCuuyKrUamEnkwQK5kzwiaQFJKGRIz5Ip0828j9jGdg5RQcWawyNIgNnYGgMOVTmZIzSwEAAHwJmT0u3tvMa3ZMCtG3L7t27WVlZ0bGlOOYCpQ7QdR3vnH+H/YfPclahxg6Wrbr4dVyvsXmx6vpvayG31fflsRbw3bzIssKlrJadlfDRSqDvpYEiRoghjf+LtXQdGNNILpEAI5aajFq6tn6F7DApjQllYe28YsgcIj6hdHlmCIEUpQ8gpETOaTTexjmhyRtorMU5dVulFFxINyShTLSEBKY2h6AZoINkpa/hjX+1U7b3HAJKbR4Yufx6EULwnrffeZt9+w8x0f8pCVn9NbJv3OkRDDstvFg5LJLGGhKWCwA7Far8fEeiqEWcGKFXK09ePEDS0NE04FrtvS+hoiCBChbm4o9NJllFSIrpx6GXJHE8pAXRE/qAL/0BMY3xqHMWnMM6i8PQtAUd2EVyyCK+ZYCUMc4QsjB9yv9WV0czrBAZgqHLwD+rA+T7bAotjRx1TSAEz/e++10OHz9LGUwZ9KsWfPkqgqzdeQ0DCzTU095xLAt92WuMSADwhdVTijcmhYJC0GEddK18hqxJSkZgoYZxYpYOH3HvWhiyhqxkT0KInhQX7Vt+SAoJI2GI+JzIGuuNMbhWS+A61eMMUg3N5fpYjeVZQo3mEVpMGPsL4yBnbw046wgxY5ezThzJRHGhS8f7goHDMLC5uTkigO3tbXKGS5cu89hn/m0CsIEIv2Tr5TNZdgq7fqzjeVGQWp+XY/oyzbsDCnq1dhVY+T9nwa2ootXkSgUFS2udQSBhAuX3GTuAslp7ULw/aN1/CJHYRyJJ47u8T4vFTg0GJ4JWgduC9XP1GfXkskmL6qIWigIZgnQa+ZzIIWJDJO0TvmXkDYBkFyNC87lh/S7J0n0pQOH9NzY2mM/nowLM5zO2t2Zcv3mdAwePMEcKN+Xta+xfK0Bx6e/F9tWQkOqxuPQaEgYWiVyZhk7ILFwzrWCoWnnSC1Us3Kjl4+R7r/EjwFgl9B4tzgjB0/fayuWjKoM2u1iDM6X8rX3/ijEtjEMZ5RjbwTOLOYjxswlEGWIiR4WAKUv/YMgYIiZBty9AbmkzhFHQMiEagUljFk2i1XHPCpBzHiuCs9lsbAaZzWaE4Lm1cZvtrZ5HTp8TWpVF0lZ/wU7h18/fzbXX7j2z8Chj8lhYOgPGCrtnSxICd4SPqBZnI+QGTFSBK/WbgkLBtKgN9D34mIkhMO+1HJyi8v3SyNJYaCaNNHxobNYRF6IyTIWmdUk9SpSQkICkY9xBWoUZguYMIWkTSiDkjA/CEhirq22alqYxWBzbem0jjGEgW0fOMG+BvXfK9Z4UoJRyNzc3x5hfOICu61hZWeH69Rv0w8DpJ84yASbsxPy1QIpQEotMflnoI5XJzgQyZ7l4VgwNKy1079kDUCeaCUnsIuoqFf9HJYJCrKCgVgd7nxj6MHbwppjBGVrXYBpDbvQccvXOWYicmDMmgbPSumXygvAhaqEoC+5PMSuruGgUDak0mQpj5ZxhtXW4zmCtwzpDZw2uhY0silXnV+j18iGz1k54/cqd8rhnHiDGOPbulfp+af9unOP177xBNg1HTqzsEMRy1r4cx4sLL78rbn1UhCouOEToDWLxJaTckfOw8Ba1QpSkrnD7Pixcu9fiUN8vWL8QhOFzFoxzOAtkO87sSTPnYngjJ3k+Kh1pIkTUyrMojwgkEmImhcg8JOKQyCnRR3mMUYZDrTF0ExF048oOAiiVg9I/aK3DOIPPmZLr9fW5p8jQWc5//87rdE8KUGr7BfqVxs8SApyzXLx4nunabg7uWeD6WuCjAJZ+Vws/poVXMFaxfxF49WHrEFILfJkDqHmIqK8fg5I8XhSg9AOEqLSvZp4NlrYTJ17IHqv8QUYFGgzZGAwJF2HQNq6kLKE0dEhc9zETNGcYCtOno12oJ3DO4roy6GJxSmsanKDFUgO2eTz7xmiTqXMknQeMCAPboylPgj0rju6DooAyE+Cc27HXDxrOn3+btfX97GIBwwr0oxJEQluuVCNiLhYm2lznDqVaCAt4eDf/h7AqAAAgAElEQVRIWGN/2EkoFRg6zEXgXhPFwvGjOUGTFwOTpf8/GsZEMSdJrmwURTIYrM34BDkI2ZODFopCZMiZ2AsqSD7Re20h0+kfkZnB2UaIngaMszisKJWySaY6sVG51YthpHnFGVEo06oCBw0FVq+NhcFC2LxTpu8LBtY9APP5DGMaLrzzDg8cPMIEqf6V0u/o4tXKSu3dWTAtTDVjbdmJEspREMRC56vPwk7FqpPEgFj5ECENktXn8v4GWu0MxuqjsnwR1GWrsK1avQEblJpOogShWHEUS/ZDpA+ygCENKvyYR47fGYNtLa5pcFm7NBotC5dmUIX/DiPhT5UlIV4lAwTpO4gxY7NSxu0KkUaKQl0cXWtE8ptZgG9/+0553rcClKLQzj6AxNtvvcmuAx/Bs2jWTOpeHZJxt06E3thF82ax9GXSx7FT4Mu5xN2gYEIsIqml5yRe01iZnjGSS4kHdeo9FOJlxBOk8j8onFLcH+MCYg4pE+aBvkBALxn7PASil6HObME6S9PAxFqhdY0UckouogFGT9DpPGGWUJWR+kMqP2eSFoWGKHmDDxmTA6Z1rKxAixJEUYpChT7fxjIJ3MEC3rcCbG9vs729zebm5kgAee/p53OuXb3ORz92Eq/Cz0kGLppmJ9mz3PRRHn9YTC8/11ZeQkxABF4Su2Q0d2iF5TOg83klC1eL1hdPTn6f9HVM0tdMigr0MQzgh0QfCvEjhM+QdJwrZ5yzTJwhGZ3bsxU6qNy4VbpRPrMhGe0XTFp0isI35CwDJlIdTIRB5wmzFJ2sNaw4Q2cbjHOEAHZcCdeQCKQAg0LJux33rAB937O5uTkmfvUGkGEYuHbjCuvrh+gQCIi9E+9TPda/q4Vcx3RYxPMaLYz4X8/VNmCanR5FjXz0FIYqmUMtP4s38Jq4hSDP+9IoGrVIFBLDPOCTWHjU2rt10r83NbKzJyOPgGD/KP2Bpc5vgJwTMelGlYTARW3YyF4mi7zXqqBP0hGM8NDZSh7WNR2tk/fqOujalk0iNuu1y2i8laudXMO+ihu5bwUo7N9sNhv3+dTrXN7te2azOac+/DQraP8dd7rw+lhWyKIItcBHSFgJ2zjNH9SdlIQR7uwvKM+V1y6KEOKC9PGpQgHaDj546D0EneWLWs2ztsFNFH6BupadmDuZTA5gnNEkLo9l2jBOA2supS3gIQbmc7HsGFToGvub1uByi+sMjXNYB41R32kMkzYT2kYKWzjJSFF8CIIMWkOshkHq454UoKyCKyig8ALee5qm4d2LFwghc/TRU2jifAc+XyYoynM1RPQa1EtrVjZC3LhGzudubWR1k0lNLNWvj36mnNWyFQ4OWi8oxE8pDecoBR5rHd1UIZiVhUrRgIl5LAZl9QZJewFMECUQpKOdOElInlL2jSEx7wM+ROkY1uESayUhbDvdCm4trtFScAaMtIYLZpTzcgbdFyBdtyk3SA/Y4hqQDbuO3l2299wPUC9OLj0AMUbapuHiu+9imgmPnN6zQ9B3w/+JRQxOirvrVmxjtGDT7oSDy7WD5bBRHmteoeQLAUgehgChFwUY1Np99Q/OyVeZVaxfP+ZFUhmNESrZGlWsNBaKhpBJJLJP9FE2e2z7SOwDPms/X4ikwnk4FXixbmuxjRI91pCywY77gvSjGqvKlwg2E7Ml2bzoeLFFCQRShABvv4ds31c5eMccQIxcu3aVECOtXbj/Ha48a0WuECl60QsSshaaVhLGUkdY5gGKYtUXonxfh44aGchUz0LghfRBE0HX6FQw4x4FUNSQYsUcRskVkpHagdPvQxILD2TSIO3fQyy4PxH6yLzkDVpxssbQto2UgDG4xtI0Wga2BlM4aj0fme00Y1UwaQv62D+YAqEVSjqFDNbobgM5sZAS07UJ/bW7y/K+FaAshSqdwMF7Ll+6wgOHjrDngZ0Dmr6Xi1dgFEjYbJ1k6M6J4LV3U36vj8W117G8juNF6LCz6WPQpo/C9tXNHMZAuY9EPT9hDNrjx0g/2yzWXlrSknIDSZGB9AVmBsX7fi6NosIoRuIQ1HsYJq2DKVgjsNAYN6KTbMFmQ5AIDiZjotE6QSZrFimeKgoyUa4h+ATB41a1ABYNyaQdJxd9pusc//Llu8vzvhSgQL/SDby1tUWcTrl4/m2wDh9hw8LmNuPwQnHdk06FbqFR6FWPedXZf+3Sl8MILCw8AUFdXAji5qNat9GQIi69uiYKDUa3nlXgVj5zUdRxl17QVjGtDPohitB9pPeJ1AcGnfjJ2rzROku7NpXzNaIEMs1jxjJdSWozhmwzttDQCQa06BQhxciQ5T1jiPgY8X0mk4jAmpFQUEitUuXKBfsWyMvGB1OAGgkU4fd9T06J25ubPHT0NE0rrrY1QKexHCF/ai6gfNY6KSzxvUYHdZyP1Vcp2QYlBDIi5KzDHlYVrEzgpliFjSykVEiC+ZMBUxRHFWCsClbIwPtAPwjb52OZ0s2yEawxTKz0+mdjR7e9eM+04B0QZCCGnUlJ6gVkCRNBWcUhSDgJQ8THTA5l1NtiGsO0aYQHmLY0rWMTMQZJF+xIdCQHkwQh3XmrnntWgJQSGxsbOwRfGkNN47h86RLTtWOsAb6F2C4WFZVYfjdIWLJ2WMTwohQj5s8LUiYs9bS3rQpZhz2W2cPyHqZhpHczamlZmb28aCYpnmReEEGfGYZAHyMmZr3AmaZraLSlyOw4MStjYRpuci6j3JYckyaSOiCa0oj/UxAK2WsZOPVRF1KICtnG4FY6WmNpJlIldMZhGlhpMnPTklIhnuR/yo6j5Bv8Lug+SA6wvb1N3/fjOri2bcd9gCsrq8QUefTUh9mFTPSWNKYIH+7E57WA6kQuKQFTmL0suROmUXbPisDrPsJl6FfnCSMHoFl8mf+PGsvjIJg/DtBr3jB43ctnEtkYJo2DiWHFaJOHLmxOMWGMlSFRhXPGWlxeMG8yICrQ0utmsBAyYQj4lBiGslWNkes3VvKGxtZlYAsuY9Al0Vo3cDbjGifeK+SdLhZIVtrc71IGuHcF2LVrF03TjE0gMcbRCwQfuH17g737H6SrBFE3epQYjgoBjbdkxmpaccGZRUY+ooNW+QB+dLNoZjEYk1kIOyOIYFAOwOsoeHHzZS0MQNsa6JoFjVy9fqGSUwaLGxm+pH+QY5JlUUG6ejKZ+SwScmaYBWKWMBJ131+ICecsXWtpWsH5jXO4RjyHsRXxRInnwpFIgmsgJEkhuyCVwJIdWwg5cKAF/vGddQC4jxyg3HyhcAClL31rtsnm5gYHj5zaMb1Tu/kcFzBwjLVp9HBj+bVtJGa3jfAANfFTJ4s1tVwUrBBQNfaPWhTySvgMVf1fp7FB3xcYL3b5TCUhLFNXUfMGMyaK6sp1qKMsc5BETWJ3Pw/jVLBk9VnKvs7STHTJQ+MkYbVunCoa5xfLsWPXoCIgH7EOBmehkSQYWFh/lM+6+R4sILwPGFgvgvTDwI3rt5jNPQ8eOjJe+EK8xAxpWNTeo/rnEredUQvXopFxkkDWXqy29pryLaGjxv0ZydhLs0dZ/OBDqeHLezctTNyCdBJh7oSMMcpnKoMkaIIVSpIYBJL5EAhDpk+RYSbIIAxi6SHkUbmb1tE1BhrZ2dE0riJ7NG4nMYAyB1A2giaAkLXbWZLG6D1DzmQ/0K7tgj0LL2T0/4yF1DXY9ygE3bcClEbQAgdDCFy7comN2zcwXcsmsDVI1py9FlkUrzVOY3dTCd3Jh2ydkh7stPCa5q2TxeLhCulUpoDnw4LOjQmZ8rXS928qStmaymuowAmMxaIY5W/G5FCVNwwQYmbuJTvvveB9EXrcMb/XuoaVFcA4bXgxmGRwJpNcBc9SYUAlgIWweI2gNYMwyH6BxWKqIHlSSExNxqwknPYcjG6jgbgt3+65OwC4PwXw3o8wsEBBaw3Xbt6iXV1n38GHuBVhe0sEYBBI1k7U0jV4twWiKUYvuUIRfmIxTxir5+o2M8+iVBsV/w9xQfa0Tt63QMHCAxT3Pi581De2CWKjuYgqVGkdi1GLQ0NmmA8yCu4leYspSwnWJGzbyPq5VgRusWSbR9o+lJNEmMRI0nMTfz6kKLxDzMSc6OdR8oe5dPsI+SP3F7DG4hrHdM2x1hnMdCINOEYo4JzkIqUOwiyPivC+FSDnPMLAYv2z2Yymabh04QIbt2/JsIOSPE0HnUrUWunNp3AgKgTndiZxRdg1n1+eLx1FfVzEuZFZVFax0wmfO+BmxfiBunizE2EM2iaWku4IUgq599D3QTiAfrGePVlp52o6x6rRVS7GSteQFfwvFcwsHH3OMmCSNYanRET7ASP0OZNLN9GgiyV8lBwjqqFYx9qawzUNbaM7g7RLOFqY5YRJ2mJSLkKUH4Zd7y3be1KAgv/LWHgpB6+vr2MM7N33IA8dWaEzYNYY72JRLHmM3/qNQays2o2ANYuiUE6yMyirUEZhs8gfuqkolnE7PQkskUkl2cwaKvKiNa2PAv8G3RPUB50B8Bk/SJ2jzOfLYkv5AHXPf85pJ7uo72lMJluZEYgJiLINLKQk7WIx4wfPECJ9n8k56pIoBPo5S+sstpUmE+taRQZl8aa0m1uT6RsnHiZFguyWAaS8bCcTHjz0ARWgbP0CuYt2uUvI3r17uXnzJu3qOgcf0jVsunChsGwLKrJIRC6+QRYb5UEvWlw0ZtR/21glfJzyAM2iSFRzCzXsHLF/ldDFokhJ8oSZWvkwLKw+BkmwcsqYFl3WZCnrW8rURSIrq5dIyZGRQY0hI+1gSTt3QmbIELUL2IdIPxdLj0MmRekHwEmO0K00NMbhOktrHa7RBVRON4oqs1qup2FxjccnNENKyUoTsYPtH3JX+XtSgD179rC+vj4uhSq3h2mahqGfYZWcKMIoY1b1bp1YKoBxYeFo1l1KqSVDbyxYrQ62jeYLdoEK6rpAOe+CCKK+b2ncTFkrgl7eM/Qw79XyS9lcc4euczIRrHnKKPCCuT2kBvGxKWOieACBtjK65YEwJGIMzIeEnyeG4KVSOEhmk9HbvrUN7arDtWX9m6PR0q+xSGtZOUkHprxXEiU0WRZNzFpInSP0Qe5NBBirOwhU2T+QAgDjitf6/rfDMHDhnYscPnmWdYQFLBi7JCJBL1yZzh2JjLyAYdZBu6I8QCP5g+vu3gq+jGiKMhTXm4IIOqlrT0HWo3ktB5cE0LjFvqAxH9E3NBGi0ZpDo9g/6XP6/zFCJOqeHhkdG3rPMETm8zDuC04hkozBOeimDR0NthHrNs7SINs+kzU4l0lVHG9jJhqk0JT03GOqlldEGAbcAxNsI9YeghjOkMHbzOp6w5rjPY/7goF1O3jpCXz7nbeYrJ8hoBx6v+i6yQWSaQpfRrjEvaqFK7XrGonpVum+u/H6tcAL/s+xaulS7D/0mnWr1TuNEZ32DjoV9g5vkhbCLTODWSFI2SISNDz4mAizQJ+hn3tCiPRDFIYv5lFJu9ZiOpkXbJ2VtnALyYjw0amisTCWHUlpZZNhnkXgPsh2Uh8jvSak0cusojORPXs8hqkwkw6CjzSNXoMI19/5MShASmksA89mM+bzOdY6pTxnbAC3t8DPJNkq2bqzigTUnTdWGzFcBQVdVTAq7drLQtd4rrmO4H31KqX9vJR3Sys4HewyIvRSLEoO6ffPi3xhXAePCH1cFxMXcNAPmX7whJjp+8g8RvI80qc0ZrK2a2W+wckKV2PEuo0mg1DlKxnAavKbNNmV+D1EvaFEH5mHSOilAhn84jZ7xlm6qWO1a7GmJWTxUBigc6QgHUkksGVR0wdRgI2NDTY2Nqrt4NsY4xhS4sDDx+l72J6BCXLBJxMlXpQDcAoJneJxoyZulbnKVi1OM/6yqLEgAK9Ucu8ZFzmXJY+oknWtvl5F+CzXJEjiKgt1WEikWGhqr+ggFPwf8X1gPsRxFXwMkuXTGFZdS6MWbY2R+O7KIojF55dJ7aSKnEeFG3wgR00WB4GBvQ/SCu61OTQnHBbXOlZsg5s4WtvQtoaug9TqDuVCUVuwOWEtbAf44+9+QAXY2NjY0Q6+vb2tlPDA1Xff5cynH6KbwOoKuIiuNV1w/HK3SsbW7LHHMSpq0A9vqwtWGDixvp00bVGQ1unsfycbPo1lx5YP8iK5lKxd/j9oIhoHcfseiL0khb2HYcj080iMnr6P8lrGClc/FWTQGKn8ZQy5bOgOQnbkkEhWbkePybKkUlu7Q9KNXynLUoleGMVB2T7K8mhkN7F1Hc4ZJl1D07pxqMVag02wYmB76kg9i0HaqAmxh8lUcqAPpAClDazg4dXVVZqmIfiBRKTp1lkF+o5xyuZuHH5E4rEv6brCwMLDB3W945BmFkWo+/ZcK4J3OmXUKTSwWTyxVQuvCZ+osXCIi8dYSr9K+Awehj6SYiDGhNG58+mKwzjZ1+tcwho3ruGR3QRapLFJEELQRtEUCdGQQpJm0CRVwKEXFlGWSsZxtQzIYigmjt2Nwxpx8RlonZFEMSf1ajKDYJtEbKzMJuo1Tppn+QDZZtYncP7WB1SA1dVVuq5jGAbqu3/evr1B061x8uxHpZGzQDXLuIIdzahR1s1XvEBOmqnDuLuHXJWDG1hZU3jYaXuVq6hl1LoL6xiRca4K8w9q6T7uXAHX95KwxixrXrJW45p2Qmlls50qFIXkceJdoipZTIIMNG9IIeOz3hyqT8y1o2fuI3FIDL020+oFMEamgVdH0kd6ANCBB5sW9DUIBQzgtZRsgDQE+tVOClXIOQcfZHFVgj7B6f3wxgdRgLU1WS5XMv9yd7Dee4aUmervS+PkWF+PSlwU60v6uyxWWdy9MYviUNtVI2UqbNS9G1WKEkqsCj5F+YrqUcqwxxAWTF/fa/6gyV3xTG1j6KaNVCFdlR+giWgSq8pRBIIRTx+9uvGUSIPu+veyNsYHEbqfByF9vN7VvEBBJ0SPbeSewVhp87IFG4u4ZSE1koALQsl63ZLeuyBicmBlbUVKyCwINkrC3IN/j26ge1aAchTrL1zAzetXuX31MhjHnMXoNXkxex/LZG5fkS4of9/tLAcXRFBKtEYTw7JIyVotFqlQSCp4JE8IWrgZBlG0+cDYzJmyNqR2UnJutfxsnYSlrPlHQiw6sYCC2WtNIouXSlEKQvMQiX2mD15Wx/hI6BMeWetKI+RSO+mwraWxBtNYGmPGPka51a8dIScIIkhWXiNrH1tZQiV9BpIk5pxobMI9wNgj0Og1hoaQPA5484fI9L52BJU9wRsbGxhjuHH1Gs10lUNHHmUrwdaWjmMrREvanWIBNGnr2sUMQFPgWVfV/o0KG8ZdvoXuDFHCSG+BYUHv9v2i8cMHxoGTkVk0UixCm1MbI3CwdI+kVtBL48RrlPpBKsgDEXwYIoP3zIdM33tCH5kNeoNLxa22caw4h12V7Z7GOimGWav8uF5PRANM0lvBJWH5vAeIWqAKDPOkiEB6BnNMRCvj46sTx9p0gm0sKMmWfRhzoJAye6a8ZzfQfSnA1tbWCAPn8znGwLXbmyTTkE3m+k24eZsxAxf3usD+rZN369zCjReLrxECsCBlCmsnT41TPCWBK0JPecEbOAOTVc1HSugwO/sA9C3E0jpk7bqSPaVu4IPQxkOUwdD5EOn7oD0AMp8vN3U0NJMGZxxta/U8HE1ThUBKl5Qkc1E3U4y4f0CVSMfGBgkfPgnTGEFWw7aWdm3CrknLZNKytu5YaRpuGscwzzQWBidiNTaQ8g9HAPesAEX4pTlUVsO2XLt0kc3b19me9fgkF7ttJY5jql0+ZUS8uPYsSiA9dBp30e9ZwL3C6Ye0EH5BCrAIJa1+lTbwokejsE1VFdZ4Ps7ga+NK9Lo9VNvAZ3PP0HshYkJW6KZs5dSx6hrh762hNZakRbBS4YREhyWYpD16SZpkiORQFkDLYEmMge0+4Qcv4TMKhreuYbresTpp6DrH6kpLO2noWkPjGiYtuKnl5pWIs4Y8eLnYJpA8ZJ/JP6QQdF8KUCaByl0/27YDEo1r2b1nD7umYNdZzOIXN44m6XX2r0IoQoyKFnJeWB8oJPQLurZxQvK0DUx1pUghmLJjsec/M45xleSocEZ4vSdQUOwftZNoDjPvmc+FeZO/TxgskxWDk2CNNXLvP6MbQoHFrKaFZDIuwJAsXpcehSTdQvMQdEZRyCUfM75PWlKWewK3U8felYZp45iqwNvW0Wrfn8lgkuwa98HiZonOZRKBWPBfygwp4PuE2/1jUIBS/9+1a9d4x5A9e/YwWVnlwSPHOHJcihG2XVhaTvK9L8IvHR9IXmDywgqLoHX6aazAOW0D75zE8q70DWp3Uc3yRRWAQXMABcYlk/dogUihYD/IPYJ9SAxDYPABo0Md05VWSrDOjjdnKodBYmuJOePdvJMUhWQXcSLp7eX6GPA+E+by/XyI2JhIyN2+1tYcbTtlOrV0k5aVlVbzIxGNMRaTRNVKMgryWUNOWj9JuCGzPQTdb5yxITPf2uLBlX0fXAEOHjw4wr+UEn3fs7a2xtUrVxh8oJ3oxa9MLaMdPHERo7MKIaBJlRZadDm31AkcNBNY6cSbtJ32ARgovQ7LrdrF9Y4Fm0IqobDPQz8Xa+/nsvtPuAzRmqZ1TFYaLJZGHJtQ1XHBHhbvlHVT2pAz5DBOKeUcmc/ldeczEXrvg2wS0VHg1jpW25bJXse0a+gmLdOpo2kbJo2VOobi99IYGlEFMxJjTZAkkBAkIXaJXTmx3kZu3vYkA53JzPuMTYm1H9IMcs8KUO76Wd8IOsbIrRvXiN6TTemULSVLdvTrhajZdGAkaYzWAVwnyKBtNWFsNWfQApF1mkBXEh/xOYwrXROMu/78XN8rLBo/pEAl83uNM7RNS+MkHDkNWaiwy2RV0AaMEFkMZyaIunLF+yxbPHrPVi93Pw/zRI9gU2cNE+doViSOT1YczbRlpbU0ttFzNCRkWsgYkA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elifUcMZcZ3MwOnGIwUoJDmDOVSLAfYXaBQfjMOBg/Pa/Ia/iPuK7UT2f4e+Ltf82Wq/dcOoOhORX7GtKyE+NoZEouArGzajYYU0lB6rhGpMpu3oIbq5QhZU2KSLVVYBwmI/0u1vLU85hjlIz0YA6+yBuRxevRhLGHHuDDm4F9powmjBnpDOgIWL66GCwf4I8s5DWkJFOMiBC3vi5TABqh9epQf/nSCTf0Djjk5vuNoeOMNLd7KW7YQYlgLkUKoU4oILoZSsYEskIdgUtZwA65j7nkSj8+PvTfp8doulQ9iz9//uA/q+5JKkXfHx8fYCj9VqYaDUiYVPxEpjbjfeRabhz2X7k/XowmvJEYsHWlFkz00bgPHJ40UUyQwpoEB/9cbjkaniZSXTeFK+W/5uNVvngMej/HA2mgKSTeQnAka4q5LLQrHQHiRUQiD0VcDZWeU6WB/ms+Pj70PiMSofPxcs6cBFF2QA0LSxLt/+wmpESqOlO8tKB4JZrocYTUfMFSP1HoIZcAAcINrA5YXygpmBgESw8T1GQXwyiX7MIQ3D3pvDS4eaXSZ4ervHA/4ujZPPYadgg0zYQtH98FI8DgL/RaIFYTuQQscslcIDYB4wdf6HYd9qU4HazaNFSpp8U/xV9RpIzs9/c3B0ekJEQ4ToFr5EuWVyOLl8l0sOVkB/yz4fn7lKRJTCBnwaRwuVwQepgp05EW86C5Lp0CETBToGPocM+zMKSAS5Z1pPAk/9CeDfB2MILfEhyiS0AG98IOUAmcDoQnI+U+kL/QvEasMx0nAiqv1DGJlB/h1AlqOrUoK7i5KgZ8K16CLF5DTTRH1x5ZzK7mer4G5DWYLwD2R+bFmghsgf1f6hcLM0Ac4nKcvi1PY/83ItMwi2tkg8n18lA4IFEIk+0tUI1WqPNB0Bd6nu/vb3ZDUqnH1QOUF4SCRFLUgWY0tM5K6sXEcX7FXE8/kdZ/7RUFxQvQRI8juA2Tm+us50xxRI4gwP41oMUfoRS808GkwwHRmcoxmKpy7WuYPvOFSP10Sos4ejfnHvf8diyYhzkgUEiSCTHWa1sLzRMDR2SaHsYbc5m4gdpqzPJgz0JEUD2Vi8ST4pLg5uuskK+vL22EEPSJ0oPnEpyWekpert/38dLex7PThB9gGazkU5mdkWiKZ86Z66OQxdCP//79g9PhiYMdk9SawYEFqXzFFEclpH79rw9A5JZq6Nn/PXhhgYy8X3DLr/BpzXZjLdAI4jwRoRKsuawVoo1IK2gqL1wuF1RGaf4ilpljKNz6/v7+8+dPogljeuT5fL5cLh8fH5oZ+fv3b6KUx/l8/vz8RHWWlP8y52WkTDDl/oNfwuvkPp6aJszj62kCxin1lHAe5OEIGIHglQKcDoQhQBZznf4wZ4ZYMC7GTK8IY6dDao4wPHj4Pbz31w/nkdAq5WL5kKh6ItNMEHw90VQRNfJMEzf4H6Few9fXF8c+c85aeZXKyz5ERI85nU7IhoBB1B/hdKyOExOt3+nv5AsJiueliR5HCElEjMwzFS8Zd4OlBGsKqAaOTSIq6Z2OS11hCb8j19EQ3zEpDsUCQfiP5lbceCfv/fWtT7k5Z88fEXJJcl2wJLUKUzvUfwQLjVxLFT1Ms5sY/IWeKE2RwumQwg7cPWaBXGpzuCIzl4yslKkiqVVsiivCVTwtWTwpTfgxlsG+hhnYMfhzASVIQRkByQs4Hf/+/WM6gLhg4kg06cP8LkciZNHFQFvqp9xf/qPu9FPA8AJvNBzBrr4Jahg3JNXLVcDFmMv6d5hIpp6FxjL1rzodGsj4+/evPhXqdOhzpbJCGUcDovBitBFofupE7xPgC3kh7+MZaaKnIxbIAgSRXF7DJy8QgDB6wRzM1JBcOiPTzM5cFITQuGR4gT/6azz8Bt7pzGt+7vCn3DwMXno03RANQAgtOIJEBkKYXFLJMctcnI6cs65YIyKfn5+aLv3+/jYd0IOFVtnRmIhQKXd2JRX+jvmrexI8HU30OELIAlnSgyNguopEKQmmAHAEfI1meZWPRPC6+xyP8GoiXxMRPTM+yrwfTBPSkQM3nsqfBxbOut1HQ6XY5Eyr+ErxTLXUkiu1pHgWzCDe6cC/L5bJ6egGPA4wyPl8nstCe3oYZqC9ovfxXDTRJAiAZTwLBzZsUxaFjaAGZDoulwvKq8zBcz3RK1GyM7lpGolmgv8UOyyc/PFIlNa9JVHS5AvcTLZ/mJl3Q0AKgdbjxrr7//79Ux8BSZBES2ZqCEOne2gDQwJ8jfP5rA0cLGX0Up9FSnhCygyUVC+6YbwPvsznIYvnogmpB4QmUzQDEz2PY6ZkJ8jCiwhWHBykNGdOrZqIXLs/pud8LXe6Uc8M08kDn3u+t1fdEIzhudQyIGoA+9SUB8YDOB0or1I5yZJBSlgBTod+XalnLtNGhdSNFPXRfCQ4eHHUjToET0cTitySFfD/m74G+whs+Vw9yYEJznTAT+m9eiOTo8EiItdhCMMUck8R8RI0IUf4I7klK7AruOosExFMJal5Ke8EAX2EUkwlpc5Kis/IoQqT6eAzSFmhV3ex96FfV5JiSmLvw1zXc3KEPA9NNA2MvQxjqGj3fA11LnS7CgrQgeY1Es3XwLcSJUcSJTKYHeBZXDovB5d7ZjFSa+2ZVwE6H90EyjVo8oW51XBzQg0ewy+XS6CXGCNnieDF6XT69+8fvIac8zzP6nQgRKXWrk7Hf//734+PD63R1HQJF1zpeZSkwGs814NvSKhTv09CGU9EE80GSwnDFEwWTV+D1QRCm01fA3mN5tt3mB3mep0bT23mKm6/IW+J5tXdYhLMIDwmexKJZZVNHJzrJIg2OAaZ6D3GKK8yHYZLoh+N98G5j1RKvxLN+0i0ULC/ih/HU9BEc8j1OmKm4oi0mNfg2gfwhWoKUIZfWoJPkuk9GpliIlIvWivlf7x8Ob2NW2/L26B3aSutoikreBfsX2huCP59Kh9mKqPG/1StfaKXgHDKQ/UCbNs3OFop/dwHd5i756nhScjih2kCt0ZIODA1ZDeti7UDZmfAa/gu0Da7G6AJVFXxylSQHvrTPA0015EIiIh0beE52W7qzZP8ErCd7OYL/C/gemD05sN6SZDz+azjRy4rdKvxI9NxuVyE4hGc8vj4+Pj3759+lNr7UBGq4gJRD4Qt+BIQLuGYa/5p7+Mp1ASDmUKKvOe4wNzJaHhfg2d/csDSUENyL90BF+TFdIZc44hNV33Q/XsHLIiFTSfhzKhQnUVySZBY3ug1l1X/LzQTRL+uW0IImg7TpSWEzJvjIJAM8D6UKUIIc8mAzDTrXOpFd39cPhj8JE2wbRgpIUXMe78Dtj1TvsNEGVhooGHWlWG9cGktGJHKqpa5A3FksXCBm+7GwFaDyR1x7jmi+a1LmZSBwQDF3VNZUNdEH0REVUYuS2zlUmeVSwxLiveBWq+5VHxJHaTg7Aw/Tk+SBPl5p0MoqSEUlYC7eKnrpmeKSpqiKe9rsA8CoYEEB6+pj4ClIQimKs8Rt7ODvHjy4q7QO7w+LWKsKzsHBB+NpMdcj+zW4/76+tK9OitM/YhcAlLqdIgIUh7qfZjcBx6bRGsaSqm84vcbh1LTISXqkUnR/BR+jCaMsRmOQIODiJle4QfiQL1D09cwZRHa8K5KcllP/r96dsAl/NTdG9gEWCCPyfj3JSphwL8bByNDAb0AWaFxCiGPg9u6V30KVStzWXJd6B0lQt5HplhmdiUhP8gUP0MTzXG4Rw0mEmEijqwvlC8u5d0ZfDyzRqKMRtPXaMqHqxwxWON5kFs+C5OFsToOGaJoCnsv5TWiQskL431IXWqJgk4UU2E9bqUPI3AUiF/05MNPkcUP0ARzRKrnSuU6ZMi+RqrXlVHVwPKBnQ72Nfy0cb809qWeppHrgKXhCM9x+whi+BorkW4oymK7Yo3AZIFBW9Mf0P8oZOCla9j7+Pv3L2xbExwafWCnQ3MfUiaYghdSSn/+/LmUwtBY1vJN9UJ+6JuZWvpgsvj5TAdbHZulCSXyx+96AUsTmDRzN1Id4+RIBLeNhGlKCenooPVXeswt+6243U74/9g8QyqJDwzsqWRApAQ4Ee9UZapr4XGv4HQEt7K2lGQHpzxSmT0Y6VUj8kyFmD+c6fC8YAgCRZBznc4wIQlOZ/AurrZKdaKE2Wd2s7maUqJp55uMfzDFLTB3b3cSJDu33xycShlFoBfz4GDjfUR6kyACEHA6eLrHXKonsEVKnkW3QEqklMz0MH8Vj8RDacKYXFM7ZLcglZmaxYFJrqTiGirOa/hiqkxTxTJFQFIdufQdNtfyyFs3cCNyHa3wsiJTQgS+RiwvE8KMUn5TsaY84H2k8lpDXaRX17CJMeK1Y/oU6a4QAha50AJNKUVfOBVHKFI9VezBKuPRNOEbZhj3vsZM2cq5VSJhGr0aKj7tTOv0zzRNoykfejpi0yUPHIt9ysKfxHCEURbKAjBd3Y5X9cBrQFQS0c1LeVOZbzD08cMJEy1aA/cHF5jJE9l9yfvwOJroKXYzks91kaVxQOBZGBHBmDs1VKAG42sIFdUYyM06YtDE/cD3dr3N+HG4yRFSRg4ENfEtLtnMpfJK6sBEpGX4Q5kDioa6M5gVllqvGkDAgsnCX/5jyOLHMh1GR0hZQX+uqxgudZ21mZ2BqRw6Nxxb5rIKbqpf+dnzNbgPMnyNdwcbWO54H5He2aXehz5Csbz4C7mPROUPf//+FXob0EyvEcHCnIGSLFhZTwUFghfYkmndPe7wg4MUD6IJY3hmxDZBAfAFQhJzvf698SzQWJnXyC1fQw6apjF45EewT1nw1733ketiJ/Y+YNJzyX3kMkMs0wpXHOb8+vrKpW4ilBeIcGMuM1aZF5Kb7uG7+gA8giY8R/AuE4AwroEx8mYS1McmLrRIxNzJawj5GlLzl9ymIwZTPB7mnq+xH29mufY+0PbeB1wDHGAM3oQkDClwGgWv/AmlakMoGyJuMS60H0kWd6cJtjc0eEiHoJjrUKVZkAp+hDYuZUq42cWrV7G+YD2SF32NpohYaflpVEw9AfQ/uKYWKzvvg1kg970PnD+2Xho2lzcJzWX9G7gM6o/oZKL//Oc/eua/f/9Chmhh+Ewzx/CUBnprmTz27R6Pjk340ZtilI0JmiwQVqoJDkMYv+Oqr9HkiIHfBkMf2XkfeliiyisOT0qZAGIa+i2kRXwjlZehzmUi6VxP95Afqtd+aKbDINXvv/EOAiwcWmCmAOSlzObi2MRcI1Oo8qqv4TliUMZvQHYy3hzQ8z5QZ2VyH1ICECklxCZ0i8YvjBuiXACOQEPqYVVa2vzlMx3mkgxBGAWBkISZqaGzwvWjNr6+vrDl8/PzQjPH2VtB9nSNr4Et3PndFzvwDEilBmH9V3ighlliJO95H3ykeg2hrKydymsijVeL581IFWyBKjFr1fAVGX1xV5XxMyFM3Di2XtYO/JEN/kKLX/eOgXBgUuC/np73WfjghSeH+QdttSI8IT3vA6EoUBJUAE8V5UdaeUQfVJ1IFkLQ9SbmeVadAtfYZDpSq4biruwAPIgmpBYUyWVAPVlwxMEUTfmGD0CkFrhLCwSx0v4HTTw/+H+0Mv3RPNJsZ46QWrloI1ExhR7DDewyxzCnBHpFAP5y2BK09cI04RWEkVtqt4YLLvX6VOpNeB/E70pUiwXnBZRhuCn18xrrCWJwxMthvRvCQzR/C9uh/1NJkebyrjB93nTX+XzW9bhDCJhIrnOLROTz81Ofos/Pz4+PD7gqaKA/SJcGWrY/UcEVd/gerHFfNeHJQlrFVJkKqMEXJnMxt/Id7GvMrj4C4s1Qldxm54MgXhc9sbDyuybGibN5yZDKOpdcIoGiCW3gHT/6kCOoqRvZDRGqzmA35GG5j0dP/QIvmOEd7gYHHVhomACEP2ymJMiCcFggi/VS4k73Z+ABWGlU2XkZPg/CTxH7GqG8vEcfS+xCbIJDEswXAH8LDaGl8R78EB5PE15BmOiD0Cq4M1VGzPWCEZrFuNTLUl3q6V68BCYrjkTpT/Y7bhQUt2iQgefBeu8AWqDrAAAgAElEQVRDwfKBvzWX6inM4JD6IUnldR6ZJpJHequoGgWO4eUq5pLp0FNp43K56LR0eBwmqHmnlMfdE6J811hEiPM+TGwSQQo4I6meuDG72oqFSITUjs8w+IGt8IIi1JMvAhVQYD7oTK/niGX5XDT0K9/f36FUUuiZUXCVy3sDvawQkjPoz52u/XFOB5NCpqUuU50BzVQ6ZfwO42igIIKBkwsVRFzVEYMyBprwI3Ou86O6MZWXns+UyAylOls/XsosD0QoODChYQiUYM2tgivoEZyTF866Kw6mCWOKPLCnUigBOlB7vrip4iij4rVwU0paQ5Vobji+CD0C6sl13cTtHJHGfI03gj4G++Z9SCGL5PKg/FH/YrqH7srFs9AlsC5lkf7mSfg8vDwn5qTzMUJRErP9dtxFTfQG8LmUWmaaAGrExaUscm0Clr5WIlFSY64LJaQkXA0peI5YeTkH3pyB54EXC1u/hcc70AKWeAghKPC4ipvcgQNCCJpPRZhT55WlkvJgNTGXBSzEkdctN6SHB5VXpboIks17rt/cydsZvY2J8qm59jJ8N3b7GoMp3hKsFK4e2fM++FTwCPCcI6ww1+VVSit4qnXLXFKn2AVSAMuAicAaB96QHg6jCSMcQHu5vPNCqKQqU8ySSyH4FRtzXTqFl3Ro5UmPMsSlXbljpsMrr2jgjYH/8tXcR3beR66XlkLoQQ1ezwy/BhSAFWt0oRptYIsejNni+rTnnHWCOQou9LBUirs4oqk4NuVxr4SoV/szzbMAL4AvcolTMMWCVtjRSC6pwaeVcu/4p/ddxe23YuCFsF5ZLHwLDyS0A0Z+SAZMCZ1LSRVcDDUBRDehR8wKV7wLyVShh/aVEqIK9gVMTLHnZTSrMJk7cJg5obQWv9VubCWOQRO/EGuG3+wCE6GeZ5GoJiJT5B6ZDi2sxJMMvvC5j7n2xNmIQj0D7d4pjyOdDnEeB0b4TC6WiKAsin0NZDG4cSlv3PDFVEaAGHaApvC65uqFDI74tUgrKq+YHQxHMIOk+nVh8ES4mEofNnUotKFxTW0EKp0CEfBCeKGeOeZTHs/odDSHcRGZKcGRKCuRKfTIAmGuy6sy5UG44f2O5q9vsvlBEAN5i/eRndOBBgb85AquOGCZc+byKtPI5JXzuIuYyPyQlMcxNNG0rlwnOFILxqEwcotF11wvIcEKgv1AQxNbzX7QxIBsN7Pc8T56BVepRCuQ1MBDjjkd+t1EFVZIjiBRIqWkoieBN1HeAg6gCWOWuZPgQHzRBCAwJRxuhZ+4gbbulRITNc5bboH7ufIqBgaueh/ZBSn816UunZKSqtBjcP5Yv/IH5dshBMwxR/n2TK8CEirNyC7lcWCyY/Ob4K/CWKbRSwrjfXg1gb3GMeGDmQg8Rxx+XQMDV2EewuQmKPMzbByKuVUcxNvZCtiRn0vIT+422t1KE+iW6d8ad8OEG1JdfMl3CnvRlnrKxtX+DOIYOBy9Z8xs9E+v+Wge9cviW2Y8mJWu9mcfDgthmu6mutIplfnjqZ4JygkO/zZQAH5Koninudf8PzPto65xYMAj1/kOoUgECiUyRdDgLyDlweXb6iOggZQHL8mNXXj+4XqYci9+LdAtuJUm/EhuuI3lVqawBRu8j1l6SeZJIZGi833Y0f+BAQaejfXuvf8KnsaeMSOWmamYai7vAZtLYQWbAwxKKOWRqHw7t4o7brkVN9FET2UZpjBGnp0b4qMVxtfI9aQPnBw/vZUdmlcxMGCwgynMF/Ex0wpXQsHIXHsfkV4XqA0st20efm5IbXemGxA7u8nisEyHN1eOOMDXQLaC52ssuBvsdxg1Ia1poM3b1EMac8MHVkAfqoVZ58YIM7kheMZQBAE1MdO7heGehPIGwFCvWIPpHsj06QtBMLUMPwH64PUyb8T+EKYfvbmLbMmgCenkPlhB+AQHEyfzDgSF+fXdVzQwcDuaQ3pykTsjB5qamlUGvoK8hgnPmV/xvbrloo5JiHLnWAWZLEau3Q3mBZPgMIxgGIRPyDjkWgYGjoJ/RNOiE21IgWcteVPCtxCwECoSl0MHzp1OB3cLDf7LvYeRX+jtO3rBeO24SYJyggPnwS0zd8H0AXtvuzMDA9uQ68BhdjM+Mq15JWUclTIpI5eUB8IWgVbHwzrdah3wUAItbKWuSqAVNE3H8l4f5IBMBxObseHUClh6KcE8kmsBZs7A58wtl2dln2+86oFfCDw2ayzNGySbydWUx4Ve1RFooRqDXDsaYIdU1tHa1OcF3GWGqJFGoA+vuJrZUP9d3pjIqfGCgjuz3NWBgU1YY3K5tfwE2onW4OaUR6pzmWY0VfrARzYoQxOJJpizmrgd+50OqSWD0Q5oGD+Cp2lg9udCSdVM89CZIAyJHnU7BgaOBdNEoLnn+jyHes7ohVbfVp9CZcU0TZryEJHz+SwimOUhtMa/UStMFrpLT77jKg7jm+xCFd6YPSM2AzmGUyE38CvJJTIHUww8G/wAluvcXNMETCO54GUzkCmdMfuoa9lDE72fhw1DFPFHE27I9SQWs5G1CbNM7oD7MChj4GfhH0gDY+eGJubWmgmI5TNfMMVIGT79IGr6tsNA9scmzAU3r0p9B6nnj+MvM6WZu8EeB6Zy+Pu76YKXb9/AwEokqphaczxGe3ydl9K/XC4abtQHXtMcs1t9O5UY/+l00urMuSxIg/gFfIpcZEsq4Y/d7sb/rnT3N/kW8Ec/+BuBYBjRCw0+D39FOkJuyIeBp4V/OPHENgc/YylcE2CGZC89jNWYn7sFx8zp8CyQnb/QDEmwavJyi6+Q5UNPSgy+GHgSZDeHojegikuCZJoD1rMXPQZZz9xxyVNZTdf3ZxM20wR3grf4Nnsfqfam5vqNGxdad9+zpoG/F/uufGDgYeCnlJ1feBZcEwWa0MnjnOlovunHuBuGgHw3dpDFTVWYhre8iEp18bmvj/AMYu4CTuivubml2dV91zgwsAw8WsuG1zTO7GQy2MFbgTENFRrYhfMkV38RaJ3+NV3tYVtswo/eXlnwgM8H8HWa7bMrxzZfX9mNhT4Pshg4HFcfrasDG1uBt5RMcT38kPHTzdeb5nO1G1exX02Y3nO/E8VmOXmRKN/BqY2cs/od/i4YGEq62snBDgMPQNr4dg9zfKKXY8/lVcNqFOfzORUnXUWEvnwYsgJOB76rekRKSkXqOqt92EYTCyO2tPwiprrUCbGw/XtabZ6wx5EDA0+L3vC2YC/sgBiradqOOSHaTX9nk/dxQHlVrrM7utG7GPjI0dpEaU6jF1JdK9K7y80tAwNPAj+eMS+wjjC2YIZStiDW1yJi4nrSL1Zu9mcNNtOEGd5T7RQxEYirqppparnxR7yvgXNKR6cs9zMdWqw6MLAM2PzVw9DgMdUYUSKHndtzeSm32QVeMDxiWGYfR8jtq1c1DThTeMLsMj1usmYTMlTDwLuAzbX5tPfsIrW8Dza33pE32s4GmuBfMj+caxHlL9ukQvFRD+bchyELPvkt1zkw8GyAMeOjsXApEX0pnoWxIG9oeiqctmmn/HMru7ozNpE7AkHI0WL5BLLwwsn7Wnw2z5p8ec1Lzevk38DA4ei5urnW2rLRiJoOe3bVRiuNaMeIe5PTYawRV+hJblkOeTrk8w+bH3hXsBFlp529ETWHTH+Y+Qm52YgOK6/y1s7UmOs1Qo1n0btmf7UyvI+BFweebX7Im9bujcL47EY7NM/jTUm2G9FamjDXxj+P3hv7Z71kch9eJqU6V9okkTWX2lN9AwOPQe74vL2Rz7PAgo2k4sJLPWcKoQp/vP8V/vWV2Fle1SMtvtrsfA2+GD5S6vqIHheajwMDrwg8wJi42XzgMwkEY02pzmuwNfGcjp4p5ceXV/FvN6/ZXIlvi6NVuZn8BgaeH4YR/MMvJNU9WTQNqmkyTYPdhLXL7yxwgZCdGwowsgLaoampch3RWOhGb28awc6B58DCY6wwe3l+B4sI73FIzR3G0Jg4xJnkMoMsYGcVptQSYNll8NxhroQvyTR2MN/AwGsBzznsiK0Dx0hnJO4ZHU6YazWxo4eHrawtrnZbWuEZZjV/bbyRT2uubdDHwIvCP7f+UWdqMBbEpuQNisfgY7u9IYTpOanZY7+dHYom/HmkU3/R69vh92Vg4EboE9ucvp2dUkgphRB00ToYAr96w0P6hma28+x104eVgczNdRPLe71qYCJMTi/xF7mda39kYOCNsfDwZ+c+GGXhkVaERbaa1f5i7dx3HJrXk2p/RIhWzHfNxQyyGHhjsMn4XWwC4At8ZCW+ySq3dnJDpqPXg2anWQL1Ks/5nNIqXF15NwcGXggL4x+2GPfBWBnD5D7YsnqKg39rpTXdFMLk3zBt7miisIrvMbMDf0wj3DDwa+DHSPAFNhrD8Y68t8Hex63YM6cj17LC6IIee/X2LhwvQzsM/ALwY7/SRnabVdPKrmLbehPmx7RhKkNYLymgjnzXjffRu4wdFzYw8OTwjzQ//MZMvO3wVA7+FtugOLM1Z17Z1SPXwjTdMj6Vv07T0R47DIIYeFf0nnBvFz3bYROTevw2bju27+jndZpYOK9nKXGMxX31uVJ8vccRmy9oYOA10SQLTweGFKRVYWTOIIvWtMbQ9i+Z2wyoiovN4hjjjOBsC6JDWrTq+zOCnQNPC9b/DPNgmye/lwpkM2kqdKkHb2NxaxihicPeSN7rh9liDhsWPjCwjOySILyLCUIclcgN1MC4KTbhG3xMj/Ca12a+6Lfs6OfAwPNj5cN/1Y78d/3XZa817ZxI3tzFFVaeI3z01V/k1t4PDLwxmvYiNAaz49+syDLnaZ55TU/2L3JndvkrkUVaMR+Tm/G6slebjh8YeDw2DYGGCPzXl23+ajhzK0EojpxIzh1KbuKGuJAsH28a639oMMXA82P3g90z9Z59HdflCldoYsGefSS2+RXe6+O33PZ1Wf7kAwPvBDO8m/HS7DI5QekMk8YYexmT5vE9rI1NLO9t/qr3lxa+tebMAwNviTUPuT/GDKsrPRRzzpX2devUr6Y0kBX6Ytj/wMBWXNUOPWO80eK2rV614Ahkgg+68iX5j/56Bo8M/CoY8/aGxlu8juCDexbkDU3utHqV+dUdIZOe6NhKCoNHBl4Lu5/wnkbY9Ls3RjcPmPrV3GUY8R4aYdDEwAvh8Iffj7iZIhTHduOYhOhVCri695BuDAy8GRYMp7kdTsSxA/PBdRPcp2XPoncBgzIGfjPW2EXPH8FhhxvRXcqrgCafeX/krn0YGHh1NH353pZ7YHOx9qaDVQLp3+Wvey9r5W8NDLwN/IC6fHCmteOuHr/8W8s4QE1cdZ/WE8T6X9x0/MDAM+Aej/pV49r0cz1smyEqW5yf+3kWQ24MvCgOf26bgb/1v76yP5vVBPsRAwMDL4TdZrtnkTsZsn9g4AWx22yHmhgY+C0YamJgYOAKflJNhBBuERc7vn7jLw4M/BR2POoH/tx91cQ+swwhxBhFJMZ4rFUPjhh4RdxjeFMTk71GcfAM0U1XiIPZQ1n+Op9/iIWB34lNg7+aCfsRm6xm08F3LNaGtTcJr8cFgyAGfjPW2AWOgWC/98h6ME34vja38HUOXhgYWIYR2l508AFyh7H2GJpo9t4fsLD3kG4MDLwZFgynuR0+SCDc3o39NAHBYzZe/ZYnvzVfbJ5q61cGBn4KWy3WK+41Zu/VhHH892HPl9dcrfcsDuQ2Gd7KwKvh2MfVG9RK+9pnOBtowlh+b6+qDBzG2VDzXUOWch9CGRh4foQWxEUlpLYpb27SYhBzBlnNKcDauomrV+gPNle70OmVZx4YeEusecibAzMaPUPbZLkLuMlj8f1b6Lrp/bD/gYGt8Ea0xuK2agePKzSxoBRU6gRSO82v8N4Yo/kWt42Uap58YOCd4I0ZbXF6AbYTFssljDF6O+0Z9QLWvs5ngZlCC6akyv/1p13ZY9+rMQ9t4Mmx/sFujqBNc+MtPCvCoPfFTbZ2ryrM0NEFfCU40rDd1l8ZGHhmNMf8NV/pmbq0Qpv7fmgltk398v0wFKAswH8Bk/LwDDJsfmCA0bQXfGQXHm1xjoa0RtOFXU3cqib873ny84zIe9f3dWDgtyE4Ad7TF+bjsQPwTeVVy40eBUqJZUqH55ZvxMDAO6E5rPaO4ZBfcIJ9gSNuZI09y9KYLnq28703oojZxMRv/QWbn/b9ubEQdWDgfugttmIebO+h9zIUoePUe5M5iiPkwGJt9MATnr9Cc2HmDGbLvgsbGHh+9J5wbxeeC9jieHsvVxrcuLse12li4by+x3xhXhr0OKJ5swZBDPwqNMnC80IoWsMcY8KWza/3fveqoW2e02HagdbPiQXmwnTjNE3BwYgrGZQx8GuwiRe87UzTNE1T0+X3WUX+RT7Jyq7eNJE8kIzhAEHvwjy49+a0I+Iw8HsQOs5CkzV6MOxgTPKW7m0zRW/evS1Sk4W0mAzXthywuOXyBgaeH01qQJxSWlYjfWlgjvHfMj+3BhvKq3p2bqw9EvQrUEcG/oJjf5ng0JIeAwMvB2NKzV3NWiljXPDlcZixrJ6i599aaU2b1cSmWxBICPEWPpizO9KipE09HBh4OTRN1xtFdBM3eGD21LDwc1vNamdC1NMBd9HTGNQEH7ygHWSRdAcG3gZhUSYzO4hLCwQHaQ3VTRrahLUzRM1lMOHlnL0T4f0LoVSIQUpJG3oqTZ1ow1xkbzKoHjymig48DxYMsjnEggia7oOHPzjWrorZHinAudw9j51VmP5ShWRSaIVeDPmJ41HDCFuvZGDgRWFG+94WY0FGUAit5xJbyziY39qEwxbgR8PDk2JY9FBAlnxO83ODPgZeEf65ZUv2g6sZL70RefOBETV/bh92TiT3lyGO8Pz1wP57iQ9ZfOHoMjsEItGBgZ/FwmOsMHtNjaK0HIfo8hre0HjolZYGMb++kkd2ZjoMb3liQ1uLL5uk0LwGozXMtS0zxcDA88OMr8aIgnPYm2Mt2xFqMRfIwv/opj7fOvXL/17oOxSx5V+EWo8072bzhwYGXhqeLMyuUCsCIx96xm8spXnmrV3dthamph6alxFLriHGmFLCRq2t0lyGiGDLNE3zPBtBhTMgx4H7klIyiYzQSnzEkfIY+FH07LA5oIoT5rCFpnZQwwkUsIQ19RSH/5VefxZw65wOf1OwJVK4QaS9nqdB7zy7Ozkw8MwI19bIbsIwwsrz3NLPPXM6+CNvj62wgoLrtXtTRZvfbf7WLRc8MPCzwIPtn3BPAd5Glu3IG1FspTy2GtH+Kkx/YaFTQ4XrgUDittFX0ilTNQ3TE9O9IUAGfgR4bg1Cy1Vfb0SwmqYReYuTRSPaMdAe4HRwO9ZRFmPeCx9xYf5bYeiIgfeCNxypjQjWDnPomYb/FtpNI9qHbcvS+Ov0bWmxF7qu5GemeMRFj8N8HBh4DzQ5wmw0lu+1AxuXN8nQ9zU22dSGOR38SyEETUbEkpWIJcWgCYuUklBe43Q6pZSmabpcLqGIJd3C39Kr1S24+Hme+d4h27Kczogj5THwQKy0uubg6jV4rFMY7KEH8jtiJ/fRVBa3yIoDJpIbBcF3oacpFrQTriTSxDj/Q7sveGDgR2CsgEd79jK8LfT8jkAynDcKFX0v9GRT549ZWZu72GOEpl4yf5t3wZ/8an8GBp4E/okNtaBYNpxmmz33puGY8y/3Zw02Ox34MVX1WkklJPJ1F64EDoX6FNBL6oZcLhetszqdTuogoBYrUr2W/ih8GfRh2afQO8JfGRi4B+KKzBrTgTFvhlqHHnY6nWBNp9PJZAbZ6eAtfGb8dLwtkLmfJvjiPSP6m6KCQuMRC/cIpZnmhNJRMVejD/jWiFMMHIuVVtc8zCsIYynNTGcoqpyNKLScd7/lcTQRXOzQ9Ayl1pAVpiI7lMlg+Irfq2oCJ/SX1+yGdIhg0MTAnXDV6poDm99izAEGYkyjxyA4Dx8sbgjf1HODnZkOhRoe94PbauR6VZqt8AmOr68vFVSXy8WrCfCOFF2XC7hLw/4HnhyeC/wAGVpqQn2NEML5fDb+RSj+CLZLS937buzo/zFvJA/O6QpufmtTUBgFZYSGv+Cmsth35QMDD8DCSM4PuXEfYDucBzW+hqEYL9LluJqjm2jCiIjo3CGptRBjquuserQa68rTUKupXn8GBn4WvfGMH2D4C8wRzZG1Gadgk+mZnmnvvpydIUyhlK+ImPnjnN3IOcOhiHW1FT6mlE6nk55Hw7wiog3ddblcEOzQjejDeo8D/5WR+xi4BXHjjCFjwGzSMUZ98gM5GpwNNGOq+iDYqDZovuWJ5nZBcdgUKXQFnfvfD7iK7Kag4LANGoZHQysCgi1HXcjAwCFYELz8hEdKahpBwQ+/iVx66SF1ReLt1MA4pryKd5kb0VRQUvwIXDn4le8X301zQqlJ2ndgYOCn4B9I/yR7ccHsYD7CTKS1jqy3uAUr2Gcg++smkKqMpc4q0js7kBnVi1TXAJ7F+XzW8yDToW6InkddFTSQJZnnWf0F/VFUdslIdgw8K8xgFihgh/QEexkeyHScTif9a/ayGAFT4Feao+lW7I9N4C6ggUlZ0vLHNA+qto3E51TmiQWqmDDSA0wETQWy8D1ZwxeDXAZ2YJOZ+YODE9ewDi8QONPBoruZEzSQQwlCcStNAIHii5HSE6iSYMqIpURiKmUUzBfQVzheaGIoKIPVhOGIsBjaHDQxsANrjM0PXR7gCMMXQoE8E5XsJQRDKw8ayCs/6tpvKtbmOd2B1AQIT7eAC9Sz0LaqifP5jC3MFzln9VBEBOeJ5b2B8zyLK+tCH0wPb7k7AwPrEVxIQhxTCMX4A5VFqPvAfgSSGuprxDoDguOnehkroyZMx3YTx60JUV8xDU0BeoMrwQwaKccBWQG+wDEgCMQ+zE8IFYPKxhTpwMDhwHNoNvoB32w0dhH7mQ58yzT4Y7NXu3HYywF79MmXKiU/HMj1YH2FBr4oFNr1cZp4aKnZwMCxMNTAlsxPtdR24WmCCQJ2YWjFaBY51C4OiE3wMM49Q4IDF49KkvP5rIfpRPLz+TzPs8Ym0ECmQ09ikilYHSsTxGmcZXERxwpXAytw1di8dpCaIyJF6yIFIHrZDeB8PqvH8fHxwZkO9jIM3RiJccgdOCDTYcIBoQQRkBON9ZxR3YI7pYzgVZZXYrpAHkRErKOY3AfZEpXY8ZWBX4LQ8iCWjzfGiTaeZNhw82n34jq6qRyGgEIdj/AduJ0sDpvT4Td6oQVabd4abvCCHEI0DJeEzy836KsDhdnAm+GWZ4O/y8+/ZwcpbnUIAWFLQxPm+B5liCMF04fdt+KwhGgk/a9tLYvSC1CXQZeo4pTH+XzWXR8fH//rUFnGCpkOblwuFyxso9VWsZ5gjiSI1KHNoRQG7gRWHLDG6OKLrAs4tbHgd3x8fMSS6TAJDvjvLCj8jx51jYfRBBBcZhS6gFMY+MjEuZzywLc4Rap+B+sa7cDghYHHw2hboyOa6mBBU/c28hYvJe4hjQ9Yb6KpavgG4TYh8etvGbsbTd3FjIMT8q/jd03HzPaBgaPQfMbMoCU1axiLiK1gxOl08s8/rIBVSahjor1n/vaH/7BMR6aVrGKZzaFpi1gcMBRoT/Vs8RACVs1Fgyd36MHQCJjlwWVdIQT/1nKpsx7S9z5whttvyMAbIF6bLe4HRUMHoc5x4rH3uQxkNLStuT91NP78+YOECE4S60IBqeOjzeHzRhzpdPieBcqMgj44AzKVt/hM9erbuax/B8ckl3UrMq1JgfP4usyVOdHmJQyH5ZdjvXWZIw1TSD9aH0I41ctJBAphQlCwrDAIFOP3v37g3ZCjaKJpiuaWZVpXBh8nmgxmirUnWi+T77JQzjWW6kz89f+2TTa/9fiB98MOM+PR2wzm3raNzYMdmgAXBEr2xdr7Xujz06kJFv+6JZYALFIeU1mQSieSI/ehbU55cO7j4+PjcrmIiBZlaQMpDz2/Rj3Nr3PNlWkvX0gY3sdvxVVfQ5zPHzpgq55cgsM7HchrcIKDPRHdIuWdm7AvVih3EhR3yXSg0Ut5qFjQmktWCqfTSWMTuksbJ1oRT6lkoteUYvKI0Fp7pj87BEIY3sfvww7TMgYJggh1giPWkUg0lCngWZzcvC+2jqaakBZPHXlTROQeNGGAG4dYJtdchjrYy7tO5e3E3AZfMH1kWiBHf9SvWBM2Th7dRy4Dr4uVBuZJQWpDZW+CyQJVD5EimtzGo94kBSMZvHy446051ukwphU6KQ9WB6i2VLdCiocSQrhcLlpDovM+Pj4+9CR6jLobiN/A4+Ble5EoCW6auaz2PoQyLAPvh/U2ZgiC/8a6rknq+YpMCqGsQ6WPtJKCacDRQGEVhyoQ+JROgoPJ66i7dBc14XupXVerzjTLI5a4I/wIkAjSolyFqd86lcXyYqnvnCjDijgFfnqTjuhd0WCK98O+cdg/2E01EevQI8bFya0rgV2mMa14K4fpw5F3h3B3p0NcYiJQKAFcMLkV7qa6HBMKTUS+v78neolxpHpt3Cz9LSMfZPUrBU3/1xw28HJYb1f+SL/FRAqM7wBB4V0P44N4loGCiHXUY9Ml3IKDaQIWxdwG7aABSyGTnspkcwh7WCM+aspDGzqqf3x8fH9/55w19xFj/Pz8xJmDK9aG95FpuS3u8xoKiGPW+RvhRl8DQxH7GpGC9NACHx8fLCKwDhXnNZDp8KVW8FBCXcQsfY9D7sAdd1QTRvY3tRmKKUJxSbSG6nQ6qWTg3IcC7UwrUEyu4ArRCsNcYCgZAmFgC/h5Nh9Dnd1gORApqQEv40TzviZaqw6JD/1rTsi2E1q437U/wulQ+IuEo2HsHOFJNenv72+9cRrL5OQoDg6u4ArOiJSwqPTnjA7WGGjC216owwHGjA1NBMpQeLeCScDlLiEAAB+nSURBVIH5wjgpfJ7gchyPuQ93qZsItYxnR0NEVB2EMhNcv6IN+BE55z9//uhdUF8jxogkiMlriIiuf4VfREkFzzTnA/YJCvzoLfdn4McRV9RQMULta8BEETvQjVM988LIByQv1MvQBmc01A2ZpgmOCUc6IUmkLu70guIe3HFfNRFI8AuN+YneyoOUx1SqITS0ycFLuBuZ1q0wDf1F8EIs02M4IarH3Oh0DOnx0thtRaH2MvhjrEOPodRfL2QxTjShY3LVmdEh1BEQ04Hbb8syHud0SAlSsEfAxIzMBRIcXIXZZAcgF+C0qBDnSgp0Q1pkEdbFMlceNvCEWC/UzWGeI2Cx4t6vAfhchvEvjF6YXAYk1FGPUKc5HoZ70QSbItyQTAtb6aWanIhK+qnM1JBi8CrDjIdiGnpP9eTf398670O3wPvw+RQ+j6xWCsP7eEWs9zXYCCOlHpkd0I51amMqGQ21ec10TDQl/M+fP8oO2uBd6oPEGHm5KggQQ0nRLUVzP+54UN0Exw6lLoLSq1Xi4Fgm9MVCeRUfE8o63TgJex+Zpnt472OfQDD/lSExnhC3WI6xvVAjdlIbXhQ0cxxeVvAXOXJpKMnwwmNkxYNowjdAjZkmmPMWcIHxNcwWIb5AgGMqCRGhMUTdEHYxetphJWvwf2hwxBNihxX1jmfjxEfjYgQqbQBraINDEmAHE6Q4lYkLhilCKyrBuPU2rcB96yZCXaeAS4pUCiUk+1NKmC0OsGPC/GIa+DkhrsFpsb4uqAEekFDplI9fbLrY4YY8D9a7GAA/eE2DBDswTUyUyESSAvVRms5A9dTHx4fZ4ouplC+MMDFSwnCW3NPjkAeHMBVMFmb1bRYF6kFImfqVc+ZGpEoK3aLKAllP/V/iJLlMXU9lARvuUq+eYuAXwgxIxjLZFzAjP4ceWSNM9Zxx3oJG7BRZKIRY72EKgvED5VXwMjgHgYHdF1z5RqQSLD3z9/e37tKZpuqYYFE8ToIAmPHBHdNdRlPI4I63hrc6zxHiqhViDfYj2LnAFE/DDlNdZGGEw1SnV4Pz1h9MFo9Yb0Lcog9wCkSE55iHsnYuDsg5//nzR2dw/P379+vrSxvf399fX1+m8f39rQcz939+fqIbCE/0vA/0mR0Q7vky4pj38QRYb0Kh9jKkLyJC7WuwCoglnWHKqLDsrfoXqKGapkldD+yC1lCfhWlCytyNyU0JlYe4G4oHqQlDFryd1QT+GZnWwhRaDk9rKCAQmrM88JWpLGSsTDSVaWaxlHg1vQ90Nez1QfgCB2U8Bt7g933djNs83oQ6uzHV07GYOKZWUoNXkYCaMGmOQCtfhn7M8mHsADwu05HryVfYFWgdCqEsJmgCy/ZrQ81+KjPKT2XpGs6J6hYmBbAPtqB7xvuQDkesZA3zzxs08RjcQg1+i7HGpq9hfAQTbkDdBDcQmzjRElWBQqHGi+FjTCc9r90VPxPCZL6I9HpxWPJUyh9C8REipU7BOHAxcs5wOi6XC7shuuzVPM9fX1/675Gy2tWy99Eji2H5r46m1XGDMdV5jVjSGeprgBrYxTDzwdkNOdVzOiaaXW4CHKF2KyIVUz3+jv1AsbZvBHo1Oe4IBvlIlRRqzM2Gfl2XHobfgfMw6Wh0U+7vfcgQF/fE7Qbjx2TDEcbXMK4B/prX8JhXfk6dGu2mNuGf5l+XmstuvPCteGimwxsJ1AEEAmx4ooxmLokP2L9vqPeRyrrbmIeqJdshBM2Vsmbx3gd3TG7zPvhgxeCIA7F7XPXfWuCIpq+Bj6ZoyjgdJiRhYhOc5jBMMdVTOXpX+kiyeLSaMDoClhlpUWwTR+AlqtTy4aQkWmg7luUzEdfQyR3qfYiI+iMxRo1o6D9ANYguaRHK6wWzW0erRxYyjP9FYIzKj88sH7jBFRBwOmDnbPwnmqbx9+9fNXidrwFfYyop0kj5EbADBy9jHb80TseDBcUPxCY8AjlgmWaLxbKMVawrKU5llse5vBYIq1ToFinv/kFOJITw+fkJSYLchx481etuonYDc0CMr7SbGoa4uAV8926XEgscMZWqnLCY18C0LoQe0I60cgTvMmeI9JZA7kP80WIqj5+kCfx7Mi0GgXs0UTGVlJIKKUvXCE33ABCbEApJaFokkPehuxAlMj8RSumXERHopzFvv2XhevnjoImtuJ0asCU4R8MEApBiMB5Bz9dgh8LEMjlIgWruiSo1+SeiS4LKE5DFjxVrm+hApHLJVJbkx3YlCH1LINt2osX7lZX/+9//4luxFGs2vQ/NfQhNx0j1mlehuEUsSZgyYOfBuSRrwH7Wjbf0vRG3z84AvADxIoJ1RKjjDmy97CN4X0N3wen4z3/+o1zw9+9fPcmfP38gMaA4+G+sw6VNspC9XHkjfkxNwLTMxUNNJFrSEoaq9xR2pTUU2ghl0W09FbshofY+9F3n/HUAEoM9Duw1rsd6HTHwszDaQWqOMGQxUf2CkQ/LvgY3WG4YQIMwPFsxQcgPsQPwMzTRG34DLTOVaZ0rbDmV14tKvXDmx8fH19cXRn7OjLJIEXJeAq2pqbkVNnt1VaAvuJM9jsA/cnDHj6NpVD2OYEM1eYeei8E0AbIw0zd0CwcpjK/BZME0EZ8ju8H44RBmoJlgGO2lBCZSeeFwKNkNtXC96fw/1lOp06H/bDREJJa1RtX7UF7QhlZeZZqrjvINDmEY78P4IOyAyHa+iGMmSAc9a1k43n80Y7KXD7HEwth02dcANZg4JdIZaMDXQEP9EY5cGL7AIxrrqiovKH4QT5HpYOh9MdyB+IWUKeF6cKrfRRpCOJflKhYaQu8K0gaLFD5AyPfB8RAX+aASLFy4+enfjFC7orvPIM7jCK2sp3EBOBmBBsSCKX/gsCVLDPYyWJVEB8MIz8ALBj+c6TBRQAWr+hgjFs5U++TsBgjYJ0HwijDOfUhxOk7lDQCqLM7nMyaPQkdwZzItV4H/ZSovDehxRNieBBkcIbsC+73jmSNiXc44lcg308SpFEea4CI7Cyid4tjENE2m+NpHIjjSwdoBZCF9HfGz3PHzTkegFa5CiRcYK0VRAx+j4uJyuVwuF01eQL9N0/Tv3z99FP79+wenQ0lHvwXvY5qmr68vZpzL5aIzQbiAQpMsExWDooemvII9iK32j4fjF7ohh7ADG5tugU8aKdnJAhMGPJVXbyGaECnBAR2BQinvdGiDcx8T5UeNO2NUDB5pNOQIVXUInsXpCC59EGjpGtC/Hox/80SvIJ1K8oKfAKGUhzqZunSFnhAJ0ZyzBilg8BrUFDLXqbwcINbTw6TO2vAWOcgNYbwHdzQv7RZjMAMviwggUiFjrLOPrCbY15goW4EVIiAiYpnuaXwNfMX4GlOdQwl1tNIQ3I9TA+MpaCJ0sgasCXWcj/WCX7Bhk8XI9QuKzc+h4AqqBO6DcgqCmuac3hPRj5GCF83LkV2yorn9jWnikK+zmRlATRh2YBs2wcWJaqvNlPATzQGdaIYoM0WkFImJSgS3ajbaB96oo/AUNCHkfQiZWaxjhyZmgTVp4GsY70MFpHof8DmnUpHJKQ8pK1Z8fn6GkhVTVsLLPvCLupKFWQ6HIS1O4Sttbl+J+MpFWfGGQilZ1CCGHcTRBEciTEoyFEeDAxB4dwYY4VTPBJ/o/Rp+Bgf+qoY1T2CsE5+GI55QUDwLTQDB6XZuqK1O06QRR62P0pCkHmO8j0C5D668ktbLvtTmNTaBr0vJy6KHyg6xTDwTYjEOrPjGsULAPENPqzLu9KyHlpfBjehKldg+jYg41TWRLAd4AbuTK6bqTdbASczvsoLw4Et4KjwdTShCKwnigwJ+0G56H2YAZ+sF9ahw+Pj4UJWhEgPHcIQVq/KaGEqqX1ZqfuV2N6T39d1neAAOeegXzsDnb9rbVNZqBzuEMrBPtHKEyWIwUyBtgeJLLtPu5TWavoYJXnJvD7xd98Bz0YRhh0CTzdn2VDIgToED4FBcLpe/f/8aP+Lz8zOWjJe6EkoN8D70YLgbKiu0cTqdNBuiu8wsUqRs0UmkVCE0QisPgivVxm5rN4/Xz/ojN3oWQNNg/JBr2CHWeY3g/M2J5n3iJeCRFqGKZQqGFxFKEPyaP+NrIISBvAaSKdCnhrO4z8vX/oN4LppQMCNIXXCVqeyKvY+pzn2oHECcUv8NJvdhJIOUUgj4F3qMEooyhY5LPgkCj2Mq9d14as1SN80Y5+FawDxkD9Aad32szclZL+BjrGdeYwgJnXQGTBdbTEzBJDhO9RzQZoIjUgmWiUFMdV4jugTHA27jLXg6mvAcISTgI9U1Iy7Ax2tDU5uhlE4ZkcKr2ug5lWukTEIVetoypTw4nKlf4SRIKG88RuSCv2tCsOEObog/z+2nWvlzBz7fC6daEBHMDsYUjeCPlOzEdmQ3Oe7QdDrYMWGng0+74Gt4jvB37wnJ4uloQmHYIbS8D8y5iLQOFeQGdIT6FHA6EIbgTIdumef5379/+nx8fX3B6dBd2ubgJV4XpAlUVSLgC1aS3g2ROrohtTPyeDnws2gahpEM0gpVRlc65QdwRA1PNIkLHoGREnBDUCjFUgKZDn3qeG44YhOQJ+AIZoeer+GVxVPhSWlC4ZVF6Hgf0JzwPk6nk4YbVDLM86zPBPQF/wrqrLRqW2htCx6mlAhCqfIWmicGVwVaY8ENCa0kyP2oYc3Dt/BzV79+1MPtB1Xzb4ItLbgYU71OHMcjTm5uBbaw77DsdJjURnTRSh+nfF1fA3hemvAcIYveh5BDEUpsIpbq7FxKp4SW20z0dkLd5V8aBj6S8tIwnnWuykIrNZgdWDJ4NyTXc8YMRyw4I829a27jMpY54h4P8RrqwTFeRDA7BALbJ4uI0IpETK4iG7EGTnZ6p4OdEaaeQMvVTf3iCO7zpnvyg3hemlAYdggt70OhJn0qrwUTETVgLbhKKX19feH/p9kQdUnYs1DH5Hw+f35+GqcjhKAhD42bKjVgi/4WuAAs5t2QSNNe2dHw1yW1J8I3BDhEdNyJC/yvLGz3fTCa3EOcixEokRHcS71DKaMyEUfeqDmLWMqrwBqghia5xLp8k0nBOB3+uhbuzPPg2WlCEZyyMINwpNyHFOUv5INoqkKN+XT6/6vmKGOsCyi0plvJBWdDJlUpRug/jWiF6hcORkBoKHiqGI4Relz40sy1y4uHKnpDaLNhhl8pvAA0PX+ODgRaaYYjEVAT8CxiHaTgaeOgABCBIaBYh0gNU5gL6d2KZ8YL0ITnCHF2Be9AbTvTqhD4Fo/toXYoYJYorxIijkBOh9RJEBRNgAVAAbGObrJ8CMXfYfdE6tyNrAtY+EftSUhkjQ3AePyW4BDLUmZmY6jVhKEJZgpfB7UwX2NqZTqiq9TUnwBHGFHjOaJ5yYfe+LvgBWhCYdghdLwPKWHF8/ls4osalZymSYkglulkyHRoguN0OpnyKjgdelpNgigfaUPPgAAE5n2gFiuXFx2ngliqzhHRzK1siMKIDq8seEvzsbsfdyw/5X7wNFt4Y3DCQWgACM7hN+O2YQfABxHU4GM9SRxOR6RIxHJxRKjDokbRMJHJa/oawMvQhCI4ZRGc92GOwb9HOQLHcxkVPItcr+IdY0REQ0SUOLAwN4KdQvNBtCHka/BfPB+5BC8hWDgtYmIWaPDXzRbpcMEDxEXvcfccwW0/wDa3BKqdi+TwqylKvTxcrDORTBwTzb+AHFjgC1+jzR5HpIBlk628jrh6u54Zr0QTniPEeR+Kqby+HAYZ6rIobDmVWZ5qn7zGf6TMhUYrEPUUioaEUqDF0gar2kjJgOIt6qH4GoFiE9g+lSpS44/w9Xq+MFjjm9wP+C3zo82BNNSI5ABGV3YNC5yo6JYtdiqv4YnkYuCvcTE4SIFyCc5xMDVE52jEX+BrAC+5hPyCJk+0uDYqr9XaMdRr4kMbKhCwUZfn1obqBRyGXd/f37yLv4Wf0L0KhDBwDLsYPnLBH/0FNr0S6QgQ3nt1yxr4h3thS28gNfYjTkeEOv5nBHyo178OdeTSLxLF+QhTN4lJGdhl9MVEGdBm6RREDdroavMCm3fs+fFKaoIRnLIwsiJQ9CFSkUWo9YU29K2iMOx5ntnpwGmVU6QIXfVHQATwHdj+UTbOXeLwBGQFuyqGKVKZZtajCXPtyU39Mrfrxtve+6iINPXLjKKGHSLFHTwpSLljEPNSUlcQEZ4vvDFz/jK2pm/E2ukANfDXsT2S04G+LYiI5Xv1KnhJmrjKEUJOASwzlMKHWOIX5/MZs8KNZ4GTpLLKXoxRHQedchpL7kOjFexioMgCvcLXc6kHU3UTKCTB5IKrS5Q6DRSSEBfXDOSAsKHy8f6p3UQcCxzRbHuD8ZYT+9XWevBEM8GnuuyaN4ILYMa92Z+xFFlz9NH4I3BV2PUItWyZ6tlcps2XvHAPXwUv6XQARmZ770OKx4ExH95Hzlldg0wLYcJZYHdDoW4InA7sgtOhbeQ+jBsCT0co3qkdxnJYuATjj/ClgWsW/A4vNJbb69F86P1Gv93QBIIL2GLkeqT661OZgg0pgTN4/c95DcMXk8uDsr5Q8ARwjmuAiUJdwRXrWEl0vgaT5o4b/iR4STXhEdwsCf0PsaY13keu3yGG787ljUF6vHoWumuaJjgdU1mPG+GPiYqvpH4tUCpZT2gNnNOzQ3ITTDOVgYS6KMvoC/+Xn8470QS3zd/QURas14TUBLMDC4reSD7V6Qw2bzAFexa8ZaLMhZEesY594ld8x8TRYpMjXh2vTROwIv4IZKqeEnJDtDICA3UoM8RhmZHSGZAAgbIVsayFg3zKVHKZkdKfoAkUWeAX4YPowwdRk12K1MgKaUknIyK8prj6sbnFP+WeF/wBPWrghhl+I5VOxTpO2dyCMT+40ikjIlgsGKeDPQuUbOIYMxMEPIUHIDjgApk1Fu7VC+G1nQ4D1uG5DxX5Uuqp4RHAPWGnIxcn5fPzE04EUiTshsDpYDcEX9cTYkumzMtC7oNDJ4YUoC9SXWrBNwHH8EZ/067e2B4j8K5IE/CkpgbWDmYv1MSpXtzJswOP6p4dsMXrAtYXU137AL4IZQKIzg/kE3JUQvuMrjbRvDmvjtdWEx6hLiXgfxtsZioFkSwBQpmUocecaAZ6KEJDRQEWsIiuUhNzOkIJl+rBCEmoYxKpZBO0BfpgmsDlmABnoteFBAptGh3Bj2lTYjDWqAneZfYyTfS4ABsNF0jRF8H5GoGmeMJWe+kMhBgMKZiMpnFMYsu5MLTVFBGe9ZZv2uvirWiCOUL/c2xI+I/qxqnM7w5UK81imIsmpVRMYVoX2CEUnwXEAdLJpdwzUR03GiCF6DKj6GSsZ5rmunZTSgLV0wQuXO9Grv0RgD9epYnQUtGB1ERwOsJ8Bcd4LjC7WO1PVLxk2AGkgPiiiTtESnMEkgwgAuYLnRPImgVaw/dQauLr3Z/3wFs5HYAZOdnjEFLpMNdQAo2KXCdBsAVugn4L6QxkPbhwK5W1/PmE2JVduReLCP4hEEeiYgp2Q8x2cS6Gby+zg4fniyaDNGmiyQ7Ynutlr41ZGu2A2IQREaG1MpXni2ZdZiQXJlA6A9tzWSEtutwtLkTemiPkzdSEQSgBTh76ePjFvzzR+ldSJ0ECVUzFsggNHg7dxc90ojmj+njxFqgJnhUW6xAm+yPshkBB4FuGJmRFvab5KNtpomkVPR1haAIf5Vo6g02XnY5eMqK5xcsKL0ZCHYlgHcEdM5CaK9+PFwzekyZC/22DQv/USCVYEPkmCcL5S+yKdTpDaAISQhJTmVeCiEakdxHpMbnEO5QOUEDB/ghoAsoitioymx95o17yQmP5fi40zNDqP/qNC9Y4uXpK3F6WAzz4w/VYkAxMQ8wphpLwf5Ra+3Bbah3RvFFvhvd0Ohi94dSbU24lQdjLgA3rFjgmxtdIpciqtyXXyQ7eYvwRbESH53p5m+ZV+Atf4IvmR0ZoyWk2GN7V44hYuxuwQ6E1LHmEZ6OFVfMWE3RsbuFGoGTn5Mou+OdCP53hLzw4bfWWeE81YYD/YnYRTbmWBOEzJCqgiPUiuvA+2A3hLfpQJnoJEBbm5i255XRASuRaXzQ5wvCg1PEIQ5rASpqQlnksE0STLEzDsECsfQ3Y+cmtatkjhVhHKE1eI9SORqBIhKxOZ7w9NTDenyZCqwQrlOyGf9AzLV2JZwWeBXgBogOssVBVlSioiS2xfqVgpiAF9AVPSGO9sx7S4QvFAjv07mSoxcUadvDw6cZcKs0MKQQXwjRFDQtbzLdM0Xes0eQv6cslc1veG+/vdBjwcOoNKdVJkKbaRxlVrn2ETPkRfB3sIOUlQ9gC4zcuxkyT36EvmCkUzY2Z8qm59q385csNNGHGVXyMraXoQi0T2A7x10civBsSXcBSSv6Sl4GI/SkYTDSh9n1wmLTSGdLhi1+C30gTaCcqUpQ6WsHmZ0zRVEMxXyASAXBqEx+ZAtitwJnBDrmOj/DGTKVWninyot8hLWVxFcZgvBWFVtYz1IGJWEcBvCWziDAjf3NJmObHSNWTTDF8Zt8381Fq5yLW825/FU28v9NhEFrvOhc3Syp2sglow0QDvd0nlGwI8iNTmSQOR2Mui/pGCkmwP5KL98HUIPVU19yq4zZ8IUQTM71tSPoRCnHemb97UhsPCtKMafGAHFsV2awdeAsXKUAphKI4cFdjSXCEes4osh7omAlA8C5PEwbN+/CrCELx69QEw1tLorUeskOiwIQRAokijpmCjs0sBs/+YGngq7ZxjDnY9IrZhI+RDi+YvSthLMf/jTQHPDjJYAZt9gKCS4iGVo22oQDmF56gxVRi2EHKAIC9nhfQeb5w+ZXsAPw6NWGA/32ukyD4yAfHUkCFj7muAQ/1ylSJ6qlRTxVKEgRCA3Ye69LsRCUSnia835EokoJjtKupNQesqSl6aqLJEUJS3Mt12Ke4Yiq2fGaHWAcOjNBgZom1t+JlBfOF4QJsgd7hbjNZbH2c3hW/miZCnQSR8pQwZfAuHoQNmySahK5mjwcRH6FH4G4YEQFSQF6W+UKKtZtiCq71kOIHseiQWj4YWZEo79vjiFjP3ZKWXeF6M70JJZQaBCF9EWntFmPnsP/QkRXNbxlxEZwG4R6GWt30rqX5qPxa/Gqnw8DrcGNd5iPMNdRuCFOAr4aCfGBr99FKFiNmlzkbk4J3SYx8wDmDK1S9ikD1JtFN+mSwHcbWWhIsEMTlGtjIY6sEiynDEAdTidSZF/AO91n6Qkl+PTsAv1pNNIEnI9duCPbCukwkElsyzeMMNP000hKY+kCDXPArRmh4++81pBXCZKKRWkqwiFiPuLioRHPQlnoBu+UG27l3TJpbmCb4PNLKuTC4/6Y9YDBo4v9hCELIGPKiG5JrxYFdbKWBCrpYIGR6KweUhRSb9/KkGYDIJZ1h2ME4FJnkEkuM9Xdmwa6iqziA2jdGK3V2g+2c/REmBS9GlllGWhwhQ0TsxXA6lsDDr9ni2cEM8maEN6GEpgpouhX+GG0YUmDfp9mx7AQFrsg0AGYEs9EbntkeW0EKrwIMLzBBGAoQsnwOdphjeGOPFHq8MNihh0ETS+Cb44dib3tmqDfBheWGFDnAYC4w5zRbZPWM8lyriebFKrzZwMakY3jciC4JYhRHk0EAFiOeR/iEXq0Y4jANfy296x1QDJpYheYgvGCHrBSkzj40acJ/i2mC4bXDQmyixxH+6noX3rOcqxwRahUgLX3hScF/q8cOoZNVYXnSa5irG+xwFYMmtsEbmx+lm8aJ1fEWzLvpR/SSF3677x5+wnc1O9brXXLTrtjA2D6bGw1xeKzxUKRFN5NbAh9AZ3xX/XUNLGPQxDZ46zKW2RvJzUeOVjYtX1w9pY96mJP3fnqhtwuXJuukhLS4o2m0wTkCxmUwX2mGGHgjH9/rgOnwmqsb8Bg0sRNNe2sO7IYsTHuh8EHqnIU5YaorLJvHbKKJ9VhJE+w16Bd9vMDnRwxBsHZoEoQ5odTcgS3N9sBKDJq4FQt8IU5l8Mdm/KLJJrwRk7g8KTR/unmM6Zj5ojiJ7hvi2AEbFxgEfOErI/2RuR93EMcFXkEstAe2YtRNHAPzFOZ6vqk5LJfaCjzZuV6WKrr5qdAOOO2CdugRh7TYwcAwRe8yTaNJCk3j12+ZhmEH71ngt5o01GwMHIihJo5EzwibIzws35v3wi4jLpYbpif+f51XVG2Hug7V7BI3aC+TRU8+4CTNRKbZ5X/LdEkGXxyKQRN3wcKgbcxYyJ6xxRdZ+7kYV7WDJ4jmLt9noGdp3sibu/iv+Zjd3BDs6tWD+/M0uzrY4R4YTsd94Z/a5sicix9uNsJ0Y//VXgsc0XM9mlhPE9jbHNsXdi2ICE8TUnNNszHwGAw18QgsKP81g7902MGfSpziMLtW9orRG8DFUYPUSsH7AmtoYlme8MG9jwOHY9DEz2DZbtcQB7Z7+eDdEDTC9vnjHsFFK5ouBnZdZQ1/cPN43x54DAZN/AwWogM9BvFfacqN5tmWf3cH1tjwAneYvc3v9uhg0MTjMWji57HskvQa4ojgKk0c/r++aupo9NyEq9rBfxx4PAZNPCOu2nbPp+gdtrBrE7zFLoQVe7s2fRx4BgyaeEasSUmst/yrOY5bsBzg9FuussCgiSfEoIlXwkoPYpMY2YHdcmAIhxfFoIk3wT3oYBNGxPGNMcqr3hnDRAcOwVATvx1rHoBBN78cgyYGBgauIF4/ZGBg4Hdj0MTAwMAVDJoYGBi4gkETAwMDVzBoYmBg4AoGTQwMDFzBoImBgYErGDQxMDBwBf8HXFbeGxqAJxwAAAAASUVORK5CYII="/>+ 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elifUcMZcZ3MwOnGIwUoJDmDOVSLAfYXaBQfjMOBg/Pa/Ia/iPuK7UT2f4e+Ltf82Wq/dcOoOhORX7GtKyE+NoZEouArGzajYYU0lB6rhGpMpu3oIbq5QhZU2KSLVVYBwmI/0u1vLU85hjlIz0YA6+yBuRxevRhLGHHuDDm4F9powmjBnpDOgIWL66GCwf4I8s5DWkJFOMiBC3vi5TABqh9epQf/nSCTf0Djjk5vuNoeOMNLd7KW7YQYlgLkUKoU4oILoZSsYEskIdgUtZwA65j7nkSj8+PvTfp8doulQ9iz9//uA/q+5JKkXfHx8fYCj9VqYaDUiYVPxEpjbjfeRabhz2X7k/XowmvJEYsHWlFkz00bgPHJ40UUyQwpoEB/9cbjkaniZSXTeFK+W/5uNVvngMej/HA2mgKSTeQnAka4q5LLQrHQHiRUQiD0VcDZWeU6WB/ms+Pj70PiMSofPxcs6cBFF2QA0LSxLt/+wmpESqOlO8tKB4JZrocYTUfMFSP1HoIZcAAcINrA5YXygpmBgESw8T1GQXwyiX7MIQ3D3pvDS4eaXSZ4ervHA/4ujZPPYadgg0zYQtH98FI8DgL/RaIFYTuQQscslcIDYB4wdf6HYd9qU4HazaNFSpp8U/xV9RpIzs9/c3B0ekJEQ4ToFr5EuWVyOLl8l0sOVkB/yz4fn7lKRJTCBnwaRwuVwQepgp05EW86C5Lp0CETBToGPocM+zMKSAS5Z1pPAk/9CeDfB2MILfEhyiS0AG98IOUAmcDoQnI+U+kL/QvEasMx0nAiqv1DGJlB/h1AlqOrUoK7i5KgZ8K16CLF5DTTRH1x5ZzK7mer4G5DWYLwD2R+bFmghsgf1f6hcLM0Ac4nKcvi1PY/83ItMwi2tkg8n18lA4IFEIk+0tUI1WqPNB0Bd6nu/vb3ZDUqnH1QOUF4SCRFLUgWY0tM5K6sXEcX7FXE8/kdZ/7RUFxQvQRI8juA2Tm+us50xxRI4gwP41oMUfoRS808GkwwHRmcoxmKpy7WuYPvOFSP10Sos4ejfnHvf8diyYhzkgUEiSCTHWa1sLzRMDR2SaHsYbc5m4gdpqzPJgz0JEUD2Vi8ST4pLg5uuskK+vL22EEPSJ0oPnEpyWekpert/38dLex7PThB9gGazkU5mdkWiKZ86Z66OQxdCP//79g9PhiYMdk9SawYEFqXzFFEclpH79rw9A5JZq6Nn/PXhhgYy8X3DLr/BpzXZjLdAI4jwRoRKsuawVoo1IK2gqL1wuF1RGaf4ilpljKNz6/v7+8+dPogljeuT5fL5cLh8fH5oZ+fv3b6KUx/l8/vz8RHWWlP8y52WkTDDl/oNfwuvkPp6aJszj62kCxin1lHAe5OEIGIHglQKcDoQhQBZznf4wZ4ZYMC7GTK8IY6dDao4wPHj4Pbz31w/nkdAq5WL5kKh6ItNMEHw90VQRNfJMEzf4H6Few9fXF8c+c85aeZXKyz5ERI85nU7IhoBB1B/hdKyOExOt3+nv5AsJiueliR5HCElEjMwzFS8Zd4OlBGsKqAaOTSIq6Z2OS11hCb8j19EQ3zEpDsUCQfiP5lbceCfv/fWtT7k5Z88fEXJJcl2wJLUKUzvUfwQLjVxLFT1Ms5sY/IWeKE2RwumQwg7cPWaBXGpzuCIzl4yslKkiqVVsiivCVTwtWTwpTfgxlsG+hhnYMfhzASVIQRkByQs4Hf/+/WM6gLhg4kg06cP8LkciZNHFQFvqp9xf/qPu9FPA8AJvNBzBrr4Jahg3JNXLVcDFmMv6d5hIpp6FxjL1rzodGsj4+/evPhXqdOhzpbJCGUcDovBitBFofupE7xPgC3kh7+MZaaKnIxbIAgSRXF7DJy8QgDB6wRzM1JBcOiPTzM5cFITQuGR4gT/6azz8Bt7pzGt+7vCn3DwMXno03RANQAgtOIJEBkKYXFLJMctcnI6cs65YIyKfn5+aLv3+/jYd0IOFVtnRmIhQKXd2JRX+jvmrexI8HU30OELIAlnSgyNguopEKQmmAHAEfI1meZWPRPC6+xyP8GoiXxMRPTM+yrwfTBPSkQM3nsqfBxbOut1HQ6XY5Eyr+ErxTLXUkiu1pHgWzCDe6cC/L5bJ6egGPA4wyPl8nstCe3oYZqC9ovfxXDTRJAiAZTwLBzZsUxaFjaAGZDoulwvKq8zBcz3RK1GyM7lpGolmgv8UOyyc/PFIlNa9JVHS5AvcTLZ/mJl3Q0AKgdbjxrr7//79Ux8BSZBES2ZqCEOne2gDQwJ8jfP5rA0cLGX0Up9FSnhCygyUVC+6YbwPvsznIYvnogmpB4QmUzQDEz2PY6ZkJ8jCiwhWHBykNGdOrZqIXLs/pud8LXe6Uc8M08kDn3u+t1fdEIzhudQyIGoA+9SUB8YDOB0or1I5yZJBSlgBTod+XalnLtNGhdSNFPXRfCQ4eHHUjToET0cTitySFfD/m74G+whs+Vw9yYEJznTAT+m9eiOTo8EiItdhCMMUck8R8RI0IUf4I7klK7AruOosExFMJal5Ke8EAX2EUkwlpc5Kis/IoQqT6eAzSFmhV3ex96FfV5JiSmLvw1zXc3KEPA9NNA2MvQxjqGj3fA11LnS7CgrQgeY1Es3XwLcSJUcSJTKYHeBZXDovB5d7ZjFSa+2ZVwE6H90EyjVo8oW51XBzQg0ewy+XS6CXGCNnieDF6XT69+8fvIac8zzP6nQgRKXWrk7Hf//734+PD63R1HQJF1zpeZSkwGs814NvSKhTv09CGU9EE80GSwnDFEwWTV+D1QRCm01fA3mN5tt3mB3mep0bT23mKm6/IW+J5tXdYhLMIDwmexKJZZVNHJzrJIg2OAaZ6D3GKK8yHYZLoh+N98G5j1RKvxLN+0i0ULC/ih/HU9BEc8j1OmKm4oi0mNfg2gfwhWoKUIZfWoJPkuk9GpliIlIvWivlf7x8Ob2NW2/L26B3aSutoikreBfsX2huCP59Kh9mKqPG/1StfaKXgHDKQ/UCbNs3OFop/dwHd5i756nhScjih2kCt0ZIODA1ZDeti7UDZmfAa/gu0Da7G6AJVFXxylSQHvrTPA0015EIiIh0beE52W7qzZP8ErCd7OYL/C/gemD05sN6SZDz+azjRy4rdKvxI9NxuVyE4hGc8vj4+Pj3759+lNr7UBGq4gJRD4Qt+BIQLuGYa/5p7+Mp1ASDmUKKvOe4wNzJaHhfg2d/csDSUENyL90BF+TFdIZc44hNV33Q/XsHLIiFTSfhzKhQnUVySZBY3ug1l1X/LzQTRL+uW0IImg7TpSWEzJvjIJAM8D6UKUIIc8mAzDTrXOpFd39cPhj8JE2wbRgpIUXMe78Dtj1TvsNEGVhooGHWlWG9cGktGJHKqpa5A3FksXCBm+7GwFaDyR1x7jmi+a1LmZSBwQDF3VNZUNdEH0REVUYuS2zlUmeVSwxLiveBWq+5VHxJHaTg7Aw/Tk+SBPl5p0MoqSEUlYC7eKnrpmeKSpqiKe9rsA8CoYEEB6+pj4ClIQimKs8Rt7ODvHjy4q7QO7w+LWKsKzsHBB+NpMdcj+zW4/76+tK9OitM/YhcAlLqdIgIUh7qfZjcBx6bRGsaSqm84vcbh1LTISXqkUnR/BR+jCaMsRmOQIODiJle4QfiQL1D09cwZRHa8K5KcllP/r96dsAl/NTdG9gEWCCPyfj3JSphwL8bByNDAb0AWaFxCiGPg9u6V30KVStzWXJd6B0lQt5HplhmdiUhP8gUP0MTzXG4Rw0mEmEijqwvlC8u5d0ZfDyzRqKMRtPXaMqHqxwxWON5kFs+C5OFsToOGaJoCnsv5TWiQskL431IXWqJgk4UU2E9bqUPI3AUiF/05MNPkcUP0ARzRKrnSuU6ZMi+RqrXlVHVwPKBnQ72Nfy0cb809qWeppHrgKXhCM9x+whi+BorkW4oymK7Yo3AZIFBW9Mf0P8oZOCla9j7+Pv3L2xbExwafWCnQ3MfUiaYghdSSn/+/LmUwtBY1vJN9UJ+6JuZWvpgsvj5TAdbHZulCSXyx+96AUsTmDRzN1Id4+RIBLeNhGlKCenooPVXeswt+6243U74/9g8QyqJDwzsqWRApAQ4Ee9UZapr4XGv4HQEt7K2lGQHpzxSmT0Y6VUj8kyFmD+c6fC8YAgCRZBznc4wIQlOZ/AurrZKdaKE2Wd2s7maUqJp55uMfzDFLTB3b3cSJDu33xycShlFoBfz4GDjfUR6kyACEHA6eLrHXKonsEVKnkW3QEqklMz0MH8Vj8RDacKYXFM7ZLcglZmaxYFJrqTiGirOa/hiqkxTxTJFQFIdufQdNtfyyFs3cCNyHa3wsiJTQgS+RiwvE8KMUn5TsaY84H2k8lpDXaRX17CJMeK1Y/oU6a4QAha50AJNKUVfOBVHKFI9VezBKuPRNOEbZhj3vsZM2cq5VSJhGr0aKj7tTOv0zzRNoykfejpi0yUPHIt9ysKfxHCEURbKAjBd3Y5X9cBrQFQS0c1LeVOZbzD08cMJEy1aA/cHF5jJE9l9yfvwOJroKXYzks91kaVxQOBZGBHBmDs1VKAG42sIFdUYyM06YtDE/cD3dr3N+HG4yRFSRg4ENfEtLtnMpfJK6sBEpGX4Q5kDioa6M5gVllqvGkDAgsnCX/5jyOLHMh1GR0hZQX+uqxgudZ21mZ2BqRw6Nxxb5rIKbqpf+dnzNbgPMnyNdwcbWO54H5He2aXehz5Csbz4C7mPROUPf//+FXob0EyvEcHCnIGSLFhZTwUFghfYkmndPe7wg4MUD6IJY3hmxDZBAfAFQhJzvf698SzQWJnXyC1fQw6apjF45EewT1nw1733ketiJ/Y+YNJzyX3kMkMs0wpXHOb8+vrKpW4ilBeIcGMuM1aZF5Kb7uG7+gA8giY8R/AuE4AwroEx8mYS1McmLrRIxNzJawj5GlLzl9ymIwZTPB7mnq+xH29mufY+0PbeB1wDHGAM3oQkDClwGgWv/AmlakMoGyJuMS60H0kWd6cJtjc0eEiHoJjrUKVZkAp+hDYuZUq42cWrV7G+YD2SF32NpohYaflpVEw9AfQ/uKYWKzvvg1kg970PnD+2Xho2lzcJzWX9G7gM6o/oZKL//Oc/eua/f/9Chmhh+Ewzx/CUBnprmTz27R6Pjk340ZtilI0JmiwQVqoJDkMYv+Oqr9HkiIHfBkMf2XkfeliiyisOT0qZAGIa+i2kRXwjlZehzmUi6VxP95Afqtd+aKbDINXvv/EOAiwcWmCmAOSlzObi2MRcI1Oo8qqv4TliUMZvQHYy3hzQ8z5QZ2VyH1ICECklxCZ0i8YvjBuiXACOQEPqYVVa2vzlMx3mkgxBGAWBkISZqaGzwvWjNr6+vrDl8/PzQjPH2VtB9nSNr4Et3PndFzvwDEilBmH9V3ighlliJO95H3ykeg2hrKydymsijVeL581IFWyBKjFr1fAVGX1xV5XxMyFM3Di2XtYO/JEN/kKLX/eOgXBgUuC/np73WfjghSeH+QdttSI8IT3vA6EoUBJUAE8V5UdaeUQfVJ1IFkLQ9SbmeVadAtfYZDpSq4biruwAPIgmpBYUyWVAPVlwxMEUTfmGD0CkFrhLCwSx0v4HTTw/+H+0Mv3RPNJsZ46QWrloI1ExhR7DDewyxzCnBHpFAP5y2BK09cI04RWEkVtqt4YLLvX6VOpNeB/E70pUiwXnBZRhuCn18xrrCWJwxMthvRvCQzR/C9uh/1NJkebyrjB93nTX+XzW9bhDCJhIrnOLROTz81Ofos/Pz4+PD7gqaKA/SJcGWrY/UcEVd/gerHFfNeHJQlrFVJkKqMEXJnMxt/Id7GvMrj4C4s1Qldxm54MgXhc9sbDyuybGibN5yZDKOpdcIoGiCW3gHT/6kCOoqRvZDRGqzmA35GG5j0dP/QIvmOEd7gYHHVhomACEP2ymJMiCcFggi/VS4k73Z+ABWGlU2XkZPg/CTxH7GqG8vEcfS+xCbIJDEswXAH8LDaGl8R78EB5PE15BmOiD0Cq4M1VGzPWCEZrFuNTLUl3q6V68BCYrjkTpT/Y7bhQUt2iQgefBeu8AWqDrAAAgAElEQVRDwfKBvzWX6inM4JD6IUnldR6ZJpJHequoGgWO4eUq5pLp0FNp43K56LR0eBwmqHmnlMfdE6J811hEiPM+TGwSQQo4I6meuDG72oqFSITUjs8w+IGt8IIi1JMvAhVQYD7oTK/niGX5XDT0K9/f36FUUuiZUXCVy3sDvawQkjPoz52u/XFOB5NCpqUuU50BzVQ6ZfwO42igIIKBkwsVRFzVEYMyBprwI3Ou86O6MZWXns+UyAylOls/XsosD0QoODChYQiUYM2tgivoEZyTF866Kw6mCWOKPLCnUigBOlB7vrip4iij4rVwU0paQ5Vobji+CD0C6sl13cTtHJHGfI03gj4G++Z9SCGL5PKg/FH/YrqH7srFs9AlsC5lkf7mSfg8vDwn5qTzMUJRErP9dtxFTfQG8LmUWmaaAGrExaUscm0Clr5WIlFSY64LJaQkXA0peI5YeTkH3pyB54EXC1u/hcc70AKWeAghKPC4ipvcgQNCCJpPRZhT55WlkvJgNTGXBSzEkdctN6SHB5VXpboIks17rt/cydsZvY2J8qm59jJ8N3b7GoMp3hKsFK4e2fM++FTwCPCcI6ww1+VVSit4qnXLXFKn2AVSAMuAicAaB96QHg6jCSMcQHu5vPNCqKQqU8ySSyH4FRtzXTqFl3Ro5UmPMsSlXbljpsMrr2jgjYH/8tXcR3beR66XlkLoQQ1ezwy/BhSAFWt0oRptYIsejNni+rTnnHWCOQou9LBUirs4oqk4NuVxr4SoV/szzbMAL4AvcolTMMWCVtjRSC6pwaeVcu/4p/ddxe23YuCFsF5ZLHwLDyS0A0Z+SAZMCZ1LSRVcDDUBRDehR8wKV7wLyVShh/aVEqIK9gVMTLHnZTSrMJk7cJg5obQWv9VubCWOQRO/EGuG3+wCE6GeZ5GoJiJT5B6ZDi2sxJMMvvC5j7n2xNmIQj0D7d4pjyOdDnEeB0b4TC6WiKAsin0NZDG4cSlv3PDFVEaAGHaApvC65uqFDI74tUgrKq+YHQxHMIOk+nVh8ES4mEofNnUotKFxTW0EKp0CEfBCeKGeOeZTHs/odDSHcRGZKcGRKCuRKfTIAmGuy6sy5UG44f2O5q9vsvlBEAN5i/eRndOBBgb85AquOGCZc+byKtPI5JXzuIuYyPyQlMcxNNG0rlwnOFILxqEwcotF11wvIcEKgv1AQxNbzX7QxIBsN7Pc8T56BVepRCuQ1MBDjjkd+t1EFVZIjiBRIqWkoieBN1HeAg6gCWOWuZPgQHzRBCAwJRxuhZ+4gbbulRITNc5bboH7ufIqBgaueh/ZBSn816UunZKSqtBjcP5Yv/IH5dshBMwxR/n2TK8CEirNyC7lcWCyY/Ob4K/CWKbRSwrjfXg1gb3GMeGDmQg8Rxx+XQMDV2EewuQmKPMzbByKuVUcxNvZCtiRn0vIT+422t1KE+iW6d8ad8OEG1JdfMl3CnvRlnrKxtX+DOIYOBy9Z8xs9E+v+Wge9cviW2Y8mJWu9mcfDgthmu6mutIplfnjqZ4JygkO/zZQAH5Koninudf8PzPto65xYMAj1/kOoUgECiUyRdDgLyDlweXb6iOggZQHL8mNXXj+4XqYci9+LdAtuJUm/EhuuI3lVqawBRu8j1l6SeZJIZGi833Y0f+BAQaejfXuvf8KnsaeMSOWmamYai7vAZtLYQWbAwxKKOWRqHw7t4o7brkVN9FET2UZpjBGnp0b4qMVxtfI9aQPnBw/vZUdmlcxMGCwgynMF/Ex0wpXQsHIXHsfkV4XqA0st20efm5IbXemGxA7u8nisEyHN1eOOMDXQLaC52ssuBvsdxg1Ia1poM3b1EMac8MHVkAfqoVZ58YIM7kheMZQBAE1MdO7heGehPIGwFCvWIPpHsj06QtBMLUMPwH64PUyb8T+EKYfvbmLbMmgCenkPlhB+AQHEyfzDgSF+fXdVzQwcDuaQ3pykTsjB5qamlUGvoK8hgnPmV/xvbrloo5JiHLnWAWZLEau3Q3mBZPgMIxgGIRPyDjkWgYGjoJ/RNOiE21IgWcteVPCtxCwECoSl0MHzp1OB3cLDf7LvYeRX+jtO3rBeO24SYJyggPnwS0zd8H0AXtvuzMDA9uQ68BhdjM+Mq15JWUclTIpI5eUB8IWgVbHwzrdah3wUAItbKWuSqAVNE3H8l4f5IBMBxObseHUClh6KcE8kmsBZs7A58wtl2dln2+86oFfCDw2ayzNGySbydWUx4Ve1RFooRqDXDsaYIdU1tHa1OcF3GWGqJFGoA+vuJrZUP9d3pjIqfGCgjuz3NWBgU1YY3K5tfwE2onW4OaUR6pzmWY0VfrARzYoQxOJJpizmrgd+50OqSWD0Q5oGD+Cp2lg9udCSdVM89CZIAyJHnU7BgaOBdNEoLnn+jyHes7ohVbfVp9CZcU0TZryEJHz+SwimOUhtMa/UStMFrpLT77jKg7jm+xCFd6YPSM2AzmGUyE38CvJJTIHUww8G/wAluvcXNMETCO54GUzkCmdMfuoa9lDE72fhw1DFPFHE27I9SQWs5G1CbNM7oD7MChj4GfhH0gDY+eGJubWmgmI5TNfMMVIGT79IGr6tsNA9scmzAU3r0p9B6nnj+MvM6WZu8EeB6Zy+Pu76YKXb9/AwEokqphaczxGe3ydl9K/XC4abtQHXtMcs1t9O5UY/+l00urMuSxIg/gFfIpcZEsq4Y/d7sb/rnT3N/kW8Ec/+BuBYBjRCw0+D39FOkJuyIeBp4V/OPHENgc/YylcE2CGZC89jNWYn7sFx8zp8CyQnb/QDEmwavJyi6+Q5UNPSgy+GHgSZDeHojegikuCZJoD1rMXPQZZz9xxyVNZTdf3ZxM20wR3grf4Nnsfqfam5vqNGxdad9+zpoG/F/uufGDgYeCnlJ1feBZcEwWa0MnjnOlovunHuBuGgHw3dpDFTVWYhre8iEp18bmvj/AMYu4CTuivubml2dV91zgwsAw8WsuG1zTO7GQy2MFbgTENFRrYhfMkV38RaJ3+NV3tYVtswo/eXlnwgM8H8HWa7bMrxzZfX9mNhT4Pshg4HFcfrasDG1uBt5RMcT38kPHTzdeb5nO1G1exX02Y3nO/E8VmOXmRKN/BqY2cs/od/i4YGEq62snBDgMPQNr4dg9zfKKXY8/lVcNqFOfzORUnXUWEvnwYsgJOB76rekRKSkXqOqt92EYTCyO2tPwiprrUCbGw/XtabZ6wx5EDA0+L3vC2YC/sgBiradqOOSHaTX9nk/dxQHlVrrM7utG7GPjI0dpEaU6jF1JdK9K7y80tAwNPAj+eMS+wjjC2YIZStiDW1yJi4nrSL1Zu9mcNNtOEGd5T7RQxEYirqppparnxR7yvgXNKR6cs9zMdWqw6MLAM2PzVw9DgMdUYUSKHndtzeSm32QVeMDxiWGYfR8jtq1c1DThTeMLsMj1usmYTMlTDwLuAzbX5tPfsIrW8Dza33pE32s4GmuBfMj+caxHlL9ukQvFRD+bchyELPvkt1zkw8GyAMeOjsXApEX0pnoWxIG9oeiqctmmn/HMru7ozNpE7AkHI0WL5BLLwwsn7Wnw2z5p8ec1Lzevk38DA4ei5urnW2rLRiJoOe3bVRiuNaMeIe5PTYawRV+hJblkOeTrk8w+bH3hXsBFlp529ETWHTH+Y+Qm52YgOK6/y1s7UmOs1Qo1n0btmf7UyvI+BFweebX7Im9bujcL47EY7NM/jTUm2G9FamjDXxj+P3hv7Z71kch9eJqU6V9okkTWX2lN9AwOPQe74vL2Rz7PAgo2k4sJLPWcKoQp/vP8V/vWV2Fle1SMtvtrsfA2+GD5S6vqIHheajwMDrwg8wJi42XzgMwkEY02pzmuwNfGcjp4p5ceXV/FvN6/ZXIlvi6NVuZn8BgaeH4YR/MMvJNU9WTQNqmkyTYPdhLXL7yxwgZCdGwowsgLaoampch3RWOhGb28awc6B58DCY6wwe3l+B4sI73FIzR3G0Jg4xJnkMoMsYGcVptQSYNll8NxhroQvyTR2MN/AwGsBzznsiK0Dx0hnJO4ZHU6YazWxo4eHrawtrnZbWuEZZjV/bbyRT2uubdDHwIvCP7f+UWdqMBbEpuQNisfgY7u9IYTpOanZY7+dHYom/HmkU3/R69vh92Vg4EboE9ucvp2dUkgphRB00ToYAr96w0P6hma28+x104eVgczNdRPLe71qYCJMTi/xF7mda39kYOCNsfDwZ+c+GGXhkVaERbaa1f5i7dx3HJrXk2p/RIhWzHfNxQyyGHhjsMn4XWwC4At8ZCW+ySq3dnJDpqPXg2anWQL1Ks/5nNIqXF15NwcGXggL4x+2GPfBWBnD5D7YsnqKg39rpTXdFMLk3zBt7miisIrvMbMDf0wj3DDwa+DHSPAFNhrD8Y68t8Hex63YM6cj17LC6IIee/X2LhwvQzsM/ALwY7/SRnabVdPKrmLbehPmx7RhKkNYLymgjnzXjffRu4wdFzYw8OTwjzQ//MZMvO3wVA7+FtugOLM1Z17Z1SPXwjTdMj6Vv07T0R47DIIYeFf0nnBvFz3bYROTevw2bju27+jndZpYOK9nKXGMxX31uVJ8vccRmy9oYOA10SQLTweGFKRVYWTOIIvWtMbQ9i+Z2wyoiovN4hjjjOBsC6JDWrTq+zOCnQNPC9b/DPNgmye/lwpkM2kqdKkHb2NxaxihicPeSN7rh9liDhsWPjCwjOySILyLCUIclcgN1MC4KTbhG3xMj/Ca12a+6Lfs6OfAwPNj5cN/1Y78d/3XZa817ZxI3tzFFVaeI3z01V/k1t4PDLwxmvYiNAaz49+syDLnaZ55TU/2L3JndvkrkUVaMR+Tm/G6slebjh8YeDw2DYGGCPzXl23+ajhzK0EojpxIzh1KbuKGuJAsH28a639oMMXA82P3g90z9Z59HdflCldoYsGefSS2+RXe6+O33PZ1Wf7kAwPvBDO8m/HS7DI5QekMk8YYexmT5vE9rI1NLO9t/qr3lxa+tebMAwNviTUPuT/GDKsrPRRzzpX2devUr6Y0kBX6Ytj/wMBWXNUOPWO80eK2rV614Ahkgg+68iX5j/56Bo8M/CoY8/aGxlu8juCDexbkDU3utHqV+dUdIZOe6NhKCoNHBl4Lu5/wnkbY9Ls3RjcPmPrV3GUY8R4aYdDEwAvh8Iffj7iZIhTHduOYhOhVCri695BuDAy8GRYMp7kdTsSxA/PBdRPcp2XPoncBgzIGfjPW2EXPH8FhhxvRXcqrgCafeX/krn0YGHh1NH353pZ7YHOx9qaDVQLp3+Wvey9r5W8NDLwN/IC6fHCmteOuHr/8W8s4QE1cdZ/WE8T6X9x0/MDAM+Aej/pV49r0cz1smyEqW5yf+3kWQ24MvCgOf26bgb/1v76yP5vVBPsRAwMDL4TdZrtnkTsZsn9g4AWx22yHmhgY+C0YamJgYOAKflJNhBBuERc7vn7jLw4M/BR2POoH/tx91cQ+swwhxBhFJMZ4rFUPjhh4RdxjeFMTk71GcfAM0U1XiIPZQ1n+Op9/iIWB34lNg7+aCfsRm6xm08F3LNaGtTcJr8cFgyAGfjPW2AWOgWC/98h6ME34vja38HUOXhgYWIYR2l508AFyh7H2GJpo9t4fsLD3kG4MDLwZFgynuR0+SCDc3o39NAHBYzZe/ZYnvzVfbJ5q61cGBn4KWy3WK+41Zu/VhHH892HPl9dcrfcsDuQ2Gd7KwKvh2MfVG9RK+9pnOBtowlh+b6+qDBzG2VDzXUOWch9CGRh4foQWxEUlpLYpb27SYhBzBlnNKcDauomrV+gPNle70OmVZx4YeEusecibAzMaPUPbZLkLuMlj8f1b6Lrp/bD/gYGt8Ea0xuK2agePKzSxoBRU6gRSO82v8N4Yo/kWt42Uap58YOCd4I0ZbXF6AbYTFssljDF6O+0Z9QLWvs5ngZlCC6akyv/1p13ZY9+rMQ9t4Mmx/sFujqBNc+MtPCvCoPfFTbZ2ryrM0NEFfCU40rDd1l8ZGHhmNMf8NV/pmbq0Qpv7fmgltk398v0wFKAswH8Bk/LwDDJsfmCA0bQXfGQXHm1xjoa0RtOFXU3cqib873ny84zIe9f3dWDgtyE4Ad7TF+bjsQPwTeVVy40eBUqJZUqH55ZvxMDAO6E5rPaO4ZBfcIJ9gSNuZI09y9KYLnq28703oojZxMRv/QWbn/b9ubEQdWDgfugttmIebO+h9zIUoePUe5M5iiPkwGJt9MATnr9Cc2HmDGbLvgsbGHh+9J5wbxeeC9jieHsvVxrcuLse12li4by+x3xhXhr0OKJ5swZBDPwqNMnC80IoWsMcY8KWza/3fveqoW2e02HagdbPiQXmwnTjNE3BwYgrGZQx8GuwiRe87UzTNE1T0+X3WUX+RT7Jyq7eNJE8kIzhAEHvwjy49+a0I+Iw8HsQOs5CkzV6MOxgTPKW7m0zRW/evS1Sk4W0mAzXthywuOXyBgaeH01qQJxSWlYjfWlgjvHfMj+3BhvKq3p2bqw9EvQrUEcG/oJjf5ng0JIeAwMvB2NKzV3NWiljXPDlcZixrJ6i599aaU2b1cSmWxBICPEWPpizO9KipE09HBh4OTRN1xtFdBM3eGD21LDwc1vNamdC1NMBd9HTGNQEH7ygHWSRdAcG3gZhUSYzO4hLCwQHaQ3VTRrahLUzRM1lMOHlnL0T4f0LoVSIQUpJG3oqTZ1ow1xkbzKoHjymig48DxYMsjnEggia7oOHPzjWrorZHinAudw9j51VmP5ShWRSaIVeDPmJ41HDCFuvZGDgRWFG+94WY0FGUAit5xJbyziY39qEwxbgR8PDk2JY9FBAlnxO83ODPgZeEf65ZUv2g6sZL70RefOBETV/bh92TiT3lyGO8Pz1wP57iQ9ZfOHoMjsEItGBgZ/FwmOsMHtNjaK0HIfo8hre0HjolZYGMb++kkd2ZjoMb3liQ1uLL5uk0LwGozXMtS0zxcDA88OMr8aIgnPYm2Mt2xFqMRfIwv/opj7fOvXL/17oOxSx5V+EWo8072bzhwYGXhqeLMyuUCsCIx96xm8spXnmrV3dthamph6alxFLriHGmFLCRq2t0lyGiGDLNE3zPBtBhTMgx4H7klIyiYzQSnzEkfIY+FH07LA5oIoT5rCFpnZQwwkUsIQ19RSH/5VefxZw65wOf1OwJVK4QaS9nqdB7zy7Ozkw8MwI19bIbsIwwsrz3NLPPXM6+CNvj62wgoLrtXtTRZvfbf7WLRc8MPCzwIPtn3BPAd5Glu3IG1FspTy2GtH+Kkx/YaFTQ4XrgUDittFX0ilTNQ3TE9O9IUAGfgR4bg1Cy1Vfb0SwmqYReYuTRSPaMdAe4HRwO9ZRFmPeCx9xYf5bYeiIgfeCNxypjQjWDnPomYb/FtpNI9qHbcvS+Ov0bWmxF7qu5GemeMRFj8N8HBh4DzQ5wmw0lu+1AxuXN8nQ9zU22dSGOR38SyEETUbEkpWIJcWgCYuUklBe43Q6pZSmabpcLqGIJd3C39Kr1S24+Hme+d4h27Kczogj5THwQKy0uubg6jV4rFMY7KEH8jtiJ/fRVBa3yIoDJpIbBcF3oacpFrQTriTSxDj/Q7sveGDgR2CsgEd79jK8LfT8jkAynDcKFX0v9GRT549ZWZu72GOEpl4yf5t3wZ/8an8GBp4E/okNtaBYNpxmmz33puGY8y/3Zw02Ox34MVX1WkklJPJ1F64EDoX6FNBL6oZcLhetszqdTuogoBYrUr2W/ih8GfRh2afQO8JfGRi4B+KKzBrTgTFvhlqHHnY6nWBNp9PJZAbZ6eAtfGb8dLwtkLmfJvjiPSP6m6KCQuMRC/cIpZnmhNJRMVejD/jWiFMMHIuVVtc8zCsIYynNTGcoqpyNKLScd7/lcTQRXOzQ9Ayl1pAVpiI7lMlg+Irfq2oCJ/SX1+yGdIhg0MTAnXDV6poDm99izAEGYkyjxyA4Dx8sbgjf1HODnZkOhRoe94PbauR6VZqt8AmOr68vFVSXy8WrCfCOFF2XC7hLw/4HnhyeC/wAGVpqQn2NEML5fDb+RSj+CLZLS937buzo/zFvJA/O6QpufmtTUBgFZYSGv+Cmsth35QMDD8DCSM4PuXEfYDucBzW+hqEYL9LluJqjm2jCiIjo3CGptRBjquuserQa68rTUKupXn8GBn4WvfGMH2D4C8wRzZG1Gadgk+mZnmnvvpydIUyhlK+ImPnjnN3IOcOhiHW1FT6mlE6nk55Hw7wiog3ddblcEOzQjejDeo8D/5WR+xi4BXHjjCFjwGzSMUZ98gM5GpwNNGOq+iDYqDZovuWJ5nZBcdgUKXQFnfvfD7iK7Kag4LANGoZHQysCgi1HXcjAwCFYELz8hEdKahpBwQ+/iVx66SF1ReLt1MA4pryKd5kb0VRQUvwIXDn4le8X301zQqlJ2ndgYOCn4B9I/yR7ccHsYD7CTKS1jqy3uAUr2Gcg++smkKqMpc4q0js7kBnVi1TXAJ7F+XzW8yDToW6InkddFTSQJZnnWf0F/VFUdslIdgw8K8xgFihgh/QEexkeyHScTif9a/ayGAFT4Feao+lW7I9N4C6ggUlZ0vLHNA+qto3E51TmiQWqmDDSA0wETQWy8D1ZwxeDXAZ2YJOZ+YODE9ewDi8QONPBoruZEzSQQwlCcStNAIHii5HSE6iSYMqIpURiKmUUzBfQVzheaGIoKIPVhOGIsBjaHDQxsANrjM0PXR7gCMMXQoE8E5XsJQRDKw8ayCs/6tpvKtbmOd2B1AQIT7eAC9Sz0LaqifP5jC3MFzln9VBEBOeJ5b2B8zyLK+tCH0wPb7k7AwPrEVxIQhxTCMX4A5VFqPvAfgSSGuprxDoDguOnehkroyZMx3YTx60JUV8xDU0BeoMrwQwaKccBWQG+wDEgCMQ+zE8IFYPKxhTpwMDhwHNoNvoB32w0dhH7mQ58yzT4Y7NXu3HYywF79MmXKiU/HMj1YH2FBr4oFNr1cZp4aKnZwMCxMNTAlsxPtdR24WmCCQJ2YWjFaBY51C4OiE3wMM49Q4IDF49KkvP5rIfpRPLz+TzPs8Ym0ECmQ09ikilYHSsTxGmcZXERxwpXAytw1di8dpCaIyJF6yIFIHrZDeB8PqvH8fHxwZkO9jIM3RiJccgdOCDTYcIBoQQRkBON9ZxR3YI7pYzgVZZXYrpAHkRErKOY3AfZEpXY8ZWBX4LQ8iCWjzfGiTaeZNhw82n34jq6qRyGgEIdj/AduJ0sDpvT4Td6oQVabd4abvCCHEI0DJeEzy836KsDhdnAm+GWZ4O/y8+/ZwcpbnUIAWFLQxPm+B5liCMF04fdt+KwhGgk/a9tLYvSC1CXQZeo4pTH+XzWXR8fH//rUFnGCpkOblwuFyxso9VWsZ5gjiSI1KHNoRQG7gRWHLDG6OKLrAs4tbHgd3x8fMSS6TAJDvjvLCj8jx51jYfRBBBcZhS6gFMY+MjEuZzywLc4Rap+B+sa7cDghYHHw2hboyOa6mBBU/c28hYvJe4hjQ9Yb6KpavgG4TYh8etvGbsbTd3FjIMT8q/jd03HzPaBgaPQfMbMoCU1axiLiK1gxOl08s8/rIBVSahjor1n/vaH/7BMR6aVrGKZzaFpi1gcMBRoT/Vs8RACVs1Fgyd36MHQCJjlwWVdIQT/1nKpsx7S9z5whttvyMAbIF6bLe4HRUMHoc5x4rH3uQxkNLStuT91NP78+YOECE4S60IBqeOjzeHzRhzpdPieBcqMgj44AzKVt/hM9erbuax/B8ckl3UrMq1JgfP4usyVOdHmJQyH5ZdjvXWZIw1TSD9aH0I41ctJBAphQlCwrDAIFOP3v37g3ZCjaKJpiuaWZVpXBh8nmgxmirUnWi+T77JQzjWW6kz89f+2TTa/9fiB98MOM+PR2wzm3raNzYMdmgAXBEr2xdr7Xujz06kJFv+6JZYALFIeU1mQSieSI/ehbU55cO7j4+PjcrmIiBZlaQMpDz2/Rj3Nr3PNlWkvX0gY3sdvxVVfQ5zPHzpgq55cgsM7HchrcIKDPRHdIuWdm7AvVih3EhR3yXSg0Ut5qFjQmktWCqfTSWMTuksbJ1oRT6lkoteUYvKI0Fp7pj87BEIY3sfvww7TMgYJggh1giPWkUg0lCngWZzcvC+2jqaakBZPHXlTROQeNGGAG4dYJtdchjrYy7tO5e3E3AZfMH1kWiBHf9SvWBM2Th7dRy4Dr4uVBuZJQWpDZW+CyQJVD5EimtzGo94kBSMZvHy446051ukwphU6KQ9WB6i2VLdCiocSQrhcLlpDovM+Pj4+9CR6jLobiN/A4+Ble5EoCW6auaz2PoQyLAPvh/U2ZgiC/8a6rknq+YpMCqGsQ6WPtJKCacDRQGEVhyoQ+JROgoPJ66i7dBc14XupXVerzjTLI5a4I/wIkAjSolyFqd86lcXyYqnvnCjDijgFfnqTjuhd0WCK98O+cdg/2E01EevQI8bFya0rgV2mMa14K4fpw5F3h3B3p0NcYiJQKAFcMLkV7qa6HBMKTUS+v78neolxpHpt3Cz9LSMfZPUrBU3/1xw28HJYb1f+SL/FRAqM7wBB4V0P44N4loGCiHXUY9Ml3IKDaQIWxdwG7aABSyGTnspkcwh7WCM+aspDGzqqf3x8fH9/55w19xFj/Pz8xJmDK9aG95FpuS3u8xoKiGPW+RvhRl8DQxH7GpGC9NACHx8fLCKwDhXnNZDp8KVW8FBCXcQsfY9D7sAdd1QTRvY3tRmKKUJxSbSG6nQ6qWTg3IcC7UwrUEyu4ArRCsNcYCgZAmFgC/h5Nh9Dnd1gORApqQEv40TzviZaqw6JD/1rTsi2E1q437U/wulQ+IuEo2HsHOFJNenv72+9cRrL5OQoDg6u4ArOiJSwqPTnjA7WGGjC216owwHGjA1NBMpQeLeCScDlLiEAAB+nSURBVIH5wjgpfJ7gchyPuQ93qZsItYxnR0NEVB2EMhNcv6IN+BE55z9//uhdUF8jxogkiMlriIiuf4VfREkFzzTnA/YJCvzoLfdn4McRV9RQMULta8BEETvQjVM988LIByQv1MvQBmc01A2ZpgmOCUc6IUmkLu70guIe3HFfNRFI8AuN+YneyoOUx1SqITS0ycFLuBuZ1q0wDf1F8EIs02M4IarH3Oh0DOnx0thtRaH2MvhjrEOPodRfL2QxTjShY3LVmdEh1BEQ04Hbb8syHud0SAlSsEfAxIzMBRIcXIXZZAcgF+C0qBDnSgp0Q1pkEdbFMlceNvCEWC/UzWGeI2Cx4t6vAfhchvEvjF6YXAYk1FGPUKc5HoZ70QSbItyQTAtb6aWanIhK+qnM1JBi8CrDjIdiGnpP9eTf398670O3wPvw+RQ+j6xWCsP7eEWs9zXYCCOlHpkd0I51amMqGQ21ec10TDQl/M+fP8oO2uBd6oPEGHm5KggQQ0nRLUVzP+54UN0Exw6lLoLSq1Xi4Fgm9MVCeRUfE8o63TgJex+Zpnt472OfQDD/lSExnhC3WI6xvVAjdlIbXhQ0cxxeVvAXOXJpKMnwwmNkxYNowjdAjZkmmPMWcIHxNcwWIb5AgGMqCRGhMUTdEHYxetphJWvwf2hwxBNihxX1jmfjxEfjYgQqbQBraINDEmAHE6Q4lYkLhilCKyrBuPU2rcB96yZCXaeAS4pUCiUk+1NKmC0OsGPC/GIa+DkhrsFpsb4uqAEekFDplI9fbLrY4YY8D9a7GAA/eE2DBDswTUyUyESSAvVRms5A9dTHx4fZ4ouplC+MMDFSwnCW3NPjkAeHMBVMFmb1bRYF6kFImfqVc+ZGpEoK3aLKAllP/V/iJLlMXU9lARvuUq+eYuAXwgxIxjLZFzAjP4ceWSNM9Zxx3oJG7BRZKIRY72EKgvED5VXwMjgHgYHdF1z5RqQSLD3z9/e37tKZpuqYYFE8ToIAmPHBHdNdRlPI4I63hrc6zxHiqhViDfYj2LnAFE/DDlNdZGGEw1SnV4Pz1h9MFo9Yb0Lcog9wCkSE55iHsnYuDsg5//nzR2dw/P379+vrSxvf399fX1+m8f39rQcz939+fqIbCE/0vA/0mR0Q7vky4pj38QRYb0Kh9jKkLyJC7WuwCoglnWHKqLDsrfoXqKGapkldD+yC1lCfhWlCytyNyU0JlYe4G4oHqQlDFryd1QT+GZnWwhRaDk9rKCAQmrM88JWpLGSsTDSVaWaxlHg1vQ90Nez1QfgCB2U8Bt7g933djNs83oQ6uzHV07GYOKZWUoNXkYCaMGmOQCtfhn7M8mHsADwu05HryVfYFWgdCqEsJmgCy/ZrQ81+KjPKT2XpGs6J6hYmBbAPtqB7xvuQDkesZA3zzxs08RjcQg1+i7HGpq9hfAQTbkDdBDcQmzjRElWBQqHGi+FjTCc9r90VPxPCZL6I9HpxWPJUyh9C8REipU7BOHAxcs5wOi6XC7shuuzVPM9fX1/675Gy2tWy99Eji2H5r46m1XGDMdV5jVjSGeprgBrYxTDzwdkNOdVzOiaaXW4CHKF2KyIVUz3+jv1AsbZvBHo1Oe4IBvlIlRRqzM2Gfl2XHobfgfMw6Wh0U+7vfcgQF/fE7Qbjx2TDEcbXMK4B/prX8JhXfk6dGu2mNuGf5l+XmstuvPCteGimwxsJ1AEEAmx4ooxmLokP2L9vqPeRyrrbmIeqJdshBM2Vsmbx3gd3TG7zPvhgxeCIA7F7XPXfWuCIpq+Bj6ZoyjgdJiRhYhOc5jBMMdVTOXpX+kiyeLSaMDoClhlpUWwTR+AlqtTy4aQkWmg7luUzEdfQyR3qfYiI+iMxRo1o6D9ANYguaRHK6wWzW0erRxYyjP9FYIzKj88sH7jBFRBwOmDnbPwnmqbx9+9fNXidrwFfYyop0kj5EbADBy9jHb80TseDBcUPxCY8AjlgmWaLxbKMVawrKU5llse5vBYIq1ToFinv/kFOJITw+fkJSYLchx481etuonYDc0CMr7SbGoa4uAV8926XEgscMZWqnLCY18C0LoQe0I60cgTvMmeI9JZA7kP80WIqj5+kCfx7Mi0GgXs0UTGVlJIKKUvXCE33ABCbEApJaFokkPehuxAlMj8RSumXERHopzFvv2XhevnjoImtuJ0asCU4R8MEApBiMB5Bz9dgh8LEMjlIgWruiSo1+SeiS4LKE5DFjxVrm+hApHLJVJbkx3YlCH1LINt2osX7lZX/+9//4luxFGs2vQ/NfQhNx0j1mlehuEUsSZgyYOfBuSRrwH7Wjbf0vRG3z84AvADxIoJ1RKjjDmy97CN4X0N3wen4z3/+o1zw9+9fPcmfP38gMaA4+G+sw6VNspC9XHkjfkxNwLTMxUNNJFrSEoaq9xR2pTUU2ghl0W09FbshofY+9F3n/HUAEoM9Duw1rsd6HTHwszDaQWqOMGQxUf2CkQ/LvgY3WG4YQIMwPFsxQcgPsQPwMzTRG34DLTOVaZ0rbDmV14tKvXDmx8fH19cXRn7OjLJIEXJeAq2pqbkVNnt1VaAvuJM9jsA/cnDHj6NpVD2OYEM1eYeei8E0AbIw0zd0CwcpjK/BZME0EZ8ju8H44RBmoJlgGO2lBCZSeeFwKNkNtXC96fw/1lOp06H/bDREJJa1RtX7UF7QhlZeZZqrjvINDmEY78P4IOyAyHa+iGMmSAc9a1k43n80Y7KXD7HEwth02dcANZg4JdIZaMDXQEP9EY5cGL7AIxrrqiovKH4QT5HpYOh9MdyB+IWUKeF6cKrfRRpCOJflKhYaQu8K0gaLFD5AyPfB8RAX+aASLFy4+enfjFC7orvPIM7jCK2sp3EBOBmBBsSCKX/gsCVLDPYyWJVEB8MIz8ALBj+c6TBRQAWr+hgjFs5U++TsBgjYJ0HwijDOfUhxOk7lDQCqLM7nMyaPQkdwZzItV4H/ZSovDehxRNieBBkcIb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elifUcMZcZ3MwOnGIwUoJDmDOVSLAfYXaBQfjMOBg/Pa/Ia/iPuK7UT2f4e+Ltf82Wq/dcOoOhORX7GtKyE+NoZEouArGzajYYU0lB6rhGpMpu3oIbq5QhZU2KSLVVYBwmI/0u1vLU85hjlIz0YA6+yBuRxevRhLGHHuDDm4F9powmjBnpDOgIWL66GCwf4I8s5DWkJFOMiBC3vi5TABqh9epQf/nSCTf0Djjk5vuNoeOMNLd7KW7YQYlgLkUKoU4oILoZSsYEskIdgUtZwA65j7nkSj8+PvTfp8doulQ9iz9//uA/q+5JKkXfHx8fYCj9VqYaDUiYVPxEpjbjfeRabhz2X7k/XowmvJEYsHWlFkz00bgPHJ40UUyQwpoEB/9cbjkaniZSXTeFK+W/5uNVvngMej/HA2mgKSTeQnAka4q5LLQrHQHiRUQiD0VcDZWeU6WB/ms+Pj70PiMSofPxcs6cBFF2QA0LSxLt/+wmpESqOlO8tKB4JZrocYTUfMFSP1HoIZcAAcINrA5YXygpmBgESw8T1GQXwyiX7MIQ3D3pvDS4eaXSZ4ervHA/4ujZPPYadgg0zYQtH98FI8DgL/RaIFYTuQQscslcIDYB4wdf6HYd9qU4HazaNFSpp8U/xV9RpIzs9/c3B0ekJEQ4ToFr5EuWVyOLl8l0sOVkB/yz4fn7lKRJTCBnwaRwuVwQepgp05EW86C5Lp0CETBToGPocM+zMKSAS5Z1pPAk/9CeDfB2MILfEhyiS0AG98IOUAmcDoQnI+U+kL/QvEasMx0nAiqv1DGJlB/h1AlqOrUoK7i5KgZ8K16CLF5DTTRH1x5ZzK7mer4G5DWYLwD2R+bFmghsgf1f6hcLM0Ac4nKcvi1PY/83ItMwi2tkg8n18lA4IFEIk+0tUI1WqPNB0Bd6nu/vb3ZDUqnH1QOUF4SCRFLUgWY0tM5K6sXEcX7FXE8/kdZ/7RUFxQvQRI8juA2Tm+us50xxRI4gwP41oMUfoRS808GkwwHRmcoxmKpy7WuYPvOFSP10Sos4ejfnHvf8diyYhzkgUEiSCTHWa1sLzRMDR2SaHsYbc5m4gdpqzPJgz0JEUD2Vi8ST4pLg5uuskK+vL22EEPSJ0oPnEpyWekpert/38dLex7PThB9gGazkU5mdkWiKZ86Z66OQxdCP//79g9PhiYMdk9SawYEFqXzFFEclpH79rw9A5JZq6Nn/PXhhgYy8X3DLr/BpzXZjLdAI4jwRoRKsuawVoo1IK2gqL1wuF1RGaf4ilpljKNz6/v7+8+dPogljeuT5fL5cLh8fH5oZ+fv3b6KUx/l8/vz8RHWWlP8y52WkTDDl/oNfwuvkPp6aJszj62kCxin1lHAe5OEIGIHglQKcDoQhQBZznf4wZ4ZYMC7GTK8IY6dDao4wPHj4Pbz31w/nkdAq5WL5kKh6ItNMEHw90VQRNfJMEzf4H6Few9fXF8c+c85aeZXKyz5ERI85nU7IhoBB1B/hdKyOExOt3+nv5AsJiueliR5HCElEjMwzFS8Zd4OlBGsKqAaOTSIq6Z2OS11hCb8j19EQ3zEpDsUCQfiP5lbceCfv/fWtT7k5Z88fEXJJcl2wJLUKUzvUfwQLjVxLFT1Ms5sY/IWeKE2RwumQwg7cPWaBXGpzuCIzl4yslKkiqVVsiivCVTwtWTwpTfgxlsG+hhnYMfhzASVIQRkByQs4Hf/+/WM6gLhg4kg06cP8LkciZNHFQFvqp9xf/qPu9FPA8AJvNBzBrr4Jahg3JNXLVcDFmMv6d5hIpp6FxjL1rzodGsj4+/evPhXqdOhzpbJCGUcDovBitBFofupE7xPgC3kh7+MZaaKnIxbIAgSRXF7DJy8QgDB6wRzM1JBcOiPTzM5cFITQuGR4gT/6azz8Bt7pzGt+7vCn3DwMXno03RANQAgtOIJEBkKYXFLJMctcnI6cs65YIyKfn5+aLv3+/jYd0IOFVtnRmIhQKXd2JRX+jvmrexI8HU30OELIAlnSgyNguopEKQmmAHAEfI1meZWPRPC6+xyP8GoiXxMRPTM+yrwfTBPSkQM3nsqfBxbOut1HQ6XY5Eyr+ErxTLXUkiu1pHgWzCDe6cC/L5bJ6egGPA4wyPl8nstCe3oYZqC9ovfxXDTRJAiAZTwLBzZsUxaFjaAGZDoulwvKq8zBcz3RK1GyM7lpGolmgv8UOyyc/PFIlNa9JVHS5AvcTLZ/mJl3Q0AKgdbjxrr7//79Ux8BSZBES2ZqCEOne2gDQwJ8jfP5rA0cLGX0Up9FSnhCygyUVC+6YbwPvsznIYvnogmpB4QmUzQDEz2PY6ZkJ8jCiwhWHBykNGdOrZqIXLs/pud8LXe6Uc8M08kDn3u+t1fdEIzhudQyIGoA+9SUB8YDOB0or1I5yZJBSlgBTod+XalnLtNGhdSNFPXRfCQ4eHHUjToET0cTitySFfD/m74G+whs+Vw9yYEJznTAT+m9eiOTo8EiItdhCMMUck8R8RI0IUf4I7klK7AruOosExFMJal5Ke8EAX2EUkwlpc5Kis/IoQqT6eAzSFmhV3ex96FfV5JiSmLvw1zXc3KEPA9NNA2MvQxjqGj3fA11LnS7CgrQgeY1Es3XwLcSJUcSJTKYHeBZXDovB5d7ZjFSa+2ZVwE6H90EyjVo8oW51XBzQg0ewy+XS6CXGCNnieDF6XT69+8fvIac8zzP6nQgRKXWrk7Hf//734+PD63R1HQJF1zpeZSkwGs814NvSKhTv09CGU9EE80GSwnDFEwWTV+D1QRCm01fA3mN5tt3mB3mep0bT23mKm6/IW+J5tXdYhLMIDwmexKJZZVNHJzrJIg2OAaZ6D3GKK8yHYZLoh+N98G5j1RKvxLN+0i0ULC/ih/HU9BEc8j1OmKm4oi0mNfg2gfwhWoKUIZfWoJPkuk9GpliIlIvWivlf7x8Ob2NW2/L26B3aSutoikreBfsX2huCP59Kh9mKqPG/1StfaKXgHDKQ/UCbNs3OFop/dwHd5i756nhScjih2kCt0ZIODA1ZDeti7UDZmfAa/gu0Da7G6AJVFXxylSQHvrTPA0015EIiIh0beE52W7qzZP8ErCd7OYL/C/gemD05sN6SZDz+azjRy4rdKvxI9NxuVyE4hGc8vj4+Pj3759+lNr7UBGq4gJRD4Qt+BIQLuGYa/5p7+Mp1ASDmUKKvOe4wNzJaHhfg2d/csDSUENyL90BF+TFdIZc44hNV33Q/XsHLIiFTSfhzKhQnUVySZBY3ug1l1X/LzQTRL+uW0IImg7TpSWEzJvjIJAM8D6UKUIIc8mAzDTrXOpFd39cPhj8JE2wbRgpIUXMe78Dtj1TvsNEGVhooGHWlWG9cGktGJHKqpa5A3FksXCBm+7GwFaDyR1x7jmi+a1LmZSBwQDF3VNZUNdEH0REVUYuS2zlUmeVSwxLiveBWq+5VHxJHaTg7Aw/Tk+SBPl5p0MoqSEUlYC7eKnrpmeKSpqiKe9rsA8CoYEEB6+pj4ClIQimKs8Rt7ODvHjy4q7QO7w+LWKsKzsHBB+NpMdcj+zW4/76+tK9OitM/YhcAlLqdIgIUh7qfZjcBx6bRGsaSqm84vcbh1LTISXqkUnR/BR+jCaMsRmOQIODiJle4QfiQL1D09cwZRHa8K5KcllP/r96dsAl/NTdG9gEWCCPyfj3JSphwL8bByNDAb0AWaFxCiGPg9u6V30KVStzWXJd6B0lQt5HplhmdiUhP8gUP0MTzXG4Rw0mEmEijqwvlC8u5d0ZfDyzRqKMRtPXaMqHqxwxWON5kFs+C5OFsToOGaJoCnsv5TWiQskL431IXWqJgk4UU2E9bqUPI3AUiF/05MNPkcUP0ARzRKrnSuU6ZMi+RqrXlVHVwPKBnQ72Nfy0cb809qWeppHrgKXhCM9x+whi+BorkW4oymK7Yo3AZIFBW9Mf0P8oZOCla9j7+Pv3L2xbExwafWCnQ3MfUiaYghdSSn/+/LmUwtBY1vJN9UJ+6JuZWvpgsvj5TAdbHZulCSXyx+96AUsTmDRzN1Id4+RIBLeNhGlKCenooPVXeswt+6243U74/9g8QyqJDwzsqWRApAQ4Ee9UZapr4XGv4HQEt7K2lGQHpzxSmT0Y6VUj8kyFmD+c6fC8YAgCRZBznc4wIQlOZ/AurrZKdaKE2Wd2s7maUqJp55uMfzDFLTB3b3cSJDu33xycShlFoBfz4GDjfUR6kyACEHA6eLrHXKonsEVKnkW3QEqklMz0MH8Vj8RDacKYXFM7ZLcglZmaxYFJrqTiGirOa/hiqkxTxTJFQFIdufQdNtfyyFs3cCNyHa3wsiJTQgS+RiwvE8KMUn5TsaY84H2k8lpDXaRX17CJMeK1Y/oU6a4QAha50AJNKUVfOBVHKFI9VezBKuPRNOEbZhj3vsZM2cq5VSJhGr0aKj7tTOv0zzRNoykfejpi0yUPHIt9ysKfxHCEURbKAjBd3Y5X9cBrQFQS0c1LeVOZbzD08cMJEy1aA/cHF5jJE9l9yfvwOJroKXYzks91kaVxQOBZGBHBmDs1VKAG42sIFdUYyM06YtDE/cD3dr3N+HG4yRFSRg4ENfEtLtnMpfJK6sBEpGX4Q5kDioa6M5gVllqvGkDAgsnCX/5jyOLHMh1GR0hZQX+uqxgudZ21mZ2BqRw6Nxxb5rIKbqpf+dnzNbgPMnyNdwcbWO54H5He2aXehz5Csbz4C7mPROUPf//+FXob0EyvEcHCnIGSLFhZTwUFghfYkmndPe7wg4MUD6IJY3hmxDZBAfAFQhJzvf698SzQWJnXyC1fQw6apjF45EewT1nw1733ketiJ/Y+YNJzyX3kMkMs0wpXHOb8+vrKpW4ilBeIcGMuM1aZF5Kb7uG7+gA8giY8R/AuE4AwroEx8mYS1McmLrRIxNzJawj5GlLzl9ymIwZTPB7mnq+xH29mufY+0PbeB1wDHGAM3oQkDClwGgWv/AmlakMoGyJuMS60H0kWd6cJtjc0eEiHoJjrUKVZkAp+hDYuZUq42cWrV7G+YD2SF32NpohYaflpVEw9AfQ/uKYWKzvvg1kg970PnD+2Xho2lzcJzWX9G7gM6o/oZKL//Oc/eua/f/9Chmhh+Ewzx/CUBnprmTz27R6Pjk340ZtilI0JmiwQVqoJDkMYv+Oqr9HkiIHfBkMf2XkfeliiyisOT0qZAGIa+i2kRXwjlZehzmUi6VxP95Afqtd+aKbDINXvv/EOAiwcWmCmAOSlzObi2MRcI1Oo8qqv4TliUMZvQHYy3hzQ8z5QZ2VyH1ICECklxCZ0i8YvjBuiXACOQEPqYVVa2vzlMx3mkgxBGAWBkISZqaGzwvWjNr6+vrDl8/PzQjPH2VtB9nSNr4Et3PndFzvwDEilBmH9V3ighlliJO95H3ykeg2hrKydymsijVeL581IFWyBKjFr1fAVGX1xV5XxMyFM3Di2XtYO/JEN/kKLX/eOgXBgUuC/np73WfjghSeH+QdttSI8IT3vA6EoUBJUAE8V5UdaeUQfVJ1IFkLQ9SbmeVadAtfYZDpSq4biruwAPIgmpBYUyWVAPVlwxMEUTfmGD0CkFrhLCwSx0v4HTTw/+H+0Mv3RPNJsZ46QWrloI1ExhR7DDewyxzCnBHpFAP5y2BK09cI04RWEkVtqt4YLLvX6VOpNeB/E70pUiwXnBZRhuCn18xrrCWJwxMthvRvCQzR/C9uh/1NJkebyrjB93nTX+XzW9bhDCJhIrnOLROTz81Ofos/Pz4+PD7gqaKA/SJcGWrY/UcEVd/gerHFfNeHJQlrFVJkKqMEXJnMxt/Id7GvMrj4C4s1Qldxm54MgXhc9sbDyuybGibN5yZDKOpdcIoGiCW3gHT/6kCOoqRvZDRGqzmA35GG5j0dP/QIvmOEd7gYHHVhomACEP2ymJMiCcFggi/VS4k73Z+ABWGlU2XkZPg/CTxH7GqG8vEcfS+xCbIJDEswXAH8LDaGl8R78EB5PE15BmOiD0Cq4M1VGzPWCEZrFuNTLUl3q6V68BCYrjkTpT/Y7bhQUt2iQgefBeu8AWqDrAAAgAElEQVRDwfKBvzWX6inM4JD6IUnldR6ZJpJHequoGgWO4eUq5pLp0FNp43K56LR0eBwmqHmnlMfdE6J811hEiPM+TGwSQQo4I6meuDG72oqFSITUjs8w+IGt8IIi1JMvAhVQYD7oTK/niGX5XDT0K9/f36FUUuiZUXCVy3sDvawQkjPoz52u/XFOB5NCpqUuU50BzVQ6ZfwO42igIIKBkwsVRFzVEYMyBprwI3Ou86O6MZWXns+UyAylOls/XsosD0QoODChYQiUYM2tgivoEZyTF866Kw6mCWOKPLCnUigBOlB7vrip4iij4rVwU0paQ5Vobji+CD0C6sl13cTtHJHGfI03gj4G++Z9SCGL5PKg/FH/YrqH7srFs9AlsC5lkf7mSfg8vDwn5qTzMUJRErP9dtxFTfQG8LmUWmaaAGrExaUscm0Clr5WIlFSY64LJaQkXA0peI5YeTkH3pyB54EXC1u/hcc70AKWeAghKPC4ipvcgQNCCJpPRZhT55WlkvJgNTGXBSzEkdctN6SHB5VXpboIks17rt/cydsZvY2J8qm59jJ8N3b7GoMp3hKsFK4e2fM++FTwCPCcI6ww1+VVSit4qnXLXFKn2AVSAMuAicAaB96QHg6jCSMcQHu5vPNCqKQqU8ySSyH4FRtzXTqFl3Ro5UmPMsSlXbljpsMrr2jgjYH/8tXcR3beR66XlkLoQQ1ezwy/BhSAFWt0oRptYIsejNni+rTnnHWCOQou9LBUirs4oqk4NuVxr4SoV/szzbMAL4AvcolTMMWCVtjRSC6pwaeVcu/4p/ddxe23YuCFsF5ZLHwLDyS0A0Z+SAZMCZ1LSRVcDDUBRDehR8wKV7wLyVShh/aVEqIK9gVMTLHnZTSrMJk7cJg5obQWv9VubCWOQRO/EGuG3+wCE6GeZ5GoJiJT5B6ZDi2sxJMMvvC5j7n2xNmIQj0D7d4pjyOdDnEeB0b4TC6WiKAsin0NZDG4cSlv3PDFVEaAGHaApvC65uqFDI74tUgrKq+YHQxHMIOk+nVh8ES4mEofNnUotKFxTW0EKp0CEfBCeKGeOeZTHs/odDSHcRGZKcGRKCuRKfTIAmGuy6sy5UG44f2O5q9vsvlBEAN5i/eRndOBBgb85AquOGCZc+byKtPI5JXzuIuYyPyQlMcxNNG0rlwnOFILxqEwcotF11wvIcEKgv1AQxNbzX7QxIBsN7Pc8T56BVepRCuQ1MBDjjkd+t1EFVZIjiBRIqWkoieBN1HeAg6gCWOWuZPgQHzRBCAwJRxuhZ+4gbbulRITNc5bboH7ufIqBgaueh/ZBSn816UunZKSqtBjcP5Yv/IH5dshBMwxR/n2TK8CEirNyC7lcWCyY/Ob4K/CWKbRSwrjfXg1gb3GMeGDmQg8Rxx+XQMDV2EewuQmKPMzbByKuVUcxNvZCtiRn0vIT+422t1KE+iW6d8ad8OEG1JdfMl3CnvRlnrKxtX+DOIYOBy9Z8xs9E+v+Wge9cviW2Y8mJWu9mcfDgthmu6mutIplfnjqZ4JygkO/zZQAH5Koninudf8PzPto65xYMAj1/kOoUgECiUyRdDgLyDlweXb6iOggZQHL8mNXXj+4XqYci9+LdAtuJUm/EhuuI3lVqawBRu8j1l6SeZJIZGi833Y0f+BAQaejfXuvf8KnsaeMSOWmamYai7vAZtLYQWbAwxKKOWRqHw7t4o7brkVN9FET2UZpjBGnp0b4qMVxtfI9aQPnBw/vZUdmlcxMGCwgynMF/Ex0wpXQsHIXHsfkV4XqA0st20efm5IbXemGxA7u8nisEyHN1eOOMDXQLaC52ssuBvsdxg1Ia1poM3b1EMac8MHVkAfqoVZ58YIM7kheMZQBAE1MdO7heGehPIGwFCvWIPpHsj06QtBMLUMPwH64PUyb8T+EKYfvbmLbMmgCenkPlhB+AQHEyfzDgSF+fXdVzQwcDuaQ3pykTsjB5qamlUGvoK8hgnPmV/xvbrloo5JiHLnWAWZLEau3Q3mBZPgMIxgGIRPyDjkWgYGjoJ/RNOiE21IgWcteVPCtxCwECoSl0MHzp1OB3cLDf7LvYeRX+jtO3rBeO24SYJyggPnwS0zd8H0AXtvuzMDA9uQ68BhdjM+Mq15JWUclTIpI5eUB8IWgVbHwzrdah3wUAItbKWuSqAVNE3H8l4f5IBMBxObseHUClh6KcE8kmsBZs7A58wtl2dln2+86oFfCDw2ayzNGySbydWUx4Ve1RFooRqDXDsaYIdU1tHa1OcF3GWGqJFGoA+vuJrZUP9d3pjIqfGCgjuz3NWBgU1YY3K5tfwE2onW4OaUR6pzmWY0VfrARzYoQxOJJpizmrgd+50OqSWD0Q5oGD+Cp2lg9udCSdVM89CZIAyJHnU7BgaOBdNEoLnn+jyHes7ohVbfVp9CZcU0TZryEJHz+SwimOUhtMa/UStMFrpLT77jKg7jm+xCFd6YPSM2AzmGUyE38CvJJTIHUww8G/wAluvcXNMETCO54GUzkCmdMfuoa9lDE72fhw1DFPFHE27I9SQWs5G1CbNM7oD7MChj4GfhH0gDY+eGJubWmgmI5TNfMMVIGT79IGr6tsNA9scmzAU3r0p9B6nnj+MvM6WZu8EeB6Zy+Pu76YKXb9/AwEokqphaczxGe3ydl9K/XC4abtQHXtMcs1t9O5UY/+l00urMuSxIg/gFfIpcZEsq4Y/d7sb/rnT3N/kW8Ec/+BuBYBjRCw0+D39FOkJuyIeBp4V/OPHENgc/YylcE2CGZC89jNWYn7sFx8zp8CyQnb/QDEmwavJyi6+Q5UNPSgy+GHgSZDeHojegikuCZJoD1rMXPQZZz9xxyVNZTdf3ZxM20wR3grf4Nnsfqfam5vqNGxdad9+zpoG/F/uufGDgYeCnlJ1feBZcEwWa0MnjnOlovunHuBuGgHw3dpDFTVWYhre8iEp18bmvj/AMYu4CTuivubml2dV91zgwsAw8WsuG1zTO7GQy2MFbgTENFRrYhfMkV38RaJ3+NV3tYVtswo/eXlnwgM8H8HWa7bMrxzZfX9mNhT4Pshg4HFcfrasDG1uBt5RMcT38kPHTzdeb5nO1G1exX02Y3nO/E8VmOXmRKN/BqY2cs/od/i4YGEq62snBDgMPQNr4dg9zfKKXY8/lVcNqFOfzORUnXUWEvnwYsgJOB76rekRKSkXqOqt92EYTCyO2tPwiprrUCbGw/XtabZ6wx5EDA0+L3vC2YC/sgBiradqOOSHaTX9nk/dxQHlVrrM7utG7GPjI0dpEaU6jF1JdK9K7y80tAwNPAj+eMS+wjjC2YIZStiDW1yJi4nrSL1Zu9mcNNtOEGd5T7RQxEYirqppparnxR7yvgXNKR6cs9zMdWqw6MLAM2PzVw9DgMdUYUSKHndtzeSm32QVeMDxiWGYfR8jtq1c1DThTeMLsMj1usmYTMlTDwLuAzbX5tPfsIrW8Dza33pE32s4GmuBfMj+caxHlL9ukQvFRD+bchyELPvkt1zkw8GyAMeOjsXApEX0pnoWxIG9oeiqctmmn/HMru7ozNpE7AkHI0WL5BLLwwsn7Wnw2z5p8ec1Lzevk38DA4ei5urnW2rLRiJoOe3bVRiuNaMeIe5PTYawRV+hJblkOeTrk8w+bH3hXsBFlp529ETWHTH+Y+Qm52YgOK6/y1s7UmOs1Qo1n0btmf7UyvI+BFweebX7Im9bujcL47EY7NM/jTUm2G9FamjDXxj+P3hv7Z71kch9eJqU6V9okkTWX2lN9AwOPQe74vL2Rz7PAgo2k4sJLPWcKoQp/vP8V/vWV2Fle1SMtvtrsfA2+GD5S6vqIHheajwMDrwg8wJi42XzgMwkEY02pzmuwNfGcjp4p5ceXV/FvN6/ZXIlvi6NVuZn8BgaeH4YR/MMvJNU9WTQNqmkyTYPdhLXL7yxwgZCdGwowsgLaoampch3RWOhGb28awc6B58DCY6wwe3l+B4sI73FIzR3G0Jg4xJnkMoMsYGcVptQSYNll8NxhroQvyTR2MN/AwGsBzznsiK0Dx0hnJO4ZHU6YazWxo4eHrawtrnZbWuEZZjV/bbyRT2uubdDHwIvCP7f+UWdqMBbEpuQNisfgY7u9IYTpOanZY7+dHYom/HmkU3/R69vh92Vg4EboE9ucvp2dUkgphRB00ToYAr96w0P6hma28+x104eVgczNdRPLe71qYCJMTi/xF7mda39kYOCNsfDwZ+c+GGXhkVaERbaa1f5i7dx3HJrXk2p/RIhWzHfNxQyyGHhjsMn4XWwC4At8ZCW+ySq3dnJDpqPXg2anWQL1Ks/5nNIqXF15NwcGXggL4x+2GPfBWBnD5D7YsnqKg39rpTXdFMLk3zBt7miisIrvMbMDf0wj3DDwa+DHSPAFNhrD8Y68t8Hex63YM6cj17LC6IIee/X2LhwvQzsM/ALwY7/SRnabVdPKrmLbehPmx7RhKkNYLymgjnzXjffRu4wdFzYw8OTwjzQ//MZMvO3wVA7+FtugOLM1Z17Z1SPXwjTdMj6Vv07T0R47DIIYeFf0nnBvFz3bYROTevw2bju27+jndZpYOK9nKXGMxX31uVJ8vccRmy9oYOA10SQLTweGFKRVYWTOIIvWtMbQ9i+Z2wyoiovN4hjjjOBsC6JDWrTq+zOCnQNPC9b/DPNgmye/lwpkM2kqdKkHb2NxaxihicPeSN7rh9liDhsWPjCwjOySILyLCUIclcgN1MC4KTbhG3xMj/Ca12a+6Lfs6OfAwPNj5cN/1Y78d/3XZa817ZxI3tzFFVaeI3z01V/k1t4PDLwxmvYiNAaz49+syDLnaZ55TU/2L3JndvkrkUVaMR+Tm/G6slebjh8YeDw2DYGGCPzXl23+ajhzK0EojpxIzh1KbuKGuJAsH28a639oMMXA82P3g90z9Z59HdflCldoYsGefSS2+RXe6+O33PZ1Wf7kAwPvBDO8m/HS7DI5QekMk8YYexmT5vE9rI1NLO9t/qr3lxa+tebMAwNviTUPuT/GDKsrPRRzzpX2devUr6Y0kBX6Ytj/wMBWXNUOPWO80eK2rV614Ahkgg+68iX5j/56Bo8M/CoY8/aGxlu8juCDexbkDU3utHqV+dUdIZOe6NhKCoNHBl4Lu5/wnkbY9Ls3RjcPmPrV3GUY8R4aYdDEwAvh8Iffj7iZIhTHduOYhOhVCri695BuDAy8GRYMp7kdTsSxA/PBdRPcp2XPoncBgzIGfjPW2EXPH8FhhxvRXcqrgCafeX/krn0YGHh1NH353pZ7YHOx9qaDVQLp3+Wvey9r5W8NDLwN/IC6fHCmteOuHr/8W8s4QE1cdZ/WE8T6X9x0/MDAM+Aej/pV49r0cz1smyEqW5yf+3kWQ24MvCgOf26bgb/1v76yP5vVBPsRAwMDL4TdZrtnkTsZsn9g4AWx22yHmhgY+C0YamJgYOAKflJNhBBuERc7vn7jLw4M/BR2POoH/tx91cQ+swwhxBhFJMZ4rFUPjhh4RdxjeFMTk71GcfAM0U1XiIPZQ1n+Op9/iIWB34lNg7+aCfsRm6xm08F3LNaGtTcJr8cFgyAGfjPW2AWOgWC/98h6ME34vja38HUOXhgYWIYR2l508AFyh7H2GJpo9t4fsLD3kG4MDLwZFgynuR0+SCDc3o39NAHBYzZe/ZYnvzVfbJ5q61cGBn4KWy3WK+41Zu/VhHH892HPl9dcrfcsDuQ2Gd7KwKvh2MfVG9RK+9pnOBtowlh+b6+qDBzG2VDzXUOWch9CGRh4foQWxEUlpLYpb27SYhBzBlnNKcDauomrV+gPNle70OmVZx4YeEusecibAzMaPUPbZLkLuMlj8f1b6Lrp/bD/gYGt8Ea0xuK2agePKzSxoBRU6gRSO82v8N4Yo/kWt42Uap58YOCd4I0ZbXF6AbYTFssljDF6O+0Z9QLWvs5ngZlCC6akyv/1p13ZY9+rMQ9t4Mmx/sFujqBNc+MtPCvCoPfFTbZ2ryrM0NEFfCU40rDd1l8ZGHhmNMf8NV/pmbq0Qpv7fmgltk398v0wFKAswH8Bk/LwDDJsfmCA0bQXfGQXHm1xjoa0RtOFXU3cqib873ny84zIe9f3dWDgtyE4Ad7TF+bjsQPwTeVVy40eBUqJZUqH55ZvxMDAO6E5rPaO4ZBfcIJ9gSNuZI09y9KYLnq28703oojZxMRv/QWbn/b9ubEQdWDgfugttmIebO+h9zIUoePUe5M5iiPkwGJt9MATnr9Cc2HmDGbLvgsbGHh+9J5wbxeeC9jieHsvVxrcuLse12li4by+x3xhXhr0OKJ5swZBDPwqNMnC80IoWsMcY8KWza/3fveqoW2e02HagdbPiQXmwnTjNE3BwYgrGZQx8GuwiRe87UzTNE1T0+X3WUX+RT7Jyq7eNJE8kIzhAEHvwjy49+a0I+Iw8HsQOs5CkzV6MOxgTPKW7m0zRW/evS1Sk4W0mAzXthywuOXyBgaeH01qQJxSWlYjfWlgjvHfMj+3BhvKq3p2bqw9EvQrUEcG/oJjf5ng0JIeAwMvB2NKzV3NWiljXPDlcZixrJ6i599aaU2b1cSmWxBICPEWPpizO9KipE09HBh4OTRN1xtFdBM3eGD21LDwc1vNamdC1NMBd9HTGNQEH7ygHWSRdAcG3gZhUSYzO4hLCwQHaQ3VTRrahLUzRM1lMOHlnL0T4f0LoVSIQUpJG3oqTZ1ow1xkbzKoHjymig48DxYMsjnEggia7oOHPzjWrorZHinAudw9j51VmP5ShWRSaIVeDPmJ41HDCFuvZGDgRWFG+94WY0FGUAit5xJbyziY39qEwxbgR8PDk2JY9FBAlnxO83ODPgZeEf65ZUv2g6sZL70RefOBETV/bh92TiT3lyGO8Pz1wP57iQ9ZfOHoMjsEItGBgZ/FwmOsMHtNjaK0HIfo8hre0HjolZYGMb++kkd2ZjoMb3liQ1uLL5uk0LwGozXMtS0zxcDA88OMr8aIgnPYm2Mt2xFqMRfIwv/opj7fOvXL/17oOxSx5V+EWo8072bzhwYGXhqeLMyuUCsCIx96xm8spXnmrV3dthamph6alxFLriHGmFLCRq2t0lyGiGDLNE3zPBtBhTMgx4H7klIyiYzQSnzEkfIY+FH07LA5oIoT5rCFpnZQwwkUsIQ19RSH/5VefxZw65wOf1OwJVK4QaS9nqdB7zy7Ozkw8MwI19bIbsIwwsrz3NLPPXM6+CNvj62wgoLrtXtTRZvfbf7WLRc8MPCzwIPtn3BPAd5Glu3IG1FspTy2GtH+Kkx/YaFTQ4XrgUDittFX0ilTNQ3TE9O9IUAGfgR4bg1Cy1Vfb0SwmqYReYuTRSPaMdAe4HRwO9ZRFmPeCx9xYf5bYeiIgfeCNxypjQjWDnPomYb/FtpNI9qHbcvS+Ov0bWmxF7qu5GemeMRFj8N8HBh4DzQ5wmw0lu+1AxuXN8nQ9zU22dSGOR38SyEETUbEkpWIJcWgCYuUklBe43Q6pZSmabpcLqGIJd3C39Kr1S24+Hme+d4h27Kczogj5THwQKy0uubg6jV4rFMY7KEH8jtiJ/fRVBa3yIoDJpIbBcF3oacpFrQTriTSxDj/Q7sveGDgR2CsgEd79jK8LfT8jkAynDcKFX0v9GRT549ZWZu72GOEpl4yf5t3wZ/8an8GBp4E/okNtaBYNpxmmz33puGY8y/3Zw02Ox34MVX1WkklJPJ1F64EDoX6FNBL6oZcLhetszqdTuogoBYrUr2W/ih8GfRh2afQO8JfGRi4B+KKzBrTgTFvhlqHHnY6nWBNp9PJZAbZ6eAtfGb8dLwtkLmfJvjiPSP6m6KCQuMRC/cIpZnmhNJRMVejD/jWiFMMHIuVVtc8zCsIYynNTGcoqpyNKLScd7/lcTQRXOzQ9Ayl1pAVpiI7lMlg+Irfq2oCJ/SX1+yGdIhg0MTAnXDV6poDm99izAEGYkyjxyA4Dx8sbgjf1HODnZkOhRoe94PbauR6VZqt8AmOr68vFVSXy8WrCfCOFF2XC7hLw/4HnhyeC/wAGVpqQn2NEML5fDb+RSj+CLZLS937buzo/zFvJA/O6QpufmtTUBgFZYSGv+Cmsth35QMDD8DCSM4PuXEfYDucBzW+hqEYL9LluJqjm2jCiIjo3CGptRBjquuserQa68rTUKupXn8GBn4WvfGMH2D4C8wRzZG1Gadgk+mZnmnvvpydIUyhlK+ImPnjnN3IOcOhiHW1FT6mlE6nk55Hw7wiog3ddblcEOzQjejDeo8D/5WR+xi4BXHjjCFjwGzSMUZ98gM5GpwNNGOq+iDYqDZovuWJ5nZBcdgUKXQFnfvfD7iK7Kag4LANGoZHQysCgi1HXcjAwCFYELz8hEdKahpBwQ+/iVx66SF1ReLt1MA4pryKd5kb0VRQUvwIXDn4le8X301zQqlJ2ndgYOCn4B9I/yR7ccHsYD7CTKS1jqy3uAUr2Gcg++smkKqMpc4q0js7kBnVi1TXAJ7F+XzW8yDToW6InkddFTSQJZnnWf0F/VFUdslIdgw8K8xgFihgh/QEexkeyHScTif9a/ayGAFT4Feao+lW7I9N4C6ggUlZ0vLHNA+qto3E51TmiQWqmDDSA0wETQWy8D1ZwxeDXAZ2YJOZ+YODE9ewDi8QONPBoruZEzSQQwlCcStNAIHii5HSE6iSYMqIpURiKmUUzBfQVzheaGIoKIPVhOGIsBjaHDQxsANrjM0PXR7gCMMXQoE8E5XsJQRDKw8ayCs/6tpvKtbmOd2B1AQIT7eAC9Sz0LaqifP5jC3MFzln9VBEBOeJ5b2B8zyLK+tCH0wPb7k7AwPrEVxIQhxTCMX4A5VFqPvAfgSSGuprxDoDguOnehkroyZMx3YTx60JUV8xDU0BeoMrwQwaKccBWQG+wDEgCMQ+zE8IFYPKxhTpwMDhwHNoNvoB32w0dhH7mQ58yzT4Y7NXu3HYywF79MmXKiU/HMj1YH2FBr4oFNr1cZp4aKnZwMCxMNTAlsxPtdR24WmCCQJ2YWjFaBY51C4OiE3wMM49Q4IDF49KkvP5rIfpRPLz+TzPs8Ym0ECmQ09ikilYHSsTxGmcZXERxwpXAytw1di8dpCaIyJF6yIFIHrZDeB8PqvH8fHxwZkO9jIM3RiJccgdOCDTYcIBoQQRkBON9ZxR3YI7pYzgVZZXYrpAHkRErKOY3AfZEpXY8ZWBX4LQ8iCWjzfGiTaeZNhw82n34jq6qRyGgEIdj/AduJ0sDpvT4Td6oQVabd4abvCCHEI0DJeEzy836KsDhdnAm+GWZ4O/y8+/ZwcpbnUIAWFLQxPm+B5liCMF04fdt+KwhGgk/a9tLYvSC1CXQZeo4pTH+XzWXR8fH//rUFnGCpkOblwuFyxso9VWsZ5gjiSI1KHNoRQG7gRWHLDG6OKLrAs4tbHgd3x8fMSS6TAJDvjvLCj8jx51jYfRBBBcZhS6gFMY+MjEuZzywLc4Rap+B+sa7cDghYHHw2hboyOa6mBBU/c28hYvJe4hjQ9Yb6KpavgG4TYh8etvGbsbTd3FjIMT8q/jd03HzPaBgaPQfMbMoCU1axiLiK1gxOl08s8/rIBVSahjor1n/vaH/7BMR6aVrGKZzaFpi1gcMBRoT/Vs8RACVs1Fgyd36MHQCJjlwWVdIQT/1nKpsx7S9z5whttvyMAbIF6bLe4HRUMHoc5x4rH3uQxkNLStuT91NP78+YOECE4S60IBqeOjzeHzRhzpdPieBcqMgj44AzKVt/hM9erbuax/B8ckl3UrMq1JgfP4usyVOdHmJQyH5ZdjvXWZIw1TSD9aH0I41ctJBAphQlCwrDAIFOP3v37g3ZCjaKJpiuaWZVpXBh8nmgxmirUnWi+T77JQzjWW6kz89f+2TTa/9fiB98MOM+PR2wzm3raNzYMdmgAXBEr2xdr7Xujz06kJFv+6JZYALFIeU1mQSieSI/ehbU55cO7j4+PjcrmIiBZlaQMpDz2/Rj3Nr3PNlWkvX0gY3sdvxVVfQ5zPHzpgq55cgsM7HchrcIKDPRHdIuWdm7AvVih3EhR3yXSg0Ut5qFjQmktWCqfTSWMTuksbJ1oRT6lkoteUYvKI0Fp7pj87BEIY3sfvww7TMgYJggh1giPWkUg0lCngWZzcvC+2jqaakBZPHXlTROQeNGGAG4dYJtdchjrYy7tO5e3E3AZfMH1kWiBHf9SvWBM2Th7dRy4Dr4uVBuZJQWpDZW+CyQJVD5EimtzGo94kBSMZvHy446051ukwphU6KQ9WB6i2VLdCiocSQrhcLlpDovM+Pj4+9CR6jLobiN/A4+Ble5EoCW6auaz2PoQyLAPvh/U2ZgiC/8a6rknq+YpMCqGsQ6WPtJKCacDRQGEVhyoQ+JROgoPJ66i7dBc14XupXVerzjTLI5a4I/wIkAjSolyFqd86lcXyYqnvnCjDijgFfnqTjuhd0WCK98O+cdg/2E01EevQI8bFya0rgV2mMa14K4fpw5F3h3B3p0NcYiJQKAFcMLkV7qa6HBMKTUS+v78neolxpHpt3Cz9LSMfZPUrBU3/1xw28HJYb1f+SL/FRAqM7wBB4V0P44N4loGCiHXUY9Ml3IKDaQIWxdwG7aABSyGTnspkcwh7WCM+aspDGzqqf3x8fH9/55w19xFj/Pz8xJmDK9aG95FpuS3u8xoKiGPW+RvhRl8DQxH7GpGC9NACHx8fLCKwDhXnNZDp8KVW8FBCXcQsfY9D7sAdd1QTRvY3tRmKKUJxSbSG6nQ6qWTg3IcC7UwrUEyu4ArRCsNcYCgZAmFgC/h5Nh9Dnd1gORApqQEv40TzviZaqw6JD/1rTsi2E1q437U/wulQ+IuEo2HsHOFJNenv72+9cRrL5OQoDg6u4ArOiJSwqPTnjA7WGGjC216owwHGjA1NBMpQeLeCScDlLiEAAB+nSURBVIH5wjgpfJ7gchyPuQ93qZsItYxnR0NEVB2EMhNcv6IN+BE55z9//uhdUF8jxogkiMlriIiuf4VfREkFzzTnA/YJCvzoLfdn4McRV9RQMULta8BEETvQjVM988LIByQv1MvQBmc01A2ZpgmOCUc6IUmkLu70guIe3HFfNRFI8AuN+YneyoOUx1SqITS0ycFLuBuZ1q0wDf1F8EIs02M4IarH3Oh0DOnx0thtRaH2MvhjrEOPodRfL2QxTjShY3LVmdEh1BEQ04Hbb8syHud0SAlSsEfAxIzMBRIcXIXZZAcgF+C0qBDnSgp0Q1pkEdbFMlceNvCEWC/UzWGeI2Cx4t6vAfhchvEvjF6YXAYk1FGPUKc5HoZ70QSbItyQTAtb6aWanIhK+qnM1JBi8CrDjIdiGnpP9eTf398670O3wPvw+RQ+j6xWCsP7eEWs9zXYCCOlHpkd0I51amMqGQ21ec10TDQl/M+fP8oO2uBd6oPEGHm5KggQQ0nRLUVzP+54UN0Exw6lLoLSq1Xi4Fgm9MVCeRUfE8o63TgJex+Zpnt472OfQDD/lSExnhC3WI6xvVAjdlIbXhQ0cxxeVvAXOXJpKMnwwmNkxYNowjdAjZkmmPMWcIHxNcwWIb5AgGMqCRGhMUTdEHYxetphJWvwf2hwxBNihxX1jmfjxEfjYgQqbQBraINDEmAHE6Q4lYkLhilCKyrBuPU2rcB96yZCXaeAS4pUCiUk+1NKmC0OsGPC/GIa+DkhrsFpsb4uqAEekFDplI9fbLrY4YY8D9a7GAA/eE2DBDswTUyUyESSAvVRms5A9dTHx4fZ4ouplC+MMDFSwnCW3NPjkAeHMBVMFmb1bRYF6kFImfqVc+ZGpEoK3aLKAllP/V/iJLlMXU9lARvuUq+eYuAXwgxIxjLZFzAjP4ceWSNM9Zxx3oJG7BRZKIRY72EKgvED5VXwMjgHgYHdF1z5RqQSLD3z9/e37tKZpuqYYFE8ToIAmPHBHdNdRlPI4I63hrc6zxHiqhViDfYj2LnAFE/DDlNdZGGEw1SnV4Pz1h9MFo9Yb0Lcog9wCkSE55iHsnYuDsg5//nzR2dw/P379+vrSxvf399fX1+m8f39rQcz939+fqIbCE/0vA/0mR0Q7vky4pj38QRYb0Kh9jKkLyJC7WuwCoglnWHKqLDsrfoXqKGapkldD+yC1lCfhWlCytyNyU0JlYe4G4oHqQlDFryd1QT+GZnWwhRaDk9rKCAQmrM88JWpLGSsTDSVaWaxlHg1vQ90Nez1QfgCB2U8Bt7g933djNs83oQ6uzHV07GYOKZWUoNXkYCaMGmOQCtfhn7M8mHsADwu05HryVfYFWgdCqEsJmgCy/ZrQ81+KjPKT2XpGs6J6hYmBbAPtqB7xvuQDkesZA3zzxs08RjcQg1+i7HGpq9hfAQTbkDdBDcQmzjRElWBQqHGi+FjTCc9r90VPxPCZL6I9HpxWPJUyh9C8REipU7BOHAxcs5wOi6XC7shuuzVPM9fX1/675Gy2tWy99Eji2H5r46m1XGDMdV5jVjSGeprgBrYxTDzwdkNOdVzOiaaXW4CHKF2KyIVUz3+jv1AsbZvBHo1Oe4IBvlIlRRqzM2Gfl2XHobfgfMw6Wh0U+7vfcgQF/fE7Qbjx2TDEcbXMK4B/prX8JhXfk6dGu2mNuGf5l+XmstuvPCteGimwxsJ1AEEAmx4ooxmLokP2L9vqPeRyrrbmIeqJdshBM2Vsmbx3gd3TG7zPvhgxeCIA7F7XPXfWuCIpq+Bj6ZoyjgdJiRhYhOc5jBMMdVTOXpX+kiyeLSaMDoClhlpUWwTR+AlqtTy4aQkWmg7luUzEdfQyR3qfYiI+iMxRo1o6D9ANYguaRHK6wWzW0erRxYyjP9FYIzKj88sH7jBFRBwOmDnbPwnmqbx9+9fNXidrwFfYyop0kj5EbADBy9jHb80TseDBcUPxCY8AjlgmWaLxbKMVawrKU5llse5vBYIq1ToFinv/kFOJITw+fkJSYLchx481etuonYDc0CMr7SbGoa4uAV8926XEgscMZWqnLCY18C0LoQe0I60cgTvMmeI9JZA7kP80WIqj5+kCfx7Mi0GgXs0UTGVlJIKKUvXCE33ABCbEApJaFokkPehuxAlMj8RSumXERHopzFvv2XhevnjoImtuJ0asCU4R8MEApBiMB5Bz9dgh8LEMjlIgWruiSo1+SeiS4LKE5DFjxVrm+hApHLJVJbkx3YlCH1LINt2osX7lZX/+9//4luxFGs2vQ/NfQhNx0j1mlehuEUsSZgyYOfBuSRrwH7Wjbf0vRG3z84AvADxIoJ1RKjjDmy97CN4X0N3wen4z3/+o1zw9+9fPcmfP38gMaA4+G+sw6VNspC9XHkjfkxNwLTMxUNNJFrSEoaq9xR2pTUU2ghl0W09FbshofY+9F3n/HUAEoM9Duw1rsd6HTHwszDaQWqOMGQxUf2CkQ/LvgY3WG4YQIMwPFsxQcgPsQPwMzTRG34DLTOVaZ0rbDmV14tKvXDmx8fH19cXRn7OjLJIEXJeAq2pqbkVNnt1VaAvuJM9jsA/cnDHj6NpVD2OYEM1eYeei8E0AbIw0zd0CwcpjK/BZME0EZ8ju8H44RBmoJlgGO2lBCZSeeFwKNkNtXC96fw/1lOp06H/bDREJJa1RtX7UF7QhlZeZZqrjvINDmEY78P4IOyAyHa+iGMmSAc9a1k43n80Y7KXD7HEwth02dcANZg4JdIZaMDXQEP9EY5cGL7AIxrrqiovKH4QT5HpYOh9MdyB+IWUKeF6cKrfRRpCOJflKhYaQu8K0gaLFD5AyPfB8RAX+aASLFy4+enfjFC7orvPIM7jCK2sp3EBOBmBBsSCKX/gsCVLDPYyWJVEB8MIz8ALBj+c6TBRQAWr+hgjFs5U++TsBgjYJ0HwijDOfUhxOk7lDQCqLM7nMyaPQkdwZzItV4H/ZSovDehxRNieBBkcIbsC+73jmSNiXc44lcg308SpFEea4CI7Cyid4tjENE2m+NpHIjjSwdoBZCF9HfGz3PHzTkegFa5CiRcYK0VRAx+j4uJyuVwuF01eQL9N0/Tv3z99FP79+wenQ0lHvwXvY5qmr68vZpzL5aIzQbiAQpMsExWDooemvII9iK32j4fjF7ohh7ADG5tugU8aKdnJAhMGPJVXbyGaECnBAR2BQinvdGiDcx8T5UeNO2NUDB5pNOQIVXUInsXpCC59EGjpGtC/Hox/80SvIJ1K8oKfAKGUhzqZunSFnhAJ0ZyzBilg8BrUFDLXqbwcINbTw6TO2vAWOcgNYbwHdzQv7RZjMAMviwggUiFjrLOPrCbY15goW4EVIiAiYpnuaXwNfMX4GlOdQwl1tNIQ3I9TA+MpaCJ0sgasCXWcj/WCX7Bhk8XI9QuKzc+h4AqqBO6DcgqCmuac3hPRj5GCF83LkV2yorn9jWnikK+zmRlATRh2YBs2wcWJaqvNlPATzQGdaIYoM0WkFImJSgS3ajbaB96oo/AUNCHkfQiZWaxjhyZmgTVp4GsY70MFpHof8DmnUpHJKQ8pK1Z8fn6GkhVTVsLLPvCLupKFWQ6HIS1O4Sttbl+J+MpFWfGGQilZ1CCGHcTRBEciTEoyFEeDAxB4dwYY4VTPBJ/o/Rp+Bgf+qoY1T2CsE5+GI55QUDwLTQDB6XZuqK1O06QRR62P0pCkHmO8j0C5D668ktbLvtTmNTaBr0vJy6KHyg6xTDwTYjEOrPjGsULAPENPqzLu9KyHlpfBjehKldg+jYg41TWRLAd4AbuTK6bqTdbASczvsoLw4Et4KjwdTShCKwnigwJ+0G56H2YAZ+sF9ahw+Pj4UJWhEgPHcIQVq/KaGEqqX1ZqfuV2N6T39d1neAAOeegXzsDnb9rbVNZqBzuEMrBPtHKEyWIwUyBtgeJLLtPu5TWavoYJXnJvD7xd98Bz0YRhh0CTzdn2VDIgToED4FBcLpe/f/8aP+Lz8zOWjJe6EkoN8D70YLgbKiu0cTqdNBuiu8wsUqRs0UmkVCE0QisPgivVxm5rN4/Xz/ojN3oWQNNg/JBr2CHWeY3g/M2J5n3iJeCRFqGKZQqGFxFKEPyaP+NrIISBvAaSKdCnhrO4z8vX/oN4LppQMCNIXXCVqeyKvY+pzn2oHECcUv8NJvdhJIOUUgj4F3qMEooyhY5LPgkCj2Mq9d14as1SN80Y5+FawDxkD9Aad32szclZL+BjrGdeYwgJnXQGTBdbTEzBJDhO9RzQZoIjUgmWiUFMdV4jugTHA27jLXg6mvAcISTgI9U1Iy7Ax2tDU5uhlE4ZkcKr2ug5lWukTEIVetoypTw4nKlf4SRIKG88RuSCv2tCsOEObog/z+2nWvlzBz7fC6daEBHMDsYUjeCPlOzEdmQ3Oe7QdDrYMWGng0+74Gt4jvB37wnJ4uloQmHYIbS8D8y5iLQOFeQGdIT6FHA6EIbgTIdumef5379/+nx8fX3B6dBd2ubgJV4XpAlUVSLgC1aS3g2ROrohtTPyeDnws2gahpEM0gpVRlc65QdwRA1PNIkLHoGREnBDUCjFUgKZDn3qeG44YhOQJ+AIZoeer+GVxVPhSWlC4ZVF6Hgf0JzwPk6nk4YbVDLM86zPBPQF/wrqrLRqW2htCx6mlAhCqfIWmicGVwVaY8ENCa0kyP2oYc3Dt/BzV79+1MPtB1Xzb4ItLbgYU71OHMcjTm5uBbaw77DsdJjURnTRSh+nfF1fA3hemvAcIYveh5BDEUpsIpbq7FxKp4SW20z0dkLd5V8aBj6S8tIwnnWuykIrNZgdWDJ4NyTXc8YMRyw4I829a27jMpY54h4P8RrqwTFeRDA7BALbJ4uI0IpETK4iG7EGTnZ6p4OdEaaeQMvVTf3iCO7zpnvyg3hemlAYdggt70OhJn0qrwUTETVgLbhKKX19feH/p9kQdUnYs1DH5Hw+f35+GqcjhKAhD42bKjVgi/4WuAAs5t2QSNNe2dHw1yW1J8I3BDhEdNyJC/yvLGz3fTCa3EOcixEokRHcS71DKaMyEUfeqDmLWMqrwBqghia5xLp8k0nBOB3+uhbuzPPg2WlCEZyyMINwpNyHFOUv5INoqkKN+XT6/6vmKGOsCyi0plvJBWdDJlUpRug/jWiF6hcORkBoKHiqGI4Relz40sy1y4uHKnpDaLNhhl8pvAA0PX+ODgRaaYYjEVAT8CxiHaTgaeOgABCBIaBYh0gNU5gL6d2KZ8YL0ITnCHF2Be9AbTvTqhD4Fo/toXYoYJYorxIijkBOh9RJEBRNgAVAAbGObrJ8CMXfYfdE6tyNrAtY+EftSUhkjQ3AePyW4BDLUmZmY6jVhKEJZgpfB7UwX2NqZTqiq9TUnwBHGFHjOaJ5yYfe+LvgBWhCYdghdLwPKWHF8/ls4osalZymSYkglulkyHRoguN0OpnyKjgdelpNgigfaUPPgAAE5n2gFiuXFx2ngliqzhHRzK1siMKIDq8seEvzsbsfdyw/5X7wNFt4Y3DCQWgACM7hN+O2YQfABxHU4GM9SRxOR6RIxHJxRKjDokbRMJHJa/oawMvQhCI4ZRGc92GOwb9HOQLHcxkVPItcr+IdY0REQ0SUOLAwN4KdQvNBtCHka/BfPB+5BC8hWDgtYmIWaPDXzRbpcMEDxEXvcfccwW0/wDa3BKqdi+TwqylKvTxcrDORTBwTzb+AHFjgC1+jzR5HpIBlk628jrh6u54Zr0QTniPEeR+Kqby+HAYZ6rIobDmVWZ5qn7zGf6TMhUYrEPUUioaEUqDF0gar2kjJgOIt6qH4GoFiE9g+lSpS44/w9Xq+MFjjm9wP+C3zo82BNNSI5ABGV3YNC5yo6JYtdiqv4YnkYuCvcTE4SIFyCc5xMDVE52jEX+BrAC+5hPyCJk+0uDYqr9XaMdRr4kMbKhCwUZfn1obqBRyGXd/f37yLv4Wf0L0KhDBwDLsYPnLBH/0FNr0S6QgQ3nt1yxr4h3thS28gNfYjTkeEOv5nBHyo178OdeTSLxLF+QhTN4lJGdhl9MVEGdBm6RREDdroavMCm3fs+fFKaoIRnLIwsiJQ9CFSkUWo9YU29K2iMOx5ntnpwGmVU6QIXfVHQATwHdj+UTbOXeLwBGQFuyqGKVKZZtajCXPtyU39Mrfrxtve+6iINPXLjKKGHSLFHTwpSLljEPNSUlcQEZ4vvDFz/jK2pm/E2ukANfDXsT2S04G+LYiI5Xv1KnhJmrjKEUJOASwzlMKHWOIX5/MZs8KNZ4GTpLLKXoxRHQedchpL7kOjFexioMgCvcLXc6kHU3UTKCTB5IKrS5Q6DRSSEBfXDOSAsKHy8f6p3UQcCxzRbHuD8ZYT+9XWevBEM8GnuuyaN4ILYMa92Z+xFFlz9NH4I3BV2PUItWyZ6tlcps2XvHAPXwUv6XQARmZ770OKx4ExH95Hzlldg0wLYcJZYHdDoW4InA7sgtOhbeQ+jBsCT0co3qkdxnJYuATjj/ClgWsW/A4vNJbb69F86P1Gv93QBIIL2GLkeqT661OZgg0pgTN4/c95DcMXk8uDsr5Q8ARwjmuAiUJdwRXrWEl0vgaT5o4b/iR4STXhEdwsCf0PsaY13keu3yGG787ljUF6vHoWumuaJjgdU1mPG+GPiYqvpH4tUCpZT2gNnNOzQ3ITTDOVgYS6KMvoC/+Xn8470QS3zd/QURas14TUBLMDC4reSD7V6Qw2bzAFexa8ZaLMhZEesY594ld8x8TRYpMjXh2vTROwIv4IZKqeEnJDtDICA3UoM8RhmZHSGZAAgbIVsayFg3zKVHKZkdKfoAkUWeAX4YPowwdRk12K1MgKaUknIyK8prj6sbnFP+WeF/wBPWrghhl+I5VOxTpO2dyCMT+40ikjIlgsGKeDPQuUbOIYMxMEPIUHIDjgApk1Fu7VC+G1nQ4D1uG5DxX5Uuqp4RHAPWGnIxcn5fPzE04EUiTshsDpYDcEX9cTYkumzMtC7oNDJ4YUoC9SXWrBNwHH8EZ/067e2B4j8K5IE/CkpgbWDmYv1MSpXtzJswOP6p4dsMXrAtYXU137AL4IZQKIzg/kE3JUQvuMrjbRvDmvjtdWEx6hLiXgfxtsZioFkSwBQpmUocecaAZ6KEJDRQEWsIiuUhNzOkIJl+rBCEmoYxKpZBO0BfpgmsDlmABnoteFBAptGh3Bj2lTYjDWqAneZfYyTfS4ABsNF0jRF8H5GoGmeMJWe+kMhBgMKZiMpnFMYsu5MLTVFBGe9ZZv2uvirWiCOUL/c2xI+I/qxqnM7w5UK81imIsmpVRMYVoX2CEUnwXEAdLJpdwzUR03GiCF6DKj6GSsZ5rmunZTSgLV0wQuXO9Grv0RgD9epYnQUtGB1ERwOsJ8Bcd4LjC7WO1PVLxk2AGkgPiiiTtESnMEkgwgAuYLnRPImgVaw/dQauLr3Z/3wFs5HYAZOdnjEFLpMNdQAo2KXCdBsAVugn4L6QxkPbhwK5W1/PmE2JVduReLCP4hEEeiYgp2Q8x2cS6Gby+zg4fniyaDNGmiyQ7Ynutlr41ZGu2A2IQREaG1MpXni2ZdZiQXJlA6A9tzWSEtutwtLkTemiPkzdSEQSgBTh76ePjFvzzR+ldSJ0ECVUzFsggNHg7dxc90ojmj+njxFqgJnhUW6xAm+yPshkBB4FuGJmRFvab5KNtpomkVPR1haAIf5Vo6g02XnY5eMqK5xcsKL0ZCHYlgHcEdM5CaK9+PFwzekyZC/22DQv/USCVYEPkmCcL5S+yKdTpDaAISQhJTmVeCiEakdxHpMbnEO5QOUEDB/ghoAsoitioymx95o17yQmP5fi40zNDqP/qNC9Y4uXpK3F6WAzz4w/VYkAxMQ8wphpLwf5Ra+3Bbah3RvFFvhvd0Ohi94dSbU24lQdjLgA3rFjgmxtdIpciqtyXXyQ7eYvwRbESH53p5m+ZV+Atf4IvmR0ZoyWk2GN7V44hYuxuwQ6E1LHmEZ6OFVfMWE3RsbuFGoGTn5Mou+OdCP53hLzw4bfWWeE81YYD/YnYRTbmWBOEzJCqgiPUiuvA+2A3hLfpQJnoJEBbm5i255XRASuRaXzQ5wvCg1PEIQ5rASpqQlnksE0STLEzDsECsfQ3Y+cmtatkjhVhHKE1eI9SORqBIhKxOZ7w9NTDenyZCqwQrlOyGf9AzLV2JZwWeBXgBogOssVBVlSioiS2xfqVgpiAF9AVPSGO9sx7S4QvFAjv07mSoxcUadvDw6cZcKs0MKQQXwjRFDQtbzLdM0Xes0eQv6cslc1veG+/vdBjwcOoNKdVJkKbaRxlVrn2ETPkRfB3sIOUlQ9gC4zcuxkyT36EvmCkUzY2Z8qm59q385csNNGHGVXyMraXoQi0T2A7x10civBsSXcBSSv6Sl4GI/SkYTDSh9n1wmLTSGdLhi1+C30gTaCcqUpQ6WsHmZ0zRVEMxXyASAXBqEx+ZAtitwJnBDrmOj/DGTKVWninyot8hLWVxFcZgvBWFVtYz1IGJWEcBvCWziDAjf3NJmObHSNWTTDF8Zt8381Fq5yLW825/FU28v9NhEFrvOhc3Syp2sglow0QDvd0nlGwI8iNTmSQOR2Mui/pGCkmwP5KL98HUIPVU19yq4zZ8IUQTM71tSPoRCnHemb97UhsPCtKMafGAHFsV2awdeAsXKUAphKI4cFdjSXCEes4osh7omAlA8C5PEwbN+/CrCELx69QEw1tLorUeskOiwIQRAokijpmCjs0sBs/+YGngq7ZxjDnY9IrZhI+RDi+YvSthLMf/jTQHPDjJYAZt9gKCS4iGVo22oQDmF56gxVRi2EHKAIC9nhfQeb5w+ZXsAPw6NWGA/32ukyD4yAfHUkCFj7muAQ/1ylSJ6qlRTxVKEgRCA3Ye69LsRCUSnia835EokoJjtKupNQesqSl6aqLJEUJS3Mt12Ke4Yiq2fGaHWAcOjNBgZom1t+JlBfOF4QJsgd7hbjNZbH2c3hW/miZCnQSR8pQwZfAuHoQNmySahK5mjwcRH6FH4G4YEQFSQF6W+UKKtZtiCq71kOIHseiQWj4YWZEo79vjiFjP3ZKWXeF6M70JJZQaBCF9EWntFmPnsP/QkRXNbxlxEZwG4R6GWt30rqX5qPxa/Gqnw8DrcGNd5iPMNdRuCFOAr4aCfGBr99FKFiNmlzkbk4J3SYx8wDmDK1S9ikD1JtFN+mSwHcbWWhIsEMTlGtjIY6sEiynDEAdTidSZF/AO91n6Qkl+PTsAv1pNNIEnI9duCPbCukwkElsyzeMMNP000hKY+kCDXPArRmh4++81pBXCZKKRWkqwiFiPuLioRHPQlnoBu+UG27l3TJpbmCb4PNLKuTC4/6Y9YDBo4v9hCELIGPKiG5JrxYFdbKWBCrpYIGR6KweUhRSb9/KkGYDIJZ1h2ME4FJnkEkuM9Xdmwa6iqziA2jdGK3V2g+2c/REmBS9GlllGWhwhQ0TsxXA6lsDDr9ni2cEM8maEN6GEpgpouhX+GG0YUmDfp9mx7AQFrsg0AGYEs9EbntkeW0EKrwIMLzBBGAoQsnwOdphjeGOPFHq8MNihh0ETS+Cb44dib3tmqDfBheWGFDnAYC4w5zRbZPWM8lyriebFKrzZwMakY3jciC4JYhRHk0EAFiOeR/iEXq0Y4jANfy296x1QDJpYheYgvGCHrBSkzj40acJ/i2mC4bXDQmyixxH+6noX3rOcqxwRahUgLX3hScF/q8cOoZNVYXnSa5irG+xwFYMmtsEbmx+lm8aJ1fEWzLvpR/SSF3677x5+wnc1O9brXXLTrtjA2D6bGw1xeKzxUKRFN5NbAh9AZ3xX/XUNLGPQxDZ46zKW2RvJzUeOVjYtX1w9pY96mJP3fnqhtwuXJuukhLS4o2m0wTkCxmUwX2mGGHgjH9/rgOnwmqsb8Bg0sRNNe2sO7IYsTHuh8EHqnIU5YaorLJvHbKKJ9VhJE+w16Bd9vMDnRwxBsHZoEoQ5odTcgS3N9sBKDJq4FQt8IU5l8Mdm/KLJJrwRk7g8KTR/unmM6Zj5ojiJ7hvi2AEbFxgEfOErI/2RuR93EMcFXkEstAe2YtRNHAPzFOZ6vqk5LJfaCjzZuV6WKrr5qdAOOO2CdugRh7TYwcAwRe8yTaNJCk3j12+ZhmEH71ngt5o01GwMHIihJo5EzwibIzws35v3wi4jLpYbpif+f51XVG2Hug7V7BI3aC+TRU8+4CTNRKbZ5X/LdEkGXxyKQRN3wcKgbcxYyJ6xxRdZ+7kYV7WDJ4jmLt9noGdp3sibu/iv+Zjd3BDs6tWD+/M0uzrY4R4YTsd94Z/a5sicix9uNsJ0Y//VXgsc0XM9mlhPE9jbHNsXdi2ICE8TUnNNszHwGAw18QgsKP81g7902MGfSpziMLtW9orRG8DFUYPUSsH7AmtoYlme8MG9jwOHY9DEz2DZbtcQB7Z7+eDdEDTC9vnjHsFFK5ouBnZdZQ1/cPN43x54DAZN/AwWogM9BvFfacqN5tmWf3cH1tjwAneYvc3v9uhg0MTjMWji57HskvQa4ojgKk0c/r++aupo9NyEq9rBfxx4PAZNPCOu2nbPp+gdtrBrE7zFLoQVe7s2fRx4BgyaeEasSUmst/yrOY5bsBzg9FuussCgiSfEoIlXwkoPYpMY2YHdcmAIhxfFoIk3wT3oYBNGxPGNMcqr3hnDRAcOwVATvx1rHoBBN78cgyYGBgauIF4/ZGBg4Hdj0MTAwMAVDJoYGBi4gkETAwMDVzBoYmBg4AoGTQwMDFzBoImBgYErGDQxMDBwBf8HXFbeGxqAJxwAAAAASUVORK5CYII="/>+ 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elifUcMZcZ3MwOnGIwUoJDmDOVSLAfYXaBQfjMOBg/Pa/Ia/iPuK7UT2f4e+Ltf82Wq/dcOoOhORX7GtKyE+NoZEouArGzajYYU0lB6rhGpMpu3oIbq5QhZU2KSLVVYBwmI/0u1vLU85hjlIz0YA6+yBuRxevRhLGHHuDDm4F9powmjBnpDOgIWL66GCwf4I8s5DWkJFOMiBC3vi5TABqh9epQf/nSCTf0Djjk5vuNoeOMNLd7KW7YQYlgLkUKoU4oILoZSsYEskIdgUtZwA65j7nkSj8+PvTfp8doulQ9iz9//uA/q+5JKkXfHx8fYCj9VqYaDUiYVPxEpjbjfeRabhz2X7k/XowmvJEYsHWlFkz00bgPHJ40UUyQwpoEB/9cbjkaniZSXTeFK+W/5uNVvngMej/HA2mgKSTeQnAka4q5LLQrHQHiRUQiD0VcDZWeU6WB/ms+Pj70PiMSofPxcs6cBFF2QA0LSxLt/+wmpESqOlO8tKB4JZrocYTUfMFSP1HoIZcAAcINrA5YXygpmBgESw8T1GQXwyiX7MIQ3D3pvDS4eaXSZ4ervHA/4ujZPPYadgg0zYQtH98FI8DgL/RaIFYTuQQscslcIDYB4wdf6HYd9qU4HazaNFSpp8U/xV9RpIzs9/c3B0ekJEQ4ToFr5EuWVyOLl8l0sOVkB/yz4fn7lKRJTCBnwaRwuVwQepgp05EW86C5Lp0CETBToGPocM+zMKSAS5Z1pPAk/9CeDfB2MILfEhyiS0AG98IOUAmcDoQnI+U+kL/QvEasMx0nAiqv1DGJlB/h1AlqOrUoK7i5KgZ8K16CLF5DTTRH1x5ZzK7mer4G5DWYLwD2R+bFmghsgf1f6hcLM0Ac4nKcvi1PY/83ItMwi2tkg8n18lA4IFEIk+0tUI1WqPNB0Bd6nu/vb3ZDUqnH1QOUF4SCRFLUgWY0tM5K6sXEcX7FXE8/kdZ/7RUFxQvQRI8juA2Tm+us50xxRI4gwP41oMUfoRS808GkwwHRmcoxmKpy7WuYPvOFSP10Sos4ejfnHvf8diyYhzkgUEiSCTHWa1sLzRMDR2SaHsYbc5m4gdpqzPJgz0JEUD2Vi8ST4pLg5uuskK+vL22EEPSJ0oPnEpyWekpert/38dLex7PThB9gGazkU5mdkWiKZ86Z66OQxdCP//79g9PhiYMdk9SawYEFqXzFFEclpH79rw9A5JZq6Nn/PXhhgYy8X3DLr/BpzXZjLdAI4jwRoRKsuawVoo1IK2gqL1wuF1RGaf4ilpljKNz6/v7+8+dPogljeuT5fL5cLh8fH5oZ+fv3b6KUx/l8/vz8RHWWlP8y52WkTDDl/oNfwuvkPp6aJszj62kCxin1lHAe5OEIGIHglQKcDoQhQBZznf4wZ4ZYMC7GTK8IY6dDao4wPHj4Pbz31w/nkdAq5WL5kKh6ItNMEHw90VQRNfJMEzf4H6Few9fXF8c+c85aeZXKyz5ERI85nU7IhoBB1B/hdKyOExOt3+nv5AsJiueliR5HCElEjMwzFS8Zd4OlBGsKqAaOTSIq6Z2OS11hCb8j19EQ3zEpDsUCQfiP5lbceCfv/fWtT7k5Z88fEXJJcl2wJLUKUzvUfwQLjVxLFT1Ms5sY/IWeKE2RwumQwg7cPWaBXGpzuCIzl4yslKkiqVVsiivCVTwtWTwpTfgxlsG+hhnYMfhzASVIQRkByQs4Hf/+/WM6gLhg4kg06cP8LkciZNHFQFvqp9xf/qPu9FPA8AJvNBzBrr4Jahg3JNXLVcDFmMv6d5hIpp6FxjL1rzodGsj4+/evPhXqdOhzpbJCGUcDovBitBFofupE7xPgC3kh7+MZaaKnIxbIAgSRXF7DJy8QgDB6wRzM1JBcOiPTzM5cFITQuGR4gT/6azz8Bt7pzGt+7vCn3DwMXno03RANQAgtOIJEBkKYXFLJMctcnI6cs65YIyKfn5+aLv3+/jYd0IOFVtnRmIhQKXd2JRX+jvmrexI8HU30OELIAlnSgyNguopEKQmmAHAEfI1meZWPRPC6+xyP8GoiXxMRPTM+yrwfTBPSkQM3nsqfBxbOut1HQ6XY5Eyr+ErxTLXUkiu1pHgWzCDe6cC/L5bJ6egGPA4wyPl8nstCe3oYZqC9ovfxXDTRJAiAZTwLBzZsUxaFjaAGZDoulwvKq8zBcz3RK1GyM7lpGolmgv8UOyyc/PFIlNa9JVHS5AvcTLZ/mJl3Q0AKgdbjxrr7//79Ux8BSZBES2ZqCEOne2gDQwJ8jfP5rA0cLGX0Up9FSnhCygyUVC+6YbwPvsznIYvnogmpB4QmUzQDEz2PY6ZkJ8jCiwhWHBykNGdOrZqIXLs/pud8LXe6Uc8M08kDn3u+t1fdEIzhudQyIGoA+9SUB8YDOB0or1I5yZJBSlgBTod+XalnLtNGhdSNFPXRfCQ4eHHUjToET0cTitySFfD/m74G+whs+Vw9yYEJznTAT+m9eiOTo8EiItdhCMMUck8R8RI0IUf4I7klK7AruOosExFMJal5Ke8EAX2EUkwlpc5Kis/IoQqT6eAzSFmhV3ex96FfV5JiSmLvw1zXc3KEPA9NNA2MvQxjqGj3fA11LnS7CgrQgeY1Es3XwLcSJUcSJTKYHeBZXDovB5d7ZjFSa+2ZVwE6H90EyjVo8oW51XBzQg0ewy+XS6CXGCNnieDF6XT69+8fvIac8zzP6nQgRKXWrk7Hf//734+PD63R1HQJF1zpeZSkwGs814NvSKhTv09CGU9EE80GSwnDFEwWTV+D1QRCm01fA3mN5tt3mB3mep0bT23mKm6/IW+J5tXdYhLMIDwmexKJZZVNHJzrJIg2OAaZ6D3GKK8yHYZLoh+N98G5j1RKvxLN+0i0ULC/ih/HU9BEc8j1OmKm4oi0mNfg2gfwhWoKUIZfWoJPkuk9GpliIlIvWivlf7x8Ob2NW2/L26B3aSutoikreBfsX2huCP59Kh9mKqPG/1StfaKXgHDKQ/UCbNs3OFop/dwHd5i756nhScjih2kCt0ZIODA1ZDeti7UDZmfAa/gu0Da7G6AJVFXxylSQHvrTPA0015EIiIh0beE52W7qzZP8ErCd7OYL/C/gemD05sN6SZDz+azjRy4rdKvxI9NxuVyE4hGc8vj4+Pj3759+lNr7UBGq4gJRD4Qt+BIQLuGYa/5p7+Mp1ASDmUKKvOe4wNzJaHhfg2d/csDSUENyL90BF+TFdIZc44hNV33Q/XsHLIiFTSfhzKhQnUVySZBY3ug1l1X/LzQTRL+uW0IImg7TpSWEzJvjIJAM8D6UKUIIc8mAzDTrXOpFd39cPhj8JE2wbRgpIUXMe78Dtj1TvsNEGVhooGHWlWG9cGktGJHKqpa5A3FksXCBm+7GwFaDyR1x7jmi+a1LmZSBwQDF3VNZUNdEH0REVUYuS2zlUmeVSwxLiveBWq+5VHxJHaTg7Aw/Tk+SBPl5p0MoqSEUlYC7eKnrpmeKSpqiKe9rsA8CoYEEB6+pj4ClIQimKs8Rt7ODvHjy4q7QO7w+LWKsKzsHBB+NpMdcj+zW4/76+tK9OitM/YhcAlLqdIgIUh7qfZjcBx6bRGsaSqm84vcbh1LTISXqkUnR/BR+jCaMsRmOQIODiJle4QfiQL1D09cwZRHa8K5KcllP/r96dsAl/NTdG9gEWCCPyfj3JSphwL8bByNDAb0AWaFxCiGPg9u6V30KVStzWXJd6B0lQt5HplhmdiUhP8gUP0MTzXG4Rw0mEmEijqwvlC8u5d0ZfDyzRqKMRtPXaMqHqxwxWON5kFs+C5OFsToOGaJoCnsv5TWiQskL431IXWqJgk4UU2E9bqUPI3AUiF/05MNPkcUP0ARzRKrnSuU6ZMi+RqrXlVHVwPKBnQ72Nfy0cb809qWeppHrgKXhCM9x+whi+BorkW4oymK7Yo3AZIFBW9Mf0P8oZOCla9j7+Pv3L2xbExwafWCnQ3MfUiaYghdSSn/+/LmUwtBY1vJN9UJ+6JuZWvpgsvj5TAdbHZulCSXyx+96AUsTmDRzN1Id4+RIBLeNhGlKCenooPVXeswt+6243U74/9g8QyqJDwzsqWRApAQ4Ee9UZapr4XGv4HQEt7K2lGQHpzxSmT0Y6VUj8kyFmD+c6fC8YAgCRZBznc4wIQlOZ/AurrZKdaKE2Wd2s7maUqJp55uMfzDFLTB3b3cSJDu33xycShlFoBfz4GDjfUR6kyACEHA6eLrHXKonsEVKnkW3QEqklMz0MH8Vj8RDacKYXFM7ZLcglZmaxYFJrqTiGirOa/hiqkxTxTJFQFIdufQdNtfyyFs3cCNyHa3wsiJTQgS+RiwvE8KMUn5TsaY84H2k8lpDXaRX17CJMeK1Y/oU6a4QAha50AJNKUVfOBVHKFI9VezBKuPRNOEbZhj3vsZM2cq5VSJhGr0aKj7tTOv0zzRNoykfejpi0yUPHIt9ysKfxHCEURbKAjBd3Y5X9cBrQFQS0c1LeVOZbzD08cMJEy1aA/cHF5jJE9l9yfvwOJroKXYzks91kaVxQOBZGBHBmDs1VKAG42sIFdUYyM06YtDE/cD3dr3N+HG4yRFSRg4ENfEtLtnMpfJK6sBEpGX4Q5kDioa6M5gVllqvGkDAgsnCX/5jyOLHMh1GR0hZQX+uqxgudZ21mZ2BqRw6Nxxb5rIKbqpf+dnzNbgPMnyNdwcbWO54H5He2aXehz5Csbz4C7mPROUPf//+FXob0EyvEcHCnIGSLFhZTwUFghfYkmndPe7wg4MUD6IJY3hmxDZBAfAFQhJzvf698SzQWJnXyC1fQw6apjF45EewT1nw1733ketiJ/Y+YNJzyX3kMkMs0wpXHOb8+vrKpW4ilBeIcGMuM1aZF5Kb7uG7+gA8giY8R/AuE4AwroEx8mYS1McmLrRIxNzJawj5GlLzl9ymIwZTPB7mnq+xH29mufY+0PbeB1wDHGAM3oQkDClwGgWv/AmlakMoGyJuMS60H0kWd6cJtjc0eEiHoJjrUKVZkAp+hDYuZUq42cWrV7G+YD2SF32NpohYaflpVEw9AfQ/uKYWKzvvg1kg970PnD+2Xho2lzcJzWX9G7gM6o/oZKL//Oc/eua/f/9Chmhh+Ewzx/CUBnprmTz27R6Pjk340ZtilI0JmiwQVqoJDkMYv+Oqr9HkiIHfBkMf2XkfeliiyisOT0qZAGIa+i2kRXwjlZehzmUi6VxP95Afqtd+aKbDINXvv/EOAiwcWmCmAOSlzObi2MRcI1Oo8qqv4TliUMZvQHYy3hzQ8z5QZ2VyH1ICECklxCZ0i8YvjBuiXACOQEPqYVVa2vzlMx3mkgxBGAWBkISZqaGzwvWjNr6+vrDl8/PzQjPH2VtB9nSNr4Et3PndFzvwDEilBmH9V3ighlliJO95H3ykeg2hrKydymsijVeL581IFWyBKjFr1fAVGX1xV5XxMyFM3Di2XtYO/JEN/kKLX/eOgXBgUuC/np73WfjghSeH+QdttSI8IT3vA6EoUBJUAE8V5UdaeUQfVJ1IFkLQ9SbmeVadAtfYZDpSq4biruwAPIgmpBYUyWVAPVlwxMEUTfmGD0CkFrhLCwSx0v4HTTw/+H+0Mv3RPNJsZ46QWrloI1ExhR7DDewyxzCnBHpFAP5y2BK09cI04RWEkVtqt4YLLvX6VOpNeB/E70pUiwXnBZRhuCn18xrrCWJwxMthvRvCQzR/C9uh/1NJkebyrjB93nTX+XzW9bhDCJhIrnOLROTz81Ofos/Pz4+PD7gqaKA/SJcGWrY/UcEVd/gerHFfNeHJQlrFVJkKqMEXJnMxt/Id7GvMrj4C4s1Qldxm54MgXhc9sbDyuybGibN5yZDKOpdcIoGiCW3gHT/6kCOoqRvZDRGqzmA35GG5j0dP/QIvmOEd7gYHHVhomACEP2ymJMiCcFggi/VS4k73Z+ABWGlU2XkZPg/CTxH7GqG8vEcfS+xCbIJDEswXAH8LDaGl8R78EB5PE15BmOiD0Cq4M1VGzPWCEZrFuNTLUl3q6V68BCYrjkTpT/Y7bhQUt2iQgefBeu8AWqDrAAAgAElEQVRDwfKBvzWX6inM4JD6IUnldR6ZJpJHequoGgWO4eUq5pLp0FNp43K56LR0eBwmqHmnlMfdE6J811hEiPM+TGwSQQo4I6meuDG72oqFSITUjs8w+IGt8IIi1JMvAhVQYD7oTK/niGX5XDT0K9/f36FUUuiZUXCVy3sDvawQkjPoz52u/XFOB5NCpqUuU50BzVQ6ZfwO42igIIKBkwsVRFzVEYMyBprwI3Ou86O6MZWXns+UyAylOls/XsosD0QoODChYQiUYM2tgivoEZyTF866Kw6mCWOKPLCnUigBOlB7vrip4iij4rVwU0paQ5Vobji+CD0C6sl13cTtHJHGfI03gj4G++Z9SCGL5PKg/FH/YrqH7srFs9AlsC5lkf7mSfg8vDwn5qTzMUJRErP9dtxFTfQG8LmUWmaaAGrExaUscm0Clr5WIlFSY64LJaQkXA0peI5YeTkH3pyB54EXC1u/hcc70AKWeAghKPC4ipvcgQNCCJpPRZhT55WlkvJgNTGXBSzEkdctN6SHB5VXpboIks17rt/cydsZvY2J8qm59jJ8N3b7GoMp3hKsFK4e2fM++FTwCPCcI6ww1+VVSit4qnXLXFKn2AVSAMuAicAaB96QHg6jCSMcQHu5vPNCqKQqU8ySSyH4FRtzXTqFl3Ro5UmPMsSlXbljpsMrr2jgjYH/8tXcR3beR66XlkLoQQ1ezwy/BhSAFWt0oRptYIsejNni+rTnnHWCOQou9LBUirs4oqk4NuVxr4SoV/szzbMAL4AvcolTMMWCVtjRSC6pwaeVcu/4p/ddxe23YuCFsF5ZLHwLDyS0A0Z+SAZMCZ1LSRVcDDUBRDehR8wKV7wLyVShh/aVEqIK9gVMTLHnZTSrMJk7cJg5obQWv9VubCWOQRO/EGuG3+wCE6GeZ5GoJiJT5B6ZDi2sxJMMvvC5j7n2xNmIQj0D7d4pjyOdDnEeB0b4TC6WiKAsin0NZDG4cSlv3PDFVEaAGHaApvC65uqFDI74tUgrKq+YHQxHMIOk+nVh8ES4mEofNnUotKFxTW0EKp0CEfBCeKGeOeZTHs/odDSHcRGZKcGRKCuRKfTIAmGuy6sy5UG44f2O5q9vsvlBEAN5i/eRndOBBgb85AquOGCZc+byKtPI5JXzuIuYyPyQlMcxNNG0rlwnOFILxqEwcotF11wvIcEKgv1AQxNbzX7QxIBsN7Pc8T56BVepRCuQ1MBDjjkd+t1EFVZIjiBRIqWkoieBN1HeAg6gCWOWuZPgQHzRBCAwJRxuhZ+4gbbulRITNc5bboH7ufIqBgaueh/ZBSn816UunZKSqtBjcP5Yv/IH5dshBMwxR/n2TK8CEirNyC7lcWCyY/Ob4K/CWKbRSwrjfXg1gb3GMeGDmQg8Rxx+XQMDV2EewuQmKPMzbByKuVUcxNvZCtiRn0vIT+422t1KE+iW6d8ad8OEG1JdfMl3CnvRlnrKxtX+DOIYOBy9Z8xs9E+v+Wge9cviW2Y8mJWu9mcfDgthmu6mutIplfnjqZ4JygkO/zZQAH5Koninudf8PzPto65xYMAj1/kOoUgECiUyRdDgLyDlweXb6iOggZQHL8mNXXj+4XqYci9+LdAtuJUm/EhuuI3lVqawBRu8j1l6SeZJIZGi833Y0f+BAQaejfXuvf8KnsaeMSOWmamYai7vAZtLYQWbAwxKKOWRqHw7t4o7brkVN9FET2UZpjBGnp0b4qMVxtfI9aQPnBw/vZUdmlcxMGCwgynMF/Ex0wpXQsHIXHsfkV4XqA0st20efm5IbXemGxA7u8nisEyHN1eOOMDXQLaC52ssuBvsdxg1Ia1poM3b1EMac8MHVkAfqoVZ58YIM7kheMZQBAE1MdO7heGehPIGwFCvWIPpHsj06QtBMLUMPwH64PUyb8T+EKYfvbmLbMmgCenkPlhB+AQHEyfzDgSF+fXdVzQwcDuaQ3pykTsjB5qamlUGvoK8hgnPmV/xvbrloo5JiHLnWAWZLEau3Q3mBZPgMIxgGIRPyDjkWgYGjoJ/RNOiE21IgWcteVPCtxCwECoSl0MHzp1OB3cLDf7LvYeRX+jtO3rBeO24SYJyggPnwS0zd8H0AXtvuzMDA9uQ68BhdjM+Mq15JWUclTIpI5eUB8IWgVbHwzrdah3wUAItbKWuSqAVNE3H8l4f5IBMBxObseHUClh6KcE8kmsBZs7A58wtl2dln2+86oFfCDw2ayzNGySbydWUx4Ve1RFooRqDXDsaYIdU1tHa1OcF3GWGqJFGoA+vuJrZUP9d3pjIqfGCgjuz3NWBgU1YY3K5tfwE2onW4OaUR6pzmWY0VfrARzYoQxOJJpizmrgd+50OqSWD0Q5oGD+Cp2lg9udCSdVM89CZIAyJHnU7BgaOBdNEoLnn+jyHes7ohVbfVp9CZcU0TZryEJHz+SwimOUhtMa/UStMFrpLT77jKg7jm+xCFd6YPSM2AzmGUyE38CvJJTIHUww8G/wAluvcXNMETCO54GUzkCmdMfuoa9lDE72fhw1DFPFHE27I9SQWs5G1CbNM7oD7MChj4GfhH0gDY+eGJubWmgmI5TNfMMVIGT79IGr6tsNA9scmzAU3r0p9B6nnj+MvM6WZu8EeB6Zy+Pu76YKXb9/AwEokqphaczxGe3ydl9K/XC4abtQHXtMcs1t9O5UY/+l00urMuSxIg/gFfIpcZEsq4Y/d7sb/rnT3N/kW8Ec/+BuBYBjRCw0+D39FOkJuyIeBp4V/OPHENgc/YylcE2CGZC89jNWYn7sFx8zp8CyQnb/QDEmwavJyi6+Q5UNPSgy+GHgSZDeHojegikuCZJoD1rMXPQZZz9xxyVNZTdf3ZxM20wR3grf4Nnsfqfam5vqNGxdad9+zpoG/F/uufGDgYeCnlJ1feBZcEwWa0MnjnOlovunHuBuGgHw3dpDFTVWYhre8iEp18bmvj/AMYu4CTuivubml2dV91zgwsAw8WsuG1zTO7GQy2MFbgTENFRrYhfMkV38RaJ3+NV3tYVtswo/eXlnwgM8H8HWa7bMrxzZfX9mNhT4Pshg4HFcfrasDG1uBt5RMcT38kPHTzdeb5nO1G1exX02Y3nO/E8VmOXmRKN/BqY2cs/od/i4YGEq62snBDgMPQNr4dg9zfKKXY8/lVcNqFOfzORUnXUWEvnwYsgJOB76rekRKSkXqOqt92EYTCyO2tPwiprrUCbGw/XtabZ6wx5EDA0+L3vC2YC/sgBiradqOOSHaTX9nk/dxQHlVrrM7utG7GPjI0dpEaU6jF1JdK9K7y80tAwNPAj+eMS+wjjC2YIZStiDW1yJi4nrSL1Zu9mcNNtOEGd5T7RQxEYirqppparnxR7yvgXNKR6cs9zMdWqw6MLAM2PzVw9DgMdUYUSKHndtzeSm32QVeMDxiWGYfR8jtq1c1DThTeMLsMj1usmYTMlTDwLuAzbX5tPfsIrW8Dza33pE32s4GmuBfMj+caxHlL9ukQvFRD+bchyELPvkt1zkw8GyAMeOjsXApEX0pnoWxIG9oeiqctmmn/HMru7ozNpE7AkHI0WL5BLLwwsn7Wnw2z5p8ec1Lzevk38DA4ei5urnW2rLRiJoOe3bVRiuNaMeIe5PTYawRV+hJblkOeTrk8w+bH3hXsBFlp529ETWHTH+Y+Qm52YgOK6/y1s7UmOs1Qo1n0btmf7UyvI+BFweebX7Im9bujcL47EY7NM/jTUm2G9FamjDXxj+P3hv7Z71kch9eJqU6V9okkTWX2lN9AwOPQe74vL2Rz7PAgo2k4sJLPWcKoQp/vP8V/vWV2Fle1SMtvtrsfA2+GD5S6vqIHheajwMDrwg8wJi42XzgMwkEY02pzmuwNfGcjp4p5ceXV/FvN6/ZXIlvi6NVuZn8BgaeH4YR/MMvJNU9WTQNqmkyTYPdhLXL7yxwgZCdGwowsgLaoampch3RWOhGb28awc6B58DCY6wwe3l+B4sI73FIzR3G0Jg4xJnkMoMsYGcVptQSYNll8NxhroQvyTR2MN/AwGsBzznsiK0Dx0hnJO4ZHU6YazWxo4eHrawtrnZbWuEZZjV/bbyRT2uubdDHwIvCP7f+UWdqMBbEpuQNisfgY7u9IYTpOanZY7+dHYom/HmkU3/R69vh92Vg4EboE9ucvp2dUkgphRB00ToYAr96w0P6hma28+x104eVgczNdRPLe71qYCJMTi/xF7mda39kYOCNsfDwZ+c+GGXhkVaERbaa1f5i7dx3HJrXk2p/RIhWzHfNxQyyGHhjsMn4XWwC4At8ZCW+ySq3dnJDpqPXg2anWQL1Ks/5nNIqXF15NwcGXggL4x+2GPfBWBnD5D7YsnqKg39rpTXdFMLk3zBt7miisIrvMbMDf0wj3DDwa+DHSPAFNhrD8Y68t8Hex63YM6cj17LC6IIee/X2LhwvQzsM/ALwY7/SRnabVdPKrmLbehPmx7RhKkNYLymgjnzXjffRu4wdFzYw8OTwjzQ//MZMvO3wVA7+FtugOLM1Z17Z1SPXwjTdMj6Vv07T0R47DIIYeFf0nnBvFz3bYROTevw2bju27+jndZpYOK9nKXGMxX31uVJ8vccRmy9oYOA10SQLTweGFKRVYWTOIIvWtMbQ9i+Z2wyoiovN4hjjjOBsC6JDWrTq+zOCnQNPC9b/DPNgmye/lwpkM2kqdKkHb2NxaxihicPeSN7rh9liDhsWPjCwjOySILyLCUIclcgN1MC4KTbhG3xMj/Ca12a+6Lfs6OfAwPNj5cN/1Y78d/3XZa817ZxI3tzFFVaeI3z01V/k1t4PDLwxmvYiNAaz49+syDLnaZ55TU/2L3JndvkrkUVaMR+Tm/G6slebjh8YeDw2DYGGCPzXl23+ajhzK0EojpxIzh1KbuKGuJAsH28a639oMMXA82P3g90z9Z59HdflCldoYsGefSS2+RXe6+O33PZ1Wf7kAwPvBDO8m/HS7DI5QekMk8YYexmT5vE9rI1NLO9t/qr3lxa+tebMAwNviTUPuT/GDKsrPRRzzpX2devUr6Y0kBX6Ytj/wMBWXNUOPWO80eK2rV614Ahkgg+68iX5j/56Bo8M/CoY8/aGxlu8juCDexbkDU3utHqV+dUdIZOe6NhKCoNHBl4Lu5/wnkbY9Ls3RjcPmPrV3GUY8R4aYdDEwAvh8Iffj7iZIhTHduOYhOhVCri695BuDAy8GRYMp7kdTsSxA/PBdRPcp2XPoncBgzIGfjPW2EXPH8FhhxvRXcqrgCafeX/krn0YGHh1NH353pZ7YHOx9qaDVQLp3+Wvey9r5W8NDLwN/IC6fHCmteOuHr/8W8s4QE1cdZ/WE8T6X9x0/MDAM+Aej/pV49r0cz1smyEqW5yf+3kWQ24MvCgOf26bgb/1v76yP5vVBPsRAwMDL4TdZrtnkTsZsn9g4AWx22yHmhgY+C0YamJgYOAKflJNhBBuERc7vn7jLw4M/BR2POoH/tx91cQ+swwhxBhFJMZ4rFUPjhh4RdxjeFMTk71GcfAM0U1XiIPZQ1n+Op9/iIWB34lNg7+aCfsRm6xm08F3LNaGtTcJr8cFgyAGfjPW2AWOgWC/98h6ME34vja38HUOXhgYWIYR2l508AFyh7H2GJpo9t4fsLD3kG4MDLwZFgynuR0+SCDc3o39NAHBYzZe/ZYnvzVfbJ5q61cGBn4KWy3WK+41Zu/VhHH892HPl9dcrfcsDuQ2Gd7KwKvh2MfVG9RK+9pnOBtowlh+b6+qDBzG2VDzXUOWch9CGRh4foQWxEUlpLYpb27SYhBzBlnNKcDauomrV+gPNle70OmVZx4YeEusecibAzMaPUPbZLkLuMlj8f1b6Lrp/bD/gYGt8Ea0xuK2agePKzSxoBRU6gRSO82v8N4Yo/kWt42Uap58YOCd4I0ZbXF6AbYTFssljDF6O+0Z9QLWvs5ngZlCC6akyv/1p13ZY9+rMQ9t4Mmx/sFujqBNc+MtPCvCoPfFTbZ2ryrM0NEFfCU40rDd1l8ZGHhmNMf8NV/pmbq0Qpv7fmgltk398v0wFKAswH8Bk/LwDDJsfmCA0bQXfGQXHm1xjoa0RtOFXU3cqib873ny84zIe9f3dWDgtyE4Ad7TF+bjsQPwTeVVy40eBUqJZUqH55ZvxMDAO6E5rPaO4ZBfcIJ9gSNuZI09y9KYLnq28703oojZxMRv/QWbn/b9ubEQdWDgfugttmIebO+h9zIUoePUe5M5iiPkwGJt9MATnr9Cc2HmDGbLvgsbGHh+9J5wbxeeC9jieHsvVxrcuLse12li4by+x3xhXhr0OKJ5swZBDPwqNMnC80IoWsMcY8KWza/3fveqoW2e02HagdbPiQXmwnTjNE3BwYgrGZQx8GuwiRe87UzTNE1T0+X3WUX+RT7Jyq7eNJE8kIzhAEHvwjy49+a0I+Iw8HsQOs5CkzV6MOxgTPKW7m0zRW/evS1Sk4W0mAzXthywuOXyBgaeH01qQJxSWlYjfWlgjvHfMj+3BhvKq3p2bqw9EvQrUEcG/oJjf5ng0JIeAwMvB2NKzV3NWiljXPDlcZixrJ6i599aaU2b1cSmWxBICPEWPpizO9KipE09HBh4OTRN1xtFdBM3eGD21LDwc1vNamdC1NMBd9HTGNQEH7ygHWSRdAcG3gZhUSYzO4hLCwQHaQ3VTRrahLUzRM1lMOHlnL0T4f0LoVSIQUpJG3oqTZ1ow1xkbzKoHjymig48DxYMsjnEggia7oOHPzjWrorZHinAudw9j51VmP5ShWRSaIVeDPmJ41HDCFuvZGDgRWFG+94WY0FGUAit5xJbyziY39qEwxbgR8PDk2JY9FBAlnxO83ODPgZeEf65ZUv2g6sZL70RefOBETV/bh92TiT3lyGO8Pz1wP57iQ9ZfOHoMjsEItGBgZ/FwmOsMHtNjaK0HIfo8hre0HjolZYGMb++kkd2ZjoMb3liQ1uLL5uk0LwGozXMtS0zxcDA88OMr8aIgnPYm2Mt2xFqMRfIwv/opj7fOvXL/17oOxSx5V+EWo8072bzhwYGXhqeLMyuUCsCIx96xm8spXnmrV3dthamph6alxFLriHGmFLCRq2t0lyGiGDLNE3zPBtBhTMgx4H7klIyiYzQSnzEkfIY+FH07LA5oIoT5rCFpnZQwwkUsIQ19RSH/5VefxZw65wOf1OwJVK4QaS9nqdB7zy7Ozkw8MwI19bIbsIwwsrz3NLPPXM6+CNvj62wgoLrtXtTRZvfbf7WLRc8MPCzwIPtn3BPAd5Glu3IG1FspTy2GtH+Kkx/YaFTQ4XrgUDittFX0ilTNQ3TE9O9IUAGfgR4bg1Cy1Vfb0SwmqYReYuTRSPaMdAe4HRwO9ZRFmPeCx9xYf5bYeiIgfeCNxypjQjWDnPomYb/FtpNI9qHbcvS+Ov0bWmxF7qu5GemeMRFj8N8HBh4DzQ5wmw0lu+1AxuXN8nQ9zU22dSGOR38SyEETUbEkpWIJcWgCYuUklBe43Q6pZSmabpcLqGIJd3C39Kr1S24+Hme+d4h27Kczogj5THwQKy0uubg6jV4rFMY7KEH8jtiJ/fRVBa3yIoDJpIbBcF3oacpFrQTriTSxDj/Q7sveGDgR2CsgEd79jK8LfT8jkAynDcKFX0v9GRT549ZWZu72GOEpl4yf5t3wZ/8an8GBp4E/okNtaBYNpxmmz33puGY8y/3Zw02Ox34MVX1WkklJPJ1F64EDoX6FNBL6oZcLhetszqdTuogoBYrUr2W/ih8GfRh2afQO8JfGRi4B+KKzBrTgTFvhlqHHnY6nWBNp9PJZAbZ6eAtfGb8dLwtkLmfJvjiPSP6m6KCQuMRC/cIpZnmhNJRMVejD/jWiFMMHIuVVtc8zCsIYynNTGcoqpyNKLScd7/lcTQRXOzQ9Ayl1pAVpiI7lMlg+Irfq2oCJ/SX1+yGdIhg0MTAnXDV6poDm99izAEGYkyjxyA4Dx8sbgjf1HODnZkOhRoe94PbauR6VZqt8AmOr68vFVSXy8WrCfCOFF2XC7hLw/4HnhyeC/wAGVpqQn2NEML5fDb+RSj+CLZLS937buzo/zFvJA/O6QpufmtTUBgFZYSGv+Cmsth35QMDD8DCSM4PuXEfYDucBzW+hqEYL9LluJqjm2jCiIjo3CGptRBjquuserQa68rTUKupXn8GBn4WvfGMH2D4C8wRzZG1Gadgk+mZnmnvvpydIUyhlK+ImPnjnN3IOcOhiHW1FT6mlE6nk55Hw7wiog3ddblcEOzQjejDeo8D/5WR+xi4BXHjjCFjwGzSMUZ98gM5GpwNNGOq+iDYqDZovuWJ5nZBcdgUKXQFnfvfD7iK7Kag4LANGoZHQysCgi1HXcjAwCFYELz8hEdKahpBwQ+/iVx66SF1ReLt1MA4pryKd5kb0VRQUvwIXDn4le8X301zQqlJ2ndgYOCn4B9I/yR7ccHsYD7CTKS1jqy3uAUr2Gcg++smkKqMpc4q0js7kBnVi1TXAJ7F+XzW8yDToW6InkddFTSQJZnnWf0F/VFUdslIdgw8K8xgFihgh/QEexkeyHScTif9a/ayGAFT4Feao+lW7I9N4C6ggUlZ0vLHNA+qto3E51TmiQWqmDDSA0wETQWy8D1ZwxeDXAZ2YJOZ+YODE9ewDi8QONPBoruZEzSQQwlCcStNAIHii5HSE6iSYMqIpURiKmUUzBfQVzheaGIoKIPVhOGIsBjaHDQxsANrjM0PXR7gCMMXQoE8E5XsJQRDKw8ayCs/6tpvKtbmOd2B1AQIT7eAC9Sz0LaqifP5jC3MFzln9VBEBOeJ5b2B8zyLK+tCH0wPb7k7AwPrEVxIQhxTCMX4A5VFqPvAfgSSGuprxDoDguOnehkroyZMx3YTx60JUV8xDU0BeoMrwQwaKccBWQG+wDEgCMQ+zE8IFYPKxhTpwMDhwHNoNvoB32w0dhH7mQ58yzT4Y7NXu3HYywF79MmXKiU/HMj1YH2FBr4oFNr1cZp4aKnZwMCxMNTAlsxPtdR24WmCCQJ2YWjFaBY51C4OiE3wMM49Q4IDF49KkvP5rIfpRPLz+TzPs8Ym0ECmQ09ikilYHSsTxGmcZXERxwpXAytw1di8dpCaIyJF6yIFIHrZDeB8PqvH8fHxwZkO9jIM3RiJccgdOCDTYcIBoQQRkBON9ZxR3YI7pYzgVZZXYrpAHkRErKOY3AfZEpXY8ZWBX4LQ8iCWjzfGiTaeZNhw82n34jq6qRyGgEIdj/AduJ0sDpvT4Td6oQVabd4abvCCHEI0DJeEzy836KsDhdnAm+GWZ4O/y8+/ZwcpbnUIAWFLQxPm+B5liCMF04fdt+KwhGgk/a9tLYvSC1CXQZeo4pTH+XzWXR8fH//rUFnGCpkOblwuFyxso9VWsZ5gjiSI1KHNoRQG7gRWHLDG6OKLrAs4tbHgd3x8fMSS6TAJDvjvLCj8jx51jYfRBBBcZhS6gFMY+MjEuZzywLc4Rap+B+sa7cDghYHHw2hboyOa6mBBU/c28hYvJe4hjQ9Yb6KpavgG4TYh8etvGbsbTd3FjIMT8q/jd03HzPaBgaPQfMbMoCU1axiLiK1gxOl08s8/rIBVSahjor1n/vaH/7BMR6aVrGKZzaFpi1gcMBRoT/Vs8RACVs1Fgyd36MHQCJjlwWVdIQT/1nKpsx7S9z5whttvyMAbIF6bLe4HRUMHoc5x4rH3uQxkNLStuT91NP78+YOECE4S60IBqeOjzeHzRhzpdPieBcqMgj44AzKVt/hM9erbuax/B8ckl3UrMq1JgfP4usyVOdHmJQyH5ZdjvXWZIw1TSD9aH0I41ctJBAphQlCwrDAIFOP3v37g3ZCjaKJpiuaWZVpXBh8nmgxmirUnWi+T77JQzjWW6kz89f+2TTa/9fiB98MOM+PR2wzm3raNzYMdmgAXBEr2xdr7Xujz06kJFv+6JZYALFIeU1mQSieSI/ehbU55cO7j4+PjcrmIiBZlaQMpDz2/Rj3Nr3PNlWkvX0gY3sdvxVVfQ5zPHzpgq55cgsM7HchrcIKDPRHdIuWdm7AvVih3EhR3yXSg0Ut5qFjQmktWCqfTSWMTuksbJ1oRT6lkoteUYvKI0Fp7pj87BEIY3sfvww7TMgYJggh1giPWkUg0lCngWZzcvC+2jqaakBZPHXlTROQeNGGAG4dYJtdchjrYy7tO5e3E3AZfMH1kWiBHf9SvWBM2Th7dRy4Dr4uVBuZJQWpDZW+CyQJVD5EimtzGo94kBSMZvHy446051ukwphU6KQ9WB6i2VLdCiocSQrhcLlpDovM+Pj4+9CR6jLobiN/A4+Ble5EoCW6auaz2PoQyLAPvh/U2ZgiC/8a6rknq+YpMCqGsQ6WPtJKCacDRQGEVhyoQ+JROgoPJ66i7dBc14XupXVerzjTLI5a4I/wIkAjSolyFqd86lcXyYqnvnCjDijgFfnqTjuhd0WCK98O+cdg/2E01EevQI8bFya0rgV2mMa14K4fpw5F3h3B3p0NcYiJQKAFcMLkV7qa6HBMKTUS+v78neolxpHpt3Cz9LSMfZPUrBU3/1xw28HJYb1f+SL/FRAqM7wBB4V0P44N4loGCiHXUY9Ml3IKDaQIWxdwG7aABSyGTnspkcwh7WCM+aspDGzqqf3x8fH9/55w19xFj/Pz8xJmDK9aG95FpuS3u8xoKiGPW+RvhRl8DQxH7GpGC9NACHx8fLCKwDhXnNZDp8KVW8FBCXcQsfY9D7sAdd1QTRvY3tRmKKUJxSbSG6nQ6qWTg3IcC7UwrUEyu4ArRCsNcYCgZAmFgC/h5Nh9Dnd1gORApqQEv40TzviZaqw6JD/1rTsi2E1q437U/wulQ+IuEo2HsHOFJNenv72+9cRrL5OQoDg6u4ArOiJSwqPTnjA7WGGjC216owwHGjA1NBMpQeLeCScDlLiEAAB+nSURBVIH5wjgpfJ7gchyPuQ93qZsItYxnR0NEVB2EMhNcv6IN+BE55z9//uhdUF8jxogkiMlriIiuf4VfREkFzzTnA/YJCvzoLfdn4McRV9RQMULta8BEETvQjVM988LIByQv1MvQBmc01A2ZpgmOCUc6IUmkLu70guIe3HFfNRFI8AuN+YneyoOUx1SqITS0ycFLuBuZ1q0wDf1F8EIs02M4IarH3Oh0DOnx0thtRaH2MvhjrEOPodRfL2QxTjShY3LVmdEh1BEQ04Hbb8syHud0SAlSsEfAxIzMBRIcXIXZZAcgF+C0qBDnSgp0Q1pkEdbFMlceNvCEWC/UzWGeI2Cx4t6vAfhchvEvjF6YXAYk1FGPUKc5HoZ70QSbItyQTAtb6aWanIhK+qnM1JBi8CrDjIdiGnpP9eTf398670O3wPvw+RQ+j6xWCsP7eEWs9zXYCCOlHpkd0I51amMqGQ21ec10TDQl/M+fP8oO2uBd6oPEGHm5KggQQ0nRLUVzP+54UN0Exw6lLoLSq1Xi4Fgm9MVCeRUfE8o63TgJex+Zpnt472OfQDD/lSExnhC3WI6xvVAjdlIbXhQ0cxxeVvAXOXJpKMnwwmNkxYNowjdAjZkmmPMWcIHxNcwWIb5AgGMqCRGhMUTdEHYxetphJWvwf2hwxBNihxX1jmfjxEfjYgQqbQBraINDEmAHE6Q4lYkLhilCKyrBuPU2rcB96yZCXaeAS4pUCiUk+1NKmC0OsGPC/GIa+DkhrsFpsb4uqAEekFDplI9fbLrY4YY8D9a7GAA/eE2DBDswTUyUyESSAvVRms5A9dTHx4fZ4ouplC+MMDFSwnCW3NPjkAeHMBVMFmb1bRYF6kFImfqVc+ZGpEoK3aLKAllP/V/iJLlMXU9lARvuUq+eYuAXwgxIxjLZFzAjP4ceWSNM9Zxx3oJG7BRZKIRY72EKgvED5VXwMjgHgYHdF1z5RqQSLD3z9/e37tKZpuqYYFE8ToIAmPHBHdNdRlPI4I63hrc6zxHiqhViDfYj2LnAFE/DDlNdZGGEw1SnV4Pz1h9MFo9Yb0Lcog9wCkSE55iHsnYuDsg5//nzR2dw/P379+vrSxvf399fX1+m8f39rQcz939+fqIbCE/0vA/0mR0Q7vky4pj38QRYb0Kh9jKkLyJC7WuwCoglnWHKqLDsrfoXqKGapkldD+yC1lCfhWlCytyNyU0JlYe4G4oHqQlDFryd1QT+GZnWwhRaDk9rKCAQmrM88JWpLGSsTDSVaWaxlHg1vQ90Nez1QfgCB2U8Bt7g933djNs83oQ6uzHV07GYOKZWUoNXkYCaMGmOQCtfhn7M8mHsADwu05HryVfYFWgdCqEsJmgCy/ZrQ81+KjPKT2XpGs6J6hYmBbAPtqB7xvuQDkesZA3zzxs08RjcQg1+i7HGpq9hfAQTbkDdBDcQmzjRElWBQqHGi+FjTCc9r90VPxPCZL6I9HpxWPJUyh9C8REipU7BOHAxcs5wOi6XC7shuuzVPM9fX1/675Gy2tWy99Eji2H5r46m1XGDMdV5jVjSGeprgBrYxTDzwdkNOdVzOiaaXW4CHKF2KyIVUz3+jv1AsbZvBHo1Oe4IBvlIlRRqzM2Gfl2XHobfgfMw6Wh0U+7vfcgQF/fE7Qbjx2TDEcbXMK4B/prX8JhXfk6dGu2mNuGf5l+XmstuvPCteGimwxsJ1AEEAmx4ooxmLokP2L9vqPeRyrrbmIeqJdshBM2Vsmbx3gd3TG7zPvhgxeCIA7F7XPXfWuCIpq+Bj6ZoyjgdJiRhYhOc5jBMMdVTOXpX+kiyeLSaMDoClhlpUWwTR+AlqtTy4aQkWmg7luUzEdfQyR3qfYiI+iMxRo1o6D9ANYguaRHK6wWzW0erRxYyjP9FYIzKj88sH7jBFRBwOmDnbPwnmqbx9+9fNXidrwFfYyop0kj5EbADBy9jHb80TseDBcUPxCY8AjlgmWaLxbKMVawrKU5llse5vBYIq1ToFinv/kFOJITw+fkJSYLchx481etuonYDc0CMr7SbGoa4uAV8926XEgscMZWqnLCY18C0LoQe0I60cgTvMmeI9JZA7kP80WIqj5+kCfx7Mi0GgXs0UTGVlJIKKUvXCE33ABCbEApJaFokkPehuxAlMj8RSumXERHopzFvv2XhevnjoImtuJ0asCU4R8MEApBiMB5Bz9dgh8LEMjlIgWruiSo1+SeiS4LKE5DFjxVrm+hApHLJVJbkx3YlCH1LINt2osX7lZX/+9//4luxFGs2vQ/NfQhNx0j1mlehuEUsSZgyYOfBuSRrwH7Wjbf0vRG3z84AvADxIoJ1RKjjDmy97CN4X0N3wen4z3/+o1zw9+9fPcmfP38gMaA4+G+sw6VNspC9XHkjfkxNwLTMxUNNJFrSEoaq9xR2pTUU2ghl0W09FbshofY+9F3n/HUAEoM9Duw1rsd6HTHwszDaQWqOMGQxUf2CkQ/LvgY3WG4YQIMwPFsxQcgPsQPwMzTRG34DLTOVaZ0rbDmV14tKvXDmx8fH19cXRn7OjLJIEXJeAq2pqbkVNnt1VaAvuJM9jsA/cnDHj6NpVD2OYEM1eYeei8E0AbIw0zd0CwcpjK/BZME0EZ8ju8H44RBmoJlgGO2lBCZSeeFwKNkNtXC96fw/1lOp06H/bDREJJa1RtX7UF7QhlZeZZqrjvINDmEY78P4IOyAyHa+iGMmSAc9a1k43n80Y7KXD7HEwth02dcANZg4JdIZaMDXQEP9EY5cGL7AIxrrqiovKH4QT5HpYOh9MdyB+IWUKeF6cKrfRRpCOJflKhYaQu8K0gaLFD5AyPfB8RAX+aASLFy4+enfjFC7orvPIM7jCK2sp3EBOBmBBsSCKX/gsCVLDPYyWJVEB8MIz8ALBj+c6TBRQAWr+hgjFs5U++TsBgjYJ0HwijDOfUhxOk7lDQCqLM7nMyaPQkdwZzItV4H/ZSovDehxRNieBBkcIb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@@ -0,0 +1,1492 @@+<html><head><meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"><title>ForSyDe tutorial</title><link rel="stylesheet" href="fptools.css" type="text/css"><meta name="generator" content="DocBook XSL Stylesheets V1.73.2"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="article" lang="en"><div class="titlepage"><div><div><h2 class="title"><a name="ForSyDe-tutorial"></a>ForSyDe tutorial</h2></div><div><div class="author"><h3 class="author"><span class="firstname">Alfonso</span> <span class="surname">Acosta</span></h3><div class="affiliation"><span class="org">+	  <span class="orgname">Royal Institute of Technology (KTH)</span>+	  <span class="orgdiv">System, Architecture and Methodology (SAM) group</span>+	  <div class="address"><p><span class="city">Stockholm</span>, <span class="country">Sweden</span></p></div>+	</span></div><code class="email">&lt;<a class="email" href="mailto:alfonsoa@kth.se">alfonsoa@kth.se</a>&gt;</code></div></div><div><p class="pubdate">2008-09-20</p></div><div><div class="revhistory"><table border="1" width="100%" summary="Revision history"><tr><th align="left" valign="top" colspan="2"><b>Revision History</b></th></tr><tr><td align="left">Revision 0.2</td><td align="left">2008-09-20</td></tr><tr><td align="left" colspan="2">Complete draft.</td></tr><tr><td align="left">Revision 0.1</td><td align="left">2008-08-15</td></tr><tr><td align="left" colspan="2">First version.</td></tr></table></div></div></div><hr></div><div class="toc"><p><b>Table of Contents</b></p><dl><dt><span class="section"><a href="#intro">1. Disclaimer and Prerequisites</a></span></dt><dt><span class="section"><a href="#install">2. Installing ForSyDe</a></span></dt><dt><span class="section"><a href="#introForSYDe">3. Introduction to ForSyDe</a></span></dt><dd><dl><dt><span class="section"><a href="#id1251676">3.1. Signals</a></span></dt><dt><span class="section"><a href="#id1251727">3.2. Processes</a></span></dt><dt><span class="section"><a href="#id1251867">3.3. Process Constructors</a></span></dt><dt><span class="section"><a href="#id1251871">3.4. Models of Computation and Domain Interfaces</a></span></dt></dl></dd><dt><span class="section"><a href="#DEvsSE">4. Deep-embedded vs Shallow-embedded signals</a></span></dt><dt><span class="section"><a href="#DE">5. Using deep-embedded Signals</a></span></dt><dd><dl><dt><span class="section"><a href="#combinational">5.1. Combinational Systems</a></span></dt><dt><span class="section"><a href="#sequential">5.2. Sequential Systems</a></span></dt><dt><span class="section"><a href="#components">5.3. Using components</a></span></dt><dt><span class="section"><a href="#VHDL">5.4. VHDL Backend</a></span></dt><dt><span class="section"><a href="#GraphML">5.5. GraphML Backend</a></span></dt></dl></dd><dt><span class="section"><a href="#SE">6. Shallow-embedded signals</a></span></dt><dt><span class="appendix"><a href="#FSVec">A. <code class="literal">FSVec</code>s: Vectors parameterized in size</a></span></dt><dd><dl><dt><span class="section"><a href="#id1255404">1. Goal</a></span></dt><dt><span class="section"><a href="#id1255478">2. How?</a></span></dt><dt><span class="section"><a href="#id1255502">3. Type-level decimal numerals</a></span></dt><dt><span class="section"><a href="#id1255520">4. Fixed Sized Vectors themselves</a></span></dt><dt><span class="section"><a href="#id1255822">5. <code class="code">FSVec</code> issues</a></span></dt></dl></dd></dl></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="intro"></a>1. Disclaimer and Prerequisites</h2></div></div></div><p>+      This document has been devised as a practical hands-on+      introduction to the use of ForSyDe's implementation. Thus, it is+      intentionally informal and non-exhaustive. If you are interested+      in ForSyDe's theoretical foundations please refer to the <a class="ulink" href="http://www.ict.kth.se/org/ict/ecs/sam/projects/forsyde/www/index.html#documentation" target="_top">Documentation+      section</a> in our <a class="ulink" href="http://www.ict.kth.se/org/ict/ecs/sam/projects/forsyde/www/" target="_top">website</a>.+    </p><p>+      In order to take full advantage of this tutorial, it is+      essential to have a good background in the <a class="ulink" href="http://www.haskell.org" target="_top">Haskell</a> programming+      language. Familiarity with some Haskell extensions (<a class="ulink" href="http://www.haskell.org/th" target="_top">Template Haskell</a>,+      <a class="ulink" href="http://haskell.org/ghc/docs/latest/html/users_guide/type-class-extensions.html#functional-dependencies" target="_top">Multiparameter+      Type Classes with Functional Dependencies</a>, <a class="ulink" href="http://haskell.org/ghc/docs/latest/html/users_guide/type-class-extensions.html#instance-decls" target="_top">Undecidable+      and Overlapping Instances</a>) might help but is not vital.+    </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="install"></a>2. Installing ForSyDe</h2></div></div></div><p>+      ForSyDe is implemented as a Haskell-embedded Domain Specific+      Language (DSL). As intimidating as the previous phrase might+      sound, from a practical point of view it only means that, to all+      effects, ForSyDe is simply a Haskell library.+    </p><p>+      As it was already stated in <a class="xref" href="#intro" title="1. Disclaimer and Prerequisites">Section 1, &#8220;Disclaimer and Prerequisites&#8221;</a>, ForSyDe+      relies on many Haskell extensions, some of which are exclusive+      to GHC. For that reason, a recent version of GHC is required to+      build ForSyDe<sup>[<a name="id1251533" href="#ftn.id1251533" class="footnote">1</a>]</sup>.+    </p><p>+      ForSyDe's library is available on Haskell's <a class="ulink" href="http://hackage.haskell.org" target="_top">HackageDB</a>, a+      popular repository of Haskell <a class="ulink" href="http://www.haskell.org/cabal" target="_top">Cabal</a> packages.+      If ForSyDe is the first Cabal package you install or your memory+      needs to be refreshed in this matter, you should read <a class="ulink" href="http://haskell.org/haskellwiki/Cabal/How_to_install_a_Cabal_package" target="_top">"How+      to install a Cabal package"</a>.+    </p><p>+      At the time being, ForSyDe depends on the <a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/type-level" target="_top"><code class="code">type-level</code></a>+      and <a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/parameterized-data" target="_top"><code class="code">parameterized-data</code></a>+      packages to offer numerically-parametrized vectors, and on some+      other packages normally distributed with GHC (e.g. <a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/mtl" target="_top"><code class="code">mtl</code></a>+      ..)+    </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="introForSYDe"></a>3. Introduction to ForSyDe</h2></div></div></div><p>+      This section is a short introduction to some basic concepts+      surrounding ForSyDe which are vital to understand how to use its+      implementation.  If you cannot wait to get your hands dirty and begin+      with the implementation examples, go directly to <a class="xref" href="#DEvsSE" title="4. Deep-embedded vs Shallow-embedded signals">Section 4, &#8220;Deep-embedded vs Shallow-embedded signals&#8221;</a>.+    </p><p>+      ForSyDe, which stands for Formal System Design, is a+      methodology aimed at raising the abstraction level in which+      systems (e.g. System on Chip Systems, Hardware or Software) are designed.+    </p><p>+      ForSyDe systems are modelled as networks of <span class="emphasis"><em>processes</em></span>+      interconnected by <span class="emphasis"><em>signals</em></span>. In+      addition, the designer is allowed to use processes belonging to+      different <span class="emphasis"><em>Models of Computation</em></span>.+    </p><p>+      In order to understand how systems are modelled, it is important to+      get familiar with the concepts outlined above.+    </p><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1251676"></a>3.1. Signals</h3></div></div></div><p>+	Signals can be intuitively defined as+	streams of information which flow through the different+	processes forming a system.+      </p><p>+	For example, this is a signal containing the first 10 positive numbers+      </p><div class="example"><a name="id1251694"></a><p class="title"><b>Example 1. Signal containing the first 10 positive numbers</b></p><div class="example-contents">&lt;1,2,3,4,5,6,7,8,9,10&gt;</div></div><br class="example-break"><p>+	More formally, a signal is a sequence of events where each+	event has a tag and a value. In ForSyDe, the tag of an event+	is implicitly given by the event's position on the list. For+	instance, the sample signal above is formed by integer values+	which are identical to the signal implicit tags.+      </p><p>+	It is important to note that signals are homogeneous (i.e. a+	signal cannot carry values belonging to different types)+      </p><div class="note" style="margin-left: 0.5in; margin-right: 0.5in;"><h3 class="title">Note</h3>The interpretation of tags, as we will see, is determined+      by the <span class="emphasis"><em>Model of Computation</em></span> used, e.g. an+      identical tag of two events in different signals does not+      necessarily imply that these events happen at the same+      time. </div></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1251727"></a>3.2. Processes</h3></div></div></div><p>+	Processes are pure functions on signals, i.e. for a given set of input signals a process always gets the same+	set of output signals.+      </p><div class="figure"><a name="processfun"></a><p class="title"><b>Figure 1. Processes viewed as functions</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="360"><tr><td align="center" valign="middle"><object data="figures/processfun.svg" type="image/svg+xml" width="360" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	They can also be viewed as a black box which performs computations over its input signals and+	forward the results to adjacent processes through output signals.+      </p><div class="figure"><a name="processbox"></a><p class="title"><b>Figure 2. Processes viewed as boxes</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="225"><tr><td align="center" valign="middle"><object data="figures/processbox.svg" type="image/svg+xml" width="225" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	Note that this still allows processes to have internal+	state. A process does not necessarily react identically the+	same event applied at different times. But it will produce the same, possibly infinite,  output signals+	when confronted with identical, possibly infinite, input signals.+      </p><p>+	One of the simplest examples one can think of, is a process which merely adds one to every value in its+	only input signal: <span class="emphasis"><em>plus1</em></span>.	+      </p><div class="example"><a name="id1251834"></a><p class="title"><b>Example 2. The <span class="emphasis"><em>plus1</em></span> process</b></p><div class="example-contents">+	plus1(&lt;v<sub>1</sub>, v<sub>2</sub>, v<sub>3</sub>, ...&gt;) =+	&lt;v<sub>1</sub>+1, v<sub>2</sub>+1, v<sub>3</sub>+1, ...&gt;)+      </div></div><br class="example-break"></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1251867"></a>3.3. Process Constructors</h3></div></div></div><p>+	In ForSyDe, all processes, even <span class="emphasis"><em>plus1</em></span>, must be created from +	<span class="emphasis"><em>process constructors</em></span>. A process constructor takes zero or more+	functions and/or values which determine the initial state and behaviour of the process to be created.  +      </p><div class="figure"><a name="processcons"></a><p class="title"><b>Figure 3. A process constructor</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="270"><tr><td align="center" valign="middle"><object data="figures/processcons.svg" type="image/svg+xml" width="270" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	The ForSyDe methodology offers a set of well-defined+	process constructors. For example, certain process constructors are aimed at creating+	synchronous systems. Synchronous systems are governed by a global clock and all processes consume and produce+	exactly one signal event in each clock-cycle.+      </p><p>+	For instance, <span class="emphasis"><em>mapSY</em></span>, (where the suffix+	<span class="emphasis"><em>SY</em></span> stands for+	<span class="emphasis"><em>SY</em></span>ncrhonous) is a+	combinational<sup>[<a name="id1251950" href="#ftn.id1251950" class="footnote">2</a>]</sup> process constructor.+	<span class="emphasis"><em>mapSY</em></span> takes a function+	<span class="emphasis"><em>f</em></span> and creates a process with one input+	and output signal, resulting from the application of+	<span class="emphasis"><em>f</em></span> to every value in the input.+      </p><div class="figure"><a name="mapSY"></a><p class="title"><b>Figure 4. The synchronous, combinational map process constructor: <span class="emphasis"><em>mapSY</em></span></b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="495"><tr><td align="center" valign="middle"><object data="figures/mapSY.svg" type="image/svg+xml" width="495" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	<span class="emphasis"><em>plus1</em></span> can, in fact, be defined in terms of+	<span class="emphasis"><em>mapSY</em></span> as <span class="emphasis"><em>plus1 = mapSY+	(+1)</em></span>.+      </p><p>+	ForSyDe also supports synchronous, sequential+	systems. However, it does not allow loops formed exclusively+	by combinational processes, also known as+	<span class="emphasis"><em>combinational loops</em></span>, <span class="emphasis"><em>zero-delay+	loops</em></span> or <span class="emphasis"><em>feedback loops</em></span>, since+	their behaviour is not always decidable. Even with that,+	combinational loops are still possible if they contain at+	least one process formed by the+	<span class="emphasis"><em>delaySY<sub>k</sub></em></span>+	(<span class="emphasis"><em>k</em></span> &gt; 0) constructor, which is defined as follows.+      </p><div class="figure"><a name="delaySY"></a><p class="title"><b>Figure 5. The synchronous, sequential delay process constructor: <span class="emphasis"><em>delaySY</em></span></b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="495"><tr><td align="center" valign="middle"><object data="figures/delaySY.svg" type="image/svg+xml" width="495" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	<span class="emphasis"><em>delaySY<sub>k</sub></em></span> takes an+	initial value <span class="emphasis"><em>s<sub>0</sub></em></span>+	and creates a process which appends+	<span class="emphasis"><em>s<sub>0</sub></em></span>, replicated+	<span class="emphasis"><em>k</em></span> times, to its input+	signal. <span class="emphasis"><em>delaySY</em></span> provides the basic+	mechanism with which to build sequential systems.+      </p><p>+	Both <span class="emphasis"><em>mapSY</em></span> and+	<span class="emphasis"><em>delaySY<sub>k</sub></em></span> are+	considered primitive process constructors, since they cannot+	be defined in terms of simpler ones. Primitive constructors+	can be combined, forming derived process+	constructors. For instance, <span class="emphasis"><em>sourceSY</em></span> is+	the result of combining+	<span class="emphasis"><em>delaySY<sub>1</sub></em></span> (normally+	denoted simply as <span class="emphasis"><em>delaSY</em></span>) and+	<span class="emphasis"><em>mapSY</em></span>.+      </p><div class="figure"><a name="sourceSY"></a><p class="title"><b>Figure 6. The <span class="emphasis"><em>sourceSY</em></span> derived process constructor</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="450"><tr><td align="center" valign="middle"><object data="figures/sourceSY.svg" type="image/svg+xml" width="450" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	<span class="emphasis"><em>sourceSY</em></span> takes an initial value <span class="emphasis"><em>s<sub>0</sub></em></span>+	and a function <span class="emphasis"><em>f</em></span>, and creates a sequential process with no+	inputs and just one output, resulting from the reiterated application of <span class="emphasis"><em>f</em></span>+	to <span class="emphasis"><em>s<sub>0</sub></em></span>.+      </p><p>+	For example, <span class="emphasis"><em>sourceSY</em></span>(1,(+1)), is a+	counter with <span class="emphasis"><em>1</em></span> as its initial value.+      </p><p>+	ForSyDe supplies many other process constructors (e.g. <code class="code">zipWithSY</code>, <code class="code">mealySY</code> ...). However, a thoroughly description+	is out of the scope of this tutorial. +      </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1251871"></a>3.4. Models of Computation and Domain Interfaces</h3></div></div></div><p>+	A <span class="emphasis"><em>Model of Computation</em></span> (MoC), also known+	as <span class="emphasis"><em>Computational Model</em></span>, establishes a set of+	constraints on the possible processes and signals contained by+	a system. A system is said to belong to certain+	<span class="emphasis"><em>MoC</em></span> if it satisfies its+	constraints. +      </p><p>+	The behaviour of a process is observed in its+	<span class="emphasis"><em>evaluation</em></span>. The evaluation is divided+	in atomic steps called <span class="emphasis"><em>evaluation+	cycles</em></span>, during which the process produces and+	consumes signal values. MoCs specify how and when evaluation+	cycles are fired.+      </p><p>+	ForSyDe currently offers 3 MoCs.+      </p><div class="itemizedlist"><ul type="disc"><li><p>+	    The <span class="strong"><strong>Synchronous MoC</strong></span> was+	    already mentioned in previous section.  All systems+	    contain an implicit global clock. Its cycle matches+	    the evaluation cycle of all the system processes, during which+	    they must consume and produce exactly one value on every+	    input and output signal.+	  </p></li><li><p>+	    <span class="strong"><strong>Untimed+	    MoC</strong></span>. Communication between processes can be+	    thought as a specific variant of asynchronous, blocking+	    message passing. There is no notion of time or global+	    clock.+	  </p><p>+	    Contrary to the Synchronous MoC, in which all the system+	    processes evaluate in parallel during every cycle,+	    untimed processes are fired individually. A process only+	    evaluates when all their inputs have a minimum number of+	    values ready to be read. That number may vary between+	    inputs, but is fixed for each of them. On the other hand,+	    the number of values produced by output signals +	    may vary independently between evaluation cycles.+	  </p></li><li><p>+	    The <span class="strong"><strong>Continuous MoC</strong></span>+	    models continuous signals representing them as+	    continuous one-variable, piecewise functions.+	  </p><div class="figure"><a name="id1252356"></a><p class="title"><b>Figure 7. Continuous signal</b></p><div class="figure-contents">+	    &lt; (sin(x),[-10,0)), (-sin(x),[0,10)) &gt;+	    <div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="360"><tr><td align="center" valign="middle"><object data="figures/piecewise_sin.svg" type="image/svg+xml" width="360" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"></li></ul></div><p>+	ForSyDe specifies a set of process constructors for each MoC. A+	ForSyDe system is thus guaranteed to belong to a MoC if it was+	built using constructors from one of those sets.+      </p><p>+	Nevertheless, it is possible to build heterogeneous systems,+	i.e. systems which mix different MoCs. For that purpose,+	ForSyDe provides special<sup>[<a name="id1252412" href="#ftn.id1252412" class="footnote">3</a>]</sup> processes in+	charge of connecting two subsystems which belong to different+	MoCs or which have different timing specifications (e.g. two+	Synchronous subsystems with a different clock period).+      </p></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="DEvsSE"></a>4. Deep-embedded vs Shallow-embedded signals</h2></div></div></div><p>+      As we already mentioned, ForSyDe is implemented as a+      Domain Specific Embedded Language (DSL) on top of Haskell.+      Actually, ForSyDe offers two different DSL flavours+      according to how signals are modelled.+    </p><div class="itemizedlist"><ul type="disc"><li><p>+	  <span class="strong"><strong>Shallow-embedded signals</strong></span>+	  (<a class="ulink" href="http://hackage.haskell.org/packages/archive/ForSyDe/3.0/doc/html/ForSyDe-Shallow-Signal.htm" target="_top"><code class="code">ForSyDe.Shallow.Signal</code></a>)+	  are modelled as streams of data isomorphic to lists.+	</p><pre class="programlisting">+data Signal a = NullS | a :- Signal a+	  </pre><p>+	    Systems built with them are unfortunately restricted to+	    simulation, however, shallow-embedded signals provide a+	    rapid-prototyping framework with which to experiment with+	    Models of Computation.+	  </p></li><li><p>+	  <span class="strong"><strong>Deep-embedded signals</strong></span>+	  (<a class="ulink" href="http://hackage.haskell.org/packages/archive/ForSyDe/3.0/doc/html/ForSyDe-Signal.htm" target="_top"><code class="code">ForSyDe.Signal</code></a>)+	  are used in a similar way to shallow-embedded signals but+	  are modelled as an abstract data type which, transparently+	  to the end user, keeps track of the system+	  structure<sup>[<a name="id1252502" href="#ftn.id1252502" class="footnote">4</a>]</sup>. Based on that structural+	  information, ForSyDe's embedded compiler can perform+	  different analysis and transformations such as simulating+	  the system or translating it to other target languages+	  (e.g. VHDL and GraphML).+	</p><p>+	  As a drawback, the deep-embedded API can only currently+	  build systems belonging to the Synchronous MoC and domain+	  interfaces are not yet supported. This limitation is,+	  however, likely to change in the future.+	</p></li></ul></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="DE"></a>5. Using deep-embedded Signals</h2></div></div></div><p>+      In this section we go through a few simple sample systems+      built with ForSyDe's deep-embedded API. We will create both+      combinational and sequential systems all belonging to the+      Synchronous MoC (the only MoC currently supported by this API).+    </p><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="combinational"></a>5.1. Combinational Systems</h3></div></div></div><p>+	A system or process is combinational if its outputs are+	stateless, i.e. they don't depend on past system events.+      </p><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="plus1"></a>5.1.1. A naive combinational system: <span class="emphasis"><em>plus1</em></span></h4></div></div></div><p>+	  We are going to implement <span class="emphasis"><em>plus1</em></span>, ForSyDe's <span class="emphasis"><em>Hello World</em></span>, a+	  system with takes integer values, adds 1 to them and forwards the result+	  through its output signal.+	</p><p>+	  As we mentioned previously, the <span class="emphasis"><em>plus1</em></span>+	  process can be created in terms of the+	  <span class="emphasis"><em>mapSY</em></span> process constructor.  Here is the+	  signature of <code class="code">mapSY</code> in the deep-embedded API.+	</p><pre class="programlisting">+mapSY :: (ProcType a, ProcType b) =&gt;+         ProcId -&gt; ProcFun (a -&gt; b) -&gt; Signal a -&gt; Signal b	+	</pre><p>+	  <code class="code">mapSY</code> works similarly to Haskell's+	  <code class="code">map</code> function. It creates a process which applies a+	  function to every value in a signal. Let's have a closer look+	  at its arguments.+	</p><div class="variablelist"><dl><dt><span class="term"><code class="code">ProcId</code></span></dt><dd>+	      The process identifier, simply a textual tag which+	      univocally identifies the process created (<code class="code">type ProcId+	      = String</code>).+	    </dd><dt><span class="term"><code class="code">ProcFun (a-&gt;b)</code></span></dt><dd><p>+		A process function. The function which will be applied to every element in the input signal. In the+		case of <code class="code">plus1</code> we will need a function computationally equivalent to <code class="code">(+1)</code>.+	      </p><p>+		Both <code class="code">a</code> and <code class="code">b</code> must be instances+		of <code class="code">ProcType</code> (read Process Type).+		<code class="code">ProcType</code> is used by ForSyDe's embedded+		compiler to extract type and structure information of expressions. +	      </p></dd><dt><span class="term"><code class="code">Signal a</code></span></dt><dd>+	      Input signal.+	    </dd><dt><span class="term"><code class="code">Signal b</code></span></dt><dd>+	      Output signal.+	    </dd></dl></div>+	+	+	Now, we are ready to start implementing <span class="emphasis"><em>plus1</em></span>.+	+	<pre class="programlisting">+{-# LANGUAGE TemplateHaskell #-}+module Plus1 where++import ForSyDe+import Data.Int (Int32)+	</pre><p>+	  We need to import ForSyDe's library and+	  <code class="code">Int32</code>. Since deep-embedded systems might be+	  later translated to hardware, it is required to be specific+	  about the size of integers used (the size of <code class="code">Int</code> is+	  platform-specific).  Additionally, in all ForSyDe+	  deep-embedded designs we need to tell GHC to enable the <a class="ulink" href="http://www.haskell.org/th/" target="_top">Template+	  Haskell</a> (TH) extension, here is why:+	</p><pre class="programlisting">+-- A process function which adds one to its input+addOnef :: ProcFun (Int32 -&gt; Int32)+addOnef = $(newProcFun [d|addOnef :: Int32 -&gt; Int32 +                          addOnef n = n + 1     |])+	</pre><p>+	  In the code above, we declared the <code class="code">ProcFun</code> needed+	  by <code class="code">mapSY</code>. It simply takes an <code class="code">Int32</code> value+	  and adds 1 to it.+	</p><p>+	  Instead of creating a specific DSL to express computations+	  in the deep-embedded model, ForSyDe uses TH to allow using+	  plain Haskell. In principle, <code class="code">ProcFun</code>s can make+	  use of any Haskell feature supported by TH. However, such+	  features might not be supported or make sense for certain+	  backends (e.g. lists and thus, list comprehensions, are+	  difficult to support in VHDL). Thus, in this tutorial we will+	  create systems which are compatible with every backend. For example,+	  writing <code class="code">addOnef = (+1)</code> instead of <code class="code">addOnef n = n +1</code>+	  is more compact, however the VHDL backend does not currently support+	  sections nor points-free notation.+	</p><p>+	  In order to use ForSyDe it is not vital to understand what is+	  really happening, but, for those curious about it, here is how+	  the TH trick works. First, the <code class="code">[d| .. |]</code> brackets+	  enclosing the function declaration lift its AST (Abstract+	  Syntax Tree). Then, the AST is used by <code class="code">newProcFun</code>+	  to splice (expand in TH's terminology) a <code class="code">ProcFun</code>.+	  It is important to note that everything happens at compile-time.+	</p><p>+	  Here is the rest of the system definition.  +	</p><pre class="programlisting">+-- System function (simply a process in this case) which uses addOnef+plus1Proc :: Signal Int32 -&gt; Signal Int32+plus1Proc = mapSY "plus1Proc" addOnef+++-- System definition associated to the system function+plus1SysDef :: SysDef (Signal Int32 -&gt; Signal Int32)+plus1SysDef = newSysDef plus1Proc "plus1" ["inSignal"] ["outSignal"]+	</pre><p>+	  First, we use <code class="code">mapSY</code> to create process. Then we create the final definition+	  of the <span class="emphasis"><em>plus1</em></span> system with <code class="code">newSysDef</code>. Here is its type signature.+	</p><pre class="programlisting">+newSysDef :: (SysFun f) =&gt; f -&gt; SysId -&gt; [PortId] -&gt; [PortId] -&gt; SysDef f+	</pre><div class="variablelist"><dl><dt><span class="term"><code class="code">f</code></span></dt><dd>+	      A <code class="code">SysFun</code> (system function) describing the+	      system. It results from the combination of one or more+	      processes. ForSyDe uses a trick similar to <a class="ulink" href="http://www.haskell.org/ghc/docs/latest/html/libraries/base/Text-Printf.html" target="_top"><code class="code">Text.Printf</code></a>+	      in order to emulate variadic functions (different systems+	      are obviously allowed to have different number of inputs+	      and outputs).+	    </dd><dt><span class="term"><code class="code">SysId</code></span></dt><dd>+	      Textual tag identifying the system. <code class="code">type SysId = String</code>.+	    </dd><dt><span class="term"><code class="code">[PortId]</code></span></dt><dd>+	      List of port identifiers for the system inputs and outputs. <code class="code">type PortId = String</code>.+	    </dd></dl></div><p>+	  Now we can simulate our system, or, as we will see later on, translate it to VHDL or GraphML.+	</p><pre class="programlisting">+simulate :: SysFunToSimFun sysFun simFun =&gt; SysDef sysFun -&gt; simFun+	</pre><p>+	  <code class="code">simulate</code> transforms our system definition into a+	  list-based function with the help of a multiparameter+	  typeclass, <code class="code">SysFunToSimFun</code>, in charge of+	  implementing the <span class="emphasis"><em>type-level</em></span> translation of the system+	  signals to lists.+	</p><pre class="screen">+<code class="prompt">$</code> ghci Plus1.hs+<code class="prompt">*Plus1&gt;</code> let simPlus1 = simulate plus1SysDef +<code class="prompt">*Plus1&gt;</code> :t simPlus1+simPlus1 :: [Int32] -&gt; [Int32]+<code class="prompt">*Plus1&gt;</code> simPlus1 [1..10]+[2,3,4,5,6,7,8,9,10,11]+	</pre><p>+	  Simulation is lazy, allowing to work with infinite signals.+	</p><pre class="screen">+<code class="prompt">*Plus1&gt;</code> take 10 $ simPlus1 [1,1..] +[2,2,2,2,2,2,2,2,2,2]+	</pre><p>+	  It is important to remark that ForSyDe does not support+	  systems containing <span class="emphasis"><em>combinational loops</em></span>.+	  If such a loop is found, an error will be reported.+	</p><p>+	  For example, here is a system containing a combinational+	  loop, built with a mutually recursive call between two+	  processes adding one to their inputs.+	</p><pre class="programlisting">+combLoopSysDef :: SysDef (Signal Int32)+combLoopSysDef = newSysDef s "combLoop" [] ["out"] + where s  = mapSY "addOne1" addOnef s'+       s' = mapSY "addOne2" addOnef s+	</pre><p>+	  As we mentioned, <code class="code">combLoopSysDef</code> cannot be simulated.+	</p><pre class="screen">+*Plus1&gt; simulate combLoopSysDef +*** Exception: detected combinational loop+	</pre></div><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="id1253066"></a>5.1.2. Keypad encoder</h4></div></div></div><p>+	  Here is a slightly more complex example. We have a keypad with+	  4 arrow buttons connected to our synchronous system. The+	  key-presses are sent in the form of a 4-bit vector. Each bit+	  indicates whether the corresponding button is pressed (high+	  value) or not (low value) according to the diagram below.+	</p><div class="figure"><a name="encoderfig"></a><p class="title"><b>Figure 8. Keypad encoder</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="225"><tr><td align="center" valign="middle"><object data="figures/encoder.svg" type="image/svg+xml" width="225" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	  In order to work more comfortably and forget about multiple+	  key-strokes at once, we want to encode each key-press event+	  with a specific Haskell type: <code class="code">data Direction = Left |+	  Down | Right | Up</code>.+	</p><p>+	  Of course, keys are not necessarily pressed all the time.+	  Thus, instead of encoding the input vector into a signal of+	  <code class="code">Direction</code> we will output signals of+	  <code class="code">AbstExt Direction</code>.+	</p><pre class="programlisting">+data AbstExt a = Abst | Prst a+	  </pre><p>+	  <code class="code">AbstExt</code> (read absent-extended) is ForSyDe's+	  equivalent to the popular Haskell type <code class="code">Maybe</code>.+	  It is used to introduce absent values in signals, in our+	  particular case it will denote an absence of key presses.+	</p>++	+	Here is the definition of <code class="code">Direction</code> together with+	the necessary imports for the definition of the whole system.++	+	<pre class="programlisting">+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-}+module Encoder where++import ForSyDe+import Language.Haskell.TH.Lift (deriveLift1)++import Prelude hiding (Left, Right)+import Data.Generics (Data,Typeable)+import Data.Param.FSVec+import Data.TypeLevel.Num hiding ((==))+++data Direction = Left | Down | Right | Up+ deriving (Typeable, Data, Show)++$(deriveLift1 ''Direction)+	</pre><p>+	  There are a few things worth remarking+	  </p><div class="itemizedlist"><ul type="disc"><li><p>+		Since we are defining new constructors named <code class="code">Left</code> and <code class="code">Right</code>, to avoid clashes+		with the identically-named constructors of <code class="code">Either</code> we hide their import from+		the <code class="code">Prelude</code>.+	      </p></li><li><p>+		We are defining a custom enumerated+		datatype<sup>[<a name="id1253225" href="#ftn.id1253225" class="footnote">5</a>]</sup> (<code class="code">Direction</code>)+		whose values will be carried by system signals. All+		the values used in a system, and+		<code class="code">Direction</code> in particular, must be+		instances of the private typeclass+		<code class="code">ProcType</code>.+	      </p><pre class="programlisting">+class (Data a, Lift a) =&gt; ProcType a++-- Some existing (overlapping) instances of ProcType+instance (Data a, Lift a) =&gt; ProcType a+instance ProcType a =&gt;  ProcType (AbstExt a)+instance (ProcType a, ProcType b) =&gt;  ProcType (a,b)+...  +	      </pre><p>+		The <code class="code">ProcType</code> constraint is required,+		among other reasons, to provide type and structural+		information of datatypes to ForSyDe's embedded+		compiler. The overlapping instances are needed to+		obtain datatype information regardless of +		the nesting of values in other supported datastructures.+	      </p><p>+		Due to the <code class="code">(Data a, Lift a) =&gt; ProcType a</code>+		instance all we need to do in order to use our custom+		enumerated datatypes with ForSyDe is creating+		instances of <code class="code">Data</code> (which implicitly+		requires an instantiation of <code class="code">Typeable</code>)+		and Template Haskell's <code class="code">Lift</code> class.+	      </p><p>+		Fortunately, thanks to a GHC extension it is possible+		to derive instances for <code class="code">Typeable</code> and+		<code class="code">Data</code> (hence the+		<code class="code">DeriveDataTypeable</code> language+		pragma). Additionally, ForSyDe provides a Template+		Haskell module+		<code class="code">Language.Haskell.TH.Lift</code><sup>[<a name="id1253310" href="#ftn.id1253310" class="footnote">6</a>]</sup> to automatically generate+		instances of <code class="code">Lift</code>. In this case, since we+		needed to instantiate a single datatype, we used+		<code class="code">deriveLift1</code>.+	      </p></li><li><p>+		The rest of the imports (<code class="code">Data.Param.FSVec</code>+		and <code class="code">Data.TypeLevel.Num</code>) come from the+		<a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/parameterized-data" target="_top"><code class="code">parameterized-data</code></a>+		and+		<a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/type-level" target="_top"><code class="code">type-level</code></a>+		packages in order to support fixed-sized vectors.+	      </p></li></ul></div><p>++	</p><p>+	  Here is the code of the process function, needed to encode the button presses:+	</p><pre class="programlisting">+encoderFun :: ProcFun (FSVec D4 Bit -&gt; AbstExt Direction)+encoderFun = $(newProcFun +  [d| encode :: FSVec D4 Bit -&gt; AbstExt Direction+      encode v = if v ! d0 == H then Prst Left  else+                 if v ! d1 == H then Prst Down  else+                 if v ! d2 == H then Prst Right else+                 if v ! d3 == H then Prst Up else Abst  |])+	</pre><p>+	  The code should be self-explanatory, it makes use of the+	  type <code class="code">ForSyDe.Bit.Bit</code>, with data constructors+	  <code class="code">L</code> (low) and <code class="code">H</code> (high), and of+	  vectors of size 4 (hence the <code class="code">D4</code> type+	  parameter).  In order to get a deeper insight on how+	  <code class="code">FSVec</code>s work, check <a class="xref" href="#FSVec" title="A. FSVecs: Vectors parameterized in size">Appendix A, <i><code class="literal">FSVec</code>s: Vectors parameterized in size</i></a>. It+	  is important to note that the system does not take+	  simultaneous key-strokes in account, choosing the direction+	  with higher precedence (i.e. situated in the outermost <code class="code">if</code>+	  expression). Also, using pattern matching with multiple+	  function clauses instead of nested <code class="code">if</code>+	  expressions would had been more clear. However, the VHDL+	  backend currently only supports one clause.+	</p><p>+	  Here is the remaining code needed to build the rest of the system.+	</p><pre class="programlisting">+encoderProc :: Signal (FSVec D4 Bit) -&gt; Signal (AbstExt Direction)+encoderProc = mapSY "encoder" encoderFun++encoderSysDef :: SysDef (Signal (FSVec D4 Bit) -&gt; Signal (AbstExt Direction))+encoderSysDef = newSysDef encoderProc "KeypadEncoder" ["arrowBits"] ["direction"]	  +	</pre><p>+	  Finally, we can evaluate some simulations.+	</p><pre class="screen">+<code class="prompt">$</code> ghci -XTemplateHaskell Encoder.hs+<code class="prompt">*Encoder&gt;</code> let simEncoder = simulate encoderSysDef +<code class="prompt">*Encoder&gt;</code> :t simEncoder+simEncoder :: [FSVec D4 Bit] -&gt; [AbstExt Direction]+<code class="prompt">*Encoder&gt;</code> simEncoder [$(vectorTH [L,H,L,L]), $(vectorTH [L,L,L,L])]+[Down,_]+	</pre></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="sequential"></a>5.2. Sequential Systems</h3></div></div></div><p>+	Now we are going to have a look at a couple of sequential systems, whose outputs, contrary to combinational systems,+	can depend on the system history (i.e. can have a state).+      </p><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="counter"></a>5.2.1. A naive sequential system: <span class="emphasis"><em>counter</em></span></h4></div></div></div><p>+	  Our goal is to generate a signal whose values match its tags+	  or, more intuitively, a counter from 1 to infinity.+	</p><p>+	  This is clearly a sequential system since its output signal+	  is not stateless, each output value depends on the previous+	  one.+	</p><pre class="programlisting">+{-# LANGUAGE TemplateHaskell #-}+module Counter where++import ForSyDe+import Data.Int (Int32)+import Plus1 (addOnef)++counterProc :: Signal Int32+counterProc = out'+  where out  = mapSY "addOneProc" addOnef out'+        out' = delaySY "delayOne" 1 out++counterSysDef :: SysDef (Signal Int32)+counterSysDef = newSysDef counterProc "counter" [] ["count"]+	  </pre><p>+	    We reuse <code class="code">addOnef</code> from previous examples. The counter is built by the mutually recursive calls of+	    <code class="code">mapSY</code> and <code class="code">delaySY</code> which should be interpreted as parallel equations.+	  </p><p>+	    Again, we can lazily simulate the system.+	  </p><pre class="screen">+<code class="prompt">$</code> ghci Counter.hs+<code class="prompt">*Counter&gt;</code> :t simulate counterSysDef +simulate counterSysDef :: [Int32]+<code class="prompt">*Plus1&gt;</code> simulate counterSysDef+[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17+^C Interrupted+	  </pre><p>+	    Actually, the definition of <code class="code">counterProc</code> can be+	    simplified by using <code class="code">sourceSY</code>, getting the following+	    equivalent declaration.+	  </p><pre class="programlisting">+counterProc :: Signal Int32+counterProc = sourceSY "counterProc" addOnef 1+	  </pre></div><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="id1253588"></a>5.2.2. Serial full adder</h4></div></div></div><p>+	  A serial full adder which adds two streams of bits is a,+	  still simple, but more elaborated example of a sequential+	  system. Our system will receive pairs of bits which will be+	  added together, taking the resulting carry of last cycle in+	  account.+	</p><p>+	  We are going to implement it as a Mealy FSM (Finite State Machine) following the diagram below.+	</p><div class="figure"><a name="fullAdderfig"></a><p class="title"><b>Figure 9. Full Adder: Mealy Machine</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="315"><tr><td align="center" valign="middle"><object data="figures/fullAdderMealy.svg" type="image/svg+xml" width="315" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	  ForSyDe provides derived process constructors to implement FSMs, in this case we will be using+	  <code class="code">mealySY</code>.+	</p><pre class="programlisting">+mealySY :: (ProcType c, ProcType b, ProcType a) =&gt;+           ProcId+        -&gt; ProcFun (a -&gt; b -&gt; a)+        -&gt; ProcFun (a -&gt; b -&gt; c)+        -&gt; a+        -&gt; Signal b+        -&gt; Signal c+	</pre><div class="variablelist"><dl><dt><span class="term"><code class="code">ProcId</code></span></dt><dd>+	      The process identifier, used in the same way as in the+	      rest of the process constructors+	      (e.g. <code class="code">mapSY</code> and <code class="code">delaySY</code>).+	    </dd><dt><span class="term"><code class="code">ProcFun (a- &gt; b -&gt; a)</code></span></dt><dd><p>+		A process function in charge of calculating next state+		based on current state and current input.+	      </p></dd><dt><span class="term"><code class="code">ProcFun (a -&gt; b -&gt; c)</code></span></dt><dd><p>+		A process function in charge of calculating current output+		based on current state and current input.+	      </p></dd><dt><span class="term"><code class="code">a</code></span></dt><dd><p>+		Initial state.+	      </p></dd><dt><span class="term"><code class="code">Signal b</code></span></dt><dd>+	      Input Signal.+	    </dd><dt><span class="term"><code class="code">Signal c</code></span></dt><dd>+	      Output Signal.+	    </dd></dl></div><p>+	  Here is the Haskell code, which should be straightforward to understand.+	</p><pre class="programlisting">+{-# LANGUAGE TemplateHaskell #-}+module FullAdder where++import ForSyDe++faNextState :: ProcFun (Bit -&gt; (Bit,Bit) -&gt; Bit)+faNextState = $(newProcFun+  [d| faNextState :: Bit -&gt; (Bit,Bit) -&gt; Bit+      faNextState st input =+         if st == L then+            case input of+              (H, H) -&gt; H+              _ -&gt; L+         else+            case input of+              (L,L) -&gt; L+              _ -&gt; H+     |])++faOut :: ProcFun (Bit -&gt; (Bit,Bit) -&gt; Bit)+faOut= $(newProcFun+  [d| faOut :: Bit -&gt; (Bit,Bit) -&gt; Bit+      faOut st input =+         if st == L then+            case input of+              (L, L) -&gt; L+              (L, H) -&gt; H+              (H, L) -&gt; H+              (H, H) -&gt; L+         else+            case input of+              (L, L) -&gt; H+              (L, H) -&gt; L+              (H, L) -&gt; L+              (H, H) -&gt; H+     |])+++faProc :: Signal (Bit,Bit) -&gt; Signal Bit+faProc = mealySY "addProc" faNextState faOut L++faSysDef :: SysDef (Signal (Bit,Bit) -&gt; Signal Bit)+faSysDef = newSysDef faProc "fullAdder" ["op1", "op2"] ["res"]	  +	</pre>++	Here is a little test.++	<pre class="screen">+*FullAdder&gt; let simfa = simulate faSysDef +*FullAdder&gt; simfa [(L,L),(L,H),(H,H),(L,L)]+[L,H,L,H]+*FullAdder&gt; 	+	</pre></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="components"></a>5.3. Using components</h3></div></div></div><p>+	A desired characteristic of any system design language is+	the possibility of creating hierarchical models.+      </p><p>+	In ForSyDe's deep-embedded DSL, hierarchical design is implemented through components, let's see+	an example.+      </p><div class="figure"><a name="seqaddfour"></a><p class="title"><b>Figure 10. <span class="emphasis"><em>AddFour</em></span> system</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="540"><tr><td align="center" valign="middle"><object data="figures/SeqAddFour.svg" type="image/svg+xml" width="540" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	The system above which, admittedly, would not be of much use+	in the real world, adds 4 to its input in serial steps of 1.+      </p><p>+	Instead of creating 4 different processes and connecting them+	together, we can reuse the design of <span class="emphasis"><em>plus1</em></span>+	placing 4 identical components.+      </p><p>+	ForSyDe provides a primitive to create components or instances+	of a system: <code class="code">instantiate</code>.+      </p><pre class="programlisting">+instantiate :: (SysFun f) =&gt; ProcId -&gt; SysDef f -&gt; f+      </pre><p>+	<code class="code">instantiate</code> creates a component out of a system+	definition. A component can be considered a special process+	(hence the <code class="code">ProcId</code> parameter) containing an+	instance of its parent system (the system from which it is+	created).+      </p><p>+	Instances behave identically to their parents and can be combined with+	other system processes.+      </p><p>+	For example, here we create and simulate an instance of <span class="emphasis"><em>plus1</em></span>+      </p><pre class="screen">+$ ghci Plus1.hs+*Plus1&gt; :t plus1SysDef+plus1SysDef :: SysDef (Signal Int32 -&gt; Signal Int32)+*Plus1&gt; let plus1Comp1 = instantiate "plus1_1" plus1SysDef +*Plus1&gt; :t plus1Comp1+plus1SysDef :: Signal Int32 -&gt; Signal Int32+*Plus1&gt; let nestedPlus1 = newSysDef plus1Comp1 "nestedPlus1" ["in1"] ["out1"]+*Plus1&gt; simulate nestedPlus1 $ [1,2,3,4]+[2,3,4,5]+      </pre><p>+	And here is the definition of the <span class="emphasis"><em>AddFour</em></span> system.+      </p><pre class="programlisting">+module AddFour where++import Plus1 (plus1SysDef)++import ForSyDe+import Data.Int (Int32)++addFourProc :: Signal Int32 -&gt; Signal Int32+addFourProc = plus1Comp "plus1_1" .+              plus1Comp "plus1_2" .+              plus1Comp "plus1_3" .+              plus1Comp "plus1_4"+ where plus1Comp id = instantiate id plus1SysDef++addFourSysDef :: SysDef (Signal Int32 -&gt; Signal Int32)+addFourSysDef = newSysDef addFourProc "addFour" ["in1"] ["out1"]+      </pre><p>+	Components, just like any other process, are functions over+	signals. This allows using all the combinatorial power of+	Haskell. In this particular case we have just used function+	composition.+      </p><p>+	Here is the general workflow of ForSyDe modelling, including+	the use of components.+      </p><div class="figure"><a name="cwf"></a><p class="title"><b>Figure 11. Component workflow</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="540"><tr><td align="center" valign="middle"><object data="figures/compflow.svg" type="image/svg+xml" width="540" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><div class="orderedlist"><ol type="1"><li><p>+	    The designer describes computations using process functions (<code class="code">ProcFun</code>s).+	  </p></li><li><p>+	    Those process functions, possibly with other constants,+	    are passed to process constructors in order to build+	    processes which are combined together,+	    creating the main process function.+	  </p></li><li><p>+	    The system function is transformed into a system definition by <code class="code">newSysDef</code>.+	  </p></li><li><p>+	    The system definition can be+	    </p><div class="itemizedlist"><ul type="disc"><li>+		passed to ForSyDe's embedded compiler, capable of simulating or+		translating it to other target languages (VHDL or GraphML at the time being).+	      </li><li>+		used to create components, bringing us back to step 2.+	      </li></ul></div><p>+	  </p></li></ol></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="VHDL"></a>5.4. VHDL Backend</h3></div></div></div><p>+	ForSyDe's embedded compiler is able to translate system definitions to VHDL. That is+	done through the <code class="code">writeVHDL</code>* functions.+      </p><pre class="programlisting">+writeVHDL :: SysDef a -&gt; IO ()+writeVHDLOps :: VHDLOps -&gt; SysDef a -&gt; IO ()+      </pre><p>+	For example, this is how we would generate the VHDL definition+	of <span class="emphasis"><em>AddFour</em></span> and write it to disk.+      </p><pre class="screen">+$ ghci AddFour.hs+*AddFour&gt; writeVHDL addFourSysDef +*AddFour&gt; :q+Leaving GHCi.+$ ls -R addFour+vhdl++addFour/vhdl:+addFour_lib work++addFour/vhdl/addFour_lib:+addFour_lib.vhd++addFour/vhdl/work:+addFour.vhd plus1.vhd+      </pre><p>+	Here is a diagram of the filetree generated for <code class="code">addFour</code>.+      </p><div class="figure"><a name="VHDLTree"></a><p class="title"><b>Figure 12. VHDL filetree of <code class="code">addFour</code></b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="315"><tr><td align="center" valign="middle"><object data="figures/VHDLTree.svg" type="image/svg+xml" width="315" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	<code class="code">writeVHDL</code> generates a VHDL filetree pending from current+	working directory. Assuming <code class="code">$SYSNAME</code> is the+	system's name (<code class="code">addFour</code> in this particular case):+      </p><div class="itemizedlist"><ul type="disc"><li><p>+	    The main VHDL entity and architecture is written in <code class="code">$SYSNAME/vhdl/work/$SYSNAME.vhdl</code>.+	  </p></li><li><p>+	    The VHDL translation of other systems included through component instantiation is also written under+	    <code class="code">$SYSNAME/vhdl/work/</code>. In  the case of the <code class="code">addFour</code> system, the compiler also+	    generates the file <code class="code">plus1.vhd</code>.+	  </p></li><li><p>+	    A global VHDL library, <code class="code">forsyde_lib.vhd</code>, is+	    bundled with ForSyDe's distribution and contains the+	    translation of basic monomorphic Haskell types to VHDL. It+	    is installed under the <code class="code">data</code> directory of+	    ForSyDe's Cabal package, whose location is+	    system-dependent.+	  </p></li><li><p>+	    Since VHDL lacks support for <span class="emphasis"><em>parametric+	    polymorphism</em></span>, the translation of polymorphic+	    types and functions is done on a per-system basis+	    (i.e. each different possible monotype of a polymorphic+	    Haskell type triggers a different translation). Thus, the+	    result of that translation is put in+	    <code class="code">$SYSNAME/vhdl/lib/$SYSNAME_lib.vhd</code> and not+	    <code class="code">forsyde_lib.vhd</code>.+	  </p></li></ul></div><p>+	It is important to remember that, even if ForSyDe signals are polymorphic and+	<code class="code">ProcFun</code>s can include any Haskell function definition, +	some backends might be limited. In the case of the VHDL backend:+      </p><div class="itemizedlist"><ul type="disc"><li><p>+	    Accepted <code class="code">Signal</code> types. <code class="code">Signal a</code> is a valid+	    signal for the VHDL backend if <code class="code">a</code> belongs to:+	  </p><div class="orderedlist"><ol type="1"><li><p>+		Primitive types: <code class="code">Data.Int</code>{<code class="code">8</code>, <code class="code">16</code>, <code class="code">32</code>}, <code class="code">Bool</code>,+		<code class="code">ForSyDe.Bit</code>.+	      </p></li><li><p>+		Custom types: enumerated<sup>[<a name="id1254317" href="#ftn.id1254317" class="footnote">7</a>]</sup> types.+	      </p></li><li><p>+		The following containers, which can hold any primitive+		or custom type and can be unrestrictively nested:+		<code class="code">Data.Param.FSVec</code>, tuples of unlimited+		size<sup>[<a name="id1254337" href="#ftn.id1254337" class="footnote">8</a>]</sup>,+	      </p></li></ol></div></li><li><p>+	    Although this will hopefully change in the future, the+	    declarations contained by <code class="code">ProcFun</code>s must+	    be fairly simple. For instance:+	  </p><div class="orderedlist"><ol type="1"><li><p>+		Points-free notation is not admitted.+	      </p></li><li><p>+		They can only contain a clause, multiple clauses are not accepted.+	      </p></li></ol></div></li></ul></div><p>+	Getting back to the function interface of the VHDL backend, it+	is possible to provide certain compilation options, namely to+	integrate Altera's <span class="emphasis"><em>Quartus II</em></span> and+	<span class="emphasis"><em>Modelsim</em></span> in our workflow. For that+	purpose we will use <code class="code">writeVHDLOps</code>.+      </p><p>+	For example, we can generate a <code class="code">Quartus II</code> project+	and compile the generated VHDL code setting certain configuration+	options such as the pin-mapping and the FGPA model to be used.+      </p><pre class="programlisting">+compileQuartus :: IO ()+compileQuartus = writeVHDLOps vhdlOps addFourSysDef+ where vhdlOps = defaultVHDLOps{execQuartus=Just quartusOps}+       quartusOps = QuartusOps{action=FullCompilation,+                               fMax=Just 50, -- in MHz+                               fpgaFamiliyDevice=Just ("CycloneII",+                                                       Just "EP2C35F672C6"),+                               -- Three sample pin assignments+                               pinAssigs=[("in1[0]", "PIN_W1"),+                                          ("in1[1]", "PIN_W2"),+                                          ("in1[2]", "PIN_W3")]}+      </pre><p>+	The code above generates the VHDL code for the+	<code class="code">addFour</code> system, subsequently creating a Quartus+	project and running a full compilation of the project. We set+	a minimum acceptable clock frequency of 50 MHz, the FPGA+	family (<code class="code">CycloneII</code>), specific device+	(<code class="code">EP2C35F672C6</code>) and some pin assignments, which,+	for briefness' sake are not sufficient.+      </p><p>+	It is important to note that, when needed, Quartus will+	split input and output port identifiers into several logical+	names corresponding to individual bits (e.g in1[0]).  Thus, it+	might be necessary to open Quartus in order to find out what+	logical names to use in pin assignments.+      </p><p>+	In addition to <span class="emphasis"><em>Quartus II</em></span>, the VHDL+	backend is able to interface with+	<span class="emphasis"><em>ModelSim</em></span>.  For example, the following+	function shows how can we automatically compile the generated+	VHDL code with ModelSim.+      </p><pre class="programlisting">+compileModelSim :: IO ()+compileModelSim = writeVHDLOps vhdlOps addFourSysDef+ where vhdlOps = defaultVHDLOps{compileModelsim=True}+      </pre><p>+	It is also possible to run test benches in ModelSim.+      </p><pre class="programlisting">+writeAndModelsimVHDL :: (SysFunToIOSimFun sysF simF) =&gt;+                        Maybe Int -&gt; SysDef sysF -&gt; simF+writeAndModelsimVHDLOps :: (SysFunToIOSimFun sysF simF) =&gt;+                           VHDLOps -&gt; Maybe Int -&gt; SysDef sysF -&gt; simF+      </pre>+      +      Here are two examples:+      +      <pre class="screen">+$ ghci AddFour.hs+*AddFour&gt; let vhdlSim = writeAndModelsimVHDL Nothing addFourSysDef +*AddFour&gt; :t vhdlSim+vhdlSim :: [Int32] -&gt; IO [Int32]+*AddFour&gt; vhdlSim [1..10]+[4,5,6,7,8,9,10,11,12,13,14]+      </pre><p>+      In the example above, we simulate <code class="code">addFour</code> without supplying a limit in the number of cycles to+      simulate. <code class="code">writeAndModelsimVHDL</code> is strict, so, without a limit it will only work+      with finite input stimuli.+      </p><pre class="screen">+$ ghci Counter.hs+*Counter&gt; writeAndModelsimVHDL (Just 20) counterSysDef+[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20] +      </pre><p>+	In this case the system does not have any inputs and thus the simulation implicitly results in infinite+	output stimuli. Thus, it is necessary to set a limit in the number of cycles to simulate.+      </p><p>+	In a general way, the <code class="code">writeAndModelsimVHDL</code>* functions, generate a+	simulation function which will+      </p><div class="orderedlist"><ol type="1"><li><p>+	      Generate a VHDL model (implicitly using the+	      <code class="code">writeVHDL</code>* functions).+	    </p></li><li><p>+	      Compile the resulting model with ModelSim. +	    </p></li><li><p>+	      Marshal the provided input stimuli from Haskell to VHDL+	      and generate a testbench in+	      <code class="code">$SYSNAME/vhdl/test/$SYSNAME_tb.vhd</code>.+	    </p></li><li><p>+	      Simulate the testbench with ModelSim and unmarshal the+	      results back to Haskell.+	    </p></li></ol></div><p>+	  <code class="code">writeAndModelsimVHDL</code>* give equivalent results to <code class="code">simulate</code>, with a few caveats.+	</p><div class="itemizedlist"><ul type="disc"><li><p>+	      <code class="code">writeAndModelsimVHDL</code>*, unlike+	      <code class="code">simulate</code>, are strict, and thus do not+	      support infinite stimuli. For that reason, it is+	      possible to set the number of cycles to simulate+	      (<code class="code">Maybe Int</code> parameter).+	    </p></li><li><p>+	      <code class="code">writeAndModelsimVHDL</code>* , provide <code class="code">IO</code> simulation functions+	      whereas <code class="code">simulate</code> is pure.+	    </p></li><li><p>+	      <code class="code">writeAndModelsimVHDL</code>*  suffer all the limitations of the VHDL backend whereas+	      <code class="code">simulate</code> can cope with any system.+	    </p></li></ul></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="GraphML"></a>5.5. GraphML Backend</h3></div></div></div><p>+	It is possible to use ForSyDe's GraphML backend in order to +      </p><div class="orderedlist"><ol type="1"><li><p>+	    Generate an XML-based intermediate representation of+	    a system for further processing.+	  </p></li><li><p>+	    Obtain system diagrams.+	  </p></li></ol></div><p>+	ForSyDe provides the following functions, similar to the ones of the VHDL backend. +      </p><pre class="programlisting">+writeGraphML :: SysDef a -&gt; IO ()+writeGraphMLOps :: GraphMLOps -&gt; SysDef a -&gt; IO ()+      </pre><p>+	For example, here is how we would generate the GraphML translation of <code class="code">addFour</code>+      </p><pre class="screen">+$ ghci AddFour.hs+*AddFour&gt; writeGraphML addFourSysDef +*AddFour&gt; :q+Leaving GHCi.+$ ls -R addFour+graphml++addFour/graphml:+addFour.graphml plus1.graphml+      </pre><p>+	As we can see, a <code class="code">.graphml</code> file is generated for each+	system involved. In this case, one for the main system+	(<code class="code">addFour.graphml</code>) and another one for <code class="code">plus1</code>+	which was instantiated by <code class="code">addFour</code>.+      </p><p>+	In order to embed ForSyDe metainformation, the GraphML backend+	makes use of the following <a class="ulink" href="http://graphml.graphdrawing.org/primer/graphml-primer.html#Attributes" target="_top">GraphML-Attributes</a>:+      </p><pre class="screen">+&lt;key id="process_type" for="node" attr.name="process_type" attr.type="string"/&gt;+&lt;key id="value_arg" for="node" attr.name="value_arg" attr.type="string"/&gt;+&lt;key id="procfun_arg" for="node" attr.name="procfun_arg" attr.type="string"/&gt;+&lt;key id="instance_parent" for="node" attr.name="instance_parent" attr.type="string"/&gt;+      </pre><p>+	The keys above are used to tag nodes in different ways.+      </p><div class="itemizedlist"><ul type="disc"><li><p>+	    <span class="strong"><strong><code class="code">process_type</code></strong></span> indicates what process constructor was used+	    to create a process node or if the node is an input or output port. +	  </p></li><li><p>+	    <span class="strong"><strong><code class="code">value_arg</code></strong></span> contains a value passed to a process+	    constructor.+	  </p></li><li><p>+	    <span class="strong"><strong><code class="code">procfun_arg</code></strong></span> contains a value passed to a process+	    constructor.+	  </p></li><li><p>+	    <span class="strong"><strong><code class="code">instance_parent</code></strong></span> is specific to component nodes+	    and indicates the name of the parent system from which the component was instanciated.+	  </p></li></ul></div><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="id1254817"></a>5.5.1. Obtaining diagrams of ForSyDe</h4></div></div></div><p>+	  The GraphML definition does not provide a way to specify the+	  graphical representation of graphs (e.g. edge and node+	  shapes, colours, textual tags ...)+	</p><p>+	  For that reason, <a class="ulink" href="http://www.yworks.com" target="_top"><span class="emphasis"><em>yWorks</em></span></a>, a company+	  offering graph visualization products, created yFiles-GraphML, an extension to the GraphML+	  schema which adds graphical information. +	</p><p>+	  yWorks also distributes <a class="ulink" href="http://www.yworks.com/en/products_yed_about.html" target="_top"><span class="emphasis"><em>yEd</em></span></a>,+	  a free (as in beer) multiplatform graph editor with+	  impressive automatic layout features.+	</p><p>+	  Here is an example on how to generate and edit+	  yFiles-GraphML diagrams from ForSyDe systems. For this+	  purpose, we will use our <span class="emphasis"><em>counter</em></span> system.+	</p><pre class="screen">+$ ghci Counter.hs+*Counter&gt; writeGraphMLOps defaultGraphMLOps{yFilesMarkup=True} counterSysDef +*Counter&gt; :q+$ ls -R counter+graphml++counter/graphml:+counter.graphml              sourceSY_counterProc.graphml+	</pre><p>+	  <code class="code">sourceSY_counterProc.graphml</code> contains the <span class="emphasis"><em>sourceSY</em></span> process+	  used in the counter. Let's view its representation with yEd.+	</p><p>+	  This is the unorganized representation we get right after opening <code class="code">sourceSY_counterProc.graphml</code>+	  with yEd.+	</p><div class="figure"><a name="sourceSY_counterProc1"></a><p class="title"><b>Figure 13. Initial yEd representation</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="225"><tr><td align="center" valign="middle"><object data="figures/sourceSY_counterProc1.svg" type="image/svg+xml" width="225" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"><p>+	  All nodes are overlapped because the GraphML-yFiles backend+	  does not perform any kind of node placement nor edge+	  routing. yEd, however, does a very good job in this regard.+	</p><p>+	  Before running a layout algorithm it is convenient to set+	  port constraints on the graph nodes. This is a workaround to+	  make yEd faithfully represent shared signals+	  (signals coming from the same process output), otherwise yEd+	  will treat them as different outputs. The GraphML format+	  (and GraphML-yFiles) allows edge sharing through the use of+	  <a class="link" href=""><span class="emphasis"><em>ports</em></span></a>,+	  however, yEd does not currently respect them. Our current+	  solution is to set a location for the edge ends in the+	  GraphML backend and lock that location through yEd port+	  constraints.+	</p><p>+	  In order to set the port constraints we will go to+	  <span class="emphasis"><em>Tools -&gt; Constraints -&gt; Port+	  Constraints</em></span>.+	</p><p>+	  The port constraints menu will initially look like this.+	</p><div class="figure"><a name="portConstraints1"></a><p class="title"><b>Figure 14. Port constraints default options</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="360"><tr><td align="center" valign="middle"><img src="figures/portConstraints1.png" align="middle" width="360" alt="Port constraints default options"></td></tr></table></div></div></div><br class="figure-break"><p>+	  These are the options we need to set in order to fix all+	  ports. Remember to click on OK after setting them.+	</p><div class="figure"><a name="portConstraints2"></a><p class="title"><b>Figure 15. Desired port constraint options</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="360"><tr><td align="center" valign="middle"><img src="figures/portConstraints2.png" align="middle" width="360" alt="Desired port constraint options"></td></tr></table></div></div></div><br class="figure-break"><p>+	  It is important to note that due to a bug in yFiles format+	  it is not possible to save port constraints in <code class="code">.graphml</code> files. Thus,+	  we will need to reset the port constraints every time a file is reopened.+	</p><p>+	  Now we are ready to run an automatic layout algorithm. The+	  generated GraphML-yFiles graph is prepared to be displayed+	  from left to right. The hierarchical layout+	  (<span class="emphasis"><em>Layout -&gt; Hierarchical -&gt; Classic</em></span>)+	  seems to give the best results for system diagrams. It is+	  important to set the Orientation to <span class="emphasis"><em>Left to+	  Right</em></span> and allow <span class="emphasis"><em>Backloop Routing</em></span>.+	</p><div class="figure"><a name="layout"></a><p class="title"><b>Figure 16. hierarchical layout</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="360"><tr><td align="center" valign="middle"><img src="figures/layout.png" align="middle" width="360" alt="hierarchical layout"></td></tr></table></div></div></div><br class="figure-break">+	+	After clicking on <span class="emphasis"><em>OK</em></span>, the system diagram should look like this:++	<div class="figure"><a name="sourceSY_counterProc2"></a><p class="title"><b>Figure 17. Final yEd representation</b></p><div class="figure-contents"><div class="mediaobject" align="center"><table border="0" summary="manufactured viewport for HTML img" cellspacing="0" cellpadding="0" width="450"><tr><td align="center" valign="middle"><object data="figures/sourceSY_counterProc2.svg" type="image/svg+xml" width="450" align="middle"></object></td></tr></table></div></div></div><br class="figure-break"></div><div class="section" lang="en"><div class="titlepage"><div><div><h4 class="title"><a name="id1255153"></a>5.5.2. GraphML limitations</h4></div></div></div><p>+	  Unfortunately, GraphML nor yFiles-GraphML + yEd suit all ForSyDe needs: +	</p><div class="itemizedlist"><ul type="disc"><li><p>+	      yFiles does not respect GraphML ports (source signal+	      sharing). We provide a workaround based on precalculate+	      the location of edge ends plus yEd routing port constraints+	      (which unfortunately cannot be saved).+	    </p></li><li><p>+	      yEd wipes out external <code class="code">&lt;data&gt;</code> tags+	      (external GraphML attributes). That includes ForSyDe's+	      metainformation, which will be lost after editing the+	      graph with yEd.+	    </p></li><li><p>+	      GraphML nor yFiles-GraphML explicitly support subgraphs+	      but not subgraph sharing (components). Our solution is+	      to use external &lt;data&gt; tags indicating parent+	      systems in instance nodes. However, yEd is obviously+	      unaware of that trick, not being able to offer+	      hierarchical browsing.+	    </p></li></ul></div></div></div></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="SE"></a>6. Shallow-embedded signals</h2></div></div></div><p>+      As it was previously mentioned, ForSyDe offers a flavour of+      signals called shallow-embedded signals, modelled as+      streams of data:+    </p><pre class="programlisting">+data Signal a = NullS | a :- Signal a+    </pre><p>+      This representation offers some advantages:+    </p><div class="itemizedlist"><ul type="disc"><li><p>+	  Rapid prototyping of systems.+	</p></li><li><p>+	  It is easy to include new MoCs.+	</p></li><li><p>+	  It supports all the MoCs covered by ForSyDe (Synchronous, Untimed and Continuous). +	</p></li></ul></div><p>+      Shallow-embedded signals also present some disadvantages:+    </p><div class="itemizedlist"><ul type="disc"><li><p>+	  Systems built with them can only be+	  simulated. Shallow-embedded signals don't contain any+	  structural information. Thus, the models resulting from them+	  cannot be analyzed or compiled to other target languages.+	</p></li><li><p>+	  No support for components. However, they are not really needed, components are not+	  useful for simulation and reusability can be achieved by function refactoring.+	</p></li></ul></div><p>+      Here is the implementation of <span class="emphasis"><em>plus1</em></span> using shallow-embedded signals. +    </p><pre class="programlisting">+module Plus1Shallow where++import ForSyDe.Shallow++import Data.Int(Int32)++plus1 :: Signal Int32 -&gt; Signal Int32+plus1 = mapSY (+1)+    </pre><p>+      The system can be simulated directly simply by calling <span class="emphasis"><em>plus1</em></span>.+    </p><pre class="screen">+$ ghci Plus1Shallow.hs+*Plus1Shallow&gt; :t signal+signal :: [a] -&gt; Signal a+*Plus1Shallow&gt; plus1 (signal [1..10])+{2,3,4,5,6,7,8,9,10,11}+    </pre><p>+      We can also integrate deep-embedded models into shallow-embedded+      ones by using <code class="code">simulate</code>, <code class="code">signal</code> and+      <code class="code">fromSignal</code> (the inverse of <code class="code">signal</code>).+      In the example below, we use the deep-embedded+      <code class="code">addFour</code> system and the shallow-embedded+      <code class="code">plus1</code> to build <span class="emphasis"><em>plus5</em></span>+    </p><pre class="programlisting">+module Plus5 where++import Plus1Shallow+import AddFour++import ForSyDe (simulate)+import ForSyDe.Shallow++import Data.Int (Int32)++plus5 :: Signal Int32 -&gt; Signal Int32+plus5 = plus1 . signal . simulate addFourSysDef . fromSignal+    </pre><pre class="screen">+$ ghci Plus5.hs      +*Plus5&gt; plus5 (signal [1..10])+{6,7,8,9,10,11,12,13,14,15}+    </pre></div><div class="appendix" lang="en"><h2 class="title" style="clear: both"><a name="FSVec"></a>A. <code class="literal">FSVec</code>s: Vectors parameterized in size</h2><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1255404"></a>1. Goal</h3></div></div></div><p>+      We would like to numerically parameterize vectors using their+      length in order to implement fixed-sized vectors+      (<code class="code">FSVec</code>).  Ideally, we would like to be able to+      implement something similar to this:+      </p><pre class="programlisting">+v :: FSVec 23 Int -- Not Haskell	+      </pre><p>+	<code class="code">v</code> would be a a vector containing 23 <code class="code">Int</code>s. Note it+	is not possible to directly do this in Haskell.+      </p><p>+      The vector concatenation function would be something along the lines of:+      </p><pre class="programlisting">+(++) :: FSVec s1 a -&gt; FSVec s2 a -&gt; FSVec (s1+s2) a -- Again, not valid Haskell+      </pre><p>+	We would also like to establish static security constraints on+	functions. Those constrains would be checked at compile time+	guaranteeing a correct behaviour during runtime. For instance.+      </p><pre class="programlisting">+head :: FSVec  (s &gt; 0) a -&gt; FSVec (s - 1) a -- Not Haskell+      </pre><p>+	However, Haskell does not support dependent types (a numerically+	parameterized-vector is in practice a dependent type) nor type-level+	lambdas directly. Yet, it is still possible to implement our <code class="code">FSVec</code>+	type using Haskell plus a few GHC extensions.+      </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1255478"></a>2. How?</h3></div></div></div><p>+	Before diving into the details, let me spoil the final result:+      </p><pre class="programlisting">+v :: FSVec D23 Int++(++) :: (Nat s1, Nat s2, Add s1 s2 s3) =&gt; FSVec s1 a -&gt; FSVec s2 a -&gt; FSVec s3 a++head :: Pos s =&gt; FSVec s a -&gt; a+      </pre><p>+	The code is a bit more verbose that the pseudo-Haskell code of+	previous section, but note that <span class="strong"><strong>it+	is</strong></span> Haskell code (using the Multiparameter class+	extension).+      </p><p>+	The trick is to emulate the parameters using type-level decimal+	numerals. But, What is that?+      </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1255502"></a>3. Type-level decimal numerals</h3></div></div></div><p>+	We already mentioned that the trick is to use types to represent the size of+	the vector. So, we want a type parameter to represent a number, but, How?+      </p><pre class="programlisting">+-- Numerical digits+data D0 -- empty type (supported by a EmptyDataDecls GHC extension, +        --             we could have included a phony constructor otherwise)+data D1+data D2+..+data D9++data a :* b -- connective to build multidigit numerals (empty again)+            -- note that the type constructor is infix (GHC TypeOperators extension)+      </pre><p>+	Using the definitions above we can represent arbitrarily-sized natural+	numbers. Some examples:+      </p><div class="segmentedlist"><table border="0"><thead><tr class="segtitle"><th>Number</th><th>Type-level representation</th></tr></thead><tbody><tr class="seglistitem"><td class="seg">0</td><td class="seg"><code class="code">D0</code></td></tr><tr class="seglistitem"><td class="seg">13</td><td class="seg"><code class="code">D1 :* D3</code></td></tr><tr class="seglistitem"><td class="seg">1024</td><td class="seg"><code class="code">D1 :* D0 :* D2 :* D4</code></td></tr></tbody></table></div><p>+	It seems sensible, but very verbose. It would certainly be nicer to be+	able to express 0 as <code class="code">D0</code>, 13 as <code class="code">D13</code> and so on.+      </p><p>+	We solved the problem by using Template Haskell to generate+	type synonyms (aliases) up to <code class="code">D5000</code>. The same+	trick was used to emulate binaries (up to+	<code class="code">B10000000000</code>), octals (up to <code class="code">O10000</code>)+	and hexadecimals (up to <code class="code">H1000</code>):+      </p><pre class="screen">+$ ghci -XTypeOperators  -XFlexibleContexts # Extensions used in different parts of this appendix+Prelude&gt; :m +Data.TypeLevel+Prelude Data.TypeLevel&gt; :i D124+type D124 = (D1 :* D2) :* D4+       -- Defined in Data.TypeLevel.Num.Aliases+Prelude Data.TypeLevel&gt; :i HFF+type HFF = (D2 :* D5) :* D5+       -- Defined in Data.TypeLevel.Num.Aliases+Prelude Data.TypeLevel&gt; :i B101+type B101 = D5  -- Defined in Data.TypeLevel.Num.Aliases+	</pre><p>+	  Of course, if you want to use a numeral which is out of the+	  aliases range, the only option is to use the verbose decimal+	  representation (it shouldn't be the normal case though)+	</p><p>+	  Similarly to <code class="code">D13</code>, <code class="code">D124</code> ...+	  undercase value-level aliases (<code class="code">d12</code>,+	  <code class="code">d123</code>, .. declared as <code class="code">undefined</code>)+	  are generated in order to create type-level values.+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; :i d123+d123 :: (D1 :* D2) :* D3        -- Defined in Data.TypeLevel.Num.Aliases+	</pre><p>+	  Fair enough. However, you might already have guessed that+	  <code class="code">:*</code> can be used to construct ambiguous or+	  not-normalized numerals, for instance:+	</p><pre class="programlisting">+D0 :* D0 :* D1 -- numeral with trailing zeros+(D1 :* D0) :* (D2 :* D2) -- malformed numeral+	</pre><p>	+	  Now is when the natural (<code class="code">Nat</code>) and positive+	  (<code class="code">Pos</code>) type-classes get in the game. We are+	  going to omit the instances but, trust us, they guarantee+	  that numerals are well-formed:+	</p><pre class="programlisting">+class Nat n where+ toNum :: Num a =&gt; n -&gt; a++class Nat n =&gt; Pos n+	</pre><p>+	  <code class="code">toNum</code> allows to pass the type-level numeral to value-level.+	</p><pre class="screen"> +Prelude Data.TypeLevel&gt; toNum d123+123+-- a non-normalized numeral+Prelude Data.TypeLevel&gt; toNum (undefined :: D0 :* D1)+&lt;interactive&gt;:1:0:+   No instance for (Data.TypeLevel.Num.Sets.PosI D0)+     arising from a use of `toNum' at &lt;interactive&gt;:1:0-28+   Possible fix:+     add an instance declaration for (Data.TypeLevel.Num.Sets.PosI D0)+   In the expression: toNum (undefined :: D0 :* D1)+   In the definition of `it': it = toNum (undefined :: D0 :* D1)	  +	</pre><p>+	  Based on the numerical representation we created, and using+	  multiparameter type-classes, we can define type-level+	  operations. The operations supported right now are:+	</p><div class="itemizedlist"><ul type="disc"><li><p>+	      Arithmetic: Successor, Predecesor, Addition,+	      Subtraction, Multiplication, Division, Modulus, Greatest+	      Common Divisor, Exponentiation and Logarithm.+	    </p></li><li><p>+	      Comparison: trichotomy classification, (&lt;), (&gt;) (&lt;=),+	      (&gt;=), (==), Minimum and Maximum.+	    </p></li></ul></div><p>+	  Some examples:+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; :i Data.TypeLevel.divMod+Data.TypeLevel.divMod :: (DivMod x y q r) =&gt; x -&gt; y -&gt; (q, r)+       -- Defined in Data.TypeLevel.Num.Ops+Prelude Data.TypeLevel&gt; d23 `Data.TypeLevel.divMod` d2+(11,1)+	</pre><p>+	  Note that the resulting type is calculated at compile time:+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; :t d23 `Data.TypeLevel.divMod` d2+d23 `Data.TypeLevel.divMod` d2 :: (D1 :* D1, D1)+d23 `Data.TypeLevel.divMod` d2 :: (D1 :* D1, D1)+	</pre><p>+	  Note as well that the operations are consistent, we cannot, for+	  instance, calculate the predecessor of zero:+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; Data.TypeLevel.pred d0++&lt;interactive&gt;:1:0:+   No instances for (Data.TypeLevel.Num.Ops.Failure+                       (Data.TypeLevel.Num.Ops.PredecessorOfZeroError x),+[..]+	</pre><p>+	  We can even add constraints to our own functions. For instance, we+	  want to guarantee (at compilation time) that a type-level+	  numeral number is lower than 6 and greater than 3.+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; let check :: (Nat x, x :&lt;: D6, x :;&gt;: D3, Num a) =&gt; x -&gt; a; check n = toNum n+	</pre><p>+	  For example, 2 does not meet the constraints.+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; check d2+&lt;interactive&gt;:1:0:+   Couldn't match expected type `CGT' against inferred type `CLT'+[..]+	 </pre><p>+	   Whereas 4 does+	 </p><pre class="screen">+Prelude Data.TypeLevel&gt; check d4+4+	 </pre></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1255520"></a>4. Fixed Sized Vectors themselves</h3></div></div></div><p>+	  Getting back to fixed-sized vectors themselves, FSVec offers+	  a <a class="ulink" href="http://hackage.haskell.org/packages/archive/parameterized-data/0.1.2/doc/html/Data-Param-FSVec.html" target="_top">reasonably+	  rich vector API</a> based on type-level numerals.+	</p><p>+	  For example, we can safely access the elements of a vector+	  without the risk of getting+	  <span class="emphasis"><em>out-of-bounds</em></span> errors. +	</p><pre class="programlisting">+(!) :: (Pos s, Nat i, i :&lt;: s) =&gt; FSVec s a -&gt; i -&gt; a+	</pre><p>+	  The best part of it is that the bound checks are performed+	  on the type level at compilation time, not adding any+	  overhead to the execution of our code.+	</p><pre class="screen">+Prelude Data.TypeLevel&gt; :m +Data.Param.FSVec+Prelude Data.TypeLevel Data.Param.FSVec&gt;  $(vectorTH [1::Int,2,3]) ! d0+1+Prelude Data.TypeLevel Data.Param.FSVec&gt;  $(vectorTH [1::Int,2,3]) ! d7+&lt;interactive&gt;:1:0:+    Couldn't match expected type `LT' against inferred type `GT'+    When using functional dependencies to combine+      Trich D7 D3 GT,  +      [..]+	</pre><p>+	  <code class="code">vectorTH</code> is a Template Haskell function to+	  create vectors out of lists, we will get back to why TH is+	  needed later. <code class="code">d0</code> and <code class="code">d7</code> are+	  declared as <code class="code">undefined</code> (bottom) and force the+	  inference of the <code class="code">D0</code> and <code class="code">D7</code>+	  type-level values.  Note that the explicit type signatures+	  are needed due to Haskell's monomorphism restriction, in the+	  general non-interactive code does not need this kind of type+	  annotations.+	</p><div class="warning" style="margin-left: 0.5in; margin-right: 0.5in;"><h3 class="title">Warning</h3>+	 Using numerical literals instead of the+	 <code class="code">undefined</code> values (e.g. 0 and 7 instead of+	 <code class="code">d0</code> and <code class="code">d7</code>) is a very common error.+	</div><p>+	  Here are two further examples using <code class="code">head</code>.+	</p><pre class="screen">+Prelude Data.TypeLevel Data.Param.FSVec&gt; Data.Param.FSVec.head $(vectorTH [1::Int,2,3])+1+Prelude Data.TypeLevel Data.Param.FSVec&gt; Data.Param.FSVec.head empty++&lt;interactive&gt;:1:0:+    No instance for (Data.TypeLevel.Num.Sets.PosI D0)+      arising from a use of `Data.Param.FSVec.head'+	</pre><p>+	  Again, attempting to obtain the head of an empty vector triggers a compile-time error.+	</p><p>+	  Even if FSVec offers many nice features, it also has a few problems.+	</p></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id1255822"></a>5. <code class="code">FSVec</code> issues</h3></div></div></div><div class="orderedlist"><ol type="1"><li><p>+	      Some functions such as <code class="code">filter</code> cannot be+	      implemented. One can think about something along the+	      lines of:+	    </p><pre class="programlisting">+filter :: (a -&gt; Bool) -&gt; FSVec s a -&gt; FSVec s2 a+	    </pre><p>+	      However, the size of the output vector (<code class="code">s2</code>) cannot be precalculated+	      statically.+	    </p></li><li><p>+	      Since <code class="code">FSVec</code> is an abstract data type,+	      pattern matching is lost, but that is the general case+	      in vector implementations+	      <sup>[<a name="id1255999" href="#ftn.id1255999" class="footnote">9</a>]</sup>.+	    </p></li><li><p>+	      It is difficult to build a vector from a list. Again, the first thing one would+	      think of would be+	    </p><pre class="programlisting">  +vector :: Nat s =&gt; [a] -&gt; FSVec s a+	    </pre><p>+	      However, since <code class="code">s</code> would be a different type+	      depending on the length of <code class="code">[a]</code>, this is not+	      a valid Haskell function.  <code class="code">s</code> is+	      existentially quantified, a feature not supported+	      directly by Haskell98.+	    </p><p>+	      In addition, since the list-length is a run-time+	      condition, it is impossible to guess at compile+	      time.+	    </p><p>+	      However, there are a few workarounds which are already+	      included in the library:+	    </p><div class="orderedlist"><ol type="a"><li><p>+		  As suggested in Eaton's <a class="ulink" href="http://ofb.net/~frederik/vectro/draft-r2.pdf" target="_top">Statically+		  Typed Linear Algebra in Haskell</a>, emulate an+		  existential through <a class="ulink" href="http://en.wikibooks.org/wiki/Haskell/Continuation_passing_style" target="_top">CPS</a>+		  (Continuation passing style). CPS is a style of+		  programming where functions never return values, but+		  instead take an extra parameter which they give+		  their result to.+		</p><pre class="programlisting">+vectorCPS :: Nat s =&gt; vectorCPS :: [a] -&gt; (forall s. Nat s =&gt; FSVec s a -&gt; w) -&gt; w+		</pre><p>+		  Note that the <code class="code">forall</code> keyword is due to  using Rank2 types +		  to emulate the existential. You don't+		  really need to understand how they work but just know to use+		  vectorCPS. Here is an example:+		</p><pre class="screen">+$ ghci+Prelude&gt; :m +Data.Param+Prelude Data.Param&gt; (vectorCPS [1,2,3,4]) Data.Param.length+4+		</pre><p>+		  Note that length is passed to the result of <code class="code">vectorCPS</code> and not the+		  other way around.+		</p></li><li><p>+		  Unsafely provide the length of the resulting vector:+		</p><pre class="programlisting">+unsafeVector :: Nat s =&gt; s -&gt; [a] -&gt; FSVec s a+		</pre><p>+		  <code class="code">unsafeVector</code> does not suffer the+		  "existential type" problem of <code class="code">vectorCPS</code>,+		  however it can happen that the dynamic length of the+		  list does not match the provided length (that is why the+		  function name has an "unsafe" prefix). Furthermore if+		  that is the case, we will only be able to know at+		  runtime.+		</p><pre class="programlisting">+Prelude Data.Param&gt; :m +Data.TypeLevel+Prelude Data.Param Data.TypeLevel&gt; unsafeVector d8 [1,2]+*** Exception: unsafeVector: dynamic/static length mismatch+Prelude Data.Param Data.TypeLevel&gt; unsafeVector d2 [1,2]+&lt;1,2&gt;+		</pre></li><li><p>+		  Template Haskell.+		</p><p>+		  This is the preferred solution. The only problem is that, of course,+		  the TH extension is required (but we already had that dependency in ForSyDe) and you+		  can only use it with lists which are available at compile time (which,+		  for the general case of ForSyDe designs should not be a problem).+		</p><pre class="screen">+$ ghci -XTemplateHaskell+Prelude&gt; :m +Data.Param+Prelude Data.Param&gt; $(vectorTH [1 :: Int,2,3,4])+Prelude Data.Param&gt; :t $(vectorTH [1 :: Int,2,3,4])+$(vectorTH [1 :: Int,2,3,4]) :: (Num t) =&gt; FSVec Data.TypeLevel.Num.Reps.D4 t+		</pre></li></ol></div></li></ol></div></div></div><div class="footnotes"><br><hr width="100" align="left"><div class="footnote"><p><sup>[<a name="ftn.id1251533" href="#id1251533" class="para">1</a>] </sup>ForSyDe has been tested to run+      successfully on Linux, OSX-Leopard-x86 and Windows when compiled+      under GHC version 6.8.2. Due to the massive number of instances+      automatically generated in ForSyDe, it is not recommended to use+      a higher version of GHC until <a class="ulink" href="http://hackage.haskell.org/trac/ghc/ticket/2328" target="_top">bug+      #2328</a> is fixed.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1251950" href="#id1251950" class="para">2</a>] </sup>The term combinational comes from+	Digital Circuit Theory. In the context of ForSyDe, a+	synchronous process is combinational, as opposed to+	sequential, if its outputs don't depend on the history of the+	input signals. That is, the process is stateless, all output+	values can only depend on the input values consumed in the+	same clock cycle.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1252412" href="#id1252412" class="para">3</a>] </sup>In the sense of+	belonging to any particular MoC</p></div><div class="footnote"><p><sup>[<a name="ftn.id1252502" href="#id1252502" class="para">4</a>] </sup>Current implementation is based on+	  <a class="ulink" href="http://www.cs.chalmers.se/~koen/Lava/" target="_top">Lava</a>'s+	  <a class="ulink" href="http://www.cs.chalmers.se/~koen/pubs/entry-asian99-lava.html" target="_top">Observable+	  Sharing</a>.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1253225" href="#id1253225" class="para">5</a>] </sup>More formally, a datatype with+		data constructors whose arity is zero in all+		cases.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1253310" href="#id1253310" class="para">6</a>] </sup>Based+		on the <a class="ulink" href="http://hackage.haskell.org/cgi-bin/hackage-scripts/package/th-lift" target="_top"><code class="code">th-lift</code></a>+		package</p></div><div class="footnote"><p><sup>[<a name="ftn.id1254317" href="#id1254317" class="para">7</a>] </sup>Again,+		consider an enumerated type to be an algebraic type+		whose data constructors all have arity+		zero.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1254337" href="#id1254337" class="para">8</a>] </sup>In practice, the upper limit is+		Haskell-compiler dependent. In the case of GHC,+		current limit is 62.</p></div><div class="footnote"><p><sup>[<a name="ftn.id1255999" href="#id1255999" class="para">9</a>] </sup>+		  We tried to implement pattern matching using the+		  <a class="ulink" href="http://www.haskell.org/ghc/dist/current/docs/users_guide/template-haskell.html#th-quasiquotation" target="_top">new+		  Quasiquoting mechanism in GHC</a> <a class="ulink" href="http://www.haskell.org/pipermail/template-haskell/2008-February/000655.html" target="_top">+		  without success</a>.+		</p></div></div></div></body></html>
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+ examples/ALU.hs view
@@ -0,0 +1,343 @@+{-# LANGUAGE TemplateHaskell #-}++-- The following example is designed as tutorial example for the paper.+--+-- It implements a simple ALU, which has the following modes+--   HH: out <- a AND b +--   HL: out <- a OR b +--   LH: (cout, out) <- ADD a b+--   LL: out <- shiftl a 0+--+-- The expressiveness of the compiler could be clearly improved, if the+-- higher-order function 'zipWith' that works on vectors would be synthesizable. +-- Check 'and4BitFun'!+--+-- We could improve the example even further, if we use enumeration types for the +-- multiplexer. So far I have not done it, but should only be a matter of time!+ +module ALU where++import ForSyDe+import Data.Bits+import Data.Param.FSVec+import Data.TypeLevel.Num.Reps+import Data.TypeLevel.Num.Aliases+++----- AND - 4 Bit++and4BitFun :: ProcFun (FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit)+and4BitFun = $(newProcFun [d| and4BitFun :: FSVec D4 Bit +                                         -> FSVec D4 Bit +                                         -> FSVec D4 Bit+                              --and4BitFun a b = Data.Param.FSVec.zipWith (.&.) a b +                              and4BitFun a b =  (a!d3 .&. b!d3) +> (a!d2 .&. b!d2) +> (a!d1 .&. b!d1) +> (a!d0 .&. b!d0) +> empty+                            |])+++and4BitProc :: Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit)+and4BitProc = zipWithSY "and4" and4BitFun+              ++and4BitSys :: SysDef (Signal (FSVec D4 Bit) +                   -> Signal (FSVec D4 Bit) +                   -> Signal (FSVec D4 Bit))+and4BitSys =  $(newSysDefTHName 'and4BitProc ["a", "b"] ["y"])++simAnd4Bit :: [FSVec D4 Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit]+simAnd4Bit = simulate and4BitSys++vhdlAnd4Bit = writeVHDL and4BitSys+++----- OR - 4 Bit++or4BitFun :: ProcFun (FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit)+or4BitFun = $(newProcFun [d| or4BitFun :: FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit+                              --or4BitFun a b = Data.Param.FSVec.zipWith (.&.) a b +                             or4BitFun a b =  (a!d3 .|. b!d3) +> (a!d2 .|. b!d2) +> (a!d1 .|. b!d1) +> (a!d0 .|. b!d0) +> empty+                            |])+++or4BitProc :: Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit)+or4BitProc = zipWithSY "or4" or4BitFun+              ++or4BitSys :: SysDef (Signal (FSVec D4 Bit) +                   -> Signal (FSVec D4 Bit) +                   -> Signal (FSVec D4 Bit))+or4BitSys =  $(newSysDefTHName 'or4BitProc ["a", "b"] ["y"])++simOr4Bit :: [FSVec D4 Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit]+simOr4Bit = simulate or4BitSys++vhdlOr4Bit = writeVHDL or4BitSys++----- Logical Shift Left++lslFun :: ProcFun (FSVec D4 Bit -> FSVec D4 Bit) +lslFun = $(newProcFun [d| lslFun :: FSVec D4 Bit -> FSVec D4 Bit+                          lslFun a = shiftl a L+                        |])++lslProc :: Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) +lslProc = mapSY "lsl" lslFun++lslSys :: SysDef (Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit))+lslSys = $(newSysDefTHName 'lslProc ["in"] ["out"])++simLsl :: [FSVec D4 Bit] -> [FSVec D4 Bit]+simLsl = simulate lslSys++vhdlLsl = writeVHDL lslSys++----- Mux 4/1 (no use of FSVec as input, only for selection)++mux41Fun :: ProcFun (FSVec D2 Bit +                  -> FSVec D4 Bit  +                  -> FSVec D4 Bit  +                  -> FSVec D4 Bit  +                  -> FSVec D4 Bit  +                  -> FSVec D4 Bit)+mux41Fun = $(newProcFun [d| mux41Fun :: FSVec D2 Bit +                                     -> FSVec D4 Bit  +                                     -> FSVec D4 Bit  +                                     -> FSVec D4 Bit  +                                     -> FSVec D4 Bit  +                                     -> FSVec D4 Bit+                            mux41Fun sel x3 x2 x1 x0 +                               = if sel == H +> H +> empty then+                                    x3+                                 else +                                    if sel == H +> L +> empty then+                                       x2+                                    else+                                       if sel == L +> H +> empty then +                                          x1+                                       else+                                          x0+                          |])++mux41Proc :: Signal (FSVec D2 Bit) -> Signal (FSVec D4 Bit) +          -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)  +          -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)+mux41Proc = zipWith5SY "mux41" mux41Fun++mux41Sys :: SysDef (Signal (FSVec D2 Bit) -> Signal (FSVec D4 Bit) +                 -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)  +                 -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit))+mux41Sys = $(newSysDefTHName 'mux41Proc ["sel", "d3", "d2", "d1", "d0"] ["out"])++simMux41 :: [FSVec D2 Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit] +         -> [FSVec D4 Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit]+simMux41 = simulate mux41Sys++vhdlMux41 = writeVHDL mux41Sys++----- Convert FSVector to Tuple (Size 4)++convFromFSVec4Fun :: ProcFun (FSVec D4 Bit -> (Bit, Bit, Bit, Bit))+convFromFSVec4Fun = $(newProcFun [d| convFromFSVec4Fun :: FSVec D4 Bit -> (Bit, Bit, Bit, Bit)+				     convFromFSVec4Fun v+                                       = (v!d3, v!d2, v!d1, v!d0)+                                   |])++convFromFSVec4Proc :: Signal (FSVec D4 Bit) -> (Signal Bit, Signal Bit, Signal Bit, Signal Bit)+convFromFSVec4Proc = (unzip4SY "unzip4" . mapSY "conv4" convFromFSVec4Fun)   ++convFromFSVec4Sys :: SysDef (Signal (FSVec D4 Bit) -> (Signal Bit, Signal Bit, Signal Bit, Signal Bit))+convFromFSVec4Sys = $(newSysDefTHName 'convFromFSVec4Proc ["vector4"] ["v3", "v2", "v1", "v0"])++simConvFromFSVec4 :: [FSVec D4 Bit] -> ([Bit], [Bit], [Bit], [Bit])+simConvFromFSVec4 = simulate convFromFSVec4Sys++vhdlConvFromFSVec4 =  writeVHDL convFromFSVec4Sys ++----- Convert To FSVector (Size 4)++convToFSVec4Fun :: ProcFun (Bit -> Bit -> Bit -> Bit -> FSVec D4 Bit)+convToFSVec4Fun = $(newProcFun [d| convToFSVec4Fun :: Bit -> Bit -> Bit -> Bit -> FSVec D4 Bit+                                   convToFSVec4Fun x3 x2 x1 x0 +                                      = x3 +> x2 +> x1 +> x0 +> empty |])++convToFSVec4Proc :: Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal (FSVec D4 Bit)+convToFSVec4Proc = zipWith4SY "toVector4" convToFSVec4Fun++convToFSVec4Sys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal (FSVec D4 Bit))+convToFSVec4Sys =  $(newSysDefTHName 'convToFSVec4Proc ["x3", "x2", "x1", "x0"] ["vec4"])++simConvToFSVec4 = simulate convToFSVec4Sys++vhdlConvToFSVec4 = writeVHDL convToFSVec4Sys++------ Full Adder++fullAddFun :: ProcFun (Bit -> Bit -> Bit -> (Bit, Bit))+fullAddFun = $(newProcFun [d|fullAddFun :: Bit -> Bit -> Bit -> (Bit, Bit)+                             -- I would like to use 'where'-clauses. Is this possible?+                             -- fullAddFun a b c_in = (c_out, sum)+                             --  where c_out = (a .&. b) .|. (a .&. c_in) .|. (b .&. c_in)+                             --        sum = (a `xor` b) `xor` c_in  |])+                             fullAddFun a b c_in = ((a .&. b) .|. (a .&. c_in) .|. (b .&. c_in),+						    (a `xor` b) `xor` c_in) |])++--fullAddProc :: Signal Bit -> Signal Bit -> Signal Bit -> Signal (Bit, Bit)+--fullAddProc = zipWith3SY "fulladd" fullAddFun+fullAddProc :: Signal Bit -> Signal Bit -> Signal Bit -> (Signal Bit, Signal Bit)+fullAddProc a b c_in = (unzipSY "unzipSY") $ (zipWith3SY "fulladd" fullAddFun a b c_in)++fullAddSys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit -> (Signal Bit, Signal Bit))+fullAddSys = $(newSysDefTHName 'fullAddProc ["a", "b", "c_in"] ["cout", "sum"])++simFullAdd :: [Bit] -> [Bit] -> [Bit] -> ([Bit], [Bit])+simFullAdd = simulate fullAddSys++--vhdlFullAdd = writeVHDL fullAddSys++a_in = [L,L,L,L,H,H,H,H]+b_in = [L,H,L,H,L,H,L,H]+c_in = [L,L,H,H,L,L,H,H]++------ 4-bit Adder Chain++fourBitAdder :: Signal Bit   -- C_IN+	     -> Signal Bit   -- A3+             -> Signal Bit   -- A2+             -> Signal Bit   -- A1+	     -> Signal Bit   -- A0+             -> Signal Bit   -- B3+	     -> Signal Bit   -- B2+	     -> Signal Bit   -- B1+	     -> Signal Bit   -- B0+	     -> (Signal Bit, -- C_OUT+	         Signal Bit, -- SUM3+	         Signal Bit, -- SUM2+	         Signal Bit, -- SUM1+	         Signal Bit) -- SUM0+fourBitAdder c_in a3 a2 a1 a0 b3 b2 b1 b0 +                = (c_out, sum3, sum2, sum1, sum0)+		  where (c_out, sum3) = (instantiate "add3" fullAddSys) a3 b3 c2+		        (c2, sum2)    = (instantiate "add2" fullAddSys) a2 b2 c1+		        (c1, sum1)    = (instantiate "add1" fullAddSys) a1 b1 c0+		        (c0, sum0)    = (instantiate "add0" fullAddSys) a0 b0 c_in++fourBitAdderSys :: SysDef (Signal Bit   -- C_IN+			-> Signal Bit   -- A3+			-> Signal Bit   -- A2+			-> Signal Bit   -- A1+			-> Signal Bit   -- A0+			-> Signal Bit   -- B3+			-> Signal Bit   -- B2+			-> Signal Bit   -- B1+			-> Signal Bit   -- B0+			-> (Signal Bit, -- C_OUT+			    Signal Bit, -- SUM3+			    Signal Bit, -- SUM2+			    Signal Bit, -- SUM1+			    Signal Bit)) -- SUM0 	+fourBitAdderSys = $(newSysDefTHName 'fourBitAdder ["C_IN", "A3", "A2", "A1", "A0",+                                             "B3", "B2", "B1", "B0"]+                                            ["C_OUT", "SUM3", "SUM2", "SUM1", "SUM0"])++simFourBitAdder = simulate fourBitAdderSys++vhdlFourBitAdder = writeVHDL fourBitAdderSys++a0 = [L,L,L,L,L,L,L,L,H,H,H,H,H,H,H,H]+a1 = [L,L,L,L,H,H,H,H,L,L,L,L,H,H,H,H]+a2 = [L,L,H,H,L,L,H,H,L,L,H,H,L,L,H,H]+a3 = [L,H,L,H,L,H,L,H,L,H,L,H,L,H,L,H]+zero = [L,L,L,L,L,L,L,L,L,L,L,L,L,L,L,L]+one = [H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H]+++simAdd_0 = simFourBitAdder zero a3 a2 a1 a0 a3 a2 a1 a0 +simAdd_1 = simFourBitAdder one a3 a2 a1 a0 a3 a2 a1 a0  +++----- FSVec Adder+add4FSVecProc :: Signal (FSVec D4 Bit)+              -> Signal (FSVec D4 Bit)+              -> (Signal Bit, Signal (FSVec D4 Bit))+add4FSVecProc a b = (cout, sum)+                    where+                       (a3,a2,a1,a0) = (instantiate "split_a" convFromFSVec4Sys) a+                       (b3,b2,b1,b0) = (instantiate "split_b" convFromFSVec4Sys) b +                       (cout, s3, s2, s1, s0) = (instantiate "adder" fourBitAdderSys) zero a3 a2 a1 a0 b3 b2 b1 b0                +                       sum = (instantiate "merge" convToFSVec4Sys) s3 s2 s1 s0+                       zero = instantiate "Zero" zeroSys          ++add4FSVecSys :: SysDef (Signal (FSVec D4 Bit)+              -> Signal (FSVec D4 Bit)+              -> (Signal Bit, Signal (FSVec D4 Bit)))+add4FSVecSys = $(newSysDefTHName 'add4FSVecProc ["a", "b"] ["cout", "sum"])++simAdd4FSVecSys = simulate add4FSVecSys++vhdlAdd4FSVecSys = writeVHDL add4FSVecSys++----- Constant Signals++-- Constant input 'H' modeled with constSY+oneProc :: Signal Bit+oneProc = constSY "high" H++oneSys :: SysDef (Signal Bit)+oneSys = $(newSysDefTHName 'oneProc [] ["one"])++-- Constant input 'L' modeled with constSY+zeroProc :: Signal Bit+zeroProc = constSY "low" L+ +zeroSys :: SysDef (Signal Bit)+zeroSys = $(newSysDefTHName 'zeroProc [] ["zero"])++----- ALU++aluProc :: Signal(FSVec D2 Bit) +        ->  Signal (FSVec D4 Bit)+        ->  Signal (FSVec D4 Bit)+        ->  (Signal Bit, Signal (FSVec D4 Bit))+aluProc sel a b = (cout, out)+                  where+                     andOut = (instantiate "and" and4BitSys) a b+                     orOut = (instantiate "or" or4BitSys) a b+                     (cout, sum) = (instantiate "add" add4FSVecSys) a b+                     lslOut = (instantiate "lsl" lslSys) a+                     out =  (instantiate "mux" mux41Sys) sel andOut orOut sum lslOut++                     ++aluSys :: SysDef (Signal(FSVec D2 Bit) +              ->  Signal (FSVec D4 Bit)+              ->  Signal (FSVec D4 Bit)+              ->  (Signal Bit, Signal (FSVec D4 Bit)))+aluSys = $(newSysDefTHName 'aluProc ["sel", "a", "b"] ["cout", "data"])+    ++simALU :: [FSVec D2 Bit] ->  [FSVec D4 Bit] -> [FSVec D4 Bit] -> ([Bit], [FSVec D4 Bit])+simALU = simulate aluSys++vhdlALU = writeVHDL aluSys+                                      ++----- Test-Inputs++sel = [reallyUnsafeVector [H,H], -- AND+       reallyUnsafeVector [H,L], -- OR+       reallyUnsafeVector [L,H], -- ADD+       reallyUnsafeVector [L,L]] -- LSL++a = [reallyUnsafeVector [L,H,H,H], -- LSB D1 D2 MSB+     reallyUnsafeVector [L,H,L,H],+     reallyUnsafeVector [H,H,H,H],+     reallyUnsafeVector [L,H,H,H]]++b = [reallyUnsafeVector [H,H,H,H],+     reallyUnsafeVector [H,H,L,H],+     reallyUnsafeVector [H,L,L,L], +     reallyUnsafeVector [H,H,H,H]]
+ examples/ALU_Shallow.hs view
@@ -0,0 +1,185 @@+{-# LANGUAGE TemplateHaskell #-}++-- *** Shallow-Embedded ForSyDe Model ***+--+-- The following example is designed as tutorial example for the paper.+--+-- It implements a simple ALU, which has the following modes+--   HH: out <- a AND b +--   HL: out <- a OR b +--   LH: (cout, out) <- ADD a b+--   LL: out <- shiftl a 0+--+ +module ALU_Shallow where++import ForSyDe.Shallow+import ForSyDe.Bit+import Data.Bits+import Data.Param.FSVec+import Data.TypeLevel.Num.Reps+import Data.TypeLevel.Num.Aliases++++----- AND - 4 Bit++and4Bit :: Signal (FSVec D4 Bit) +        -> Signal (FSVec D4 Bit) +        -> Signal (FSVec D4 Bit)+and4Bit = zipWithSY (Data.Param.FSVec.zipWith (.&.)) ++----- OR - 4 Bit++or4Bit :: Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit) +            -> Signal (FSVec D4 Bit)+or4Bit =  zipWithSY (Data.Param.FSVec.zipWith (.|.))++----- Logical Shift Left++++lsl :: Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) +lsl = mapSY shiftl_L where+         shiftl_L v = shiftl v L  ++----- Mux 4/1 (no use of FSVec as input, only for selection)++mux41Fun :: FSVec D2 Bit +            -> FSVec D4 Bit  +            -> FSVec D4 Bit  +            -> FSVec D4 Bit  +            -> FSVec D4 Bit  +            -> FSVec D4 Bit+mux41Fun sel x3 x2 x1 x0 = if sel == H +> H +> empty then+                              x3+                           else +                              if sel == H +> L +> empty then+                                 x2+                              else+                                 if sel == L +> H +> empty then +                                    x1+                                 else+                                    x0+                         ++mux41 :: Signal (FSVec D2 Bit) -> Signal (FSVec D4 Bit) +          -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)  +          -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)+mux41 = zipWith5SY mux41Fun++----- Convert FSVector to Tuple (Size 4)++convFromFSVec4 :: FSVec D4 a -> (a, a, a, a)+convFromFSVec4 v = (v!d3, v!d2, v!d1, v!d0)++----- Convert To FSVector (Size 4)++convToFSVec4 :: a -> a -> a -> a -> FSVec D4 a+convToFSVec4 x3 x2 x1 x0 = x3 +> x2 +> x1 +> x0 +> empty++----- 4-Bit Adder++------ 4-bit Adder Chain+++fourBitAdder :: Signal Bit   -- C_IN+	     -> Signal Bit   -- A3+             -> Signal Bit   -- A2+             -> Signal Bit   -- A1+	     -> Signal Bit   -- A0+             -> Signal Bit   -- B3+	     -> Signal Bit   -- B2+	     -> Signal Bit   -- B1+	     -> Signal Bit   -- B0+	     -> (Signal Bit, -- C_OUT+	         Signal Bit, -- SUM3+	         Signal Bit, -- SUM2+	         Signal Bit, -- SUM1+	         Signal Bit) -- SUM0+fourBitAdder c_in a3 a2 a1 a0 b3 b2 b1 b0 +                = (c_out, sum3, sum2, sum1, sum0)+		  where (c_out, sum3) = unzipSY $ zipWith3SY fullAdd a3 b3 c2+		        (c2, sum2)    = unzipSY $ zipWith3SY fullAdd a2 b2 c1+		        (c1, sum1)    = unzipSY $ zipWith3SY fullAdd a1 b1 c0+		        (c0, sum0)    = unzipSY $ zipWith3SY fullAdd a0 b0 c_in++fullAdd a b cin = (cout, sum) +                  where+                     cout = (a .&. b) .|. (a .&. cin) .|. (b .&. cin)+                     sum  = (a `xor` b) `xor` cin++----- FSVec Adder+add4FSVec :: Signal (FSVec D4 Bit)+          -> Signal (FSVec D4 Bit)+          -> (Signal Bit, Signal (FSVec D4 Bit))+add4FSVec a b = (cout, sum)+                 where+                    (a3,a2,a1,a0) = unzip4SY $ mapSY convFromFSVec4 a+                    (b3,b2,b1,b0) = unzip4SY $ mapSY convFromFSVec4 b +                    (cout, s3, s2, s1, s0) = fourBitAdder zero a3 a2 a1 a0 b3 b2 b1 b0                +                    sum = zipWith4SY convToFSVec4 s3 s2 s1 s0+                    zero = sourceSY id L         ++----- ALU++alu :: Signal(FSVec D2 Bit) +    -> Signal (FSVec D4 Bit)+    -> Signal (FSVec D4 Bit)+     ->  (Signal Bit, Signal (FSVec D4 Bit))+alu sel a b = (cout, out)+              where+                  andOut = and4Bit a b+                  orOut = or4Bit a b+                  (cout, sum) = add4FSVec a b+                  lslOut = lsl a+                  out = mux41 sel andOut orOut sum lslOut++                  ++----- Test-Inputs++sel = signal [reallyUnsafeVector [H,H], -- AND+       reallyUnsafeVector [H,L], -- OR+       reallyUnsafeVector [L,H], -- ADD+       reallyUnsafeVector [L,L]] -- LSL++a = signal [reallyUnsafeVector [L,H,H,H],+     reallyUnsafeVector [L,H,L,H],+     reallyUnsafeVector [L,H,H,H],+     reallyUnsafeVector [L,H,H,H]]++b = signal [reallyUnsafeVector [H,H,H,H],+     reallyUnsafeVector [H,H,L,H],+     reallyUnsafeVector [H,H,H,H],+     reallyUnsafeVector [H,H,H,H]]++c = signal [reallyUnsafeVector [L,L,L,L], -- LSB D1 D2 MSB+     reallyUnsafeVector [H,L,L,L],+     reallyUnsafeVector [L,L,L,H],+     reallyUnsafeVector [L,L,L,H]]++d = signal [reallyUnsafeVector [L,L,L,L],+     reallyUnsafeVector [L,L,L,L],+     reallyUnsafeVector [L,L,L,H],+     reallyUnsafeVector [H,H,H,H]]++x0 = signal [L,L,L,L]+x1 = signal [H,H,H,H]++-- Helper functions+zipWith5SY :: (a -> b -> c -> d -> e -> f) +           -> Signal a+           -> Signal b+           -> Signal c+           -> Signal d+           -> Signal e+           -> Signal f+zipWith5SY _ NullS _ _ _ _ = NullS+zipWith5SY _ _ NullS _ _ _ = NullS+zipWith5SY _ _ _ NullS _ _ = NullS+zipWith5SY _ _ _ _ NullS _ = NullS+zipWith5SY _ _ _ _ _ NullS = NullS+zipWith5SY f (a :- as) (b :- bs) (c :- cs)  (d :- ds) (e:-es) = + f a b c d e :- zipWith5SY f as bs cs ds es
+ examples/BitVector.hs view
@@ -0,0 +1,19 @@+{-# LANGUAGE TemplateHaskell #-}+-- example module to test bit conversion functions+module BitVector where++import ForSyDe+import Data.Int (Int32)+import Data.Param.FSVec+import Data.TypeLevel.Num (D32)++to32BitFun :: ProcFun (Int32 -> FSVec D32 Bit)+to32BitFun = $(newProcFun+ [d| to32Bit :: Int32 -> FSVec D32 Bit+     to32Bit i = toBitVector32 i |])++to32BitProc :: Signal Int32 -> Signal (FSVec D32 Bit)+to32BitProc = mapSY "to32Proc" to32BitFun ++to32BitSysDef :: SysDef (Signal Int32 -> Signal (FSVec D32 Bit))+to32BitSysDef = newSysDef to32BitProc "to32BitSys" ["in1"] ["out1"]
+ examples/ButtonEncoder.hs view
@@ -0,0 +1,43 @@+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-}++module ButtonEncoder where++import ForSyDe+import Language.Haskell.TH.Lift+import Data.Generics (Data, Typeable)+import Prelude hiding (Either(..))++-- Combinational syncrhonous system to encode the keypresses of+-- an arrow-keypad into directions which are easier to process+-- +-- This example shows how the VHDL backend can process custom Enumerated+-- Algebraic types (ie. Algebraic types whose data constructors have all+-- zero arity)+++data Direction = Up | Down | Left | Right | Unknown+ deriving (Data, Typeable, Show, Eq)++$(deriveLift1 ''Direction)++type ButtonPress = (Bit, -- is left pressed +                    Bit, -- is right pressed+                    Bit, -- is up pressed  +                    Bit) -- is down pressed++buttonEncoder :: Signal ButtonPress -> Signal Direction  +buttonEncoder = mapSY "encoder" transFun+  where transFun = +           $(newProcFun [d| transFun (left,right,up,down) =+                               if left  == H then Left else+                                if right == H then Right else+                                 if up == H then Up else+                                  if down == H then Down else Unknown |])++buttonEncoderSys :: SysDef (Signal ButtonPress -> Signal Direction)+buttonEncoderSys = $(newSysDefTHName 'buttonEncoder ["buttonPress"] ["direction"])+++simButtonEncoder :: [ButtonPress] -> [Direction]+simButtonEncoder = simulate buttonEncoderSys+
+ examples/CarrySelectAdder.hs view
@@ -0,0 +1,386 @@+{-# LANGUAGE TemplateHaskell #-}++-- This module models a 16-bit carry select adder+++module CarrySelectAdder where++import ForSyDe     -- Definition of Bit data type+import Data.Bits   -- Operations for Bit data type+import Data.Param.FSVec+import Data.TypeLevel.Num.Reps+import Data.TypeLevel.Num.Aliases++-- First we create a four bit carry select adder.+-- It uses eight full adders and five 2/1 muxes.++------ Full Adder++fullAddFun :: ProcFun (Bit -> Bit -> Bit -> (Bit, Bit))+fullAddFun = $(newProcFun [d|fullAddFun :: Bit -> Bit -> Bit -> (Bit, Bit)+                             -- I would like to use 'where'-clauses. Is this possible?+                             -- fullAddFun a b c_in = (c_out, sum)+                             --  where c_out = (a .&. b) .|. (a .&. c_in) .|. (b .&. c_in)+                             --        sum = (a `xor` b) `xor` c_in  |])+                             fullAddFun a b c_in = ((a .&. b) .|. (a .&. c_in) .|. (b .&. c_in),+						    (a `xor` b) `xor` c_in) |])++--fullAddProc :: Signal Bit -> Signal Bit -> Signal Bit -> Signal (Bit, Bit)+--fullAddProc = zipWith3SY "fulladd" fullAddFun+fullAddProc :: Signal Bit -> Signal Bit -> Signal Bit -> (Signal Bit, Signal Bit)+fullAddProc a b c_in = (unzipSY "unzipSY") $ (zipWith3SY "fulladd" fullAddFun a b c_in)++fullAddSys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit -> (Signal Bit, Signal Bit))+fullAddSys = $(newSysDefTHName 'fullAddProc ["a", "b", "c_in"] ["cout", "sum"])++simFullAdd :: [Bit] -> [Bit] -> [Bit] -> ([Bit], [Bit])+simFullAdd = simulate fullAddSys++--vhdlFullAdd = writeVHDL fullAddSys++a_in = [L,L,L,L,H,H,H,H]+b_in = [L,H,L,H,L,H,L,H]+c_in = [L,L,H,H,L,L,H,H]+++------ 2/1 Multiplexer++--mux21Fun :: ProcFun (Bit -> Bit -> Bit -> Bit)+--mux21Fun = $(newProcFun [d|mux21Fun :: Bit -> Bit -> Bit -> Bit+--                           mux21Fun sel d1 d0 = if (sel == L) then+--                                                   d0+--                                                else+--                                                   d1 |])++mux21Proc :: Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit+mux21Proc = zipWith3SY "mux21" mux21Fun++mux21Sys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit)+mux21Sys = $(newSysDefTHName 'mux21Proc ["sel", "d1", "d0"] ["out"])++simMux21 :: [Bit] -> [Bit] -> [Bit] -> [Bit]+simMux21 = simulate mux21Sys++vhdlMux21 = writeVHDL mux21Sys++------ 4-bit Adder Chain++fourBitAdder :: Signal Bit   -- C_IN+	     -> Signal Bit   -- A3+             -> Signal Bit   -- A2+             -> Signal Bit   -- A1+	     -> Signal Bit   -- A0+             -> Signal Bit   -- B3+	     -> Signal Bit   -- B2+	     -> Signal Bit   -- B1+	     -> Signal Bit   -- B0+	     -> (Signal Bit, -- C_OUT+	         Signal Bit, -- SUM3+	         Signal Bit, -- SUM2+	         Signal Bit, -- SUM1+	         Signal Bit) -- SUM0+fourBitAdder c_in a3 a2 a1 a0 b3 b2 b1 b0 +                = (c_out, sum3, sum2, sum1, sum0)+		  where (c_out, sum3) = (instantiate "add3" fullAddSys) a3 b3 c2+		        (c2, sum2)    = (instantiate "add2" fullAddSys) a2 b2 c1+		        (c1, sum1)    = (instantiate "add1" fullAddSys) a1 b1 c0+		        (c0, sum0)    = (instantiate "add0" fullAddSys) a0 b0 c_in++fourBitAdderSys :: SysDef (Signal Bit   -- C_IN+			-> Signal Bit   -- A3+			-> Signal Bit   -- A2+			-> Signal Bit   -- A1+			-> Signal Bit   -- A0+			-> Signal Bit   -- B3+			-> Signal Bit   -- B2+			-> Signal Bit   -- B1+			-> Signal Bit   -- B0+			-> (Signal Bit, -- C_OUT+			    Signal Bit, -- SUM3+			    Signal Bit, -- SUM2+			    Signal Bit, -- SUM1+			    Signal Bit)) -- SUM0 	+fourBitAdderSys = $(newSysDefTHName 'fourBitAdder ["C_IN", "A3", "A2", "A1", "A0",+                                             "B3", "B2", "B1", "B0"]+                                            ["C_OUT", "SUM3", "SUM2", "SUM1", "SUM0"])++simFourBitAdder = simulate fourBitAdderSys++vhdlFourBitAdder = writeVHDL fourBitAdderSys++a0 = [L,L,L,L,L,L,L,L,H,H,H,H,H,H,H,H]+a1 = [L,L,L,L,H,H,H,H,L,L,L,L,H,H,H,H]+a2 = [L,L,H,H,L,L,H,H,L,L,H,H,L,L,H,H]+a3 = [L,H,L,H,L,H,L,H,L,H,L,H,L,H,L,H]+zero = [L,L,L,L,L,L,L,L,L,L,L,L,L,L,L,L]+one = [H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H]+++simAdd_0 = simFourBitAdder zero a3 a2 a1 a0 a3 a2 a1 a0 +simAdd_1 = simFourBitAdder one a3 a2 a1 a0 a3 a2 a1 a0  ++----- fourBitCarrySelectAdder+++fourBitCSAdder :: Signal Bit   -- C_IN+	       -> Signal Bit   -- A3+               -> Signal Bit   -- A2+               -> Signal Bit   -- A1+	       -> Signal Bit   -- A0+               -> Signal Bit   -- B3+	       -> Signal Bit   -- B2+	       -> Signal Bit   -- B1+	       -> Signal Bit   -- B0+	       -> (Signal Bit, -- C_OUT+	          Signal Bit, -- SUM3+	          Signal Bit, -- SUM2+	          Signal Bit, -- SUM1+	          Signal Bit) -- SUM0fourBitCSAdder :: +fourBitCSAdder c_in a3 a2 a1 a0 b3 b2 b1 b0+               = (c_out, sum3, sum2, sum1, sum0)+                 where c_out = (instantiate "mux4" mux21Sys) c_in c_out_1 c_out_0+                       sum3  = (instantiate "mux3" mux21Sys) c_in sum3_1 sum3_0+                       sum2  = (instantiate "mux2" mux21Sys) c_in sum2_1 sum2_0+                       sum1  = (instantiate "mux1" mux21Sys) c_in sum1_1 sum1_0 +                       sum0  = (instantiate "mux0" mux21Sys) c_in sum0_1 sum0_0+                       (c_out_1, sum3_1, sum2_1, sum1_1, sum0_1) +                             = (instantiate "Adder_1" fourBitAdderSys) +                                one a3 a2 a1 a0 b3 b2 b1 b0+                       (c_out_0, sum3_0, sum2_0, sum1_0, sum0_0) +                             = (instantiate "Adder_1" fourBitAdderSys) +                                zero a3 a2 a1 a0 b3 b2 b1 b0+                       one = instantiate "One" oneSys+                       zero = instantiate "Zero" zeroSys++fourBitCSAdderSys = $(newSysDefTHName 'fourBitCSAdder ["C_IN", "A3", "A2", "A1", "A0",+                                             "B3", "B2", "B1", "B0"]+                                            ["C_OUT", "SUM3", "SUM2", "SUM1", "SUM0"])+++simFourBitCSAdder = simulate fourBitCSAdderSys++vhdlFourBitCSAdder = writeVHDL fourBitCSAdderSys+                           +simCSAdd_0 = simFourBitAdder zero a3 a2 a1 a0 a3 a2 a1 a0 +simCSAdd_1 = simFourBitAdder one a3 a2 a1 a0 a3 a2 a1 a0  ++----- Convert Output to FSVec++convertToFSVec5 :: a -> a -> a -> a -> a -> FSVec D5 a+convertToFSVec5 x4 x3 x2 x1 x0 = x4 +> x3 +> x2 +> x1 +> (singleton x0)++convOutput :: ProcFun (Bit -> Bit -> Bit -> Bit -> Bit -> FSVec D5 Bit)+convOutput = $(newProcFun [d|convOutput :: Bit -> Bit -> Bit -> Bit -> Bit -> FSVec D5 Bit+                             convOutput x4 x3 x2 x1 x0 +                                    = convertToFSVec5 x4 x3 x2 x1 x0 |])++convOutputProc :: Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal (FSVec D5 Bit)+convOutputProc = zipWith5SY "toVector5" convOutput++convOutputSys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal Bit -> Signal (FSVec D5 Bit))+convOutputSys =  $(newSysDefTHName 'convOutputProc ["x4", "x3", "x2", "x1", "x0"] ["vec5"])++fourBitCSAdder' :: Signal Bit   -- C_IN+	        -> Signal Bit   -- A3+                -> Signal Bit   -- A2+                -> Signal Bit   -- A1+	        -> Signal Bit   -- A0+                -> Signal Bit   -- B3+	        -> Signal Bit   -- B2+	        -> Signal Bit   -- B1+	        -> Signal Bit   -- B0+	        -> Signal (FSVec D5 Bit) -- <C_OUT, SUM3, SUM2, SUM1, SUM0>+fourBitCSAdder' c_in a3 a2 a1 a0 b3 b2 b1 b0 = out5+               where+                  out5 = (instantiate "toVector5" convOutputSys) c_out sum3 sum2 sum1 sum0+                  (c_out, sum3, sum2, sum1, sum0) = (instantiate "Adder" fourBitCSAdderSys) c_in a3 a2 a1 a0 b3 b2 b1 b0  ++fourBitCSAdderSys2 :: SysDef (Signal Bit   -- C_IN+	        -> Signal Bit   -- A3+                -> Signal Bit   -- A2+                -> Signal Bit   -- A1+	        -> Signal Bit   -- A0+                -> Signal Bit   -- B3+	        -> Signal Bit   -- B2+	        -> Signal Bit   -- B1+	        -> Signal Bit   -- B0+	        -> Signal (FSVec D5 Bit))+fourBitCSAdderSys2 = $(newSysDefTHName 'fourBitCSAdder' ["C_IN", "A3", "A2", "A1", "A0",+                                             "B3", "B2", "B1", "B0"]+                                            ["vect5"])++simFourBitCSAdder2 = simulate fourBitCSAdderSys2++vhdlFourBitCSAdder2 = writeVHDL fourBitCSAdderSys2++simCSAdd_0' = simFourBitCSAdder2 zero a3 a2 a1 a0 a3 a2 a1 a0 +simCSAdd_1' = simFourBitCSAdder2 one a3 a2 a1 a0 a3 a2 a1 a0  +++----- Four Bit Adder +--+-- The four bit adder is modelled as a set of equations. +-- It uses fixed-size vectors for the 4-bit input and output values.++adder4BitFun :: ProcFun (Bit -> FSVec D4 Bit -> FSVec D4 Bit -> (Bit, FSVec D4 Bit))+adder4BitFun = $(newProcFun [d|adder4BitFun :: Bit -> FSVec D4 Bit -> FSVec D4 Bit -> (Bit, FSVec D4 Bit)+                               adder4BitFun cin a b = (cout, sum) where+                                  cout = (a!d3 .&. b!d3) .|. (a!d3 .&. c2) .|. (b!d3 .&. c2)+                                  c2 = (a!d2 .&. b!d2) .|. (a!d2 .&. c1) .|. (b!d2 .&. c1)+                                  c1 = (a!d1 .&. b!d1) .|. (a!d1 .&. c0) .|. (b!d1 .&. c0)+                                  c0 = (a!d0 .&. b!d0) .|. (a!d0 .&. cin) .|. (b!d0 .&. cin)+                                  s3 = (a!d3 `xor` b!d3) `xor` c2+                                  s2 = (a!d2 `xor` b!d2) `xor` c1+                                  s1 = (a!d1 `xor` b!d1) `xor` c0+                                  s0 = (a!d0 `xor` b!d0) `xor` cin+                                  sum = s0 +> s1 +> s2 +> s3 +> empty |])++adder4BitProc :: Signal Bit -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> (Signal Bit, Signal (FSVec D4 Bit))+adder4BitProc cin a b = (unzipSY "unzip") $ (zipWith3SY "4BitAdder" adder4BitFun cin a b)++adder4BitSys :: SysDef (Signal Bit -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> (Signal Bit, Signal (FSVec D4 Bit)))+adder4BitSys = $(newSysDefTHName 'adder4BitProc ["cin", "a", "b"] ["cout", "sum"])++simAdder4Bit = simulate adder4BitSys++vhdlAdder4Bit = writeVHDL adder4BitSys++----- 4-Bit 2/1 Multiplexer+--+-- The multiplexer uses fixed size vectors for input and output values.++mux21Fun :: ProcFun (Bit -> a -> a -> a)+mux21Fun = $(newProcFun [d|mux21Fun :: Bit -> a -> a -> a+                           mux21Fun sel d1 d0 = if (sel == L) then+                                                   d0+                                                else+                                                   d1 |])++mux21_4BitProc :: Signal Bit -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit)+mux21_4BitProc = zipWith3SY "mux21" mux21Fun++mux21_4BitSys :: SysDef (Signal Bit -> Signal ( FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit))+mux21_4BitSys = $(newSysDefTHName 'mux21_4BitProc ["sel", "d1", "d0"] ["out"])++simMux21_4Bit :: [Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit] -> [FSVec D4 Bit]+simMux21_4Bit = simulate mux21_4BitSys++vhdlMux21_4Bit = writeVHDL mux21_4BitSys+++----- 4-Bit Carry Select Adder++-- The carry select adder has two input that are connected to 'H' or 'L' respectively++-- Constant input 'H' modeled with constSY+oneProc :: Signal Bit+oneProc = constSY "high" H++oneSys :: SysDef (Signal Bit)+oneSys = $(newSysDefTHName 'oneProc [] ["one"])++-- Constant input 'L' modeled with constSY+zeroProc :: Signal Bit+zeroProc = constSY "low" L+ +zeroSys :: SysDef (Signal Bit)+zeroSys = $(newSysDefTHName 'zeroProc [] ["zero"])++-- The 4-Bit carry select adder is implemented as a composition of components+csAdder4BitProc :: Signal Bit -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> (Signal Bit, Signal (FSVec D4 Bit))+csAdder4BitProc cin a b = (cout, sum) where+                          cout = (instantiate "mux" mux21Sys) cin cout_1 cout_0+                          sum = (instantiate "mux4Bit" mux21_4BitSys) cin sum_1 sum_0+                          (cout_1, sum_1) = (instantiate "adder1" adder4BitSys) one a b+                          (cout_0, sum_0) = (instantiate "adder0" adder4BitSys) zero a b                  +                          one = instantiate "One" oneSys+                          zero = instantiate "Zero" zeroSys+                           +csAdder4BitSys :: SysDef (Signal Bit -> Signal (FSVec D4 Bit) -> Signal (FSVec D4 Bit) -> (Signal Bit, Signal (FSVec D4 Bit)))+csAdder4BitSys = $(newSysDefTHName 'csAdder4BitProc ["cin", "a", "b"] ["cout", "sum"])++simCSAdder4Bit = simulate csAdder4BitSys++vhdlCSAdder4Bit = writeVHDL csAdder4BitSys++----- 16 Bit Adder++csAdder16BitProc :: Signal (FSVec D16 Bit) -> Signal (FSVec D16 Bit) -> (Signal Bit, Signal (FSVec D16 Bit))+csAdder16BitProc a b = (cout, sum) where+                       sum = zipWith4SY "concat4" concat4Fun sum3_0 sum7_4 sum11_8 sum15_12+                       (cout, sum15_12) = (instantiate "csadder3" csAdder4BitSys) c11 a15_12 b15_12+                       (c11, sum11_8) = (instantiate "csadder2" csAdder4BitSys) c7 a11_8 b11_8+                       (c7, sum7_4) = (instantiate "csadder3" csAdder4BitSys) c3 a7_4 b7_4+                       (c3, sum3_0) = (instantiate "csadder3" csAdder4BitSys) zero a3_0 b3_0+                       a15_12 = mapSY "a15_12" select15_12Fun a+                       a11_8  = mapSY "a11_8"  select11_8Fun a+                       a7_4   = mapSY "a7_4"   select7_4Fun a+                       a3_0   = mapSY "a3_0"   select3_0Fun a+                       b15_12 = mapSY "b15_12" select15_12Fun b+                       b11_8  = mapSY "b11_8"  select11_8Fun b+                       b7_4   = mapSY "b7_4"   select7_4Fun b+                       b3_0   = mapSY "b3 _0"  select3_0Fun b+                       zero = instantiate "Zero" zeroSys         +++csAdder16BitSys = $(newSysDefTHName 'csAdder16BitProc ["a", "b"] ["cout", "sum"])++simCSAdder16Bit = simulate csAdder16BitSys++vhdlCSAdder16Bit = writeVHDL csAdder16BitSys++-- Helper functions++select15_12Fun :: ProcFun (FSVec D16 Bit -> FSVec D4 Bit)+select15_12Fun = $(newProcFun [d|select15_12 :: FSVec D16 Bit -> FSVec D4 Bit+                                 select15_12 v = select d12 d1 d4 v |])++select11_8Fun :: ProcFun (FSVec D16 Bit -> FSVec D4 Bit)+select11_8Fun = $(newProcFun [d|select11_8 :: FSVec D16 Bit -> FSVec D4 Bit+                                select11_8 v = select d8 d1 d4 v |])++select7_4Fun :: ProcFun (FSVec D16 Bit -> FSVec D4 Bit)+select7_4Fun = $(newProcFun [d|select7_4 :: FSVec D16 Bit -> FSVec D4 Bit+                               select7_4 v = select d4 d1 d4 v |])++select3_0Fun :: ProcFun (FSVec D16 Bit -> FSVec D4 Bit)+select3_0Fun = $(newProcFun [d|select3_0 :: FSVec D16 Bit -> FSVec D4 Bit+                               select3_0 v = select d0 d1 d4 v |])++concat4Fun :: ProcFun (FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit -> FSVec D16 Bit)+concat4Fun = $(newProcFun [d|concat4Fun :: FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit -> FSVec D4 Bit -> FSVec D16 Bit+                             concat4Fun v1 v2 v3 v4 = v1 Data.Param.FSVec.++ +                                                      v2 Data.Param.FSVec.++ +                                                      v3 Data.Param.FSVec.++ +                                                      v4 |])++-- 16 Bit Test Values++v_0000 = reallyUnsafeVector [L,L,L,L, L,L,L,L, L,L,L,L, L,L,L,L]+v_8000 = reallyUnsafeVector [L,L,L,L, L,L,L,L, L,L,L,L, L,L,L,H] -- H is MSB+v_0001 = reallyUnsafeVector [H,L,L,L, L,L,L,L, L,L,L,L, L,L,L,L]+v_ffff = reallyUnsafeVector [H,H,H,H, H,H,H,H, H,H,H,H, H,H,H,H]++a16 = v_0000 : v_0000 : v_0001 : v_8000 : v_ffff : v_ffff : []+b16 = v_0000 : v_0001 : v_0001 : v_8000 : v_ffff : v_0001 : []++test16Bit = simCSAdder16Bit a16 b16++-- 4 Bit Test Values++v_0 = reallyUnsafeVector [L,L,L,L]+v_1 = reallyUnsafeVector [H,L,L,L]+v_8 = reallyUnsafeVector [L,L,L,H]+v_f = reallyUnsafeVector [H,H,H,H]++a4 = v_0 : v_0 : v_1 : v_8 : v_f : v_1 : []+b4 = v_0 : v_1 : v_1 : v_8 : v_f : v_f : []++c_low = [L,L,L,L,L,L]+c_high = [H,H,H,H,H,H] ++test4Bit = simCSAdder4Bit c_low a4 b4 ++-- Test FSVector++fv = 0 +> 1 +> 2 +> 3 +> empty -- LSB fv!d0 = 0, MSB fv!d3 = 3
+ examples/Counter.hs view
@@ -0,0 +1,20 @@+{-# LANGUAGE TemplateHaskell #-}++-- A counter, the simplest system with which to test netlist loops++module Counter where++import ForSyDe+import Data.Int++counter :: Signal Int32+counter  = sourceSY "counterSource" add1 (0 :: Int32)+ where add1 = $(newProcFun [d| add1 :: Int32 -> Int32 +                               add1 a = a + 1   |]) +++counterSys :: SysDef (Signal Int32)+counterSys = $(newSysDefTHName 'counter [] ["countVal"])++simCounter :: [Int32]+simCounter = simulate counterSys
+ examples/DeepShallow.hs view
@@ -0,0 +1,22 @@+-- This example shows how to mix shallow-embedded and+-- deep-embedded signals by building an heterogeneous+-- system which adds five to its input+module DeepShallow where++import SeqAddFour (addFourSys)+import ForSyDe(simulate)+import ForSyDe.Shallow+import Data.Int++-- addOne using shallow-embedded signals+addOne :: Signal Int32 -> Signal Int32+addOne = mapSY (+1)++-- addFourSys uses deep-embedded signals, but we can transform them to lists+-- using simulate+addFourLists :: [Int32] -> [Int32]+addFourLists = simulate addFourSys++-- addFive uses addOne and addFourLists+addFive :: Signal Int32 -> Signal Int32+addFive = signal.addFourLists.fromSignal.addOne
+ examples/Equalizer_Shallow/AudioAnalyzer.lhs view
@@ -0,0 +1,55 @@+\subsection{Overview}++The \process{Audio Analyzer} analyzes the current bass level and raises a flag when the bass level exceeds a limit. ++\begin{figure}+\centering+\scalebox{0.8}{\mbox{\input{Figures/AudioAnalyzer.pstex_t}}}+\caption{The \textit{Audio Analyzer} subsystem}+\label{fig:AudioAnalyzerSubsystem}+\end{figure}++As illutsrated in Figure \ref{fig:AudioAnalyzerSubsystem} the \process{Audio Analyzer} is divided into four blocks. The input signal is first grouped into samples of size $N$ in the process \process{Group Samples} and then processed with a \process{DFT} in order to get the frequency spectrum of the signal. Then the power spectrum is calculated in \process{Spectrum}. In \process{CheckBass} the lowest frequencies are compared with a threshold value. If they exceed this value, the output \process{Distortion Flag} will have the value \constant{Fail}.++Since \process{Group Samples} needs $N$ cycles for the grouping, it produces $N-1$ absent values $\perp$ for each grouped sample. Thus the following processes \process{DFT}, \process{Spectrum} and \process{Check Bass} are all $\Psi$-extended in order to be able to process the absent value $\Abst$.+\begin{code}+module AudioAnalyzer (audioAnalyzer) where++import ForSyDe.Shallow+import Complex+import EqualizerTypes++input = 0.1 :- 0.2 :- input++limit :: Double+limit = 1.0++nLow :: Int+nLow = 3++audioAnalyzer :: Int -> Signal Double -> Signal (AbstExt AnalyzerMsg)+audioAnalyzer pts =  mapSY (psi checkBass) -- Check Bass +		   . mapSY (psi spectrum)  -- Spectrum+		   . mapSY (psi (dft pts)) -- DFT+		   . groupSY pts	   -- Group Samples +		   . mapSY toComplex++spectrum :: (RealFloat a) => Vector (Complex a) -> Vector a+spectrum =  mapV log10 . selectLow nLow . mapV power . selectHalf . dropV 1+  where+    log10 x        = log x / log 10+    selectLow n xs = takeV n xs+    selectHalf xs  = takeV half xs+	       where half = floor (fromIntegral (lengthV xs) / 2)  +    power x = (magnitude x) ^ 2++checkBass :: Vector Double -> AnalyzerMsg+checkBass = checkLimit limit . sumV+  where+    checkLimit limit x | x > limit  = Fail+	               | otherwise  = Pass+    sumV vs = foldlV (+) 0.0 vs+++toComplex x = x :+ 0+\end{code}
+ examples/Equalizer_Shallow/AudioFilter.lhs view
@@ -0,0 +1,34 @@+\subsection{Overview}+Figure \ref{fig:AudioFilter} shows the structure of the \process{AudioFilter}. The task of this subsystem is to amplify different frequencies of the audio signal independently according to the assigned levels. The audio signal is splitted into three identical signals, one for each frequency region. The signals are filtered and then amplified according to the assigned amplification level. As the equalizer in this design only has a bass and treble control, the middle frequencies are not amplified. The output signal from the \process{Audio Filter} is the addition of the three filtered and amplified signals.++\begin{figure}[h]+\centering+\input{Figures/AudioFilter.pstex_t}+\caption{Subsystems of the \emph{Audio Filter}}+\label{fig:AudioFilter}+\end{figure}++We model this structure as a network of blocks directly from Figure \ref{fig:AudioFilter}. It consists of three filters, two amplifiers and an adder. These blocks are modeled in the process layer. The \process{Audio Filter} has the filter coefficients for the low pass, band pass and high pass filter as parameters.+%+\begin{code}+module AudioFilter where++import ForSyDe.Shallow+import ForSyDe.Shallow.FIR++audioFilter :: Floating a => Vector a -> Vector a -> Vector a +	    -> Signal a -> Signal a -> Signal a -> Signal a+audioFilter lpCoeff bpCoeff hpCoeff bass treble audioIn = audioOut+   where audioOut      = zipWith3SY add3 bassPath middlePath treblePath+	 bassPath      = ((amplify bass) . lowPass) audioIn+	 middlePath    = bandPass audioIn+	 treblePath    = ((amplify treble) . highPass) audioIn+	 lowPass       = firSY lpCoeff+	 bandPass      = firSY bpCoeff+	 highPass      = firSY hpCoeff+	 amplify       = zipWithSY scale+	 add3 x y z    = x + y + z+	 scale x y     = y * (base ** x)  +	 base	       = 1.1+\end{code}+
+ examples/Equalizer_Shallow/ButtonControl.lhs view
@@ -0,0 +1,140 @@+\subsection{Overview}++The subsystem \process{Button Control} works as a user interface in the equalizer system. It receives the four input signals \signal{BassDn}, \signal{BassUp}, \signal{TrebleDn}, \signal{TrebleUp} and the override signal \process{Override} from the \process{Distortion Control} and calculates the new bass and treble values for the output signals \signal{Bass} and \signal{Treble}. The subsytem contains the main processes \process{Button Interface} and \process{Level Control}. The process \process{Level Control} outputs a new value, if either the signal \signal{Button} or the signal \signal{Overr} is present, otherwise the output value is absent. The process \process{Hold Level} is modeled by means of \process{holdSY (0.0, 0.0)} that outputs the last present value, if the input value is absent. The process \process{unzipSY} transforms a signal of tuples (the current bass and treble level) into a tuple of signals (a bass and a treble signal).++\begin{figure}+\centering+\scalebox{0.8}{\mbox{\input{Figures/ButtonControl.pstex_t}}}+\caption{The Subsystem \process{Button Control}}+\end{figure}++\begin{code}+module ButtonControl (buttonControl) where ++import ForSyDe.Shallow+import EqualizerTypes+import Combinators++data State   = Operating +	     | Locked deriving(Eq, Show)+type Level   = Double+type Bass    = Level+type Treble  = Level++buttonControl :: Signal (AbstExt OverrideMsg) -> Signal (AbstExt Sensor) + 	      -> Signal (AbstExt Sensor) -> Signal (AbstExt Sensor) + 	      -> Signal (AbstExt Sensor) -> (Signal Bass,Signal Treble)+buttonControl overrides bassDn bassUp trebleDn trebleUp +    = (bass, treble) +      where (bass, treble) = unzipSY levels+ 	    levels = ((holdSY (0.0, 0.0)) `funComb2` levelControl) +                           button overrides+            button = buttonInterface bassDn bassUp trebleDn trebleUp+\end{code}++\subsection{The Process \process{Button Interface}}++The \process{Button Interface} monitors the four input buttons \signal{BassDn}, \signal{BassUp}, \signal{TrebleDn}, \signal{TrebleUp} and indicates if a button is pressed. If two or more buttons are pressed the conflict is resolved by the priority order of the buttons. ++\begin{code}+buttonInterface :: Signal (AbstExt Sensor) -> Signal (AbstExt Sensor) +		-> Signal (AbstExt Sensor) -> Signal (AbstExt Sensor) +		-> Signal (AbstExt Button)+buttonInterface bassUp bassDn trebleUp trebleDn +   = zipWith4SY f bassUp bassDn trebleUp trebleDn+     where f (Prst Active) _ _ _ = Prst BassUp+	   f _ (Prst Active) _ _ = Prst BassDn+	   f _ _ (Prst Active) _ = Prst TrebleUp+	   f _ _ _ (Prst Active) = Prst TrebleDn+	   f _ _ _ _		 = Abst+\end{code}++\subsection{The Process \process{Level Control}}++The process has a local state that consists of a mode and the current values for the bass and treble levels (Figure \ref{fig:FSM_LevelControl}). The \process{Level Control} has two modes, in the mode \constant{Operating} the bass and treble values are stepwise changed in 0.2 steps. However, there exists maximum and minimum values which are -5.0 and +5.0. The process enters the mode \constant{Locked} when the \constant{Override} input has the value \constant{Lock}. In this mode an additional increase of the bass level is prohibitet and even decreased by 1.0 in case the \constant{Override} signal has the value \constant{CutBass}. The subsystem returns to the \constant{Operating} mode on the override value \constant{Release}. The output of the process is an absent extended signal of tuples with the current bass and treble levels.   ++\begin{figure}+\resizebox{\columnwidth}{!}{\mbox{\input{Figures/FSM_LevelControl.pstex_t}}}+\caption{The State Diagram of the Process \process{Level Control}}+\label{fig:FSM_LevelControl}+\end{figure}+\begin{code}+levelControl :: Signal (AbstExt Button) -> Signal (AbstExt OverrideMsg) + 	     -> Signal (AbstExt (Bass,Treble))+levelControl button overrides +  = mealy2SY nextState output (initState, initLevel) button overrides++nextState :: (State,(Double,Double)) -> AbstExt Button +	  -> AbstExt OverrideMsg -> (State,(Double,Double))+nextState (state, (bass, treble)) button override+  = (newState, (newBass, newTreble)) where+     newState = if state == Operating then+		   if override == Prst Lock then+		      Locked+		   else+		      Operating+	        else+		   if override == Prst Release then+		      Operating+		   else +		      Locked++     newBass = if state == Locked then+		  if override == Prst CutBass then+		     decreaseLevel bass cutStep+		  else+	             if button == Prst BassDn then+			decreaseLevel bass step+		     else+			bass+	       else -- state = Operating+		  if button == Prst BassDn then+		     decreaseLevel bass step+		  else +		     if button == Prst BassUp then+			increaseLevel bass step+		     else+			bass+		    +     newTreble = if button == Prst TrebleDn then+		    decreaseLevel treble step+		 else +		    if button == Prst TrebleUp then+		       increaseLevel treble step+		    else +		       treble++output :: (a, (Bass, Treble)) -> AbstExt Button -> AbstExt OverrideMsg + 	  -> AbstExt (Bass,Treble)+output _           Abst Abst = Abst+output (_, levels) _    _    = Prst levels	          +\end{code}++The process uses the following initial values.++\begin{code}+initState =  Operating+initLevel =  (0.0, 0.0)+maxLevel  =  5.0+minLevel  = -5.0+step      =  0.2+cutStep   =  1.0+\end{code}++The process uses the following auxiliary functions.++\begin{code}+decreaseLevel :: Level -> Level -> Level+decreaseLevel level step = if reducedLevel >= minLevel then+			      reducedLevel+		           else+			      minLevel+			   where reducedLevel = level - step++increaseLevel :: Level -> Level -> Level+increaseLevel level step = if increasedLevel <= maxLevel then+			      increasedLevel+		           else+			      maxLevel+			   where increasedLevel = level + step+\end{code}
+ examples/Equalizer_Shallow/DistortionControl.lhs view
@@ -0,0 +1,61 @@+The block \process{Distortion Control} is directly developed from the SDL-specification, that has been used for the MASCOT-model \cite{BjJa2000}. The specification is shown in Figure \ref{fig:SDL-Distortion Control}.++\begin{figure}[h]+\centering+\includegraphics[scale=0.5]{Figures/DistortionControl.eps}+\caption{SDL-description of \emph{Distortion Control}}+\label{fig:SDL-Distortion Control}+\end{figure}++The \process{Distortion Control} is a single FSM, which is modeled by means of the skeleton \process{mealySY}. The global state is not only expressed by the explicit states - \constant{Passed}, \constant{Failed} and \constant{Locked} -, but also by means of the variable \variable{cnt}. The state machine has two possible input values, \constant{Pass} and \constant{Fail}, and three output values, \constant{Lock}, \constant{Release} and \constant{CutBass}. ++The \process{mealySY} creates a process that can be interpreted as a Mealy-machine. It takes two functions, \function{nxtSt} to calculate the next state and \function{out} to calculate the output. The state is represented by a pair of the explicit state and the variable \variable{cnt}. The initial state is the same as in the SDL-model, given by the tuple \constant{(Passed, 0)}. The \function{nxtSt} function uses pattern matching. Whenever an input value matches a pattern of the \function{nxtSt} function the corresponding right hand side is evaluated, giving the next state. An event with an absent value leaves the state unchanged. The output function is modeled in a similar way. The output is absent, when no output message is indicated in the SDL-model.+%+\begin{code}+module DistortionControl (distortionControl) where++import ForSyDe.Shallow+import EqualizerTypes++data State =  Passed+            | Failed+            | Locked++distortionControl ::  Signal (AbstExt AnalyzerMsg) +		     -> Signal (AbstExt OverrideMsg)++distortionControl distortion +   = mealySY nxtSt out (Passed, 0) distortion++lim = 3++--     State       Input       NextState       +nxtSt (state, cnt) (Abst)      = (state,cnt)+nxtSt (Passed,cnt) (Prst Pass) = (Passed,cnt)+nxtSt (Passed,_  ) (Prst Fail) = (Failed,lim)+nxtSt (Failed,cnt) (Prst Pass) = (Locked,cnt)+nxtSt (Failed,cnt) (Prst Fail) = (Failed,cnt)+nxtSt (Locked,_  ) (Prst Fail) = (Failed,lim)+nxtSt (Locked,cnt) (Prst Pass) = (newSt,newCnt)+   where newSt = if (newCnt == 0) then Passed+	                          else Locked+         newCnt = cnt - 1++--   State         Input       Output+out (Passed,_)   (Prst Pass) = Abst+out (Passed,_)   (Prst Fail) = Prst Lock+out (Failed,_)   (Prst Pass) = Abst+out (Failed,_)   (Prst Fail) = Prst CutBass+out (Locked,_)   (Prst Fail) = Abst +out (Locked,cnt) (Prst Pass) = +   if (cnt == 1) then Prst Release+		  else Abst+out _             Abst        = Abst+\end{code}+++++++
+ examples/Equalizer_Shallow/Equalizer.lhs view
@@ -0,0 +1,55 @@+\subsection{Overview}++The main task of the equalizer system is to adjust the audio signal according to the \process{Button Control}, that works as a user interface. In addition, the bass level must not+exceed a predefined threshold to avoid damage to the speakers.++This specification can be naturally decomposed into four functions shown in+Figure \ref{fig:Equalizer-Level1}. The subsystems \process{Button Control} and \process{Distortion Control}, are control dominated (grey shaded), while the \process{Audio Filter} and the \process{Audio Analyzer} are data flow dominated subsystems.  ++\begin{figure}[h]+\centering+\input{Figures/Equalizer-Level1.pstex_t}+\caption{Subsystems of the \process{Equalizer}}+\label{fig:Equalizer-Level1}+\end{figure}++The \process{Button Control} subsystem monitors the button inputs and the override+signal from the subsystem \process{Distortion Control} and adjusts the current+bass and treble levels. This information is passed to the subsystem+\process{Audio Filter}, which receives the audio input, and filters and+amplifies the audio signal according to the current bass and treble+levels. This signal, the output signal of the equalizer, is analyzed by the +\process{Audio Analyzer} subsystem, which determines, whether the bass exceeds a+predefined threshold. The result of this analysis is passed to the subsystem \process{Distortion Control}, which decides, if a minor or major violation is encountered and issues the+necessary commands to the \process{Button Control} subsystem.  ++The frequency characteristics of the \process{Equalizer} is adjusted by the coefficients for the three FIR-filters in the \process{AudioFilter}. +%+\begin{code}+module Equalizer(equalizer) where++import ForSyDe.Shallow++import ButtonControl+import DistortionControl+import AudioAnalyzer+import AudioFilter+\end{code}+%+The structure of the equalizer is expressed as a network of blocks:+%+\begin{code}+equalizer lpCoeff bpCoeff hpCoeff dftPts +	  bassUp bassDn trebleUp trebleDn input = (bass, treble) --output +  where+    (bass, treble)  = buttonControl overrides bassUp bassDn +	                            trebleUp trebleDn+    output          = audioFilter lpCoeff bpCoeff hpCoeff bass +				  treble input+    distFlag        = audioAnalyzer dftPts output+    overrides       = distortionControl delayedDistFlag+    delayedDistFlag = delaySY Abst distFlag+\end{code}++Since the equalizer contains a feedback loop, the signal \process{DistFlag} is delayed one event cycle using the initial value \Abst.+
+ examples/Equalizer_Shallow/EqualizerTypes.lhs view
@@ -0,0 +1,21 @@+\subsection{Overview}++This module is a collection of data types that are used in the equalizer model.++\begin{code}+module EqualizerTypes where++data AnalyzerMsg = Pass+ 		 | Fail deriving(Show, Read, Eq)++data OverrideMsg = Lock+                 | CutBass+	         | Release deriving(Show, Read, Eq)++data Sensor = Active deriving(Show, Read, Eq)++data Button = BassDn+	    | BassUp+	    | TrebleDn+	    | TrebleUp deriving (Show, Read, Eq)+\end{code}
+ examples/Equalizer_Shallow/README view
@@ -0,0 +1,6 @@+This directory contains the Equalizer example, used in Sander's PhD Thesis,+and modelled using shallow-embedded signals.++[San03] Ingo Sander. System Modeling and Design Refinement in ForSyDe. +        PhD thesis, Royal Institute of Technology, Stockholm, Sweden,+        April 2003. [http://web.it.kth.se/~ingo/Papers/Thesis_Sander_2003.pdf]
+ examples/Equalizer_Shallow/Test/AudioIn.mat view
@@ -0,0 +1,1 @@+   3.0000000e+00   1.1102230e-16   6.1803399e-01   0.0000000e+00   1.6180340e+00  -1.7460502e-15  -1.6180340e+00   6.6613381e-16  -6.1803399e-01   1.4432899e-15  -3.0000000e+00   1.2212453e-15  -6.1803399e-01  -8.8817842e-16  -1.6180340e+00  -2.7554553e-15   1.6180340e+00  -1.1102230e-15   6.1803399e-01   1.6653345e-15   3.0000000e+00  -2.2204460e-16   6.1803399e-01   7.6605389e-15   1.6180340e+00   1.0397118e-15  -1.6180340e+00   1.9984014e-15  -6.1803399e-01   2.7755576e-15  -3.0000000e+00   1.7763568e-15  -6.1803399e-01  -1.6653345e-15  -1.6180340e+00   6.0051022e-15   1.6180340e+00  -7.4384943e-15   6.1803399e-01   5.2180482e-15   3.0000000e+00  -1.0214052e-14   6.1803399e-01  -4.4408921e-15   1.6180340e+00  -2.3917751e-15  -1.6180340e+00   7.1054274e-15  -6.1803399e-01  -4.6629367e-15  -3.0000000e+00  -4.5519144e-15  -6.1803399e-01   4.7739590e-15  -1.6180340e+00   9.4365891e-15   1.6180340e+00   3.3306691e-15   6.1803399e-01  -1.0991208e-14   3.0000000e+00   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+ examples/Equalizer_Shallow/TestAnalyzer.lhs view
@@ -0,0 +1,30 @@+\begin{code}+module Main(main) where++import IO+import ForSyDe.Shallow+import AudioFilter+import AudioAnalyzer++input = 0.1 :- 0.2 :- input+zeros = (0.0, 0.0) :- zeros+++k = 8+n = 2 ^ k +sig = takeS (2*(2^k)) input+pts = 4++--testFilter = audioFilter zeros input++main = do fftInfile <- openFile "Test/audioOut.dat" ReadMode+	  fftOutfile <- openFile "Test/fftOut.dat" WriteMode+	  contents <- hGetContents fftInfile+--	  hPutStr fftOutfile (writeS (audioAnalyzer 6 ((readS contents2) :: Signal Double)))+	  putStr (show (audioAnalyzer pts ((readS contents) :: Signal Double)))+	  hPutStr fftOutfile (writeS (audioAnalyzer pts ((readS contents) :: Signal Double)))+--	  hClose fftOutfile+	  putStr "\nDone.\n"+\end{code}++
+ examples/Equalizer_Shallow/TestButtonControl.lhs view
@@ -0,0 +1,38 @@+\begin{code}+module TestButtonControl where++import ButtonControl+import EqualizerTypes+import ForSyDe.Shallow+++++bassUp = signal [Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst]++bassDn = signal [Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst]++trebleUp = signal [Abst, Abst, Abst, Abst,+		 Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst, Abst,+		 Abst, Abst, Abst, Prst Active]++trebleDn = signal [Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst,  Prst Active,+		 Abst, Abst, Abst, Prst Active]++overrides = signal [Abst, Abst, Abst, Abst,+		    Prst Lock, Abst, Abst, Abst,+		    Abst, Prst CutBass, Abst, Abst,+		    Prst Release,  Abst, Abst, Abst]++testButtonControl = buttonControl overrides bassUp bassDn trebleUp trebleDn+--testButtonInterface = buttonInterface  bassUp bassDn trebleUp trebleDn +\end{code}
+ examples/Equalizer_Shallow/TestDFT.lhs view
@@ -0,0 +1,17 @@+\begin{code}+module TestFFT where++import ForSyDe.Shallow+import Complex++toComplex a = a:+0++testDFT = dft 8 v3+testFFT = fft 8 v3++testBoth = zipWithV (-) testDFT testFFT++v1 = mapV toComplex (vector [1, 2])+v2 = mapV toComplex (vector [1, 2,3,4])+v3 = mapV toComplex (vector [1, 2, 3, 4, 5, 6, 7, 8])+\end{code}
+ examples/Equalizer_Shallow/TestDistortionControl.lhs view
@@ -0,0 +1,30 @@+\begin{code}+module TestDistortionControl where++import DistortionControl+import EqualizerTypes+import ForSyDe.Shallow++flag = signal+       [Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Fail,+	Abst, Abst, Abst, Prst Fail,+	Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+	Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass,+	Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Pass,+	Abst, Abst, Abst, Prst Fail,+        Abst, Abst, Abst, Prst Pass,+        Abst, Abst, Abst, Prst Pass]        ++testDistortionControl = distortionControl flag+\end{code}
+ examples/Equalizer_Shallow/TestEqualizer.lhs view
@@ -0,0 +1,94 @@+\begin{code}+module TestEqualizer where++import IO+import Equalizer+import EqualizerTypes+import ForSyDe.Shallow+import AudioFilter+import AudioAnalyzer++audioIn = takeS (pts * 4) $ infiniteS (id) 1.0++bassUp = signal [Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst,+		 Prst Active, Prst Active, Abst, Abst]++bassDn = signal [Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst,+		 Abst, Abst, Prst Active, Abst]++trebleUp = signal [Abst, Abst, Abst, Abst,+		 Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst, Abst,+		 Abst, Abst, Abst, Prst Active]++trebleDn = signal [Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst, Prst Active,+		 Abst, Abst, Abst,  Prst Active,+		 Abst, Abst, Abst, Prst Active]++overrides = signal [Abst, Abst, Abst, Abst,+		    Prst Lock, Abst, Abst, Abst,+		    Abst, Prst CutBass, Abst, Abst,+		    Prst Release,  Abst, Abst, Abst]+bass = infiniteS id 0.0+treble = infiniteS id 0.0+dataflow = audioAnalyzer 2 (audioFilter lpCoeff bpCoeff hpCoeff bass treble audioIn)++testEqualizer = equalizer lpCoeff bpCoeff hpCoeff 2 bassUp bassDn trebleUp trebleDn audioIn+--testButtonInterface = buttonInterface  bassUp bassDn trebleUp trebleDn +\end{code}++\begin{code}+lpCoeff = vector+     [ 0.01392741661548, 0.01396895728902,+       0.01399870011280, 0.01401657422649,+       0.01402253700635, 0.01401657422649,+       0.01399870011280, 0.01396895728902,+       0.01392741661548 ]++bpCoeff = vector+     [ 0.06318761339784, 0.08131651217682,+       0.09562326700432, 0.10478344432968,+       0.10793629404886, 0.10478344432968,+       0.09562326700432, 0.08131651217682,+       0.06318761339784 ]++hpCoeff = vector+     [ -0.07883878579454, -0.09820015927379,+       -0.11354603917221, -0.12339860164118,+        0.87320570334018, -0.12339860164118,+       -0.11354603917221, -0.09820015927379,+       -0.07883878579454 ]++zeros = infiniteS id 0.0++audioFilterD = audioFilter lpCoeff bpCoeff hpCoeff zeros zeros+pts = 4++main = do +          -- Test AudioFilter+          putStr "\n-->Test AudioFilter \n"+          filterInfile <- openFile "Test/AudioIn.mat" ReadMode+          filterContents <- hGetContents filterInfile +          putStr (show (audioFilterD (readS filterContents)))+          writeFile "Test/audioOut.dat" (writeS (audioFilterD (readS filterContents)))        +          -- Test AudioAnalyzer+          putStr "\n--> Test AudioAnalyzer \n"+          analyzerInfile <- openFile "Test/audioOut.dat" ReadMode+	  analyzerOutfile <- openFile "Test/analyzerOut.dat" WriteMode+	  analyzerContents <- hGetContents analyzerInfile+          putStr (show (audioAnalyzer pts ((readS analyzerContents) :: Signal Double)))+	  hPutStr analyzerOutfile (writeS (audioAnalyzer pts ((readS analyzerContents) :: Signal Double)))+          +	  --fftInfile <- openFile "audioOut.txt" ReadMode+	  --fftOutfile <- openFile "fftOut.txt" WriteMode+	  --contents <- hGetContents fftInfile+	  --putStr (writeS (((readS contents) :: Signal Double)))+	  --hPutStr fftOutfile (writeS (((readS contents) :: Signal Double)))+	  putStr "\nDone.\n"+\end{code}+
+ examples/Equalizer_Shallow/TestFIR.lhs view
@@ -0,0 +1,10 @@+\begin{code}+module TestFIR(main) where++import ForSyDe.Shallow+import ForSyDe.Shallow.FIR+coeff = vector [0.1, -0.2, 0.5, 0.2]+s = signal [1.0, 0, 0, 0, 0]+main = do putStr (show (firSY coeff s))+          putStr "\nDone\n."+\end{code}
+ examples/Equalizer_Shallow/TestFilter.lhs view
@@ -0,0 +1,82 @@+\begin{code}+module Main where++import IO+import ForSyDe.Shallow+--import FixedPoint+import AudioFilter++zeros = infiniteS id 0.0++s = signal [0.1,0.05,0.3,0.2,-0.5,0.2,0.1,0.3,0.1,-0.1,0.0,0.2]++fs = 200+t = takeS 400 (infiniteS (+1/200) 0.0)+ +cos10 x = cos (2*pi*10*x)+cos50 x = cos (2*pi*50*x)+cos90 x = cos (2*pi*90*x)++modCos x = cos10 x + cos50 x + cos90 x++audioIn = mapSY modCos t++lpCoeffD = vector [+   0.03898579822345,+   0.09739504968381,+   0.15360490491115,+   0.19416166962179,+   0.20893350067585,+   0.19416166962179,+   0.15360490491115,   +   0.09739504968381,+   0.03898579822345+   ]++bpCoeffD = vector [+  -0.07845593083988,+   0.00000000000000,+  -0.30707118658796,+   0.00000000000000,+   0.58268794919522,+   0.00000000000000,+  -0.30707118658796,+   0.00000000000000,+  -0.07845593083988+   ]++hpCoeffD = vector [+   0.03898579822345,  +  -0.09739504968381,   +   0.15360490491115,+  -0.19416166962179,+   0.20893350067585,+  -0.19416166962179,+   0.15360490491115,+  -0.09739504968381,+   0.03898579822345+  ]++--lpCoeffF8 = mapV real2Fixed8 lpCoeffD+--bpCoeffF8 = mapV real2Fixed8 bpCoeffD+--hpCoeffF8 = mapV real2Fixed8 hpCoeffD+--sF8	  = mapSY real2Fixed8 s++--lpCoeffF16 = mapV real2Fixed16 lpCoeffD+--bpCoeffF16 = mapV real2Fixed16 bpCoeffD+--hpCoeffF16 = mapV real2Fixed16 hpCoeffD+--sF16	  = mapSY real2Fixed16 s++audioFilterD = audioFilter lpCoeffD bpCoeffD hpCoeffD zeros zeros+outDouble = audioFilter lpCoeffD bpCoeffD hpCoeffD zeros zeros s+--outF16	  = audioFilter lpCoeffF16 bpCoeffF16 hpCoeffF16 (mapSY real2Fixed16 zeros) (mapSY real2Fixed16 zeros) sF16+--outF8	  = audioFilter lpCoeffF8 bpCoeffF8 hpCoeffF8 (mapSY real2Fixed8 zeros)(mapSY real2Fixed8 zeros) sF8++--writeAudioOut = writeFile "Test/AudioOut.for") . writeS +readAudioIn = readFile "Test/AudioIn.mat"++testSeries = do contents <- readAudioIn+		writeFile "Test/AudioOutFSD.ext" (writeS (audioFilterD (readS contents)))+--		writeAudioIn++\end{code}
+ examples/LFSR.hs view
@@ -0,0 +1,58 @@+{-# LANGUAGE TemplateHaskell #-}++-- This modules implements an Linear Feedback Shiftregister++-- Source:+-- Ben Cohen. VHDL Answers to Frequently Answered Questions. Kluwer. 1998++module LFSR where++import ForSyDe     -- Definition of Bit data type+import Data.Bits   -- Operations for Bit data type+import List++-- ********************+--+-- Naive Implementation+--+-- ********************++-- Design has one XOR-component+xor2f :: ProcFun (Bit -> Bit -> Bit)+xor2f = $(newProcFun [d|xor2f :: Bit -> Bit -> Bit+                        xor2f x1 x0 = xor x1 x0    |])++xor2Proc :: Signal Bit -> Signal Bit -> Signal Bit+xor2Proc = zipWithSY "xor2" xor2f++xor2Sys :: SysDef (Signal Bit -> Signal Bit -> Signal Bit)+xor2Sys = newSysDef  xor2Proc "xor2"  ["in1", "in0"] ["out0"]+++-- Design has four D-Flip-Flops+dffProc :: Signal Bit -> Signal Bit+dffProc = delaySY "delayDFF" H -- Starting Sequence must not be LL...L++dffSys :: SysDef (Signal Bit -> Signal Bit)+dffSys = newSysDef  dffProc "DelayFF"  ["in1"] ["in0"]++-- Netlist of LFSR+lfsr :: (Signal Bit, Signal Bit, Signal Bit, Signal Bit)+lfsr = (s1, s2, s3, s4)+       where s5 = instantiate "xor2" xor2Sys s1 s4+             s1 = instantiate "dff1" dffSys s5+             s2 = instantiate "dff2" dffSys s1+             s3 = instantiate "dff3" dffSys s2+             s4 = instantiate "dff4" dffSys s3++lfsrSys :: SysDef ((Signal Bit, Signal Bit, Signal Bit, Signal Bit))+lfsrSys = newSysDef  lfsr "lfsr"  [] ["s1", "s2", "s3", "s4"]++simlfsr :: ([Bit], [Bit], [Bit], [Bit])+simlfsr = simulate lfsrSys++zip4tuple (a, b, c, d) = zip4 a b c d++createVHDL = writeVHDL lfsrSys++myLFSRtest = (take 20 . zip4tuple) (simlfsr)
+ examples/Multiplexer.hs view
@@ -0,0 +1,57 @@+{-# LANGUAGE TemplateHaskell #-}+-- multiplexer+module Multiplexer where++import ForSyDe+import Language.Haskell.TH.Lift++-- I used tuples, but a vector of bits is what I would like to have+selectf :: ProcFun((Bit, Bit) -> (Bit, Bit, Bit, Bit) -> Bit)+selectf = $(newProcFun [d| select1 :: (Bit, Bit) +				  -> (Bit, Bit, Bit, Bit) -> Bit   +			   select1 (s1, s0) (x3, x2, x1, x0) =+		             if (s1 == L) && (s0 == L) then+				x0+			     else +				if (s1 == L) && (s0 == H) then+				   x1+				else+				   if (s1 == H) && (s0 == L) then+				      x2+				   else+				      x3   |])+++-- System function (or process) which uses 'selectf'+selectProc :: Signal (Bit, Bit) -> Signal (Bit, Bit, Bit, Bit) -> Signal Bit+selectProc = zipWithSY "select1" selectf++-- System definition associated to the system process 'selectProc' +muxSysDef :: SysDef (Signal (Bit, Bit) -> Signal (Bit, Bit, Bit, Bit) -> Signal Bit)+muxSysDef = $(newSysDefTHName 'selectProc ["sel", "data"] ["out1"])++-- we simulate the system+simMux :: [(Bit, Bit)] -> [(Bit, Bit, Bit, Bit)] -> [Bit]+simMux = simulate muxSysDef+++selIn = [(L,L),(L,H),(H,L)]+dataIn = [(L,L,L,H), (L,L,L,H), (L,H,L,L)]+++-- translate to VHDL, write output and run in QUartus+vhdlMux :: IO ()+vhdlMux = writeVHDLOps defaultVHDLOps{execQuartus=Just quartusOps} muxSysDef+ where quartusOps = QuartusOps FullCompilation+                               (Just 50)+                               (Just ("CycloneII", Just "EP2C35F672C6"))+                               [("sel.tup_1","PIN_AF14"),+                                ("sel.tup_2","PIN_AD13"),+                                ("data.tup_1","PIN_N25"),+                                ("data.tup_2","PIN_N26"),+                                ("data.tup_3","PIN_P25"),+                                ("data.tup_4","PIN_AE14"),+                                ("out1","PIN_AE23")]+++
+ examples/Multiplexer_FSVector.hs view
@@ -0,0 +1,45 @@+{-# LANGUAGE TemplateHaskell #-}+-- multiplexer+module Multiplexer_FSVector where++import ForSyDe+import Language.Haskell.TH.Lift+import Data.Param.FSVec+import Data.TypeLevel.Num.Reps+import Data.TypeLevel.Num.Aliases++-- I used tuples, but a vector of bits is what I would like to have+selectf :: ProcFun(FSVec D2 Bit -> FSVec D4 Bit -> Bit)+selectf = $(newProcFun [d| select1 :: FSVec D2 Bit +				   -> FSVec D4 Bit -> Bit   +			   select1 sel input =+		             if (sel!d1 == L) && (sel!d0 == L) then+				input!d0+			     else +				if (sel!d1 == L) && (sel!d0 == H) then+				   input!d1+				else+				   if (sel!d1 == H) && (sel!d0 == L) then+				      input!d2+				   else+				      input!d3   |])+++-- System function (or process) which uses 'selectf'+selectProc :: Signal (FSVec D2 Bit) -> Signal (FSVec D4 Bit) -> Signal Bit+selectProc = zipWithSY "select1" selectf++-- System definition associated to the system process 'selectProc' +muxSysDef :: SysDef (Signal (FSVec D2 Bit) -> Signal (FSVec D4 Bit) -> Signal Bit)+muxSysDef = $(newSysDefTHName 'selectProc ["sel", "data"] ["out1"])++-- we simulate the system+simMux :: [FSVec D2 Bit] -> [FSVec D4 Bit] -> [Bit]+simMux = simulate muxSysDef++selIn = [$(vectorTH [L,L]), $(vectorTH [H,L]), $(vectorTH [L,H]) ]+dataIn = [$(vectorTH [L,H,H,H]), $(vectorTH [H,L,H,H]), $(vectorTH [H,H,L,H])]++-- Create VHDL+createVHDL = writeVHDL muxSysDef+
+ examples/Null.hs view
@@ -0,0 +1,20 @@+{-# LANGUAGE TemplateHaskell #-}++-- This module is aimed at testing the, normally useless but possible, +-- null system++module Null where++import ForSyDe++nullSysF :: ()+nullSysF = ()++nullSysDef :: SysDef ()+nullSysDef = $(newSysDefTHName 'nullSysF [] [])++nullIns0 :: ()+nullIns0 = instantiate "null0" nullSysDef++simNull :: ()+simNull = simulate nullSysDef
+ examples/ParAddFour.hs view
@@ -0,0 +1,43 @@+{-# LANGUAGE TemplateHaskell #-}+-- Naive example to test instances working in paralell+-- Adds a signal to four signals+module ParAddFour where++import ForSyDe+import Data.Int+++add :: ProcFun (Int32 -> Int32 -> Int32)+add = $(newProcFun [d| add :: Int32 -> Int32 -> Int32+                       add a b = a + b |])++addProc :: Signal Int32 -> Signal Int32 -> Signal Int32+addProc s1 s2 = zipWithSY "zip1" add s1 s2+++addSys :: SysDef (Signal Int32 -> Signal Int32 -> Signal Int32)+addSys = $(newSysDefTHName 'addProc ["in1","in2"] ["sum"])++simAdd :: [Int32] -> [Int32] -> [Int32]+simAdd = simulate addSys++parAddFour :: Signal Int32 +           -> Signal Int32 -> Signal Int32 -> Signal Int32 -> Signal Int32 +           -> (Signal Int32, Signal Int32, Signal Int32, Signal Int32)+parAddFour toAdd s1 s2 s3 s4 = (sum1, sum2, sum3, sum4)+  where sum1 = (instantiate "adder1" addSys) toAdd s1+        sum2 = (instantiate "adder2" addSys) toAdd s2+        sum3 = (instantiate "adder3" addSys) toAdd s3+        sum4 = (instantiate "adder4" addSys) toAdd s4++parAddFourSys :: SysDef (Signal Int32 +           -> Signal Int32 -> Signal Int32 -> Signal Int32 -> Signal Int32 +           -> (Signal Int32, Signal Int32, Signal Int32, Signal Int32))+parAddFourSys = $(newSysDefTHName 'parAddFour ["toAdd","s1","s2","s3","s4"]+                                        ["sum1","sum2","sum3","sum4"])+++simParAddFour :: [Int32]+              -> [Int32] -> [Int32] -> [Int32] -> [Int32]+              -> ([Int32], [Int32], [Int32], [Int32]) +simParAddFour = simulate parAddFourSys
+ examples/SeqAddFour.hs view
@@ -0,0 +1,45 @@+{-# LANGUAGE TemplateHaskell #-}++-- This module is aimed at testing a naive use-case of +-- the instantiation mechanism++-- We'll build a system which uses four single-adder components connected+-- sequentially to add four units to the values of the input signal++module SeqAddFour where++import ForSyDe+import Data.Int++-- A process function which adds one to its input+addOnef :: ProcFun (Int32 -> Int32)+addOnef = $(newProcFun [d|addOnef :: Int32 -> Int32 +                          addOnef n = n + 1     |])++-- System function (or process) which uses addOnef+addOneProc :: Signal Int32 -> Signal Int32+addOneProc = mapSY "addOne" addOnef+++-- System definition associated to the system function+addOneSysDef :: SysDef (Signal Int32 -> Signal Int32)+addOneSysDef = newSysDef addOneProc "addOne" ["in1"] ["out1"]+++-- Finally, we create the sequential add four system function+addFour :: Signal Int32 -> Signal Int32+addFour = instantiate "addOne3" addOneSysDef .+          instantiate "addOne2" addOneSysDef .+          instantiate "addOne1" addOneSysDef .+          instantiate "addOne0" addOneSysDef++-- We build the system+addFourSys :: SysDef (Signal Int32 -> Signal Int32)+addFourSys = newSysDef addFour "addFour" ["in1"] ["out1"]++-- we simulate the system+simAddFour :: [Int32] -> [Int32]+simAddFour = simulate addFourSys++-- we generate VHDL+createVHDL = writeVHDL addFourSys
+ examples/ZipTwist.hs view
@@ -0,0 +1,36 @@+{-# LANGUAGE TemplateHaskell #-}+-- An identity system of six inputs formed by various zipping and unzipping+-- processes+module ZipTwist where++import ForSyDe+import Data.Param.FSVec+import Data.TypeLevel.Num.Reps+import Data.Int++zip6xSY :: ProcId -> FSVec D6 (Signal Int32) -> Signal (FSVec D6 Int32)+zip6xSY = zipxSY++zipTwistFun :: Signal Int32 -> Signal Int32 -> Signal Int32 +            -> Signal Int32 -> Signal Int32 -> Signal Int32+            -> (Signal Int32, Signal Int32, Signal Int32,+                Signal Int32, Signal Int32, Signal Int32)+zipTwistFun i1 i2 i3 i4 i5 i6 =  (o1,o2,o3,o4,o5,o6)+ where [i1',i2',i3',i4',i5',i6'] = (fromVector.unzipxSY "unzipxSY" . zip6xSY "zip6xsy")+                                   $ reallyUnsafeVector  [i1,i2,i3,i4,i5,i6]+       zip13 = zip3SY "zip13" i1' i2' i3'+       zip46 = zip3SY "zip46" i4' i5' i6'+       (o1,o2,o3) = unzip3SY "unzip13" zip13+       (o4,o5,o6) = unzip3SY "unzip46" zip46++zipTwistSys :: SysDef (Signal Int32 -> Signal Int32 -> Signal Int32 +            -> Signal Int32 -> Signal Int32 -> Signal Int32+            -> (Signal Int32, Signal Int32, Signal Int32,+                Signal Int32, Signal Int32, Signal Int32))+zipTwistSys = $(newSysDefTHName 'zipTwistFun +                             ["in1","in2","in3","in4","in5","in6"]+                             ["out1","out2","out3","out4","out5","out6"])++simZipTwist = simulate zipTwistSys++writeVHDLZipTwist = writeVHDL zipTwistSys
+ lib/forsyde.vhd view
@@ -0,0 +1,158 @@+library ieee;+use ieee.numeric_std.all;+use ieee.std_logic_1164.all;+  +package types is+  +  function default return integer;+  function show (i : integer) return string;  +  +-- Commented out due to representation overflow (modelsim integers+-- are 32bits long)+-- subtype int64 is integer range -(2**(64-1)) to +(2**(64-1)-1);  ++-- Commented out due to a overflow in 2**32:+-- subtype int32 is integer range -(2**(32-1)) to +(2**(32-1)-1);  ++-- Note the lower bound is not -2147483648 because the LRM doesn't+-- force to include it.+  subtype int32 is integer range -2147483647 to +2147483647;  +  +  subtype int16 is integer range -(2**(16-1)) to +(2**(16-1)-1);  ++  subtype int8 is integer range -(2**(8-1)) to +(2**(8-1)-1);++  function default return std_logic;+  function show (s : std_logic) return string;+  +  function default return boolean;+  function show (b : boolean) return string;+  +  -- Indexes for unconstrained fsvecs:+  --  -1 is used to express the null vector, with bounds (0 to -1)+  subtype fsvec_index is integer range -1 to integer'high;++  -- Unconstrained translation of "FSVec _ Bit"+  -- needed for toBitVector and fromBitVector+  type fsvec_std_logic is array (fsvec_index range <>) of std_logic;++  function toBitVector8 (i : int8)  return fsvec_std_logic; +  function toBitVector16 (i : int16) return fsvec_std_logic;+  function toBitVector32 (i : int32) return fsvec_std_logic;++  function fromBitVector8 (v : fsvec_std_logic) return int8; +  function fromBitVector16 (v : fsvec_std_logic) return int16;+  function fromBitVector32 (v : fsvec_std_logic) return int32;+  +end types;++package body types is++-- Commented out due to representation overflow +--  function default return int64 is+--  begin +--   return 0;+--  end default;++  function default return integer is+  begin +   return 0;+  end default;++  function show (i : integer) return string is+  begin+    return integer'image(i);+  end show;++  function default return std_logic is+  begin+   return '0';+  end default;++  function show (s : std_logic) return string is+  begin+    if s = '1' then+      return "H";+    else+      return "L";+    end if;+  end show;++  +  function default return boolean is+  begin+   return true;+  end default;++  function show (b : boolean) return string is+  begin+    if b then+      return "True";+    else+      return "False";+    end if;+  end show;++  function toBitVector8 (i : int8) return fsvec_std_logic is+    variable inter : signed (0 to 7) := to_signed (i, 8);+    variable ret : fsvec_std_logic (0 to 7); +  begin+    for index in 0 to ret'length-1 loop+      ret(index) := inter(index);+    end loop;+    return ret;+  end toBitVector8;+++  function toBitVector16 (i : int16) return fsvec_std_logic is+    variable inter : signed (0 to 15) := to_signed (i, 16);+    variable ret : fsvec_std_logic (0 to 15); +  begin+    for index in 0 to ret'length-1 loop+      ret(index) := inter(index);+    end loop;+    return ret;+  end toBitVector16;+++  function toBitVector32 (i : int32) return fsvec_std_logic is+    variable inter : signed (0 to 31) := to_signed (i, 32);+    variable ret : fsvec_std_logic (0 to 31); +  begin+    for index in 0 to ret'length-1 loop+      ret(index) := inter(index);+    end loop;+    return ret;+  end toBitVector32;+++  function fromBitVector8 (v : fsvec_std_logic) return int8 is+    variable inter : signed (0 to 7);+  begin+    for index in 0 to inter'length-1 loop+      inter(index) := v(index);+    end loop;+    return to_integer(inter);+  end frombitVector8;++  function fromBitVector16 (v : fsvec_std_logic) return int16 is+    variable inter : signed (0 to 15);+  begin+    for index in 0 to inter'length-1 loop+      inter(index) := v(index);+    end loop;+    return to_integer(inter);+  end frombitVector16;+++  function fromBitVector32 (v : fsvec_std_logic) return int32 is+    variable inter : signed (0 to 31);+  begin+    for index in 0 to inter'length-1 loop+      inter(index) := v(index);+    end loop;+    return to_integer(inter);+  end frombitVector32;+  ++end types;
+ src/Data/Traversable/GenericZipWith.hs view
@@ -0,0 +1,71 @@+---------------------------------------------------------------------------+-- |+-- Module      :  Data.Traversable.GenericZipWith+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides generalized zipWith functions.+-- +-----------------------------------------------------------------------------+module Data.Traversable.GenericZipWith + (zipWithTF,+  zipTF,+  zipWithTFA,+  zipWithTFM) where+++import Data.Foldable+import Data.Traversable+import qualified Data.Traversable as T+import Control.Applicative+import Control.Monad.State ++-- | The state contains the list of values obtained form the foldable container+--   and a String indicating the name of the function currectly being executed+data ZipState a = ZipState {fName :: String,+                            list  :: [a]}++-- | State monad containing ZipState+type ZipM l a = State (ZipState l) a++-- | pops the first element of the list inside the state+pop :: ZipM l l+pop = do + st <- get + let xs = list st+     n = fName st+ case xs of+   (a:as) -> do put st{list=as}+                return a+   [] -> error $ n ++ ": insufficient input"++-- | pop a value form the state and supply it to the second +--   argument of a binary function +supplySecond :: (a -> b -> c) -> a -> ZipM b c+supplySecond f a = do b <- pop  +                      return $ f a b++zipWithTFError :: (Traversable t,Foldable f) => +                  String -> (a -> b -> c) -> t a -> f b -> t c  +zipWithTFError str g t f = evalState (T.mapM (supplySecond g) t) +                                     (ZipState str (toList f))+++zipWithTF :: (Traversable t,Foldable f) => (a -> b -> c) -> t a -> f b -> t c+zipWithTF = zipWithTFError "GenericZip.zipWithTF"++zipTF :: (Traversable t, Foldable f) => t a -> f b -> t (a,b)+zipTF = zipWithTFError "GenericZip.zipTF"  (,) +++zipWithTFM :: (Traversable t,Foldable f,Monad m) => +              (a -> b -> m c) -> t a -> f b -> m (t c)+zipWithTFM g t f = T.sequence (zipWithTFError "GenericZip.zipWithTFM"  g t f)+ +zipWithTFA :: (Traversable t,Foldable f,Applicative m) => +              (a -> b -> m c) -> t a -> f b -> m (t c)+zipWithTFA g t f = sequenceA (zipWithTFError "GenericZip.zipWithTFA" g t f)
+ src/Data/Typeable/TypeRepLib.hs view
@@ -0,0 +1,31 @@+---------------------------------------------------------------------------+-- |+-- Module      :  Data.Typeable.TypeRepLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides basic functions related to Data.Typeables's 'TypeRep'.+-- +-----------------------------------------------------------------------------+module Data.Typeable.TypeRepLib (unArrowT) where++import Data.Typeable+++-- | Obtains the arguments and return type of a given 'TypeRep' +--   (normally a function)+--   together with its 'Context' (non-empty if the type is polymorphic)+unArrowT :: TypeRep        -- ^ TypeRep to observe  +        ->  ([TypeRep], TypeRep) -- ^ (args 'TypeRep', ret 'TypeRep')+unArrowT rep+ | repCon == arrowTyCon = let (args', ret') = unArrowT  arrowArg2+                          in (arrowArg1:args', ret')+ | otherwise = ([], rep)+ where (repCon,~[arrowArg1,arrowArg2]) = splitTyConApp rep++arrowTyCon :: TyCon+arrowTyCon = (typeRepTyCon.typeOf) (undefined :: () -> ())
+ src/ForSyDe.hs view
@@ -0,0 +1,36 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe+-- Copyright   :  (c) SAM Group (KTH) 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module is a wrapper for all the publicly usable types and+-- functions of ForSyDe's deep-embedded Domain Specific Language+-- (DSL). For the shallow-embedded DSL, please see "ForSyDe.Shallow".+--+-- +-----------------------------------------------------------------------------+module ForSyDe +(module ForSyDe.Ids,+ module ForSyDe.Signal,+ module ForSyDe.System,+ module ForSyDe.Process,+ module ForSyDe.Backend,+ module ForSyDe.Bit,+ module ForSyDe.AbsentExt,+ module ForSyDe.DFT,+ module ForSyDe.FIR) where++import ForSyDe.Ids+import ForSyDe.Signal (Signal)+import ForSyDe.Bit+import ForSyDe.Process+import ForSyDe.System+import ForSyDe.Backend+import ForSyDe.AbsentExt+import ForSyDe.DFT+import ForSyDe.FIR
+ src/ForSyDe/AbsentExt.hs view
@@ -0,0 +1,100 @@+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-}  +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.AbsentExt+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The 'AbstExt' is used to extend existing data types with the value+--  \'absent\', which models the absence of a value.+-- +-----------------------------------------------------------------------------++module ForSyDe.AbsentExt( +		  AbstExt (Abst, Prst), fromAbstExt, unsafeFromAbstExt, +                  abstExt, psi, +	          isAbsent, isPresent, abstExtFunc)+	        where++import Data.Generics+import Language.Haskell.TH.Lift+++-- |The data type 'AbstExt' has two constructors. The constructor 'Abst' is used to model the absence of a value, while the constructor 'Prst' is used to model present values.+data AbstExt a		       =  Abst   +			       |  Prst a +  deriving (Eq, Data, Typeable)+$(deriveLift1 ''AbstExt)++++-- |The function 'fromAbstExt' extracts the inner value contained in 'AbstExt'+fromAbstExt	       :: a -- ^ Default value returned if the input is 'Abst' +                       -> AbstExt a -> a+-- |Similar to 'fromAbstExt', but without default value+unsafeFromAbstExt      :: AbstExt a -> a +-- |The functions 'isPresent' checks for the presence of a value.+isPresent	       :: AbstExt a -> Bool+-- |The functions 'isAbsent' checks for the absence of a value.+isAbsent	       :: AbstExt a -> Bool+-- |The function 'abstExtFunc' extends a function in order to process absent extended values. If the input is (\"bottom\"), the output will also be  (\"bottom\").+abstExtFunc	       :: (a -> b) -> AbstExt a -> AbstExt b+-- | The function 'psi' is identical to 'abstExtFunc' and should be used in future.+psi :: (a -> b) -> AbstExt a -> AbstExt b+-- | The function 'abstExt' converts a usual value to a present value. +abstExt :: a -> AbstExt a+++++++-- Implementation of Library Functions++-- | The data type 'AbstExt' is defined as an instance of 'Show' and 'Read'. \'_\' represents the value 'Abst' while a present value is represented with its value, e.g.  'Prst' 1 is represented as \'1\'.+instance Show a => Show (AbstExt a) where+	 showsPrec _ x	       = showsAbstExt x++showsAbstExt :: Show a => AbstExt a -> [Char] -> [Char]+showsAbstExt Abst	       = (++) "_"       +showsAbstExt (Prst x)	       = (++) (show x)++instance Read a => Read (AbstExt a) where+ 	 readsPrec _ x	       =  readsAbstExt x ++readsAbstExt		       :: (Read a) => ReadS (AbstExt a)+readsAbstExt s		       =     [(Abst, r1)    | ("_", r1) <- lex s]+                                  ++ [(Prst x, r2)  | (x, r2) <- reads s]++abstExt v		       =  Prst v++fromAbstExt x Abst	       =  x   +fromAbstExt _ (Prst y)	       =  y   ++unsafeFromAbstExt (Prst x)     =  x   +unsafeFromAbstExt Abst	       =  error "AbsentExt.unsafeFromAbstExt: Abst"++isPresent Abst		       =  False+isPresent (Prst _)	       =  True++isAbsent		       =  not . isPresent++abstExtFunc f		       = f' +  where f' Abst		       = Abst+	f' (Prst x)	       = Prst (f x)+++psi			       = abstExtFunc+++++++++
+ src/ForSyDe/Backend.hs view
@@ -0,0 +1,24 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Wrapper module exporting all the backends+-- +-----------------------------------------------------------------------------+module ForSyDe.Backend + (module ForSyDe.Backend.Simulate,+  module ForSyDe.Backend.VHDL,+  module ForSyDe.Backend.GraphML) where++import ForSyDe.Backend.Simulate+import ForSyDe.Backend.VHDL+import ForSyDe.Backend.GraphML+++
+ src/ForSyDe/Backend/GraphML.hs view
@@ -0,0 +1,45 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides the GraphML backend of ForSyDe's embedded compiler+--+-----------------------------------------------------------------------------+-- FIXME: factorize code shared between backends, and create a common interface for+--        backends (maybe based on a MPTC)++module ForSyDe.Backend.GraphML+ (writeGraphML, +  writeGraphMLOps, +  GraphMLOps(..),+  GraphMLDebugLevel(..),+  GraphMLRecursivity(..),+  defaultGraphMLOps) where++import Control.Monad.State (evalStateT)+import ForSyDe.ForSyDeErr+import ForSyDe.OSharing (readURef)+import ForSyDe.System.SysDef+import ForSyDe.Backend.GraphML.Traverse++-- | Given a System Definition whose name is A generate @A.graphml@ in current +--   working directory using the default compilation options.+writeGraphML :: SysDef a -> IO ()+writeGraphML = writeGraphMLOps defaultGraphMLOps ++-- | 'writeGraphML'-alternative which allows setting GraphML compilation +--   options.+writeGraphMLOps :: GraphMLOps -> SysDef a -> IO ()+writeGraphMLOps ops sysDef = do+  -- initiate the compilation State+  let s = initGraphMLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef+  -- Translate the code+  res <- runErrorT $ evalStateT  (setGraphMLOps ops >> writeGraphMLM) s+  -- Check if the  compilation went well and print an error in case it didn't+  either printGraphMLError return res
+ src/ForSyDe/Backend/GraphML/AST.hs view
@@ -0,0 +1,44 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML.AST+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- AST covering the GraphML subset we are interested in for this backend+-----------------------------------------------------------------------------++--FIXME: the design of this module is ugly++module ForSyDe.Backend.GraphML.AST where++import ForSyDe.Netlist++type GraphMLGraphId = String+type GraphMLPortId = String+type GraphMLNodeId = String++-- | Main AST type, a graph+data GraphMLGraph = GraphMLGraph +        GraphMLGraphId -- Graph id+        [GraphMLNode] -- Nodes +        [GraphMLEdge] -- Edges+++-- | Edge+data GraphMLEdge = GraphMLEdge +  GraphMLNode    -- Origin node+  GraphMLPortId  -- Origin port id+  GraphMLNode    -- Target node+  GraphMLPortId  -- Target port id++-- | Node+data GraphMLNode = + ProcNode (NlNode GraphMLPortId) -- Netlist node indicating the input ports+                 [GraphMLPortId]  -- Output ports + -- FIXME: This representation is ugly+                                  |+ OutNode GraphMLNodeId GraphMLPortId  -- the special output node
+ src/ForSyDe/Backend/GraphML/FileIO.hs view
@@ -0,0 +1,27 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML.FileIO+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions working with files in the GraphML backend. +--+-----------------------------------------------------------------------------+module ForSyDe.Backend.GraphML.FileIO where++import ForSyDe.Backend.GraphML.AST+import ForSyDe.Backend.GraphML.Ppr(YFilesMarkup, pprGraphWithHeaders)++import System.IO+import Text.PrettyPrint.HughesPJ++-- | Write a design file to a file in disk+writeGraph :: YFilesMarkup -> GraphMLGraph -> FilePath -> IO ()+writeGraph yFiles graph fp = do+ handle     <- openFile fp WriteMode+ hPutStr handle $ (render . pprGraphWithHeaders yFiles) graph+ hClose handle
+ src/ForSyDe/Backend/GraphML/Ppr.hs view
@@ -0,0 +1,325 @@+{-# LANGUAGE TypeSynonymInstances, MultiParamTypeClasses  #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML.Ppr+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- GraphML pretty printing instances.+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.GraphML.Ppr where++import ForSyDe.Backend.Ppr+import ForSyDe.Ids+import ForSyDe.Process.ProcVal+import ForSyDe.Process.ProcFun+import ForSyDe.Backend.GraphML.AST+import ForSyDe.Netlist+import ForSyDe.Netlist.Traverse+import ForSyDe.System.SysDef+import ForSyDe.OSharing++import Data.Maybe (fromJust)+import Data.List (findIndex)+import qualified Data.Foldable as DF (foldr, toList)+import Language.Haskell.TH (pprint, Dec(FunD), Exp, nameBase)+import Text.PrettyPrint.HughesPJ+++-- | The only accepted pretyprinting option+type YFilesMarkup = Bool++-- | Number of spaces used for indentation+nestVal :: Int+nestVal = 5+++instance PprOps YFilesMarkup GraphMLGraph where+ pprOps yFiles (GraphMLGraph id nodes edges) =+  text "<graph" <+> text ("id=\"" ++ id ++ "\"") <+> +                     text "edgedefault=\"directed\" >" $+$+    nest nestVal (vSpace $+$    +                  pprOps_list yFiles (vNSpaces 1) nodes $+$+                  vSpace $+$+                  pprOps_list yFiles (vNSpaces 1) edges $+$+                  vSpace) $+$+  text "</graph>" ++instance PprOps YFilesMarkup GraphMLNode where+ pprOps yFiles node =+   text "<node" <+> text ("id=\"" ++ id ++ "\"") <> text ">" $+$   +   nest nestVal (+     (case node of+        ProcNode ins _ ->+          case ins of+            InPort  _ -> +              process_type "InPort" $+$+              yFilesNodeTags dim "#000000" "rectangle" (Just "w") id +            Proc _ (Const pval) -> +              let arg = (expVal.valAST) pval+              in process_type "ConstSY" $+$+                 value_arg  arg $+$+                 yFilesNodeTags dim "#FFFFFF" "ellipse" Nothing ("ConstSY\n" ++ show id ++ "\nval=" ++ pprint arg)+            Proc _ (ZipWithNSY tpf i) -> +              let nins = length i+                  typ = case nins of+                           1 -> "MapSY"+                           _ -> "ZipWith" ++ show nins ++ "SY"+                  pfAST = (tpast.tast) tpf+              in process_type "ZipWithNSY" $+$+                 procfun_arg pfAST $+$+                 yFilesNodeTags dim "#6F7DBC" "roundrectangle" Nothing (typ ++ "\n" ++ show id ++ "\nfName=" ++ nameBase (name pfAST))+            Proc _ (ZipWithxSY tpf _) -> +              process_type "ZipWithxSY" $+$+              procfun_arg ((tpast.tast) tpf) $+$+              yFilesNodeTags dim "#AFADFC" "rectangle" Nothing ("ZipWithxSY\n" ++ show id)+            Proc _ (UnzipNSY t _ _) -> +              let typ = "Unzip" ++ show (length t) ++ "SY"+              in process_type "UnzipNSY"  $+$+                 yFilesNodeTags dim "#5993A3" "roundrectangle" Nothing (typ ++ "\n" ++ show id)+            Proc _ (UnzipxSY _ _ _ _) -> +              process_type "UnzipxSY" $+$+              yFilesNodeTags dim "#99D3E3" "rectangle" Nothing ("UnzipxSY\n" ++ show id )+            Proc _ (DelaySY pval _) -> +              let arg = (expVal.valAST) pval+              in process_type "DelaySY" $+$+                 value_arg  arg $+$+                 yFilesNodeTags dim "#FF934C" "diamond" Nothing ("DelaySY\n" ++ show id ++ "\nval=" ++ pprint arg)+            Proc _ (SysIns psd _) -> +              let parId = (sid.readURef.unPrimSysDef) psd+              in process_type "SysIns" $+$+                 instance_parent parId $+$+                 yFilesNodeTags dim "#FF934C" "rectangle" Nothing ("SysIns\n" ++ show id ++ "\nparent=" ++ parId)+        OutNode _ _ -> +          process_type "OutPort"  $+$+          yFilesNodeTags dim "#000000" "rectangle"  (Just "e") id +        ) $+$ vcat (map port portIds)      +       ) $+$+   text "</node>" +  where +   (id, portIds) = +           case node of+                ProcNode ins outs ->+                   let pids = arguments ins ++ outs+                   in case ins of+                       InPort id -> (id, pids)+                       Proc id _ -> (id, pids)+                OutNode id portid -> (id,[portid])+   dim = nodeDims node+   -- write the yFiles specific markup for the node+   yFilesNodeTags (xsize, ysize) color shape mSide label =+    let labelLocation = maybe "modelName=\"internal\" modelPosition=\"c\""+                              (\s -> "modelName=\"sides\" modelPosition=\""+++                                     s ++ "\"")+                              mSide in            +     if yFiles +      then +        text "<data key=\"d0\">" $+$+         nest nestVal +          (text "<y:ShapeNode>" $+$+           nest nestVal +            (text "<y:Geometry height=\"" <> float ysize <> text "\" width=\"" <> float xsize <> text "\" x=\"0.0\" y=\"0.0\"/>" $+$+             text "<y:Fill color=\"" <> text color <> text "\" transparent=\"false\"/>" $+$+             text "<y:NodeLabel alignment=\"center\" autoSizePolicy=\"content\" fontFamily=\"Dialog\" fontSize=\"12\" fontStyle=\"plain\" hasBackgroundColor=\"false\" hasLineColor=\"false\"" <+> text labelLocation <+> text "textColor=\"#000000\" visible=\"true\">" <> text label <> text "</y:NodeLabel>" $+$+             text "<y:Shape type=\"" <> text shape <> text "\"/>"+           ) $+$+          text "</y:ShapeNode>" +         ) $+$+       text "</data>"+     else empty++instance PprOps YFilesMarkup  GraphMLEdge where+ pprOps yFiles (GraphMLEdge origN origP targetN targetP) = +    text "<edge" <+> text ("source=\"" ++ origId ++ "\"") <+> +                     text ("sourceport=\"" ++ origP ++ "\"") <+>+                     text ("target=\"" ++ targetId ++ "\"") <+> +                     text ("targetport=\"" ++ targetP ++ "\"") <> +    if not yFiles +      then text "/>"+      else char '>' $+$+           nest nestVal+            (text "<data key=\"d2\">" $+$+               nest nestVal+                (text "<y:PolyLineEdge>" $+$+                 nest nestVal+                  (text "<y:Path sx=\"" <> float edgeOrigX <> text "\" sy=\"" <> float edgeOrigY <> text "\" tx=\"" <> float edgeTargetX <> text "\" ty=\""<> float edgeTargetY <> text "\"/>" $+$+                   text "<y:LineStyle color=\"#000000\" type=\"line\" width=\"1.0\"/>" $+$+                   text "<y:Arrows source=\"none\" target=\"standard\"/>" $+$+		   text "<y:BendStyle smoothed=\"false\"/>"+                  ) $+$+                 text "</y:PolyLineEdge>") $+$+             text "</data>") $+$+           text "</edge>" +  where -- Origin Node identifier+       origId = getId origN+       -- Target Node Identifier+       targetId = getId targetN+       -- Calculate the edge connection point for yFiles markup+       (edgeOrigX, edgeOrigY) = edgeConnection True +                                                origNodeDims nOPortsOrig+                                                (findOutOrder origN origP)+       (edgeTargetX, edgeTargetY) = edgeConnection False +                                               targetNodeDims nIPortsTarget+                                               (findInOrder targetN targetP)  +       (_, nOPortsOrig) = nIOPorts origN+       origNodeDims  = nodeDims origN+       (nIPortsTarget, _) = nIOPorts targetN+       targetNodeDims = nodeDims targetN       +       -- Function to calculate where to connect an edge to a node+       -- note that in yfiles the coordinates origin of a node+       -- is located in the center, but the Y axis is inverted +       -- (negative values are in the upper side)+       edgeConnection isSource (nodeXSize, nodeYSize) totalPorts portOrder = +                                                                         (x,y)+          where x = if isSource then nodeXSize / 2 else -(nodeXSize/2) +                ySep = nodeYSize/(fromIntegral totalPorts)+                -- Absolut value of y measure from the top+                yAbs = ySep/2 + (fromIntegral portOrder) * ySep+                y = yAbs - (nodeYSize / 2)++       -- helper functions+       -------------------+       -- Find the order (starting at 0) of a input Port in a node+       findInOrder node portid = findList list+          where findList = fromJust . findIndex (==portid)+                list = case node of +                 OutNode _ pid -> [pid]+                 ProcNode ins _ -> DF.toList ins+       -- Find the order (starting at 0) of an output Port in a node+       findOutOrder node portid = findList list +          where findList = fromJust . findIndex (==portid)+                list = case node of +                 OutNode _ pid -> [pid]+                 ProcNode _ outs -> outs+       -- Get the identifier of a node+       getId node  = case node of+         OutNode id _ -> id+         ProcNode n _ -> case n of+                  InPort pid -> pid+                  Proc pid _ -> pid++-- | pretty print a Graph with XML headers and key definitions+pprGraphWithHeaders :: YFilesMarkup -> GraphMLGraph -> Doc+pprGraphWithHeaders yFiles graph = +  text "<?xml version=\"1.0\" encoding=\"UTF-8\"?>" $+$+  text "<!-- Automatically generated by ForSyDe -->" $+$+  text "<graphml" <+> xmlns <+>  +  text "xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\"" <+>+  xmlns_y <+>++  xsi_schemaLocation <>+  char '>' $+$ +  nest nestVal (+    text "<key id=\"process_type\" for=\"node\" attr.name=\"process_type\" attr.type=\"string\"/>" $+$+    text "<key id=\"value_arg\" for=\"node\" attr.name=\"value_arg\" attr.type=\"string\"/>" $+$+    text "<key id=\"procfun_arg\" for=\"node\" attr.name=\"procfun_arg\" attr.type=\"string\"/>" $+$+    text "<key id=\"instance_parent\" for=\"node\" attr.name=\"instance_parent\" attr.type=\"string\"/>" $+$+    yFilesAttribs $+$+    pprOps yFiles graph) $+$+  text "</graphml>"+ where+  -- For some silly reason, yFiles uses a different GraphML target namesapce+  -- different to the one used in grapdrawing.org's GraphML primer+  xmlns = if yFiles +    then text "xmlns=\"http://graphml.graphdrawing.org/xmlns/graphml\""+    else text "xmlns=\"http://graphml.graphdrawing.org/xmlns\""+  xmlns_y = if not yFiles then empty else+    text "xmlns:y=\"http://www.yworks.com/xml/graphml\""+  xsi_schemaLocation = if yFiles +   then text "xsi:schemaLocation=\"http://graphml.graphdrawing.org/xmlns/graphml http://www.yworks.com/xml/schema/graphml/1.0/ygraphml.xsd\""+   else   text "xsi:schemaLocation=\"http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd\"" +  yFilesAttribs = if not yFiles then empty else +   text "<key for=\"node\" id=\"d0\" yfiles.type=\"nodegraphics\"/>"  $+$+   text "<key attr.name=\"description\" attr.type=\"string\" for=\"node\" id=\"d1\"/>" $+$+   text "<key for=\"edge\" id=\"d2\" yfiles.type=\"edgegraphics\"/>" $+$+   text "<key attr.name=\"description\" attr.type=\"string\" for=\"edge\" id=\"d3\"/>" ++-------------------------+-- Tag printing functions+-------------------------+  +port :: GraphMLPortId -> Doc+port id = text "<port" <+> text ("name=\"" ++ id ++ "\"") <> text "/>"   +++process_type :: String -> Doc+process_type str = + text "<data key=\"process_type\">" <> text str <> text "</data>"   +++value_arg :: Exp -> Doc+value_arg exp = + text "<data key=\"value_arg\">" <> text (pprint exp)  <> text "</data>"   ++procfun_arg :: ProcFunAST -> Doc+-- FIXME: support default parameters+procfun_arg (ProcFunAST n cls _) = + text "<data key=\"procfun_arg\">" $+$+  nest nestVal (text $ pprint (FunD n cls)) $+$+ text "</data>"   +++instance_parent :: SysId -> Doc+instance_parent  id = + text "<data key=\"instance_parent\">" <> text id <> text "</data>"   ++-------------------------+-- Other helper functions+-------------------------++-- Location of Edge connections and node size using yFiles Markup+-- ==============================================================+-- * All Nodes (except ports, of 7x7) have a constant width of 100+-- * The height depends on the node:+--   * ConstSY has a constant height of 100 +--   * DelaySY has a constant height of 100+--   * Nodes with three lines of text (ZipWithNSY, SysIns) have a minimum of 55+--   * Nodes with two lines of text (the rest) have a minimum height of 40+--+-- ** The final height of nodes with minimum height is+--    Max(minheight, MaxS*ps)+--       where MaxS = Max(number of input signals, number of output signals)+--             ps = inter-port separation+-- ** The location where both ends of an edge is trivially calculated+--   using the order of the corresponding port, the final size of the+--   node, "bi" and "ps"++-- | port separation space when connecting to a node which surpasses the +--   minimum height+portSep :: Float +portSep = 15++-- | Calculate the dimensions of a Node+nodeDims :: GraphMLNode  -> (Float, Float) -- ^ Node dimensions (x,y)+nodeDims node = case node of+   OutNode _ _ -> (7,7)+   ProcNode n _ ->+      case n of+       InPort _ -> (7,7)+       Proc _ n' ->+         case n' of+           Const _ -> (100,100)  +           DelaySY _ _ -> (100,100)+           ZipWithNSY _ _ -> (100, height 55 maxio)+           SysIns _ _ -> (100, height 55 maxio)+           _ -> (100, height 40 maxio)  + where height :: Float -- ^ Minimum height +              -> Int   -- ^ Max(input port number, output port number)+              -> Float -- ^ Final height+       height min maxio = max min +                              (portSep*(fromIntegral maxio))+       maxio :: Int -- ^ Max(input port number, output port number) +       maxio = uncurry max $ nIOPorts node+++-- | Calculate the number of input and output ports of a node+nIOPorts :: GraphMLNode -> (Int, Int)+nIOPorts node = +      case node of+          ProcNode ins outs -> (DF.foldr (\_ b -> b+1) 0 ins, length outs)+          OutNode _ _ -> (1,0)
+ src/ForSyDe/Backend/GraphML/Traverse.hs view
@@ -0,0 +1,139 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML.Traverse+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides specialized Netlist traversing functions aimed at+-- GraphML compilation.+-----------------------------------------------------------------------------+module ForSyDe.Backend.GraphML.Traverse + (writeGraphMLM,+  module ForSyDe.Backend.GraphML.Traverse.GraphMLM) where++import ForSyDe.Backend.GraphML.Traverse.GraphMLM+import ForSyDe.Backend.GraphML.FileIO+import ForSyDe.Backend.GraphML.AST+++import ForSyDe.System.SysDef+import ForSyDe.Netlist.Traverse+import ForSyDe.Netlist+import ForSyDe.OSharing++import Data.Traversable.GenericZipWith++import System.Directory+import System.FilePath+import Control.Monad.State+++-- | Internal GraphML-Monad version of 'ForSyDe.Backend.writeGraphML+writeGraphMLM :: GraphMLM ()+writeGraphMLM = do+    -- create and change to systemName/graphml+   rootDir <- gets (sid.globalSysDef.global)+   let graphmlDir = rootDir </> "graphml"+   liftIO $ createDirectoryIfMissing True graphmlDir+   liftIO $ setCurrentDirectory graphmlDir+   -- write the local results for the first-level entity+   writeLocalGraphMLM+   -- if we are in recursive mode, also write the local results+   -- for the rest of the subsystems+   rec <- isRecursiveSet+   when rec $ do subs <- gets (subSys.globalSysDef.global)+                 let writeSub s = +                        withLocalST (initLocalST ((readURef.unPrimSysDef) s))+                                    writeLocalGraphMLM +                 mapM_ writeSub subs+   -- go back to the original directory+   liftIO $ setCurrentDirectory (".." </> "..")+++-- | Traverse the netlist and write the local results (i.e. system graphs)+writeLocalGraphMLM :: GraphMLM ()+writeLocalGraphMLM = do+  lSysDefVal <- gets (currSysDef.local)+  let lSysDefId =  sid lSysDefVal+  debugMsg $ "Compiling system definition `" ++ lSysDefId ++ "' ...\n"+  -- Obtain the output Nodes of the system+  -- Obtain the netlist of the system definition +  let nl = netlist lSysDefVal+  -- Traverse the netlist, and get the traversing results+  intOutsInfo <- traverseGraphML nl +  LocalTravResult nodes edges <- gets (localRes.local)+  -- For each output signal, we need a node and an edge between its +  -- intermediate signal and the final output signal declared in the system +  -- interface.+  let outIds = map fst (oIface lSysDefVal)+      outNodes = map (\id -> OutNode id (id ++ "_in")) outIds+      outEdges = +         zipWith (\(IntSignalInfo n pId) id -> +                   GraphMLEdge n pId (OutNode id (id ++ "_in")) (id ++ "_in")) +                 intOutsInfo +                 outIds+ -- Generate the final Graph +      finalGraph = GraphMLGraph lSysDefId (nodes ++ outNodes) +                                          (edges ++ outEdges)  +  -- and write it to disk+  yFiles <- genyFilesMarkup+  return ()+  liftIO $ writeGraph yFiles finalGraph (lSysDefId ++ ".graphml") ++-- | Traverse the netlist of a System Definition, +--   returning the (implicit) final traversing state and a list+--   containing the 'IntSignalInfo' of each output of the system+traverseGraphML :: Netlist [] -> GraphMLM [IntSignalInfo]+traverseGraphML = traverseSEIO newGraphML defineGraphML++-- | \'new\' traversing function for the GraphML backend+newGraphML :: NlNode NlSignal -> GraphMLM [(NlNodeOut, IntSignalInfo)]+newGraphML node = do+   let id = case node of+             InPort id  -> id +             Proc pid _ -> pid+       -- node inputs+       insNode = zipWithTF (\_ n -> id ++ "_in" ++ show n) node [(1::Int)..]+       -- node outputs tagged with the edge label+       taggedOutsNode = zipWith (\t n -> (t, id ++ "_out" ++ show n)) +                                 (outTags node)+                                 [(1::Int)..] +       -- graphml node+       gMLNode = ProcNode insNode (map snd taggedOutsNode)+   return $ map (\(t,out) -> (t, IntSignalInfo gMLNode out)) taggedOutsNode     ++       ++       +-- | \'define\' traversing function for the GraphML backend+defineGraphML :: [(NlNodeOut, IntSignalInfo)] +             -> NlNode IntSignalInfo +             -> GraphMLM ()+defineGraphML outs ins = do + let id = case ins of+           InPort id  -> id +           Proc pid _ -> pid+     -- Formal input signals of the proces+     formalInL = [id ++ "_in" ++ show n | n <- [(1::Int)..]]+     -- Generate the graph node+     -- Formal output ports of the process+     outPids = map (\(_, IntSignalInfo _ pid) -> pid) outs+     -- Substitute actual inputs by formal inputs in "ins"+     insFormal = zipWithTF (\_ n -> n) ins formalInL+     node = ProcNode insFormal outPids+     -- Generate the input edges of the node +     -- Actual input signals of the process+     actualInL = arguments ins+     inEdges = zipWith (\(IntSignalInfo aN aPid) fPid  ->+                       GraphMLEdge aN aPid node fPid ) actualInL formalInL++ mapM_ addEdge inEdges+ addNode node++++
+ src/ForSyDe/Backend/GraphML/Traverse/GraphMLM.hs view
@@ -0,0 +1,247 @@+{-# LANGUAGE FlexibleContexts #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.GraphML.Traverse.GraphMLM+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- 'GraphMLM' (GraphML Monad), related types and functions+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.GraphML.Traverse.GraphMLM where++import ForSyDe.Backend.GraphML.AST++import ForSyDe.Ids+import ForSyDe.ForSyDeErr+import ForSyDe.System.SysDef (SysDefVal(..))+import ForSyDe.Netlist.Traverse (TravSEIO)++import Control.Monad.State+++--------------+-- GraphMLM --+--------------++-- | GraphMLM backend monad+type GraphMLM a = TravSEIO GraphMLTravST ContextErr a+++-------------------+-- GraphMLTravST --+-------------------++-- | GraphML traversing State. (see 'ForSyDe.Netlist.Traverse.traverseSIO')+data GraphMLTravST = GraphMLTravST+  {local  :: LocalGraphMLST,   -- Local State (related to the system currently +                               -- compiled)+   global :: GlobalGraphMLST}  -- Global state (related to all systems being +                               -- recursively compiled)   ++data LocalGraphMLST = LocalGraphMLST+   {currSysDef :: SysDefVal, -- System definition which is currently +                              -- being compiled+   context     :: Context,    -- Error Context+   localRes    :: LocalTravResult} -- Result accumulated during the +                                   -- traversal of current System Definition +                                   -- netlist+++++-- | initialize the local state+initLocalST :: SysDefVal -> LocalGraphMLST+initLocalST sysDefVal = + LocalGraphMLST sysDefVal (SysDefC (sid sysDefVal) (loc sysDefVal)) +             emptyLocalTravResult++-- | Execute certain operation with a concrete local state.+--   The initial local state is restored after the operation is executed+withLocalST :: LocalGraphMLST -> GraphMLM a -> GraphMLM a+withLocalST l' action =  do+  -- get the initial local state+  st <- get+  let l = local st+  -- set the modified state+  put st{local=l'}+  -- execute the action+  res <- action+  -- restore the initial local state+  st' <- get +  put st'{local=l}+  -- return the result+  return res++data GlobalGraphMLST = GlobalGraphMLST+  {globalSysDef :: SysDefVal,+   ops          :: GraphMLOps,   -- Compilation options+   globalRes    :: GlobalTravResult} -- Result accumulated during the +                                     -- whole compilation+    ++++-- | Empty initial traversing state+initGlobalGraphMLST :: SysDefVal -> GlobalGraphMLST+initGlobalGraphMLST  sysDefVal = +  GlobalGraphMLST sysDefVal defaultGraphMLOps emptyGlobalTravResult++-- | Empty initial traversing state +initGraphMLTravST :: SysDefVal -> GraphMLTravST+initGraphMLTravST sysDefVal = +  GraphMLTravST (initLocalST sysDefVal) (initGlobalGraphMLST sysDefVal)++-------------+-- TravResult+-------------++-- | Local result accumulated during the traversal of a netlist+data LocalTravResult = LocalTravResult +  {nodes  :: [GraphMLNode], -- generated nodes+   edges  :: [GraphMLEdge]} -- generated edges++++-- | empty local GraphML compilation result+emptyLocalTravResult :: LocalTravResult+emptyLocalTravResult = LocalTravResult [] []+++-- | Global Results accumulated throughout the whole compilation+--   (empty right now)+type GlobalTravResult = ()+++-- | empty global GraphML compilation result+emptyGlobalTravResult :: GlobalTravResult+emptyGlobalTravResult = ()+++-------------+-- GraphMLOps+-------------++-- | GraphML Compilation options+data GraphMLOps = GraphMLOps +   {debugGraphML :: GraphMLDebugLevel, +    recursivityGraphML :: GraphMLRecursivity,+    yFilesMarkup :: Bool -- ^ Generate yFiles markup? +                        }+ deriving (Eq, Show)++-- | Debug level+data GraphMLDebugLevel = GraphMLNormal | GraphMLVerbose+ deriving (Eq, Ord, Show)++-- | Print a message to stdout if in verbose mode+debugMsg :: String -> GraphMLM ()+debugMsg str = do+ debugLevel <- gets (debugGraphML.ops.global)+ when (debugLevel > GraphMLNormal) +      (liftIO $ putStr ("DEBUG: " ++ str))++-- | Recursivity, should the parent systems of system instances be compiled as +--   well?+data GraphMLRecursivity = GraphMLRecursive | GraphMLNonRecursive+ deriving (Eq, Show)++-- | Check if we are in recursive mode+isRecursiveSet :: GraphMLM Bool+isRecursiveSet = do +  recOp <- gets (recursivityGraphML.ops.global)+  return $ recOp == GraphMLRecursive++-- | Check if we want to generate yFiles markup+genyFilesMarkup :: GraphMLM Bool+genyFilesMarkup = gets (yFilesMarkup.ops.global)+++-- | Default traversing options+defaultGraphMLOps :: GraphMLOps+defaultGraphMLOps =  GraphMLOps GraphMLNormal GraphMLRecursive False+++-- | Set GraphML options inside the GraphML monad+setGraphMLOps :: GraphMLOps -> GraphMLM ()+setGraphMLOps options =  modify (\st -> st{global=(global st){ops=options}})+++----------------------------------------+-- Useful functions in the GraphML Monad+----------------------------------------++-- | Add a signal declaration to the 'LocalTravResult' in the State+addEdge :: GraphMLEdge -> GraphMLM ()+addEdge e = modify addFun + -- FIXME: use a queue for the declarations+  where addFun st = st{local=l{localRes=r{edges=edg ++ [e]}}}+         where l   = local st+               r   = localRes l+               edg = edges r +++-- | Add a statement to the 'LocalTravResult' in the State+addNode :: GraphMLNode -> GraphMLM ()+addNode node = modify addFun+ -- FIXME: use a queue for the statements+  where addFun st = st{local=l{localRes=r{nodes= nds ++ [node]}}}+         where l  = local st+               r  = localRes l+               nds = nodes r ++++-- | Lift an 'EProne' value to the GraphML monad setting current error context+--   for the error+liftEProne :: EProne a -> GraphMLM a+liftEProne ep = do+ cxt <- gets (context.local)+ either (throwError.(ContextErr cxt)) return ep++-- | Throw a ForSyDe error, setting current error context+throwFError :: ForSyDeErr -> GraphMLM a+throwFError = liftEProne.Left++++-- | Execute certain operation with a concrete process context.+--   The initial context is restored after the operation is executed+--   Note: the initial context must be a system context or 'InconsistenContexts'+--         will be raised.+withProcC :: ProcId -> GraphMLM a -> GraphMLM a+withProcC pid action = do+  -- get the initial context+  st <- get+  let l = local st+      c = context l+  -- set the modified name context+  put st{local=l{context=setProcC pid c}}+  -- execute the action+  res <- action+  -- restore the initial name context+  st' <- get+  let l' = local st'+  put st'{local=l'{context=c}}+  -- return the result+  return res+++++----------------+-- IntSignalInfo+----------------++-- | Intermediate edge information. Tag generated for each output of each+--   node found during the traversal. +-- (see ForSyDe.Netlist.Traverse.traverseSIO).+--   It contains the GraphML node identifier +--   and port identifier associated with the process output.+data IntSignalInfo = IntSignalInfo GraphMLNode   -- Source Node +                                   GraphMLPortId -- Source Port Identifier+
+ src/ForSyDe/Backend/Ppr.hs view
@@ -0,0 +1,107 @@+{-# LANGUAGE MultiParamTypeClasses, FunctionalDependencies #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Ppr+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- ForSyDe pretty-printing class and auxiliar functions.+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.Ppr where++import Text.PrettyPrint.HughesPJ++-- | Pretty printing class+class Ppr a where+ ppr :: a -> Doc++-- identity instantiation+instance Ppr Doc where+ ppr = id++-- | Pretty printing class with associated printing options+class PprOps ops toPpr | toPpr -> ops where+ -- NOTE: Would it be better to use a State Monad?+ -- i.e. pprOps :: toPpr -> State ops Doc+ pprOps :: ops -> toPpr -> Doc +++-- dot+dot :: Doc+dot = char '.'++-- One line vertical space+vSpace :: Doc+vSpace = text ""++-- Multi-line vertical space+multiVSpace :: Int -> Doc+multiVSpace  n = vcat (replicate n (text ""))  ++-- Pretty-print a list supplying the document joining function+ppr_list :: Ppr a => (Doc -> Doc -> Doc) -> [a] -> Doc+ppr_list _ []    = empty+ppr_list join (a1:rest) = go a1 rest +  where go a1 []        = ppr a1+        go a1 (a2:rest) = ppr a1 `join` go a2 rest++-- Pretty-print a list supplying the document joining function+-- (PprOps version)+pprOps_list :: PprOps ops toPpr => ops -> (Doc -> Doc -> Doc) -> [toPpr] -> Doc+pprOps_list _ _ [] = empty+pprOps_list ops join (a1:rest) = go a1 rest+ where go a1 [] = pprOps ops a1+       go a1 (a2:rest) = pprOps ops a1 `join` go a2 rest++-- | Join two documents vertically leaving n vertical spaces between them+vNSpaces :: Int -> Doc -> Doc -> Doc+vNSpaces n doc1 doc2 = doc1 $+$ +                        multiVSpace n $+$+                       doc2++-- Join two documents vertically putting a semicolon in the middle+vSemi :: Doc -> Doc -> Doc+vSemi doc1 doc2 = doc1 <> semi $+$ doc2+++-- Join two documents vertically putting a comma in the middle+vComma :: Doc -> Doc -> Doc+vComma doc1 doc2 = doc1 <> comma $+$ doc2++-- Join two documents horizontally putting a comma in the middle+hComma :: Doc -> Doc -> Doc+hComma doc1 doc2 = doc1 <> comma <+> doc2+++-- | apply sep to a list of prettyprintable elements, +--   previously interspersing commas+commaSep :: Ppr a => [a] -> Doc+commaSep = sep.(punctuate comma).(map ppr)+ ++-- | Only append if both of the documents are non-empty+($++$) :: Doc -> Doc -> Doc+d1 $++$ d2 + | isEmpty d1 || isEmpty d2 = empty+ | otherwise = d1 $+$ d2+++-- | Only append if both of the documents are non-empty+(<++>) :: Doc -> Doc -> Doc+d1 <++> d2 + | isEmpty d1 || isEmpty d2 = empty+ | otherwise = d1 <+> d2++-- | Enclose in parenthesis only if the document is non-empty+parensNonEmpty :: Doc -> Doc+parensNonEmpty doc | isEmpty doc = empty+parensNonEmpty doc = parens doc++-- | Enclose in parenthesis only if the predicate is True+parensIf :: Bool -> Doc -> Doc+parensIf p d = if p then parens d else d
+ src/ForSyDe/Backend/Simulate.hs view
@@ -0,0 +1,248 @@+{-# LANGUAGE ScopedTypeVariables #-} +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.Simulate+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell, LSTV)+--+-- This module provides the simulation backend of ForSyDe's embedded compiler+--+-- /This module is based on Lava2000/: <http://www.cs.chalmers.se/~koen/Lava/>+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.Simulate (simulate) where++import ForSyDe.OSharing+import ForSyDe.Netlist+import ForSyDe.Netlist.Traverse+import ForSyDe.System.SysDef+import ForSyDe.System.SysFun(SysFunToSimFun(..))+import ForSyDe.ForSyDeErr+import ForSyDe.Process.ProcVal++import Control.Monad (liftM, mapM_, zipWithM_)+import Data.Maybe (fromJust)+import Control.Monad.ST+import Data.STRef+import qualified Data.Traversable as DT+import Data.List (lookup, transpose)+import Data.Dynamic++-- | 'simulate' takes a system definition and generates a function +--   able simulate a System using a list-based representation +--   of its signals.+simulate :: SysFunToSimFun sysFun simFun => SysDef sysFun -> simFun+simulate sysDef = fromDynSimFun (simulateDyn (unSysDef sysDef)) []++-- FIXME: clean and document the following horrible code!++--------------------------------------+-- The following was adapted from Lava+--------------------------------------++type Var s+  = (STRef s Dynamic, STRef s (Wire s))++data Wire s+  = Wire+    { dependencies :: [Var s]+    , kick         :: ST s ()+    }++----------------------------------------------------------------+-- simulateDyn+++simulateDyn :: PrimSysDef  -> [[Dynamic]] -> [[Dynamic]]+simulateDyn pSysDef inps | any null inps = replicate outN []+   where outN = (length . oIface . readURef . unPrimSysDef) pSysDef+simulateDyn pSysDef inps = runST (+  do let sysDefVal = (readURef . unPrimSysDef) pSysDef+         sysDefInIface = iIface sysDefVal+     -- List where to store the Vars generated by delay processes+     roots <- newSTRef []+     -- Input port ids paired with a reference to each input value list+     inpPairs <- zipWithM (\(id,_) inputL -> +                            do {ref <- newSTRef inputL; return (id,ref)}) +                         sysDefInIface inps++     let -- Add a Var to the roots list +         root r =+           do rs <- readSTRef roots+              writeSTRef roots (r:rs)++         -- Create an empty var+         empty = do rval <- newSTRef (error "val?")+                    rwir <- newSTRef (error "wire?")+                    return (rval, rwir)+         new node = +           do mapM (\tag -> do {e <- empty; return (tag, e)}) (outTags node)+         newInstance varPairs node =+           let funName = "ForSyDe.Backend.Simulate.simulateDyn" +           in case node of+             InPort id ->+                 case lookup id varPairs of+                     -- FIXME: replace the Other error with a custom one+                     Nothing  -> intError funName (Other "inconsistency")+                     Just var -> return [(InPortOut, var)]+             _      -> new node+         +         -- define for the general traversal+         define  nodeVarPairs childVars = +           case (nodeVarPairs,childVars) of+            ([(InPortOut, var)], InPort name) -> do+              let inputRef = fromJust $ lookup name inpPairs+              relate var [] $+                do (curr:rest) <- readSTRef inputRef+                   writeSTRef inputRef rest+                   return curr+                   +            _ -> defineShared nodeVarPairs childVars++         -- define for instances+         defineInstance nodeVarPairs childVars = +           case (nodeVarPairs,childVars) of+            ([(InPortOut, _)], InPort _) -> return ()+            _ -> defineShared nodeVarPairs childVars+         +         -- Shared part of define define for instances and the main traversal+         defineShared  nodeVarPairs childVars = -- r s =+           case (nodeVarPairs,childVars) of+            ([(InPortOut, _)], InPort _) -> return ()++            (nodeVarPairs,+             Proc _ (SysIns pSysDef ins)) ->+               -- FIXME: ugly ugly ugly+               do let sysDefVal = (readURef . unPrimSysDef) pSysDef+                      taggedIns = zipWith (\(id,_) var -> (id,var)) +                                          (iIface sysDefVal) ins+                  sr  <- traverseST +                           (newInstance taggedIns)+                           defineInstance +                           (netlist sysDefVal)++                  let relateIns prevVar@(prevValR,_) (_,nextVar) =+                         relate nextVar [prevVar] (readSTRef prevValR)+ +                  zipWithM_ relateIns sr nodeVarPairs++            ([(DelaySYOut, nodeVar)], +             Proc _ (DelaySY (ProcVal init _) sigVar)) ->+               do valVar <- empty+                  relate valVar [] (return init)                    +                  delay nodeVar valVar sigVar+            _ ->+              do let evalPairs = eval `fmap` DT.mapM (readSTRef.fst) childVars+                     args = arguments childVars+                     relEval (tag, var) = +                         relate var args $+                            -- FIXME: remove fromJust and write a proper error+                            liftM (fromJust.(lookup tag)) evalPairs+                 mapM_ relEval  nodeVarPairs  +          where+           delay r ri@(rinit,_) r1@(pre,_) =+               do state <- newSTRef Nothing+                  r2 <- empty+                  root r2++                  relate r [ri] $+                    do ms <- readSTRef state+                       case ms of+                         Just s  -> return s+                         Nothing ->+                           do s <- readSTRef rinit+                              writeSTRef state (Just s)+                              return s++                  relate r2 [r,r1] $+                    do s <- readSTRef pre+                       writeSTRef state (Just s)+                       return s+     +     sr   <- traverseST new define (netlist sysDefVal)+     rs   <- readSTRef roots+     -- remove tags of the resulting vars (all the root nodes should only+     -- have one output and thus a must return a unique list)+     step <- drive (sr ++ rs)++     outs <- lazyloop $+       do step+          s <- DT.mapM (readSTRef . fst) sr+          return s+     -- Since the simulation is done in a per-cycle basis+     -- the results (outs) are transposed (not what we want)+     -- e.g.+     -- imagine a system whose outputs are its inputs plus 1+     -- then, for this these two inputs [[1,2,3],[4,5,6]]+     -- outs would be [[2,5],[3,6],[4,7]]+     --+     -- We need as well to check that all inputs are defined in+     -- each simulation cycle e.g. [[1,2,3],[4,5,6,7]] as input+     -- makes imposible to simulate cycle 4+     --+     -- NOTE: having to check this makes simulation really inneficient+     -- a solution would providing a cycle-based simulation input/output+     -- which wouldn't suffer from this problems+     -- Or, even better, a simulation which showed a diffierent type of output +     let inN = length sysDefInIface+         res = if inN == 0 then+                 transpose outs+               else transpose (checkIns inN (transpose inps) outs)+     return res+  )++   +-- evaluation order++relate :: Var s -> [Var s] -> ST s Dynamic -> ST s ()+relate (rval, rwir) rs f =+  do writeSTRef rwir $ +       Wire{ dependencies = rs+           , kick = do b <- f+                       writeSTRef rval b+           }++drive :: [Var s] -> ST s (ST s ())+drive [] =+  do return (return ())++drive ((_,rwir):rs) =+  do wire <- readSTRef rwir+     writeSTRef rwir (error "detected combinational loop")+     driv1 <- drive (dependencies wire)+     writeSTRef rwir $+       Wire { dependencies = [], kick = return () }+     driv2 <- drive rs+     return $+       do driv1+          kick wire+          driv2++----------------------------------------------------------------+-- helper functions++lazyloop :: ST s a -> ST s [a]+lazyloop m = +  do a  <- m+     as <- unsafeInterleaveST (lazyloop m)+     return (a:as)++-- | check that there will only be output as long as there are inputs +checkIns :: Int -- ^ number of inputs +         -> [[a]] -- ^ transposed inputs +         -> [[b]] -- ^ transposed outputs (infinitie list) +         -> [[b]] -- ^ selected outputs++-- The lazy pattern match is used to avoid evaluating the output list +-- if length i /= nIns. If that happens the input lists of simulate will +-- implicitly be simulated, and due to lack of inputs it will cause an error. +checkIns nIns (i:is) ~(o:os) |  length i == nIns = o : checkIns nIns is os  +checkIns _ _ _ = []++++
+ src/ForSyDe/Backend/VHDL.hs view
@@ -0,0 +1,90 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides the VHDL backend of ForSyDe's embedded compiler+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL + (writeVHDL, +  writeVHDLOps,+  writeAndModelsimVHDL,+  writeAndModelsimVHDLOps, +  VHDLOps(..),+  QuartusOps(..),+  QuartusAction(..),+  checkSynthesisQuartus,+  VHDLDebugLevel(..),+  VHDLRecursivity(..),+  defaultVHDLOps) where++import Control.Monad.State (evalStateT)+import qualified Language.Haskell.TH as TH++import ForSyDe.System.SysFun+import ForSyDe.ForSyDeErr+import ForSyDe.OSharing (readURef)+import ForSyDe.System.SysDef+import ForSyDe.Backend.VHDL.Traverse+import ForSyDe.Backend.VHDL.Modelsim++-- | Given a System Definition whose name is a valid VHDL _basic_ identifier +--   (call it \"A\") generate @A.vhd@ in current working directory using +--   default compilation options.+--   Imp: the input and output signal names of A must be valid VHDL identifiers+--        (basic or extended) and different to @clk@ and @reset@+--        which are reserved for the main clock and reset signals+writeVHDL :: SysDef a -> IO ()+writeVHDL = writeVHDLOps defaultVHDLOps ++-- | 'writeVHDL'-alternative which allows setting VHDL compilation options.+writeVHDLOps :: VHDLOps -> SysDef a -> IO ()+writeVHDLOps ops sysDef = do+  -- initiate the compilation State+  let sinit = initVHDLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef+  -- Compile the code+  res <- runErrorT $ evalStateT  (setVHDLOps ops >> writeVHDLM) sinit+  -- Check if the  compilation went well and print an error in case it didn't+  either printVHDLError return res++++-- | Generate a function which, given a system definition and some simulation+--   stimuli:+--    +--     (1) Writes a VHDL model of the system +--     +--     (2) Simulates the VHDL model with Modelsim getting the results back to Haskell+writeAndModelsimVHDL :: SysFunToIOSimFun sysF simF =>  +                        Maybe Int -- ^ Number of cycles to simulate+                                --   if 'Nothing' the number will be determined+                                --   by the length of the input stimulti.+                                --   Useful when the system to simulate doesn't+                                --   have inputs or the inputs provided are +                                --   infinite+                     -> SysDef sysF -- ^ system definition to simulate+                     -> simF +writeAndModelsimVHDL = writeAndModelsimVHDLOps defaultVHDLOps+++-- | 'VHDLOps'-alternative of 'writeAndModelsimVHDL', note that+--   compileModelSim will implicitly be set to True+writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => +                           VHDLOps -> Maybe Int -> SysDef sysF -> simF +writeAndModelsimVHDLOps ops mCycles sysDef = fromTHStrSimFun simIO []+ where sinit = initVHDLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef+       simVHDLM :: [[TH.Exp]] -> VHDLM [[String]] +       simVHDLM stimuli = do +         setVHDLOps ops{compileModelsim=True} +         writeVHDLM+         executeTestBenchModelsim mCycles stimuli +       simIO :: [[TH.Exp]] -> IO [[String]] +       simIO stimuli = do+         res <- runErrorT $ evalStateT (simVHDLM stimuli) sinit+         either printVHDLError return res
+ src/ForSyDe/Backend/VHDL/AST.hs view
@@ -0,0 +1,712 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.AST+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- A VHDL 93 subset AST (Abstract Syntax Tree), coded so that it can be easy +-- to extend, please see doc/VHDL/vhdl93-syntax.html as reference +-- in order to extend it (this AST is based on that grammar)+-----------------------------------------------------------------------------++-- This AST is aimed at code generation not parsing, and thus, +-- it was simplified+-- The incompatibilities or simplifications from the standard+-- are properly commented++-- FIXME: shouldn't be records used instead of bare algebraic types?+-- FIXME: shouldn't the unused type redefinitions be removed?+-- FIXME: It would maybe be a good idea to create a sequence ADT which+--        guaranteed to hold at least one element (i.e. the grammar+--        has some cases such as "choices ::= choice | {choice}"+--        which are not well represented as "[Choice]", +--        "Choices Choice  (Maybe [Choice])" is not easy to handle either+--        and thus, it was discarded.++module ForSyDe.Backend.VHDL.AST where++import Data.Char (toLower)+import Text.Regex.Posix++import ForSyDe.ForSyDeErr+++--------------------+-- VHDL identifiers+--------------------++-- VHDL identifier, use mkVHDLId to create it from a String, +-- making sure a string is a proper VHDL identifier+data VHDLId = Basic String | Extended String+ deriving Eq++-- | Obtain the String of a VHDL identifier+fromVHDLId :: VHDLId -> String+fromVHDLId (Basic    str) = str+fromVHDLId (Extended str) = '\\' :  (escapeBackslashes str) ++ "\\"+ where escapeBackslashes [] = []+       escapeBackslashes (x : xs) +        | x == '\\' = "\\\\" ++ escapeBackslashes xs+        | otherwise = x : escapeBackslashes xs+instance Show VHDLId where+ show  = show.fromVHDLId+++-- | unsafely create a basic VHDLId (without cheking if the string is correct)+unsafeVHDLBasicId :: String -> VHDLId+unsafeVHDLBasicId str = Basic str+++-- | unsafely create an exteded VHDLId (without cheking if the string is +--   correct)+unsafeVHDLExtId :: String -> VHDLId+unsafeVHDLExtId str = Extended str+++-- | Create a VHDL basic identifier from a String, previously checking if the  +--   String is correct+mkVHDLBasicId ::String -> EProne VHDLId+-- FIXME: we relax the fact that two consecutive underlines +--        are not allowed+mkVHDLBasicId [] = throwError EmptyVHDLId+mkVHDLBasicId id+  | id =~ basiIdPat && (not $ elem lowId reservedWords) = return $ Basic id+  | otherwise = throwError $ IncVHDLBasId id+ where lowId = map toLower id+       basiIdPat = "^[A-Za-z](_?[A-Za-z0-9])*$"++-- | Create a VHDL extended identifier from a String, previously checking +--   if the String is correct. The input string must not include the initial+--   and ending backslashes nad the intermediate backslashes shouldn't be escaped.+mkVHDLExtId :: String -> EProne VHDLId+mkVHDLExtId [] = throwError EmptyVHDLId+mkVHDLExtId id+ | id =~ extIdPat = return $ Extended id+ | otherwise = throwError $ IncVHDLExtId id+ where -- Regular expression pattern for extended identifiers.+       -- According to the VHDL93 standard, an extended identifier must:+       --  * Start and end with a backslash '\'+       --  * Its middle characters can be+       --    * two contiguous backslashes \\+       --    * an alphanumeric (A-Za-z0-9)+       --    * a Special Character +       --    * an Other Special Character +       --      (backslashes can only appear in pairs as indicated above)+       -- +       -- However, backslashes will be handled when printing the identifier,+       -- (an initial and ending backslash are added and the intermediate backslashes+       --  are escaped)+       --+       -- Note that we cannot use specialChars and otherSpecialChars+       -- to build the pattern because of the double-backslash rule+       -- and also, the right bracket (according to the posix+       -- standard) needs to go in the first place of a bracket+       -- expression to lose its special meaning.  Furthermore,+       -- (according to the POSIX standard as well) we also need to put+       -- '-' in the last place of the bracket expression.+   extIdPat = +     "^[]A-Za-z0-9 \"#&\\'()*+,./:;<=>_|!$%@?[^`{}~-]+$"+++-- | Unsafely append a string to a VHDL identifier (i.e. without checking if+--  the resulting identifier is valid)+unsafeIdAppend :: VHDLId -> String -> VHDLId+unsafeIdAppend (Basic id)    suffix = Basic $ id ++ suffix+unsafeIdAppend (Extended id) suffix = Extended $ id ++ suffix++-- | special characters as defined in the VHDL93 standard+specialChars :: [Char]+specialChars = ['"' , '#' , '&' , '\'' , '(' , ')' , '*' , '+' , ',',+                '-' , '.' , '/' , ':'  , ';' , '<' , '=' , '>' , '_' , '|']++-- | other special characters as defined in the VHDL93 standard+otherSpecialChars :: [Char]+otherSpecialChars =['!' , '$' , '%' , '@' , '?' , '[' , '\\' , ']',+                    '^' , '`' , '{' , '}' , '~']++-- | Reserved identifiers+reservedWords :: [String]+reservedWords = ["abs", "access", "after", "alias", "all", "and",+ "architecture", "array", "assert", "attribute", "begin", "block",+ "body", "buffer", "bus", "case", "component", "configuration",+ "constant", "disconnect", "downto", "else", "elsif", "end", "entity",+ "exit", "file", "for", "function", "generate", "generic", "group",+ "guarded", "if", "impure", "in", "inertial", "inout", "is", "label",+ "library", "linkage", "literal", "loop", "map", "mod", "nand", "new",+ "next", "nor", "not", "null", "of", "on", "open", "or", "others",+ "out", "package", "port", "postponed", "procedure", "process", "pure",+ "range", "record", "register", "reject", "rem", "report", "return",+ "rol", "ror", "select", "severity", "shared", "signal", "sla", "sll",+ "sra", "srl", "subtype", "then", "to", "transport", "type",+ "unaffected", "units", "until", "use", "variable", "wait", "when",+ "while", "with", "xnor", "xor"]+++++   ---------+   -- AST --+   ---------+++-- { } (0 or more) is expressed as [ ]+-- [ ] (optional) is expressed as Maybe+++-- design_file+-- Having ContextClauses associated to library units is messy+-- instead we only allow ContextClause for the whole design file.+-- Furthermore we incorrectly (and deliberately) accept a file with +-- no library units +data DesignFile = DesignFile [ContextItem] [LibraryUnit]  + deriving Show++-- context_item+-- We don't allow the "name1,name2,name3" syntax, only one name is allowed+--  at once+data ContextItem = Library VHDLId | Use SelectedName+ deriving Show++-- library_unit+-- We avoid adding the overhead of a PrimaryUnit and SecondaryUnit types+data LibraryUnit = LUEntity EntityDec      | +                   LUArch ArchBody         | +                   LUPackageDec PackageDec |+                   LUPackageBody PackageBody+ deriving Show++-- entity_declaration+-- No declarative nor statemet part is allowed +-- Only interface signal declarations are allowed in the port clause+data EntityDec = EntityDec VHDLId [IfaceSigDec]+ deriving Show++-- | interface_signal_declaration+-- We don't allow the "id1,id2,id3" syntax, only one identifier is allowed+--  at once+-- The Mode is mandatory+-- Bus is not allowed +-- Preasigned values are not allowed+-- Subtype indications are not allowed, just a typemark +-- Constraints are not allowed: just add a new type with the constarint+--  in ForSyDe.vhd if it is required+data IfaceSigDec = IfaceSigDec VHDLId Mode TypeMark+ deriving Show++-- | type_mark+-- We don't distinguish between type names and subtype names+-- We dont' support selected names, only simple names because we won't need+-- name selection (i.e. Use clauses will make name selection unnecesary)+type TypeMark = SimpleName+++-- | mode+-- INOUT | BUFFER | LINKAGE are not allowed+data Mode = In | Out+ deriving (Show, Eq)++-- | architecture_body +-- [ ARCHITECTURE ] and [ architecture_simple_name ] are not allowed+data ArchBody = ArchBody VHDLId VHDLName [BlockDecItem] [ConcSm]+ deriving Show++-- | package_declaration+--  [ PACKAGE ] and [ package_simple_name ] are not allowed+data PackageDec = PackageDec VHDLId [PackageDecItem]+ deriving Show+++-- | package_declarative_item+-- only type declarations, subtype declarations and subprogram specifications +-- (working as subprogram_declaration) allowed+data PackageDecItem = PDITD TypeDec | PDISD SubtypeDec | PDISS SubProgSpec+ deriving Show++-- | package_body+--  [ PACKAGE ] and [ package_simple_name ] are not allowed+data PackageBody = PackageBody VHDLId [PackageBodyDecItem]+ deriving Show++-- | only subprogram_body is allowed+type PackageBodyDecItem = SubProgBody++-- | subtype-declaration+data SubtypeDec = SubtypeDec VHDLId SubtypeIn+ deriving Show++-- | subtype_indication+--   resolution functions are not permitted+data SubtypeIn = SubtypeIn TypeMark (Maybe Constraint)+ deriving Show++-- | constraint+-- Only index constraints are allowed+type Constraint = IndexConstraint++-- | range+--   the direction must always be \"to\"+data Range = AttribRange AttribName | ToRange Expr Expr+ deriving Show++-- | index_constraint+data IndexConstraint = IndexConstraint [DiscreteRange]+ deriving Show++-- | discrete_range+--   only ranges are allowed+type DiscreteRange = Range++-- | type_declaration+-- only full_type_declarations are allowed+data TypeDec = TypeDec VHDLId TypeDef+ deriving Show++-- | type_declaration+-- only composite types and enumeration types (a specific scalar type)+data TypeDef = TDA ArrayTypeDef | TDR RecordTypeDef | TDE EnumTypeDef+ deriving Show++-- | array_type_definition+--     unconstrained_array_definition+--     constrained_array_definition+-- A TypeMark is used instead of a subtype_indication. If subtyping is required,+-- declare a subtype explicitly.  +data ArrayTypeDef = UnconsArrayDef [TypeMark] TypeMark |+                    ConsArrayDef IndexConstraint TypeMark+ deriving Show++-- | record_type_definition+-- [ record_type_simple_name ] not allowed+data RecordTypeDef = RecordTypeDef [ElementDec]+ deriving Show++-- | element_declaration +-- multi-identifier element declarations not allowed+-- element_subtype_definition is simplified to a type_mark+data ElementDec = ElementDec VHDLId TypeMark+ deriving Show++-- | enumeration_type_definition +--   enumeration literals can only be identifiers+data EnumTypeDef = EnumTypeDef [VHDLId]+ deriving Show++-- | name+-- operator_names are not allowed +data VHDLName = NSimple SimpleName     | +                NSelected SelectedName | +                NIndexed IndexedName   |+                NSlice SliceName       |+                NAttribute AttribName + deriving Show++-- | simple_name+type SimpleName = VHDLId++-- | selected_name+data SelectedName = Prefix :.: Suffix+ deriving Show++infixl :.:++-- | indexed_name+-- note that according to the VHDL93 grammar the index list cannot be empty +data IndexedName = IndexedName Prefix [Expr]+ deriving Show++-- | prefix+--  only names (no function calls)+type Prefix = VHDLName++-- | suffix+-- no character or operator symbols are accepted+data Suffix = SSimple SimpleName | All+ deriving Show+++-- | slice_name+data SliceName = SliceName Prefix DiscreteRange+ deriving Show++-- | attribute_name+--   signatures are not allowed+data AttribName = AttribName Prefix SimpleName (Maybe Expr)+ deriving Show++-- | block_declarative_item+-- Only subprogram bodies and signal declarations are allowed+data BlockDecItem = BDISPB SubProgBody | BDISD SigDec+ deriving Show+++-- | subprogram_body+-- No subprogram kind nor designator is allowed+data SubProgBody = SubProgBody SubProgSpec [SubProgDecItem] [SeqSm]+ deriving Show++-- | subprogram_declarative_item+--   only varaible declarations are allowed.+data SubProgDecItem = SPVD VarDec | SPSB SubProgBody+ deriving Show++-- | variable_declaration+--   identifier lists are not allowed+data VarDec = VarDec VHDLId SubtypeIn (Maybe Expr)+ deriving Show++-- | subprogram_specification+-- Only Functions are allowed+-- [Pure | Impure] is not allowed+-- Only an identifier is valid as the designator+-- In the formal parameter list only variable declarations are accepted  +data SubProgSpec = Function VHDLId [IfaceVarDec] TypeMark + deriving Show++-- | interface_variable_declaration+-- [variable] is not allowed+-- We don't allow the "id1,id2,id3" syntax, only one identifier is allowed+-- Mode is not allowed+-- Resolution functions and constraints are not allowed, thus a TypeMark+--  is used instead of a subtype_indication. If subtyping is required,+--  declare a subtype explicitly.+data IfaceVarDec = IfaceVarDec VHDLId TypeMark+ deriving Show++-- | sequential_statement+-- Only If, case, return, for loops, assignment, @wait for@ procedure calls+-- allowed.+-- Only for loops are allowed (thus loop_statement doesn't exist) and cannot+-- be provided labels.+-- The target cannot be an aggregate.+-- General wait statements are not allowed, only @wait for@+-- It is incorrect to have an empty [CaseSmAlt]+data SeqSm = IfSm  Expr [SeqSm] [ElseIf] (Maybe Else) |+             CaseSm Expr [CaseSmAlt]                  |+             ReturnSm (Maybe Expr)                    |+             ForSM VHDLId DiscreteRange [SeqSm]       |+             VHDLName := Expr                         |+             WaitFor Expr                             |+             SigAssign  VHDLName Wform                |+             ProcCall VHDLName [AssocElem]+ deriving Show++-- | helper type, they doesn't exist in the origianl grammar+data ElseIf = ElseIf Expr [SeqSm]+ deriving Show++-- | helper type, it doesn't exist in the origianl grammar+data Else = Else [SeqSm]+ deriving Show++-- | case_statement_alternative+-- it is incorrect to have an empty [Choice]+data CaseSmAlt = CaseSmAlt [Choice] [SeqSm]+ deriving Show++-- | choice+-- although any expression is allowed the grammar specfically only allows +-- simple_expressions (not covered in this AST) +data Choice = ChoiceE Expr | Others+ deriving Show++-- | signal_declaration+-- We don't allow the "id1,id2,id3" syntax, only one identifier is allowed+--  at once+-- Resolution functions and constraints are not allowed, thus a TypeMark+--  is used instead of a subtype_indication+-- Signal kinds are not allowed+data SigDec = SigDec VHDLId TypeMark (Maybe Expr)+ deriving Show++-- | concurrent_statement+-- only block statements, component instantiations and signal assignments +-- are allowed+data ConcSm = CSBSm BlockSm | +              CSSASm  ConSigAssignSm | +              CSISm CompInsSm  |+              CSPSm ProcSm+ deriving Show++-- | block_statement+-- Generics are not supported+-- The port_clause (with only signals) and port_map_aspect are mandatory+-- The ending [ block_label ] is not allowed+-- +data BlockSm = BlockSm Label [IfaceSigDec] PMapAspect [BlockDecItem] [ConcSm]+ deriving Show++-- | port_map_aspect+newtype PMapAspect = PMapAspect [AssocElem]+ deriving Show++-- | label+type Label = VHDLId++-- | association_element+data AssocElem = Maybe (FormalPart) :=>: ActualPart+ deriving Show++-- | formal_part+-- We only accept a formal_designator (which is a name after all),+-- in the forme of simple name (no need for selected names)   +--  "function_name ( formal_designator )" and "type_mark ( formal_designator )"+--  are not allowed+type FormalPart = SimpleName++-- | actual_part+-- We only accept an actual_designator,+--  "function_name ( actual_designator )" and "type_mark ( actual_designator )"+--  are not allowed+type ActualPart = ActualDesig++-- | actual_designator+data ActualDesig = ADName VHDLName | ADExpr Expr | Open+ deriving Show++-- | concurrent_signal_assignment_statement+-- Only conditional_signal_assignment is allowed (without options)+-- The LHS (targets) are simply signal names, no aggregates+data ConSigAssignSm = VHDLName :<==: ConWforms+ deriving Show++-- | conditional_waveforms +data ConWforms = ConWforms [WhenElse] Wform (Maybe When)  + deriving Show++-- | Helper type, it doesn't exist in the VHDL grammar+data WhenElse = WhenElse Wform Expr+ deriving Show++-- | Helper type, it doesn't exist in the VHDL grammar+newtype When = When Expr+ deriving Show++-- | waveform+-- although it is possible to leave [Expr] empty, that's obviously not+-- valid VHDL waveform+data Wform = Wform [WformElem] | Unaffected+ deriving Show++-- | waveform_element+--   Null is not accepted+data WformElem = WformElem Expr (Maybe Expr)+ deriving Show++           +-- | component_instantiation_statement+-- No generics supported+-- The port map aspect is mandatory+data CompInsSm = CompInsSm Label InsUnit PMapAspect+ deriving Show++-- | process_statement+--   The label is mandatory+--   Only simple names are accepted in the sensitivity list+--   No declarative part is allowed+data ProcSm = ProcSm Label [SimpleName] [SeqSm]+ deriving Show++-- | instantiated_unit+-- Only Entities are allowed and their architecture cannot be specified+data InsUnit = IUEntity VHDLName+ deriving Show++-----------------+-- Expression AST+-----------------++-- | expression, instead of creating an AST like the grammar +-- (see commented section below) we made our own expressions which are +-- easier to handle, but which don't don't show operand precedence+-- (that is a responsibility of the pretty printer)++data Expr = -- Logical operations+            And  Expr Expr    |+            Or   Expr Expr    |+            Xor  Expr Expr    |+            Nand Expr Expr    |+            Nor  Expr Expr    |+            Xnor Expr Expr    |+            -- Relational Operators+            Expr :=:  Expr    |+            Expr :/=: Expr    |+            Expr :<:  Expr    |+            Expr :<=: Expr    |+            Expr :>:  Expr    |+            Expr :>=: Expr    |+            -- Shift Operators+            Sll Expr Expr     |+            Srl Expr Expr     |+            Sla Expr Expr     |+            Sra Expr Expr     |+            Rol Expr Expr     |+            Ror Expr Expr     |+            -- Adding Operators+            Expr :+: Expr     |+            Expr :-: Expr     |+            Expr :&: Expr     |+            -- Sign Operators+            Neg Expr          |+            Pos Expr          |+            -- Multiplying Operators+            Expr :*: Expr     |+            Expr :/: Expr     |+            Mod  Expr Expr    |+            Rem  Expr Expr    |+            -- Miscellaneous Operators+            Expr :**: Expr    |+            Abs  Expr         |+            Not  Expr         |+            -- Primary expressions+            -- Only literals, names and function calls  are allowed+            PrimName VHDLName |+            PrimLit   Literal |+            PrimFCall FCall   |       +            -- Composite_types-related operators+            Aggregate [ElemAssoc]   -- (exp1,exp2,exp3, ...)+ deriving Show            ++-- operand precedences, according to the VHDL LRM: +--  "Where the language+--   allows a sequence of operators, operators with the same+--   precedence level are associated with their operands in textual+--   order, from left to right." In other words, they are all left associative+--+--   For example: a / b / c    = (a/b)/c+--                a and b or c  is illegal (mixing operators is not allowed+--                                          by the language and only+--                                          can avoid parenthesis in some +--                                          cases)++infixl 2 `And`, `Or`, `Xor`, `Nand`, `Nor`, `Xnor`+infixl 3 :=:, :/=:, :<:, :<=:, :>:, :>=:+infixl 4 `Sll`, `Srl`, `Sla`, `Sra`, `Rol`, `Ror`+infixl 5 :+:, :-:, :&:+infix  6 `Neg`, `Pos`  +infixl 7 :*:, :/:, `Mod`, `Rem`+infixl 8 :**:, `Abs`,  `Not` ++-- | Logical Operators precedence+logicalPrec :: Int+logicalPrec = 2++-- | Relational Operators Precedence+relationalPrec :: Int+relationalPrec = 3++-- | Shift Operators Precedence+shiftPrec :: Int+shiftPrec = 4++-- | Plus Operators precedence+plusPrec :: Int+plusPrec = 5++-- | Sign Operators Precedence+signPrec :: Int+signPrec = 6++-- | Multplying Operators Precedecne+multPrec :: Int+multPrec = 7++-- | Miscellaneous Operators Precedence+miscPrec :: Int+miscPrec = 8+++++-- | element_association+--   only one choice is allowed+data ElemAssoc = ElemAssoc (Maybe Choice) Expr+ deriving Show++-- | literal+-- Literals are expressed as a string (remember we are generating+-- code, not parsing)+type Literal = String++-- | function_call+data FCall = FCall VHDLName [AssocElem]+ deriving Show+             +            +{-++Expression AST following the grammar (discarded)++-- again, even if it possible to leave the [Relation] lists empty+-- that wouldn't be valid VHDL code+-- regading  NandExpr and NorExpr, their Relation list should +-- have a maximum size of two (i.e. NandExpr Expr (Maybe Expr))+data Expr = AndExpr  [Relation] | +            OrExpr   [Relation] |+            XorExpr  [Relation] |+            NandExpr [Relation] |+            NorExpr  [Relation] |+            XnorExpr [Relation]+ deriving Show++-- relation            +data Relation = Relation ShiftExpr  (Maybe (RelOp,ShiftExpr))+ deriving Show++-- relational_operator+data RelOp = Eq | NEq | Less | LessEq | Gter | GterEq + deriving Show ++-- shift_expression+data ShiftExpr = ShiftExpr SimpleExpr (Maybe(ShiftOp,SimpleExpr)) + deriving Show++-- simple_expression+data SimpleExpr = SimpleExpr (Maybe Sign) Term [(AddOp,Term)]+ deriving Show++-- sign+data Sign = Pos | Neg+ deriving Show++-- shift_operator+data ShiftOp = Sll | Srl | Sla | Sra | Rol | Ror+ deriving Show ++-- adding_operator+data AddOp = Plus | Minus | Concat + deriving Show++-- term+data Term = Term Factor (Maybe (MultOp, Factor))+ deriving Show++-- multiplying_operator+data MultOp = Mult | Div | Mod | Rem+ deriving Show++-- factor+data Factor = Exp Primary (Maybe (Primary)) |+              Abs Primary                   |+              Not Primary+ deriving Show++-- primary+-- Only literals, names and function calls  are allowed+data Primary = PrimName  VHDLName    |+               PrimLit   Literal |+               PrimFCall FCall+ deriving Show++-- literal+-- Literals are expressed as a string (remember we are generating+-- code, not parsing)+type Literal = String++-- function_call+data FCall = FCall VHDLName [AssocElem]+ deriving Show+-}
+ src/ForSyDe/Backend/VHDL/Constants.hs view
@@ -0,0 +1,338 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Constants+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Constants used in the VHDL backend+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Constants where++import ForSyDe.Backend.VHDL.AST++-- | Standard context clause used in all generated vhdl files. It imports+commonContextClause :: [ContextItem]+commonContextClause = +  [Library forsydeId, +   Library ieeeId,+   Use     $ NSelected (NSimple forsydeId :.: SSimple typesId) :.: All,+   Use     $ NSelected (NSimple ieeeId :.: SSimple std_logic_1164Id) :.: All,+   Use     $ NSelected (NSimple ieeeId :.: SSimple numeric_stdId) :.: All]+ where forsydeId = unsafeVHDLBasicId "forsyde" +       ieeeId = unsafeVHDLBasicId "ieee"+       typesId = unsafeVHDLBasicId "types"+       std_logic_1164Id = unsafeVHDLBasicId "std_logic_1164"+       numeric_stdId = unsafeVHDLBasicId "numeric_std"++--------------+-- Identifiers+--------------++-- | reset and clock signal identifiers in String form+resetStr, clockStr :: String+resetStr = "resetn"+clockStr = "clock"++-- | reset and clock signal identifiers in basic VHDLId form+resetId, clockId :: VHDLId+resetId = unsafeVHDLBasicId resetStr+clockId = unsafeVHDLBasicId clockStr+++-- | \"types\" identifier+typesId :: VHDLId+typesId = unsafeVHDLBasicId "types"++-- | work identifier+workId :: VHDLId+workId = unsafeVHDLBasicId "work"++-- | std identifier+stdId :: VHDLId+stdId = unsafeVHDLBasicId "std"+++-- | textio identifier+textioId :: VHDLId+textioId = unsafeVHDLBasicId "textio"++-- | range attribute identifier+rangeId :: VHDLId+rangeId = unsafeVHDLBasicId "range"+++-- | range attribute identifier+imageId :: VHDLId+imageId = unsafeVHDLBasicId "image"++-- | event attribute identifie+eventId :: VHDLId+eventId = unsafeVHDLBasicId "event"+++-- | default function identifier+defaultId :: VHDLId+defaultId = unsafeVHDLBasicId "default"+++-- AsbtExt function identifiers++-- | absent function identifier+absentId :: VHDLId+absentId = unsafeVHDLBasicId "absent"++-- | present function identifier+presentId :: VHDLId+presentId = unsafeVHDLBasicId "present"++-- | fromAbstExt function identifier+fromAbstExtId :: VHDLId+fromAbstExtId = unsafeVHDLBasicId "fromAbstExt"++-- | unsafeFromAbstExt function identifier+unsafeFromAbstExtId :: VHDLId+unsafeFromAbstExtId = unsafeVHDLBasicId "unsafeFromAbstExt"++-- | value element identifier+valueId :: VHDLId+valueId = unsafeVHDLBasicId "value"++-- | value element suffix+valueSuffix :: Suffix+valueSuffix = SSimple valueId++-- | isPresent function and element identifier+isPresentId :: VHDLId+isPresentId = unsafeVHDLBasicId "isPresent"++-- | isAbsent function identifier+isAbsentId :: VHDLId+isAbsentId = unsafeVHDLBasicId "isAbsent"++-- FSVec function identifiers++-- | ex (operator ! in original Haskell source) function identifier+exId :: VHDLId+exId = unsafeVHDLBasicId "ex"++-- | sel (function select in original Haskell source) function identifier+selId :: VHDLId+selId = unsafeVHDLBasicId "sel"+++-- | ltplus (function (<+) in original Haskell source) function identifier+ltplusId :: VHDLId+ltplusId = unsafeVHDLBasicId "ltplus"+++-- | plusplus (function (++) in original Haskell source) function identifier+plusplusId :: VHDLId+plusplusId = unsafeVHDLBasicId "plusplus"+++-- | empty function identifier+emptyId :: VHDLId+emptyId = unsafeVHDLBasicId "empty"++-- | plusgt (function (+>) in original Haskell source) function identifier+plusgtId :: VHDLId+plusgtId = unsafeVHDLBasicId "plusgt"++-- | singleton function identifier+singletonId :: VHDLId+singletonId = unsafeVHDLBasicId "singleton"++-- | length function identifier+lengthId :: VHDLId+lengthId = unsafeVHDLBasicId "length"+++-- | isnull (function null in original Haskell source) function identifier+isnullId :: VHDLId+isnullId = unsafeVHDLBasicId "isnull"+++-- | replace function identifier+replaceId :: VHDLId+replaceId = unsafeVHDLBasicId "replace"+++-- | head function identifier+headId :: VHDLId+headId = unsafeVHDLBasicId "head"+++-- | last function identifier+lastId :: VHDLId+lastId = unsafeVHDLBasicId "last"+++-- | init function identifier+initId :: VHDLId+initId = unsafeVHDLBasicId "init"+++-- | tail function identifier+tailId :: VHDLId+tailId = unsafeVHDLBasicId "tail"+++-- | take function identifier+takeId :: VHDLId+takeId = unsafeVHDLBasicId "take"+++-- | drop function identifier+dropId :: VHDLId+dropId = unsafeVHDLBasicId "drop"++-- | shiftl function identifier+shiftlId :: VHDLId+shiftlId = unsafeVHDLBasicId "shiftl"++-- | shiftr function identifier+shiftrId :: VHDLId+shiftrId = unsafeVHDLBasicId "shiftr"++-- | rotl function identifier+rotlId :: VHDLId+rotlId = unsafeVHDLBasicId "rotl"++-- | reverse function identifier+rotrId :: VHDLId+rotrId = unsafeVHDLBasicId "rotr"++-- | reverse function identifier+reverseId :: VHDLId+reverseId = unsafeVHDLBasicId "reverse"++-- | toBitVector8 function identifier+toBitVector8Id :: VHDLId+toBitVector8Id = unsafeVHDLBasicId "toBitVector8"++-- | toBitVector16 function identifier+toBitVector16Id :: VHDLId+toBitVector16Id = unsafeVHDLBasicId "toBitVector16"++-- | toBitVector32 function identifier+toBitVector32Id :: VHDLId+toBitVector32Id = unsafeVHDLBasicId "toBitVector32"+++-- | fromBitVector8 function identifier+fromBitVector8Id :: VHDLId+fromBitVector8Id = unsafeVHDLBasicId "fromBitVector8"+++-- | fromBitVector16 function identifier+fromBitVector16Id :: VHDLId+fromBitVector16Id = unsafeVHDLBasicId "fromBitVector16"+++-- | fromBitVector32 function identifier+fromBitVector32Id :: VHDLId+fromBitVector32Id = unsafeVHDLBasicId "fromBitVector32"++++-- | copy function identifier+copyId :: VHDLId+copyId = unsafeVHDLBasicId "copy"+++-- | show function identifier+showId :: VHDLId+showId = unsafeVHDLBasicId "show"+++-- | write function idenfier (from std.textio)+writeId :: VHDLId+writeId = unsafeVHDLBasicId "write"++-- | output file identifier (from std.textio)+outputId :: VHDLId+outputId = unsafeVHDLBasicId "output"++--------+-- Names+--------++defaultSN :: VHDLName+defaultSN = NSimple defaultId++------------------+-- VHDL type marks+------------------++-- | Stardard logic type mark+std_logicTM :: TypeMark+std_logicTM = unsafeVHDLBasicId "std_logic"++-- | boolean type mark+booleanTM :: TypeMark+booleanTM = unsafeVHDLBasicId "boolean"++-- | fsvec_index typemark+fsvec_indexTM :: TypeMark+fsvec_indexTM = unsafeVHDLBasicId "fsvec_index"++-- | natural typemark+naturalTM :: TypeMark+naturalTM = unsafeVHDLBasicId "natural"++-- | int32 typemark (defined in ForSyDe's VHDL library)+int64TM :: TypeMark+int64TM = unsafeVHDLBasicId "int64"++-- | int32 typemark (defined in ForSyDe's VHDL library)+int32TM :: TypeMark+int32TM = unsafeVHDLBasicId "int32"++-- | int32 typemark (defined in ForSyDe's VHDL library)+int16TM :: TypeMark+int16TM = unsafeVHDLBasicId "int16"++-- | int8 typemark (defined in ForSyDe's VHDL library)+int8TM :: TypeMark+int8TM = unsafeVHDLBasicId "int8"++-- | string typemark+stringTM :: TypeMark+stringTM = unsafeVHDLBasicId "string"++--------------+-- Expressions+--------------++-- | true expression+trueExpr :: Expr+trueExpr = PrimName (NSimple $ unsafeVHDLBasicId "true")+ +-- | false expression+falseExpr :: Expr+falseExpr = PrimName (NSimple $ unsafeVHDLBasicId "false")++-- | \'0\' bit expression+lowExpr :: Expr+lowExpr = PrimLit "'0'"++-- | \'1\' bit expression+highExpr :: Expr+highExpr = PrimLit "'1'"++-- | tup string record suffix+tupStrSuffix :: Int -> String+tupStrSuffix n = "tup_" ++ show n++-- | tup VHLID record suffix+tupVHDLIdSuffix :: Int -> VHDLId+tupVHDLIdSuffix = unsafeVHDLBasicId . tupStrSuffix++-- | tup VHDLName suffix+tupVHDLSuffix :: Int -> Suffix+tupVHDLSuffix = SSimple . tupVHDLIdSuffix
+ src/ForSyDe/Backend/VHDL/FileIO.hs view
@@ -0,0 +1,30 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.FileIO+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions working with files in the VHDL backend. +--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.FileIO (writeDesignFile) where++import ForSyDe.Backend.VHDL.AST+import ForSyDe.Backend.VHDL.Ppr() -- instances+import qualified ForSyDe.Backend.Ppr as ForSyDePpr (ppr)++import System.IO+import Text.PrettyPrint.HughesPJ++-- | Write a design file to a file in disk+writeDesignFile :: DesignFile -> FilePath -> IO ()+writeDesignFile df fp = do+  handle     <- openFile fp WriteMode+  hPutStrLn handle "-- Automatically generated by ForSyDe"+  hPutStr handle $ (renderStyle mystyle . ForSyDePpr.ppr) df+  hClose handle+ where mystyle = style{lineLength=80, ribbonsPerLine=1}
+ src/ForSyDe/Backend/VHDL/Generate.hs view
@@ -0,0 +1,713 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Generate+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions used to generate VHDL AST elements without making any +-- explicit translation.+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Generate where++import ForSyDe.Backend.VHDL.Constants+import ForSyDe.Backend.VHDL.AST+import ForSyDe.Backend.VHDL.Traverse.VHDLM++-- | Generate a list of asignments (in 'ConcSm' form) of intermediate signals+--   (first argument) to final output signals (second argument) +genOutAssigns :: [VHDLId] -> [VHDLId] -> [ConcSm]+genOutAssigns = zipWith assign+ where assign dest orig = CSSASm $ dest `genSignalAssign` orig++-- | Generate a simple signal assignment, from a VHDL identifier to a+--   VHDL identifier+genSignalAssign :: VHDLId -- ^ destination+               ->  VHDLId -- ^ origin+               ->  ConSigAssignSm+genSignalAssign dest orig = genExprAssign dest (PrimName $ NSimple orig) ++-- | Generate a function call asignment+genFCallAssign ::  VHDLId -- ^ destination signal+              ->  VHDLId -- ^ Function Name+              ->  [VHDLId] -- ^ Function formal parameters+              ->  [VHDLId] -- ^ Function actual parameters+              -> ConSigAssignSm+genFCallAssign dest fName formal actual =  + genExprAssign dest (PrimFCall $ genFCall fName formal actual)  ++-- | Generate a simple assignment from an expression to a name+genExprAssign :: VHDLId -> Expr -> ConSigAssignSm+genExprAssign dest origExpr =+   NSimple dest :<==: (ConWforms [] (Wform [WformElem origExpr Nothing]) +                       Nothing)  ++-- | Generate a system design file for a system from the global system +--   identifier,+--   local traversing results and the translated entity declaration+genSysDesignFile :: String -> EntityDec -> LocalTravResult -> DesignFile +genSysDesignFile globalSysId ent@(EntityDec id _) (LocalTravResult decs stms) = +   DesignFile contextClause [LUEntity ent, LUArch archBody]+ where archBody = ArchBody archId  (NSimple id) decs stms      +       archId = unsafeVHDLBasicId "synthesizable"+       libName = globalSysId ++ "_lib"+       libId = unsafeVHDLBasicId libName+       contextClause = commonContextClause ++ +                   [Library libId,+                    Use $ NSelected (NSimple libId :.: SSimple typesId) :.: All]++-- | Generate a library design file from the global results+genLibDesignFile :: GlobalTravResult -> DesignFile+genLibDesignFile  (GlobalTravResult typeDecs subtypeDecs subProgBodies) = +   DesignFile commonContextClause [LUPackageDec packageDec, +                                   LUPackageBody packageBody]+ where packageDec = PackageDec typesId (packageTypeDecs ++ +                                        packageSubtypeDecs +++                                        subProgSpecs)+       packageTypeDecs = map PDITD typeDecs+       packageSubtypeDecs = map PDISD subtypeDecs+       subProgSpecs = map (\(SubProgBody spec _ _) -> PDISS spec) subProgBodies+       packageBody = PackageBody typesId subProgBodies++  +-- | Generate a list of association from two lists of signal identifiers+--   The first one establishes the formal parameters+genAssocElems :: [VHDLId] -> [VHDLId] -> [AssocElem]+genAssocElems formalNames actualNames = zipWith genAssoc formalNames actualNames++-- | Generate a port map from two lists of signal identifiers+--   The first list establishes the formal parameters+genPMap :: [VHDLId] -> [VHDLId] -> PMapAspect+genPMap formalIds actualIds = +  PMapAspect $ genAssocElems formalIds actualIds+++-- | Generate a function call from two lists of signal identifiers+--   The first list establishes the formal parameters+genFCall :: VHDLId -> [VHDLId] -> [VHDLId] -> FCall +genFCall fName formalIds actualIds = +  FCall (NSimple fName) $ zipWith genAssoc formalIds actualIds+  ++-- | Generate a function call from the Function Name and a list of expressions+--   (its arguments)+genExprFCall :: VHDLId -> [Expr] -> Expr+genExprFCall fName args = +   PrimFCall $ FCall (NSimple fName)  $+             map (\exp -> Nothing :=>: ADExpr exp) args++-- | version of genExprFCall which requires exactly n arguments+genExprFCallN :: VHDLId -> Int -> [Expr] -> Expr+genExprFCallN fName n args = genExprFCall fName (takeExactly n args)+ where takeExactly 0 [] = []+       takeExactly n (x:xs) | n > 0 = x : takeExactly (n-1) xs+       takeExactly _ _ = error "takeExactly: non exact length of input list"++-- | Generate a function call from the Function Name (constant function)+genExprFCall0 :: VHDLId -> Expr+genExprFCall0 fName = genExprFCall fName []++-- | List version of genExprFCall0+genExprFCall0L :: VHDLId -> [Expr] -> Expr+genExprFCall0L fName [] = genExprFCall fName []+genExprFCall0L _ _ = error "ForSyDe.Backend.VHDL.Generate.genExprFCall0L incorrect length"++-- | Generate a function call from the Function Name and an expression argument+genExprFCall1 :: VHDLId -> Expr -> Expr+genExprFCall1 fName arg = genExprFCall fName [arg]++-- | List version of genExprFCall1+genExprFCall1L :: VHDLId -> [Expr] -> Expr+genExprFCall1L fName [arg] = genExprFCall fName [arg]+genExprFCall1L _ _ = error "ForSyDe.Backend.VHDL.Generate.genExprFCall1L incorrect length"++-- | Generate a function call from the Function Name and two expression arguments+genExprFCall2 :: VHDLId -> Expr -> Expr -> Expr+genExprFCall2 fName arg1 arg2 = genExprFCall fName [arg1,arg2]++-- | List version of genExprFCall2+genExprFCall2L :: VHDLId -> [Expr] -> Expr+genExprFCall2L fName [arg1, arg2] = genExprFCall fName [arg1,arg2]+genExprFCall2L _ _ = error "ForSyDe.Backend.VHDL.Generate.genExprFCall2L incorrect length"++-- | Generate a function call from the Function Name and two expression arguments+genExprFCall4 :: VHDLId -> Expr -> Expr -> Expr -> Expr -> Expr+genExprFCall4 fName arg1 arg2 arg3 arg4 = + genExprFCall fName [arg1,arg2,arg2,arg3,arg4]+++-- | List version of genExprFCall4+genExprFCall4L :: VHDLId -> [Expr] -> Expr+genExprFCall4L fName [arg1, arg2, arg3, arg4] = + genExprFCall fName [arg1,arg2,arg2,arg3,arg4]+genExprFCall4L _ _ = error "ForSyDe.Backend.VHDL.Generate.genExprFCall4L incorrect length"++-- | Generate a procedure call from the Function Name and a list of expressions+--   (its arguments)+genExprProcCall :: VHDLId -> [Expr] -> SeqSm+genExprProcCall pName args = ProcCall (NSimple pName)  $+             map (\exp -> Nothing :=>: ADExpr exp) args+++-- | Generate a procedure call from the Function Name (constant procedure)+genExprProcCall0 :: VHDLId -> SeqSm+genExprProcCall0 fName = genExprProcCall fName []+++-- | Generate a procedure call from the Function Name and an expression argument+genExprProcCall1 :: VHDLId -> Expr -> SeqSm+genExprProcCall1 pName arg = genExprProcCall pName [arg]+++-- | Generate a procedure call from the Function Name and four expression +--   arguments+genExprProcCall2 :: VHDLId -> Expr -> Expr -> SeqSm+genExprProcCall2 pName arg1 arg2 = genExprProcCall pName [arg1,arg2]+++-- | Generate a procedure call from the Function Name and two expression +--   arguments+genExprProcCall4 :: VHDLId -> Expr -> Expr -> Expr -> Expr -> SeqSm+genExprProcCall4 pName arg1 arg2 arg3 arg4 = + genExprProcCall pName [arg1,arg2,arg2,arg3,arg4]+++-- Generate an association of a formal and actual parameter+genAssoc :: VHDLId -> VHDLId -> AssocElem+genAssoc formal actual = Just formal :=>: ADName (NSimple actual)+++-- | Generate the default functions for an unconstrained custom vector type+genUnconsVectorFuns :: TypeMark -- ^ type of the vector elements+                    -> TypeMark -- ^ type of the vector+                    -> [SubProgBody]+genUnconsVectorFuns elemTM vectorTM  = +  [SubProgBody exSpec        []                  [exExpr]                    ,+   SubProgBody selSpec       [SPVD selVar]       [selFor, selRet]            ,+   SubProgBody emptySpec     [SPVD emptyVar]     [emptyExpr]                 ,+   SubProgBody lengthSpec    []                  [lengthExpr]                ,+   SubProgBody isnullSpec    []                  [isnullExpr]                ,+   SubProgBody replaceSpec   [SPVD replaceVar]   [replaceExpr, replaceRet]   ,+   SubProgBody headSpec      []                  [headExpr]                  ,+   SubProgBody lastSpec      []                  [lastExpr]                  ,+   SubProgBody initSpec      [SPVD initVar]      [initExpr, initRet]         ,+   SubProgBody tailSpec      [SPVD tailVar]      [tailExpr, tailRet]         ,+   SubProgBody takeSpec      [SPVD takeVar]      [takeExpr, takeRet]         ,+   SubProgBody dropSpec      [SPVD dropVar]      [dropExpr, dropRet]         ,+   SubProgBody shiftlSpec    [SPVD shiftlVar]    [shiftlExpr, shiftlRet]     ,+   SubProgBody shiftrSpec    [SPVD shiftrVar]    [shiftrExpr, shiftrRet]     ,+   SubProgBody rotlSpec      [SPVD rotlVar]      [rotlExpr, rotlRet]         ,+   SubProgBody rotrSpec      [SPVD rotrVar]      [rotrExpr, rotrRet]         ,+   SubProgBody reverseSpec   [SPVD reverseVar]   [reverseFor, reverseRet]    ,+   SubProgBody copySpec      [SPVD copyVar]      [copyExpr]                  ,+   SubProgBody plusgtSpec    [SPVD plusgtVar]    [plusgtExpr, plusgtRet]     ,+   SubProgBody ltplusSpec    [SPVD ltplusVar]    [ltplusExpr, ltplusRet]     ,+   SubProgBody plusplusSpec  [SPVD plusplusVar]  [plusplusExpr, plusplusRet] ,+   SubProgBody singletonSpec [SPVD singletonVar] [singletonRet]              ,+   SubProgBody showSpec      [SPSB doShowDef]    [showRet]                   ,+   SubProgBody defaultSpec   []                  [defaultExpr]               ]+ where ixPar = unsafeVHDLBasicId "ix"+       vecPar = unsafeVHDLBasicId "vec"+       vec1Par = unsafeVHDLBasicId "vec1"+       vec2Par = unsafeVHDLBasicId "vec2"+       fPar = unsafeVHDLBasicId "f"+       nPar = unsafeVHDLBasicId "n"+       sPar = unsafeVHDLBasicId "s"+       iId = unsafeVHDLBasicId "i"+       iPar = iId+       aPar = unsafeVHDLBasicId "a"+       resId = unsafeVHDLBasicId "res"+       exSpec = Function exId [IfaceVarDec vecPar vectorTM,+                               IfaceVarDec ixPar  naturalTM] elemTM+       exExpr = +          ReturnSm (Just $ PrimName $ NIndexed +                      (IndexedName (NSimple vecPar) [PrimName $ NSimple ixPar]))+       selSpec = Function selId [IfaceVarDec fPar   naturalTM,+                                 IfaceVarDec nPar   naturalTM,+                                 IfaceVarDec sPar   naturalTM,+                                 IfaceVarDec vecPar vectorTM ] vectorTM+       -- variable res : fsvec_x (0 to n-1);+       selVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                               ((PrimName (NSimple nPar)) :-:+                                (PrimLit "1"))   ]))+                Nothing+       -- for i res'range loop+       --   res(i) := vec(f+i*s);+       -- end loop;+       selFor = ForSM iId (AttribRange $ applyRangeAttrib resId) [selAssign]+       -- res(i) := vec(f+i*s);+       selAssign = let origExp = PrimName (NSimple fPar) :+: +                                   (PrimName (NSimple iId) :*: +                                    PrimName (NSimple sPar)) in+         NIndexed (IndexedName (NSimple resId) [PrimName (NSimple iId)]) :=+         (PrimName $ NIndexed (IndexedName (NSimple vecPar) [origExp]))+       -- return res;+       selRet =  ReturnSm (Just $ PrimName (NSimple resId))+       emptySpec = Function emptyId [] vectorTM+       emptyVar = +            VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimLit "-1")]))+                Nothing+       emptyExpr = ReturnSm (Just $ PrimName (NSimple resId))+       lengthSpec = Function lengthId [IfaceVarDec vecPar vectorTM] naturalTM+       lengthExpr = ReturnSm (Just $ PrimName (NAttribute $ +                                AttribName (NSimple vecPar) lengthId Nothing))+       isnullSpec = Function isnullId [IfaceVarDec vecPar vectorTM] booleanTM+       -- return vec'length = 0+       isnullExpr = ReturnSm (Just $ +                        PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :=:+                        PrimLit "0")+       replaceSpec = Function replaceId [IfaceVarDec vecPar vectorTM,+                                         IfaceVarDec iPar   naturalTM,+                                         IfaceVarDec aPar   elemTM   ] vectorTM +       -- variable res : fsvec_x (0 to vec'length-1);+       replaceVar =+         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                                (PrimLit "1"))   ]))+                Nothing+       --  res := vec(0 to i-1) & a & vec(i+1 to length'vec-1)+       replaceExpr = NSimple resId :=+           (vecSlice (PrimLit "0") (PrimName (NSimple iPar) :-: PrimLit "1") :&:+            PrimName (NSimple aPar) :&: +             vecSlice (PrimName (NSimple iPar) :+: PrimLit "1")+                      ((PrimName (NAttribute $ +                                AttribName (NSimple vecPar) lengthId Nothing)) +                                                              :-: PrimLit "1"))+       replaceRet =  ReturnSm (Just $ PrimName $ NSimple resId)+       vecSlice init last =  PrimName (NSlice +                                        (SliceName +                                              (NSimple vecPar) +                                              (ToRange init last)))+       headSpec = Function headId [IfaceVarDec vecPar vectorTM] elemTM+       -- return vec(0);+       headExpr = ReturnSm (Just $ (PrimName $ NIndexed (IndexedName +                    (NSimple vecPar) [PrimLit "0"])))+       lastSpec = Function lastId [IfaceVarDec vecPar vectorTM] elemTM+       -- return vec(vec'length-1);+       lastExpr = ReturnSm (Just $ (PrimName $ NIndexed (IndexedName +                    (NSimple vecPar) +                    [PrimName (NAttribute $ +                                AttribName (NSimple vecPar) lengthId Nothing) +                                                             :-: PrimLit "1"])))+       initSpec = Function initId [IfaceVarDec vecPar vectorTM] vectorTM +       -- variable res : fsvec_x (0 to vec'length-2);+       initVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                                (PrimLit "2"))   ]))+                Nothing+       -- res:= vec(0 to vec'length-2)+       initExpr = NSimple resId := (vecSlice +                               (PrimLit "0") +                               (PrimName (NAttribute $ +                                  AttribName (NSimple vecPar) lengthId Nothing) +                                                             :-: PrimLit "2"))+       initRet =  ReturnSm (Just $ PrimName $ NSimple resId)+       tailSpec = Function tailId [IfaceVarDec vecPar vectorTM] vectorTM+       -- variable res : fsvec_x (0 to vec'length-2); +       tailVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                                (PrimLit "2"))   ]))+                Nothing       +       -- res := vec(1 to vec'length-1)+       tailExpr = NSimple resId := (vecSlice +                               (PrimLit "1") +                               (PrimName (NAttribute $ +                                  AttribName (NSimple vecPar) lengthId Nothing) +                                                             :-: PrimLit "1"))+       tailRet = ReturnSm (Just $ PrimName $ NSimple resId)+       takeSpec = Function takeId [IfaceVarDec nPar   naturalTM,+                                   IfaceVarDec vecPar vectorTM ] vectorTM+       -- variable res : fsvec_x (0 to n-1);+       takeVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                               ((PrimName (NSimple nPar)) :-:+                                (PrimLit "1"))   ]))+                Nothing+       -- res := vec(0 to n-1)+       takeExpr = NSimple resId := +                    (vecSlice (PrimLit "1") +                              (PrimName (NSimple $ nPar) :-: PrimLit "1"))+       takeRet =  ReturnSm (Just $ PrimName $ NSimple resId)+       dropSpec = Function dropId [IfaceVarDec nPar   naturalTM,+                                   IfaceVarDec vecPar vectorTM ] vectorTM +       -- variable res : fsvec_x (0 to vec'length-n-1);+       dropVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimName $ NSimple nPar):-: (PrimLit "1")) ]))+               Nothing+       -- res := vec(n to vec'length-1)+       dropExpr = NSimple resId := (vecSlice +                               (PrimName $ NSimple nPar) +                               (PrimName (NAttribute $ +                                  AttribName (NSimple vecPar) lengthId Nothing) +                                                             :-: PrimLit "1"))+       dropRet =  ReturnSm (Just $ PrimName $ NSimple resId)+       shiftlSpec = Function shiftlId [IfaceVarDec vecPar vectorTM,+                                       IfaceVarDec aPar   elemTM  ] vectorTM +       -- variable res : fsvec_x (0 to vec'length-1);+       shiftlVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimLit "1")) ]))+                Nothing+       -- res := a & init(vec)+       shiftlExpr = NSimple resId :=+                      (PrimName (NSimple aPar) :&:+                       genExprFCall1 initId (PrimName $ NSimple vecPar))+       shiftlRet =  ReturnSm (Just $ PrimName $ NSimple resId)       +       shiftrSpec = Function shiftrId [IfaceVarDec vecPar vectorTM,+                                       IfaceVarDec aPar   elemTM  ] vectorTM +       -- variable res : fsvec_x (0 to vec'length-1);+       shiftrVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimLit "1")) ]))+                Nothing+       -- res := tail(vec) & a+       shiftrExpr = NSimple resId :=+                      (genExprFCall1 tailId (PrimName $ NSimple vecPar) :&:+                       PrimName (NSimple aPar))+       shiftrRet =  ReturnSm (Just $ PrimName $ NSimple resId)       +       rotlSpec = Function rotlId [IfaceVarDec vecPar vectorTM] vectorTM +       -- variable res : fsvec_x (0 to vec'length-1);+       rotlVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimLit "1")) ]))+                Nothing+       -- if null(vec) then res := vec else res := last(vec) & init(vec)+       rotlExpr = IfSm (genExprFCall1 isnullId (PrimName $ NSimple vecPar)) +                       [NSimple resId := (PrimName $ NSimple vecPar)]+                       []+                       (Just $ Else [rotlExprRet])+        where rotlExprRet = +                  NSimple resId := +                          (genExprFCall1 lastId (PrimName $ NSimple vecPar) :&:+                           genExprFCall1 initId (PrimName $ NSimple vecPar))+       rotlRet =  ReturnSm (Just $ PrimName $ NSimple resId)       +       rotrSpec = Function rotrId [IfaceVarDec vecPar vectorTM] vectorTM +       -- variable res : fsvec_x (0 to vec'length-1);+       rotrVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimLit "1")) ]))+                Nothing+       -- if null(vec) then res := vec else res := tail(vec) & head(vec)+       rotrExpr = IfSm (genExprFCall1 isnullId (PrimName $ NSimple vecPar)) +                       [NSimple resId := (PrimName $ NSimple vecPar)]+                       []+                       (Just $ Else [rotrExprRet])  +        where rotrExprRet = +                  NSimple resId := +                      (genExprFCall1 lastId (PrimName $ NSimple vecPar) :&:+                       genExprFCall1 initId (PrimName $ NSimple vecPar))+       rotrRet =  ReturnSm (Just $ PrimName $ NSimple resId)       +       reverseSpec = Function reverseId [IfaceVarDec vecPar vectorTM] vectorTM+       reverseVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing) :-:+                               (PrimLit "1")) ]))+                Nothing+       -- for i in 0 to res'range loop+       --   res(vec'length-i-1) := vec(i);+       -- end loop;+       reverseFor = +          ForSM iId (AttribRange $ applyRangeAttrib resId) [reverseAssign]+       -- res(vec'length-i-1) := vec(i);+       reverseAssign = NIndexed (IndexedName (NSimple resId) [destExp]) :=+         (PrimName $ NIndexed (IndexedName (NSimple vecPar) +                              [PrimName $ NSimple iId]))+           where destExp = PrimName (NAttribute $ AttribName (NSimple vecPar) +                                      lengthId Nothing) :-: +                           PrimName (NSimple iId) :-: +                           (PrimLit "1") +       -- return res;+       reverseRet =  ReturnSm (Just $ PrimName (NSimple resId))+       copySpec = Function copyId [IfaceVarDec nPar   naturalTM,+                                      IfaceVarDec aPar   elemTM   ] vectorTM +       -- variable res : fsvec_x (0 to n-1) := (others => a);+       copyVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                               ((PrimName (NSimple nPar)) :-:+                                (PrimLit "1"))   ]))+                (Just $ Aggregate [ElemAssoc (Just Others) +                                             (PrimName $ NSimple aPar)])+       -- return res+       copyExpr = ReturnSm (Just $ PrimName $ NSimple resId)+       plusgtSpec = Function plusgtId [IfaceVarDec aPar   elemTM,+                                       IfaceVarDec vecPar vectorTM] vectorTM +       -- variable res : fsvec_x (0 to vec'length);+       plusgtVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing))]))+                Nothing+       plusgtExpr = NSimple resId := +                       ((PrimName $ NSimple aPar) :&: +                        (PrimName $ NSimple vecPar))+       plusgtRet = ReturnSm (Just $ PrimName $ NSimple resId)+       ltplusSpec = Function ltplusId [IfaceVarDec vecPar vectorTM,+                                       IfaceVarDec aPar   elemTM] vectorTM +       -- variable res : fsvec_x (0 to vec'length);+       ltplusVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing))]))+                Nothing+       ltplusExpr = NSimple resId := +                       ((PrimName $ NSimple vecPar) :&: +                        (PrimName $ NSimple aPar))+       ltplusRet = ReturnSm (Just $ PrimName $ NSimple resId)+       plusplusSpec = Function plusplusId [IfaceVarDec vec1Par vectorTM,+                                           IfaceVarDec vec2Par vectorTM  ] +                               vectorTM +       -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);+       plusplusVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0")+                            (PrimName (NAttribute $ +                              AttribName (NSimple vec1Par) lengthId Nothing) :+:+                             PrimName (NAttribute $ +                              AttribName (NSimple vec2Par) lengthId Nothing) :-:+                             PrimLit "1")]))+                Nothing+       plusplusExpr = NSimple resId := +                       ((PrimName $ NSimple vec1Par) :&: +                        (PrimName $ NSimple vec2Par))+       plusplusRet = ReturnSm (Just $ PrimName $ NSimple resId)+       singletonSpec = Function singletonId [IfaceVarDec aPar elemTM ] +                                            vectorTM+       -- variable res : fsvec_x (0 to 0) := (others => a);+       singletonVar = +         VarDec resId +                (SubtypeIn vectorTM+                  (Just $ IndexConstraint +                   [ToRange (PrimLit "0") (PrimLit "0")]))+                (Just $ Aggregate [ElemAssoc (Just Others) +                                             (PrimName $ NSimple aPar)])+       singletonRet = ReturnSm (Just $ PrimName $ NSimple resId)+       showSpec  = Function showId [IfaceVarDec vecPar vectorTM] stringTM+       doShowId  = unsafeVHDLBasicId "doshow"+       doShowDef = SubProgBody doShowSpec [] [doShowRet]+          where doShowSpec = Function doShowId [IfaceVarDec vecPar vectorTM] +                                               stringTM+                -- case vec'len is+                --  when  0 => return "";+                --  when  1 => return head(vec);+                --  when others => return show(head(vec)) & ',' &+                --                        doshow (tail(vec));+                -- end case;+                doShowRet = +                  CaseSm (PrimName (NAttribute $ +                              AttribName (NSimple vecPar) lengthId Nothing))+                  [CaseSmAlt [ChoiceE $ PrimLit "0"] +                             [ReturnSm (Just $ PrimLit "\"\"")],+                   CaseSmAlt [ChoiceE $ PrimLit "1"] +                             [ReturnSm (Just $ +                              genExprFCall1 showId +                                   (genExprFCall1 headId (PrimName $ NSimple vecPar)) )],+                   CaseSmAlt [Others] +                             [ReturnSm (Just $ +                               genExprFCall1 showId +                                 (genExprFCall1 headId (PrimName $ NSimple vecPar)) :&:+                               PrimLit "','" :&:+                               genExprFCall1 doShowId +                                 (genExprFCall1 tailId (PrimName $ NSimple vecPar)) ) ]]+       -- return '<' & doshow(vec) & '>';+       showRet =  ReturnSm (Just $ PrimLit "'<'" :&:+                                   genExprFCall1 doShowId (PrimName $ NSimple vecPar) :&:+                                   PrimLit "'>'" )+       +       defaultSpec = Function defaultId [] vectorTM+       defaultExpr = +          ReturnSm (Just $ genExprFCall0 emptyId)+    +                +-- | Generate the default functions for a custom tuple type+genTupleFuns :: [TypeMark] -- ^ type of each tuple element+             -> TypeMark -- ^ type of the tuple+             -> [SubProgBody]+genTupleFuns elemTMs tupleTM = +  [SubProgBody defaultSpec [] [defaultExpr],+   SubProgBody showSpec    [] [showExpr]]+ where tupPar = unsafeVHDLBasicId "tup" +       defaultSpec = Function defaultId [] tupleTM+       defaultExpr = +          ReturnSm (Just $ Aggregate (replicate tupSize +                                       (ElemAssoc Nothing $ PrimName defaultSN)))+       showSpec = Function showId [IfaceVarDec tupPar tupleTM ] stringTM+       -- return '(' & show(tup.+       showExpr = ReturnSm (Just $+                      PrimLit "'('" :&: showMiddle :&: PrimLit "')'")+         where showMiddle = foldr1 (\e1 e2 -> e1 :&: PrimLit "','" :&: e2) $ +                  map ((genExprFCall1 showId).+                       PrimName . +                       NSelected.+                       (NSimple tupPar:.:).+                       tupVHDLSuffix) +                      [1..tupSize]+       tupSize = length elemTMs++-- | Generate the default functions for a custom abst_ext_ type+genAbstExtFuns :: TypeMark -- ^ type of the values nested in AbstExt+             -> TypeMark -- ^ type of the extended values+             -> [SubProgBody]+genAbstExtFuns elemTM absExtTM = +  [SubProgBody defaultSpec           [] [defaultExpr],+   SubProgBody absentSpec            [] [absentExpr] ,+   SubProgBody presentSpec           [] [presentExpr],+   SubProgBody fromAbstExtSpec       [] [fromAbstExtExpr],+   SubProgBody unsafeFromAbstExtSpec [] [unsafeFromAbstExtExpr],+   SubProgBody isPresentSpec         [] [isPresentExpr],+   SubProgBody isAbsentSpec          [] [isAbsentExpr],+   SubProgBody showSpec              [] [showExpr]             ]+ where defaultPar = unsafeVHDLBasicId "default"+       extPar = unsafeVHDLBasicId "extabst"+       defaultSpec = Function defaultId [] absExtTM+       defaultExpr = +          ReturnSm (Just $ PrimName $ NSimple absentId)+       absentSpec = Function absentId [] absExtTM+       absentExpr = +          ReturnSm (Just $ Aggregate +                             [ElemAssoc Nothing falseExpr, +                              ElemAssoc Nothing $ PrimName $ defaultSN ])+       presentSpec = +          Function absentId [IfaceVarDec extPar elemTM] absExtTM+       presentExpr = +          ReturnSm (Just $ Aggregate [ElemAssoc Nothing trueExpr, +                                      ElemAssoc Nothing $ PrimName $ NSimple extPar ])+       fromAbstExtSpec = Function absentId [IfaceVarDec defaultPar elemTM,+                                            IfaceVarDec extPar     absExtTM] +                                           elemTM+       fromAbstExtExpr = +          IfSm (PrimName $ NSelected (NSimple extPar :.: SSimple isPresentId))+               [ReturnSm (Just $ PrimName $ +                 (NSelected (NSimple extPar :.: SSimple valueId)))]+               []+               (Just $ Else+                 [ReturnSm (Just $ PrimName $ NSimple defaultPar)])+       unsafeFromAbstExtSpec = +          Function absentId [IfaceVarDec extPar absExtTM] elemTM+       unsafeFromAbstExtExpr =+          ReturnSm (Just $ +                    PrimName (NSelected (NSimple extPar :.: SSimple valueId)))+       isPresentSpec = +          Function absentId [IfaceVarDec extPar absExtTM] booleanTM+       isPresentExpr =+           ReturnSm (Just $+                   PrimName (NSelected (NSimple extPar :.: SSimple isPresentId)))+       isAbsentSpec = +          Function absentId [IfaceVarDec extPar absExtTM] booleanTM+       isAbsentExpr =+           ReturnSm (Just $+             Not $ PrimName (NSelected (NSimple extPar :.: SSimple isPresentId)))+       showSpec = Function showId [IfaceVarDec extPar absExtTM ] stringTM+       -- if extabs.isPresent +       --    return "Prst " & show(extabs.value);+       -- else+       --    return "Abst";+       -- end if;  +       showExpr = +          IfSm (PrimName $ NSelected (NSimple extPar :.: SSimple isPresentId))+               [ReturnSm (Just $ PrimLit "\"Prst \"" :&:+                  genExprFCall1 showId (PrimName $ +                 (NSelected (NSimple extPar :.: SSimple valueId))))]+               []+               (Just $ Else+                 [ReturnSm (Just $ PrimLit "\"Abst\"")])++       ++-- | Generate the default functions for a custom enumeration type+genEnumAlgFuns :: TypeMark -- ^ enumeration type+             -> VHDLId -- ^ First enumeration literal of the type+             -> [SubProgBody]+genEnumAlgFuns enumTM firstLit = +  [SubProgBody defaultSpec [] [defaultExpr],+   SubProgBody showSpec [] [showExpr]]+ where enumPar = unsafeVHDLBasicId "enum"+       defaultSpec = Function defaultId [] enumTM+       defaultExpr = ReturnSm (Just $ PrimName (NSimple firstLit))+       showSpec = Function showId [IfaceVarDec enumPar enumTM] stringTM+       -- we slice the resulting image in order to eliminate the+       -- leading and trailing slashes+       -- +       -- return enumTM'image(enum)(2 to enumTM'image(enum)'length-1);+       showExpr = ReturnSm (Just $ PrimName $ NSlice $ SliceName image+                  (ToRange (PrimLit "2")+                           ((PrimName $ NAttribute $+                             AttribName image lengthId Nothing) :-:+                             PrimLit "1")))+        where image = NAttribute$ AttribName (NSimple enumTM) imageId +                                  (Just $ PrimName $ NSimple enumPar)++-- | Apply the range attribute  out of a simple name+applyRangeAttrib :: SimpleName -> AttribName+applyRangeAttrib sName = AttribName (NSimple sName) rangeId Nothing+
+ src/ForSyDe/Backend/VHDL/GlobalNameTable.hs view
@@ -0,0 +1,107 @@+{-# LANGUAGE TemplateHaskell #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.GlobalNameTable+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Global tranlsation table (symbol table) from Template Haskell Names to VHDL +-- expressions+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.GlobalNameTable (globalNameTable) where++import Data.Bits+import Language.Haskell.TH+++import ForSyDe.AbsentExt+import qualified ForSyDe.Bit as B (not)+import ForSyDe.Bit hiding (not)+import qualified ForSyDe.Backend.VHDL.AST as VHDL+import ForSyDe.Backend.VHDL.AST+import ForSyDe.Backend.VHDL.Constants+import ForSyDe.Backend.VHDL.Generate+import qualified Data.Param.FSVec as V++-- | Global tranlsation table from Template Haskell function and+-- constructor Names to VHDL expressions. The table works like this+--+-- (function, constant constructor name, (arity, function to obtain a+--                                               VHDL expression+--                                               provided its+--                                               arguments are already+--                                               translated to VHDL   ))+globalNameTable :: [(Name, (Int, [VHDL.Expr] -> VHDL.Expr ) )]+globalNameTable = [+-- Unary constructors+  ('Prst            , (1, genExprFCall1L presentId                       ) ),+-- Constant constructors+  ('True            , (0, genZeroConsCall trueExpr                       ) ),+  ('False           , (0, genZeroConsCall falseExpr                      ) ),+  ('H               , (0, genZeroConsCall highExpr                       ) ),+  ('L               , (0, genZeroConsCall lowExpr                        ) ),+  ('Abst            , (0, genZeroConsCall (PrimName $ NSimple absentId)  ) ),+-- Quaternary functions+  ('V.select        , (4, genExprFCall4L selId                           ) ),+-- Binary functions+  ('(&&)            , (2, genBinOpCall And                               ) ),+  ('(||)            , (2, genBinOpCall Or                                ) ),+  ('(.&.)           , (2, genBinOpCall And                               ) ),+  ('(.|.)           , (2, genBinOpCall Or                                ) ),+  ('xor             , (2, genBinOpCall Xor                               ) ),+  ('(==)            , (2, genBinOpCall (:=:)                             ) ),+  ('(/=)            , (2, genBinOpCall (:/=:)                            ) ),+  ('(<)             , (2, genBinOpCall (:<:)                             ) ), +  ('(<=)            , (2, genBinOpCall (:<=:)                            ) ),+  ('(>)             , (2, genBinOpCall (:>:)                             ) ),+  ('(>=)            , (2, genBinOpCall (:>=:)                            ) ),  +  ('(+)             , (2, genBinOpCall (:+:)                             ) ),+  ('(-)             , (2, genBinOpCall (:-:)                             ) ),+  ('(*)             , (2, genBinOpCall (:*:)                             ) ),+  ('div             , (2, genBinOpCall (:/:)                             ) ),+  ('mod             , (2, genBinOpCall Mod                               ) ),+  ('rem             , (2, genBinOpCall Rem                               ) ),+  ('(^)             , (2, genBinOpCall (:**:)                            ) ),+  ('(V.+>)          , (2, genExprFCall2L plusgtId                        ) ),+  ('(V.<+)          , (2, genExprFCall2L ltplusId                        ) ),+  ('(V.++)          , (2, genExprFCall2L plusplusId                      ) ),+  ('(V.!)           , (2, genExprFCall2L exId                            ) ),+  ('V.take          , (2, genExprFCall2L takeId                          ) ),+  ('V.drop          , (2, genExprFCall2L dropId                          ) ),+  ('V.shiftl        , (2, genExprFCall2L shiftlId                        ) ),+  ('V.shiftr        , (2, genExprFCall2L shiftrId                        ) ),+  ('V.copy          , (2, genExprFCall2L copyId                          ) ),+-- unary functions+  ('B.not           , (1, genUnOpCall Not                                ) ),+  ('not             , (1, genUnOpCall Not                                ) ),+  ('negate          , (1, genUnOpCall Neg                                ) ),+  ('abs             , (1, genUnOpCall Abs                                ) ),+  ('abstExt         , (1, genExprFCall1L presentId                       ) ),+  ('V.singleton     , (1, genExprFCall1L singletonId                     ) ),+  ('V.length        , (1, genExprFCall1L lengthId                        ) ),+  ('V.lengthT       , (1, genExprFCall1L lengthId                        ) ),+  ('V.genericLength , (1, genExprFCall1L lengthId                        ) ),+  ('V.null          , (1, genExprFCall1L isnullId                        ) ),+  ('V.head          , (1, genExprFCall1L headId                          ) ),+  ('V.last          , (1, genExprFCall1L lastId                          ) ),+  ('V.init          , (1, genExprFCall1L initId                          ) ),+  ('V.tail          , (1, genExprFCall1L tailId                          ) ),+  ('V.rotl          , (1, genExprFCall1L rotlId                          ) ),+  ('V.rotr          , (1, genExprFCall1L rotrId                          ) ),+  ('V.reverse       , (1, genExprFCall1L reverseId                       ) ),+  ('toBitVector8    , (1, genExprFCall1L toBitVector8Id                  ) ),+  ('toBitVector16   , (1, genExprFCall1L toBitVector16Id                 ) ),+  ('toBitVector32   , (1, genExprFCall1L toBitVector32Id                 ) ),+  ('fromBitVector8  , (1, genExprFCall1L fromBitVector8Id                ) ),+  ('fromBitVector16 , (1, genExprFCall1L fromBitVector16Id               ) ),+  ('fromBitVector32 , (1, genExprFCall1L fromBitVector32Id               ) ),+-- constants+  ('V.empty               , (0, genExprFCall0L emptyId                         ) )]+ where genBinOpCall op = \[e1, e2] -> e1 `op` e2+       genUnOpCall op = \[e] -> op e+       genZeroConsCall cons = \[] -> cons
+ src/ForSyDe/Backend/VHDL/GlobalNameTable.hs-boot view
@@ -0,0 +1,7 @@+module ForSyDe.Backend.VHDL.GlobalNameTable (globalNameTable) where+++import Language.Haskell.TH+import qualified ForSyDe.Backend.VHDL.AST as VHDL++globalNameTable :: [(Name, (Int, [VHDL.Expr] -> VHDL.Expr ) )]
+ src/ForSyDe/Backend/VHDL/Modelsim.hs view
@@ -0,0 +1,169 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Modelsim+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions to process the VHDL compilation results with Modelsim.+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Modelsim (compileResultsModelsim,+                                      executeTestBenchModelsim) where++import ForSyDe.Backend.VHDL.Traverse.VHDLM+import ForSyDe.Backend.VHDL.TestBench++import ForSyDe.System.SysDef+import ForSyDe.OSharing+import ForSyDe.ForSyDeErr+import ForSyDe.Config (getDataDir)++import Data.List (intersperse)+import System.Directory (setCurrentDirectory)+import Control.Monad (liftM, when)+import Control.Monad.State (gets)+import System.Directory (findExecutable, getTemporaryDirectory)+import System.Process (runProcess, waitForProcess)+import System.Exit (ExitCode(..))+import System.IO +import System.FilePath ((</>))+import qualified Language.Haskell.TH as TH (Exp)++-- | Generate a testbench and execute it with Modelsim+--   (Note: the initial and final CWD will be / )+executeTestBenchModelsim :: Maybe Int -- ^ Number of cycles to simulate          +                         -> [[TH.Exp]] -- ^ input stimuli, each signal value+                                       --   is expressed as a template haskell+                                       --   expression +                         -> VHDLM [[String]] -- ^ results, each signal value+                                             --   is expressed as a string+executeTestBenchModelsim mCycles stimuli= do+  cycles <- writeVHDLTestBench mCycles stimuli+  sysid <- gets (sid.globalSysDef.global)+  -- change to sysid/vhdl/+  liftIO $ setCurrentDirectory (sysid </> "vhdl")+  -- compile the testbench with modelsim+  run_vcom ["-93", "-quiet", "-nologo", "-work", "work", +            "test" </> (sysid ++ "_tb.vhd")]           +  -- execute the testbench and capture the results+  tmpdir <- liftIO getTemporaryDirectory +  (file, handle) <- liftIO $ openTempFile tmpdir "tb_out.txt"+  -- we close the temporal file to avoid opening problems with vsim on windows+  liftIO $ hClose handle +  run_vsim ["-c", "-std_output", file, "-quiet", +            "-do", "run " ++ show (cycles*10) ++ " ns; exit",+            "work." ++ sysid ++ "_tb"]+  handle2 <- liftIO $ openFile file ReadMode+  flatOut <- liftIO $ hGetContents handle2+  -- go back to the original directory+  liftIO $ setCurrentDirectory (".." </> "..")+  parseTestBenchOut flatOut++-- | Compile the generated VHDL code with Modelsim+--   (Note: the initial and final CWD will be /systemName/vhdl )+compileResultsModelsim :: VHDLM ()+compileResultsModelsim = do+ -- Check if modelsim is installed+ installed <- liftIO $ isModelsimInstalled+ when (not installed) (throwFError ModelsimFailed) + -- get the name of the vhdl files to compile+ sys <- gets (globalSysDef.global)+ let sysId = sid sys+     syslib = sysId ++ "_lib"+     libFile = syslib </> (syslib ++ ".vhd")+     workFiles = ("work" </> (sysId ++ ".vhd")) :+          map (("work"</>).(++".vhd").sid.readURef.unPrimSysDef)+              (subSys sys)+ -- get the modelsim directory  of ForSyDe's vhdl library+ -- (generated during installation)+ dataPath <- liftIO $ getDataDir++ -- map the directory to the logical name forsyde+ let modelsimForSyDe = dataPath </> "lib" </> "modelsim"+ run_vmap ["forsyde", modelsimForSyDe]+ + -- compile the library of current model+ let modelsimLib = syslib </> "modelsim"+ run_vlib [modelsimLib]+ run_vcom ["-93", "-quiet", "-nologo", "-work", modelsimLib, libFile]+ -- map the directory of the library to its logical name+ run_vmap [syslib, modelsimLib]+ + -- compile the work files+ -- NOTE: Since vcom doesn't figure out+ --       the compilation order (according to compoment dependencies),+ --       we first compile the entities and then the architectures.+ --       Another option would be keeping a dependency tree in SysDef+ --       and execute vcom using a depth search (currently we keep+ --       all the subsystems in a flatenned list) + let modelsimWork = "work" </> "modelsim"+ run_vlib [modelsimWork]+ run_vcom ("-93" : "-quiet" : "-nologo" : "-work" : modelsimWork : +           "-just" : "e" : workFiles)+ run_vcom ("-93" : "-quiet" : "-nologo" : "-work" : modelsimWork : +           "-just" : "a" : workFiles)+ -- map the directory work library to its logical name+ run_vmap ["work", modelsimWork]+ ++++-- | Run vlib+run_vlib :: [String] -- ^ arguments+         -> VHDLM ()+run_vlib = runModelsimCommand "vlib"++-- | Run vmap+run_vmap :: [String] -- ^ arguments+         -> VHDLM ()+run_vmap = runModelsimCommand "vmap"+++-- | Run vmap+run_vcom :: [String] -- ^ arguments+         -> VHDLM ()+run_vcom = runModelsimCommand "vcom"++-- | Run vsim+run_vsim :: [String] -- ^ arguments+         -> VHDLM ()+run_vsim = runModelsimCommand "vsim"++-- | run a ModelSim command+runModelsimCommand :: String -- ^ Command to execute +                   -> [String] -- ^ Command arguments+                   -> VHDLM ()+runModelsimCommand command args = do+  success <- liftIO $ runWait msg command args+  when (not success) (throwFError ModelsimFailed)+ where msg = "Running: " ++ command ++ " " ++ (concat $ intersperse " " args)+++-- | Run a process, previously announcing a message and waiting for it+--   to finnish its execution.+runWait :: String -- ^ message to show+        -> FilePath -- ^ command to execute +        -> [String] -- ^ command arguments+        -> IO Bool -- ^ Did the execution end succesfully?+runWait msg proc args = do+           putStrLn msg +           h <- runProcess proc args Nothing Nothing Nothing Nothing Nothing+           code <- waitForProcess h+           return $ code == ExitSuccess +++-- Look for modelsim executables+isModelsimInstalled :: IO Bool+isModelsimInstalled =  executablePresent "vlib" <&&> +                       executablePresent "vmap" <&&> +                       executablePresent "vcom" <&&>+                       executablePresent "vsim"+ where executablePresent = (liftM (maybe False (\_-> True))) .findExecutable++-- | short-circuit and for monads+(<&&>) :: Monad m => m Bool -> m Bool -> m Bool+x <&&> y = do p <- x+              if p then y else return False
+ src/ForSyDe/Backend/VHDL/Ppr.hs view
@@ -0,0 +1,480 @@+{-# LANGUAGE FlexibleInstances #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Ppr+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- VHDL pretty-printing instances.+--+-----------------------------------------------------------------------------+++-- FIXME:  we could avoid the LANGUAGE extensions by adding ppr_list to the Ppr +--         class (see Language.Haskell.TH.Ppr)++module ForSyDe.Backend.VHDL.Ppr () where++import ForSyDe.Backend.Ppr++import ForSyDe.Backend.VHDL.AST++import Text.PrettyPrint.HughesPJ hiding (Mode)+++-- | Number of spaces used for indentation+nestVal :: Int+nestVal = 5++instance Ppr a => Ppr (Maybe a) where+ ppr (Just a) = ppr a+ ppr Nothing  = empty ++instance (Ppr a, Ppr b) => Ppr (a,b) where+ ppr (a,b) = ppr a <+> ppr b++instance Ppr VHDLId where+ ppr = text.fromVHDLId+ ++instance Ppr DesignFile where+ ppr (DesignFile cx lx) = vNSpaces spaces (ppr_list ($+$) cx) +                                          (ppr_list (vNSpaces spaces) lx)  $+$+                          vSpace+  where spaces = 2+++        +instance Ppr ContextItem where+ ppr (Library id) = text "library" <+> ppr id <> semi+ ppr (Use name) = text "use" <+> ppr name <> semi+ ++instance Ppr LibraryUnit where+ ppr (LUEntity entityDec) = ppr entityDec+ ppr (LUArch archBody)  = ppr archBody+ ppr (LUPackageDec packageDec) = ppr packageDec + ppr (LUPackageBody packageBody) = ppr packageBody++instance Ppr EntityDec where+ ppr (EntityDec id ifaceSigDecs) = +  text "entity" <+> idDoc <+> text "is" $+$+     nest nestVal (ppr ifaceSigDecs) $+$+  text "end entity" <+> idDoc <> semi+  where idDoc = ppr id  ++instance Ppr [IfaceSigDec] where+-- FIXME: improve pretty printing of the+--        declarations+-- This:+-- S1 : bit+-- Ssdds : bit+-- should really be printed as+-- S1    : bit+-- Ssdds : bit+ ppr []   = empty+ ppr decs = text "port" <+> (parens (ppr_list vSemi decs) <> semi)+++instance Ppr IfaceSigDec where+ ppr (IfaceSigDec id mode typemark) = +   ppr id <+> colon <+> ppr mode <+> ppr typemark+++instance Ppr Mode where+ ppr In  = text "in"+ ppr Out = text "out"++instance Ppr ArchBody where+ ppr (ArchBody id enName decs conSms) = +  text "architecture" <+> idDoc <+> text "of" <+> ppr enName <+> text "is" $+$+    nest nestVal (ppr decs) $+$+  text "begin" $+$+    nest nestVal (ppr_list (vNSpaces 1) conSms) $+$+  text "end architecture" <+> idDoc <> semi+  where idDoc = ppr id++instance Ppr PackageDec where+ ppr (PackageDec id decs) =+  text "package" <+> idDoc <+> text "is" $+$+   vSpace $++$+   nest nestVal (ppr_list (vNSpaces 1) decs) $++$+   vSpace $+$+  text "end package" <+> idDoc <> semi+  where idDoc = ppr id ++instance Ppr PackageDecItem where+ ppr (PDITD typeDec) = ppr typeDec+ ppr (PDISD subtypeDec) = ppr subtypeDec+ ppr (PDISS subProgSpec) = ppr subProgSpec <> semi++instance Ppr PackageBody where+ ppr (PackageBody id decs) =+  text "package body" <+> idDoc <+> text "is" $+$+   vSpace $++$+   nest nestVal (ppr_list (vNSpaces 1) decs) $++$+   vSpace $+$+  text "end package body" <+> idDoc <> semi+  where idDoc = ppr id ++instance Ppr SubtypeDec where+ ppr (SubtypeDec id si) = text "subtype" <+> ppr id <+> text "is" <+> ppr si <> semi++instance Ppr SubtypeIn where+ ppr (SubtypeIn tm mCons) = ppr tm <+> (ppr mCons)+++instance Ppr Range  where+ ppr (AttribRange an) = ppr an+ ppr (ToRange exp1 exp2) = ppr exp1 <+> text "to" <+> ppr exp2+++instance Ppr IndexConstraint where+ ppr (IndexConstraint dr) = parens (ppr_list hComma dr)+ ++instance Ppr TypeDec where+ ppr (TypeDec id typeDef) = +  hang (text "type" <+> ppr id <+> text "is") nestVal (ppr typeDef <> semi)++instance Ppr TypeDef where+ ppr (TDA arrayTD) = ppr arrayTD+ ppr (TDR recordTD) = ppr recordTD+ ppr (TDE enumTD) = ppr enumTD++instance Ppr ArrayTypeDef where+ ppr (UnconsArrayDef unconsIxs elemsTM) = +   text "array" <+> parens (ppr_list hComma $ map pprUnconsRange unconsIxs) <+>+    text "of" <+> ppr elemsTM+  where pprUnconsRange tm = ppr tm <+> text "range <>"++ ppr (ConsArrayDef consIxs elemsTM) = +  text "array" <+> ppr consIxs <+> text "of" <+> ppr elemsTM ++instance Ppr RecordTypeDef where+ ppr (RecordTypeDef elementDecs) =+  text "record" <+> (ppr_list ($+$) elementDecs) $+$ +  text "end record"++instance Ppr ElementDec where+ ppr (ElementDec id tm) = ppr id <+> colon <+> ppr tm <> semi ++instance Ppr EnumTypeDef where+ ppr (EnumTypeDef ids) = lparen <> ppr_list hComma ids <> rparen++instance Ppr VHDLName where+ ppr (NSimple simple) = ppr simple+ ppr (NSelected selected) = ppr selected+ ppr (NIndexed indexed) = ppr indexed+ ppr (NSlice slice) = ppr slice + ppr (NAttribute attrib) = ppr attrib++instance Ppr SelectedName where+ ppr (prefix :.: suffix) = ppr prefix <> dot <> ppr suffix++instance Ppr Suffix where+ ppr (SSimple simpleName) = ppr simpleName+ ppr All = text "all"++instance Ppr IndexedName where+ ppr (IndexedName prefix indexList) = +  ppr prefix <> parens ( ppr_list hComma indexList )++instance Ppr SliceName where+ ppr (SliceName prefix discreteRange) = ppr prefix <> parens (ppr discreteRange)++instance Ppr AttribName where+ ppr (AttribName prefix simpleName mExpr) = +   ppr prefix <> char '\'' <> ppr simpleName <> parensNonEmpty (ppr mExpr)++instance Ppr [BlockDecItem] where+ ppr = ppr_list ($+$)++instance Ppr BlockDecItem where+ ppr (BDISPB subProgBody) = ppr subProgBody+ ppr (BDISD  sigDec)      = ppr sigDec+++instance Ppr SubProgBody where+ ppr (SubProgBody subProgSpec decItems statements) = +  ppr subProgSpec <+> text "is" $+$+    nest nestVal (ppr_list ($+$) decItems) $+$+  text "begin" $+$+    nest nestVal  (ppr_list ($+$) statements) $+$+-- TODO, show the id here+  text "end" <> semi+++instance Ppr SubProgDecItem where+ ppr (SPVD vd) = ppr vd+ ppr (SPSB sb) = ppr sb++instance Ppr VarDec where+ ppr (VarDec id st mExpr) = +    text "variable" <+> ppr id <+> colon <+> ppr st <+>+                        (text ":=" <++>  ppr mExpr) <> semi++instance Ppr SubProgSpec where+-- FIXME: improve pretty printing of the+--        declarations+-- This:+-- (S1 : bit;+--  Ssdds : bit)+-- should really be printed as+-- (S1    : bit;+--  Ssdds : bit)+ ppr (Function name decList returnType) =+    text "function"  <+> ppr name  <+> (parensNonEmpty (ppr_decs decList) $+$+                                        text "return" <+> ppr returnType)+   where ppr_decs ds = ppr_list vSemi ds++         ++instance Ppr IfaceVarDec where+ ppr (IfaceVarDec id typemark) = ppr id <+> colon <+> ppr typemark++instance Ppr SeqSm where+ ppr (IfSm  cond sms elseIfs maybeElse) = +   text "if" <+> ppr cond <+> text "then" $+$+       nest nestVal (ppr sms) $+$+   ppr elseIfs $+$+   ppr maybeElse $+$+   text "end if" <> semi+ ppr (CaseSm patern alts) = text "case" <+> ppr patern <+> text "is" $+$+                               nest nestVal (ppr alts) $+$+                            text "end case" <> semi+ ppr (ReturnSm maybeExpr) = text "return" <+> ppr maybeExpr <> semi+ ppr (ForSM id dr sms) = +   text "for" <+> ppr id <+> text "in" <+> ppr dr <+> text "loop" $+$+     nest nestVal (ppr sms) $+$+   text "end loop" <> semi+ ppr (target := orig) = ppr target <+> text ":=" <+> ppr orig <> semi+ ppr (WaitFor expr) = text "wait for" <+> ppr expr <> semi+ ppr (targ `SigAssign` orig) = ppr targ <+> text "<=" <+> ppr orig <> semi+ ppr (ProcCall name assocs) = +   ppr name <> parensNonEmpty (commaSep assocs) <> semi++instance Ppr [SeqSm] where+ ppr = ppr_list ($+$)++instance Ppr [ElseIf] where+ ppr = ppr_list ($+$)++instance Ppr ElseIf where+ ppr (ElseIf cond sms) = text "elseif" <+> ppr cond <+> text "then" $+$+                            nest nestVal (ppr sms)++instance Ppr Else where+ ppr (Else sms) = text "else" $+$+                     nest nestVal (ppr sms)+++instance Ppr [CaseSmAlt] where+ ppr = ppr_list ($+$)++instance Ppr Choice where+ ppr (ChoiceE expr) = ppr expr+ ppr Others         = text "others" ++instance Ppr CaseSmAlt where+ ppr (CaseSmAlt alts sms) = +    text "when" <+> ppr_list joinAlts alts <+> text "=>" $+$+       nest nestVal (ppr sms)+  where joinAlts a1 a2 = a1 <+> char '|' <+> a2++instance Ppr SigDec where+ ppr (SigDec id typemark mInit) = +   text "signal" <+> ppr id <+> colon <+> ppr typemark <+> +                    (text ":=" <++>  ppr mInit) <> semi++instance Ppr [ConcSm] where+ ppr = ppr_list ($$)+  +instance Ppr ConcSm where+ ppr (CSBSm blockSm) = ppr blockSm+ ppr (CSSASm conSigAssignSm) = ppr conSigAssignSm+ ppr (CSISm compInsSm) = ppr compInsSm+ ppr (CSPSm procSm) = ppr procSm++instance Ppr BlockSm where+ ppr (BlockSm label ifaceSigDecs pMapAspect blockDecItems concSms) =+   labelDoc <+> colon <+> text "block" $+$+              nest nestVal (ppr ifaceSigDecs)          $+$+              nest nestVal (ppr pMapAspect) <> semi    $+$+              nest nestVal (ppr blockDecItems)         $+$+       text "begin" $+$+              nest nestVal (ppr concSms) $+$+       text "end block" <+> labelDoc <> semi+  where labelDoc = ppr label+   ++instance Ppr PMapAspect where+ ppr (PMapAspect assocs) = text "port map" $$ +  (nest identL $ parens (ppr_list vComma assocs))+  where identL = length "port map "+         ++instance Ppr AssocElem where+ ppr (formalPart :=>: actualPart) = formalPartDoc <+> ppr actualPart+  where formalPartDoc = maybe empty (\fp -> ppr fp <+> text "=>") formalPart++instance Ppr ActualDesig where+ ppr (ADName name) = ppr name+ ppr (ADExpr expr) = ppr expr+ ppr Open          = text "open"++instance Ppr ConSigAssignSm where+ ppr (target :<==: cWforms) = ppr target <+> text "<=" <+> (ppr cWforms <> semi)+++instance Ppr ConWforms where+ ppr (ConWforms whenElses wform lastElse) = ppr_list ($+$) whenElses $+$+                                            ppr wform <+> ppr lastElse++instance Ppr WhenElse where+ ppr (WhenElse wform expr) = ppr wform <+> text "when" <+> +                             ppr expr  <+> text "else"++instance Ppr When where+ ppr (When cond) = text "when" <+> ppr cond++instance Ppr Wform where+ ppr (Wform elems) = ppr_list vComma elems+ ppr Unaffected    = text "unaffected"++instance Ppr WformElem where+ ppr (WformElem exp mAfter) = ppr exp <+> (text "after" <++> ppr mAfter)+++instance Ppr CompInsSm where+ ppr (CompInsSm label insUnit assocElems) =+   ppr label <+> colon <+> (ppr insUnit $+$+                            nest nestVal (ppr assocElems) <> semi)++instance Ppr ProcSm where+ ppr (ProcSm label sensl seqSms) =+   ppr label <+> colon <+> text "process" <+> +   parensNonEmpty (ppr_list hComma sensl) $+$+   text "begin" $+$+        nest nestVal (ppr seqSms) $+$+   text "end process" <+> labelDoc <> semi+  where labelDoc = ppr label++instance Ppr InsUnit where+ ppr (IUEntity name) = text "entity" <+> ppr name++-- FIXME, remove parenthesis according to precedence+instance Ppr Expr where+ ppr = pprExprPrec 0 ""+++-- | Prettyprint an binary infix operator +pprExprPrecInfix :: Int -- ^ Accumulated precedence value (initialized to 0)+                 -> String -- ^ Enclosing operator (initialized to \"\")+                 -> Int -- ^ Precedence of current infix operator   +                 -> Expr -- ^ lhs expression+                 -> String -- ^ operator name+                 -> Expr -- ^ rhs expression+                 -> Doc+-- To avoid priting parenthesis based on the left+-- associativity of all operators within the same precedence class, +-- the precedence passed to the left branch is curr instead of+-- curr+1.+--+-- However, the VHDL grammar sometimes doesn't allow it +-- e.g. "and a or b and d" is illegal. In fact,+-- you can only put two operators together without parenthesis+-- in some cases:+-- +-- * logical operators: "and", "or", "xor", "xnor", but cannot be mixed up.+-- * relational operators: none+-- * shift operators: none+-- * adding operators: all, can be mixed up+-- * multiplying operator: all, can be mixed up+-- * misc operator: none+--+-- Thus, we keep track of the enclosing+-- operator, and skip parenthesis according to left parsing associativity+-- in the cases stated above.+--+-- Note that we are only making use of syntactic associativity. e.g.+-- even if "+" is semantially associative: a+(b+c)=(a+b)+c,+-- we will only skip parenthesis in (a+b)+c++pprExprPrecInfix ac encop curr lhs op rhs = + parensIf (ac>curr || (ac == curr && not skipParenSameLevel)) $+   sep [pprExprPrec curr op lhs <+> text op, pprExprPrec (curr+1) op rhs]+  where skipParenSameLevel = curr == plusPrec || curr == multPrec ||+            (encop == op && op `elem` ["and","or","xor","xnor"])++-- | Prettyprint unary prefix operators+pprExprPrecPrefix :: Int -- ^ Accumulated precedence value (initialized to 0)+                  -> Int -- ^ Precedence of current infix operator+                  -> String -- ^ operator name+                  -> Expr -- ^ operator argument+                  -> Doc+pprExprPrecPrefix ac curr op arg = parensIf (ac>curr) $+  text op <+> pprExprPrec (curr+1) op arg+++-- | Prints an expression taking precedence and left associativity+--   in account+pprExprPrec :: Int  -- ^ Accumulated precedence value (initialized to 0)+            -> String -- ^ Enclosing operator+            -> Expr -- ^ Expression curently prettyprinted +            -> Doc+-- Logical operations+pprExprPrec p e (And e1 e2)  = pprExprPrecInfix p e logicalPrec e1 "and"  e2+pprExprPrec p e (Or  e1 e2)  = pprExprPrecInfix p e logicalPrec e1 "or"   e2+pprExprPrec p e (Xor e1 e2)  = pprExprPrecInfix p e logicalPrec e1 "xor"  e2+pprExprPrec p e (Nand e1 e2) = pprExprPrecInfix p e logicalPrec e1 "nand" e2+pprExprPrec p e (Nor  e1 e2) = pprExprPrecInfix p e logicalPrec e1 "nor"  e2+pprExprPrec p e (Xnor e1 e2) = pprExprPrecInfix p e logicalPrec e1 "xnor" e2+-- Relational Operators+pprExprPrec p e (e1 :=:  e2) = pprExprPrecInfix p e relationalPrec e1 "="  e2+pprExprPrec p e (e1 :/=: e2) = pprExprPrecInfix p e relationalPrec e1 "/=" e2+pprExprPrec p e (e1 :<:  e2) = pprExprPrecInfix p e relationalPrec e1 "<"  e2+pprExprPrec p e (e1 :<=: e2) = pprExprPrecInfix p e relationalPrec e1 "<=" e2+pprExprPrec p e (e1 :>:  e2) = pprExprPrecInfix p e relationalPrec e1 ">"  e2+pprExprPrec p e (e1 :>=: e2) = pprExprPrecInfix p e relationalPrec e1 ">=" e2+-- Shift Operators+pprExprPrec p e (Sll e1 e2) = pprExprPrecInfix p e shiftPrec e1 "sll" e2+pprExprPrec p e (Srl e1 e2) = pprExprPrecInfix p e shiftPrec e1 "srl" e2+pprExprPrec p e (Sla e1 e2) = pprExprPrecInfix p e shiftPrec e1 "sla" e2+pprExprPrec p e (Sra e1 e2) = pprExprPrecInfix p e shiftPrec e1 "sra" e2+pprExprPrec p e (Rol e1 e2) = pprExprPrecInfix p e shiftPrec e1 "rol" e2+pprExprPrec p e (Ror e1 e2) = pprExprPrecInfix p e shiftPrec e1 "ror" e2+-- Adding Operators+pprExprPrec p e (e1 :+: e2) = pprExprPrecInfix p e plusPrec e1 "+" e2+pprExprPrec p e (e1 :-: e2) = pprExprPrecInfix p e plusPrec e1 "-" e2+pprExprPrec p e (e1 :&: e2) = pprExprPrecInfix p e plusPrec e1 "&" e2+-- Sign Operators+pprExprPrec p _ (Neg e) = pprExprPrecPrefix p signPrec "-" e +pprExprPrec p _ (Pos e) = pprExprPrecPrefix p signPrec "+" e +-- Multiplying Operators+pprExprPrec p e (e1 :*: e2) = pprExprPrecInfix p e multPrec e1 "*" e2+pprExprPrec p e (e1 :/: e2) = pprExprPrecInfix p e multPrec e1 "/" e2+pprExprPrec p e (Mod e1 e2) = pprExprPrecInfix p e multPrec e1 "mod" e2+pprExprPrec p e (Rem e1 e2) = pprExprPrecInfix p e multPrec e1 "rem" e2+-- Miscellaneous Operators+pprExprPrec p e (e1 :**: e2) = pprExprPrecInfix p e miscPrec e1 "**" e2+pprExprPrec p _ (Abs e) = pprExprPrecPrefix p signPrec "abs" e +pprExprPrec p _ (Not e) = pprExprPrecPrefix p signPrec "not" e +-- Primary expressions+pprExprPrec _ _ (PrimName name)    = ppr name+pprExprPrec _ _ (PrimLit  lit)     = text lit+pprExprPrec _ _ (PrimFCall fCall)  = ppr fCall+-- Composite-type  expressions+pprExprPrec _ _ (Aggregate assocs) = parens (ppr_list hComma  assocs)++instance Ppr ElemAssoc where+ ppr (ElemAssoc mChoice expr) = (ppr mChoice <++> text "=>") <+> ppr expr++instance Ppr FCall where+ ppr (FCall name assocs) = +   ppr name <> parensNonEmpty (commaSep assocs)+
+ src/ForSyDe/Backend/VHDL/Quartus.hs view
@@ -0,0 +1,116 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Quartus+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions to process the VHDL compilation results with Altera's Quartus II+-- software.+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Quartus + (callQuartus) where++import ForSyDe.ForSyDeErr+import ForSyDe.Config (getDataDir)+import ForSyDe.OSharing (readURef)+import ForSyDe.System.SysDef (subSys,sid,unPrimSysDef)++import ForSyDe.Backend.VHDL.Traverse.VHDLM ++import System.IO+import System.Directory+import System.Process+import System.FilePath+import Control.Monad.State+import System.Exit (ExitCode(..))++++-- | Analyze the results with Quartus+--   (Note: the initial and final CWD will be /systemName/vhdl )+callQuartus :: VHDLM ()+callQuartus = do+ mQuartus <- gets (execQuartus.ops.global)+ -- is it necessary to call quartus?+ case mQuartus of+  Nothing -> return ()+  -- Yes, we create the tcl script and call quartus_sh checking if it+  -- exists in the system+  Just ops -> do+    mPath <- liftIO $ findExecutable "quartus_sh"+    case mPath of+     Nothing -> do liftIO $ hPutStrLn stderr "Error: quartus_sh not found"+                   throwFError QuartusFailed+     Just _ -> do contents <- gen_quartus_tcl ops+                  liftIO $ writeFile "quartus.tcl" contents+                  liftIO $ putStrLn "Running quartus_sh -t quartus.tcl"+                  code <- liftIO $ waitForProcess =<< runCommand +                                              "quartus_sh -t quartus.tcl" +                  case code of+                      ExitFailure _ -> throwFError QuartusFailed+                      _ -> return ()+  +-- | Generate the content of quartus.tcl+--   Note that, even in windows, the tcl interpreter requires pathnames+--   to use \"/\" instead of \"\\\"+gen_quartus_tcl :: QuartusOps -> VHDLM String+gen_quartus_tcl (QuartusOps act mFMax mFamDev assigs) = do+ sysName <- gets (sid.globalSysDef.global)+ dataPath <- liftIO $ getDataDir+ recursive <- isRecursiveSet+ subs <- gets (subSys.globalSysDef.global)+ let libDir = (changeSlashes dataPath) ++  "/lib"+     sysLib = sysName ++ "_lib"+ return $ unlines (+   packages +++   [projectNew    sysName] ++ +   mDefault mFMax fmax +++   mDefault mFamDev famDev +++   map mkAssig assigs +++   [topLevelEntity sysName,+   includeVHDLFile ("work/" ++ sysName ++ ".vhd") Nothing,+   includeVHDLFile ('"' : (libDir ++ "/forsyde.vhd") ++ "\"") (Just "forsyde"),+   includeVHDLFile (sysLib ++ "/" ++ sysLib ++ ".vhd") (Just sysLib)] +++   (if recursive then+     map (\s -> includeVHDLFile +               ((("work/"++).(++".vhd").sid.readURef.unPrimSysDef) s)+               Nothing) subs+     else []) +++   [actionCmd  act]+  )+ where mDefault m f = maybe [] f m+       actionCmd act = case act of+                        AnalysisAndElaboration -> +                           "execute_flow -analysis_and_elaboration"+                        AnalysisAndSynthesis ->+                           "execute_module -tool map"+                        FullCompilation ->+                           "execute_flow -compile"+       fmax max = ["set_global_assignment -name FMAX_REQUIREMENT \"" ++ +                    show max ++ " MHz\""]+       famDev (fam, mDev) = +         ["set_global_assignment -name FAMILY " ++ show fam] +++         case mDev of+           Nothing -> []+           Just dev -> ["set_global_assignment -name DEVICE " ++ show dev]+       mkAssig (vhdlPin, fpgaPin) = "set_location_assignment " ++ +                                      fpgaPin  ++ " -to " ++ vhdlPin+       packages = ["load_package project", "load_package flow"]+       includeVHDLFile :: FilePath      -- ^ system name+                       -> Maybe String  -- ^ what library to include the +                                        -- file in+                       -> String+       includeVHDLFile file mLib = +            "set_global_assignment -name VHDL_FILE " ++ file +++            maybe "" (" -library "++)  mLib+       topLevelEntity name = +         "set_global_assignment -name TOP_LEVEL_ENTITY " ++ name+       projectNew name = "project_new " ++ name ++ " -overwrite"   +       changeSlashes [] = []+       changeSlashes ('\\':xs) = '/' : changeSlashes xs+       changeSlashes (x:xs)    = x : changeSlashes xs         +
+ src/ForSyDe/Backend/VHDL/TestBench.hs view
@@ -0,0 +1,220 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.TestBench+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions used to generate a VHDL test bech.+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.TestBench + (writeVHDLTestBench,+  parseTestBenchOut) where+++import ForSyDe.Backend.VHDL.Constants+import ForSyDe.Backend.VHDL.AST+import ForSyDe.Backend.VHDL.Translate+import ForSyDe.Backend.VHDL.Traverse.VHDLM+import ForSyDe.Backend.VHDL.Generate+import ForSyDe.Backend.VHDL.FileIO++import ForSyDe.Ids+import ForSyDe.System.SysDef++import qualified Language.Haskell.TH as TH (Exp)+import Control.Monad.State+import Data.List (transpose)+import System.Directory+import System.FilePath+++-- | Parse the output of the testbench (a tab separated files)+--   into strings denoting the individual output signals+parseTestBenchOut :: String -- ^ String containing the complete output file+                  -> VHDLM [[String]] -- ^ output signal values in form +                                      --   of strings+parseTestBenchOut str = do+     outN <- gets (length.oIface.globalSysDef.global)+     case tabSeparatedRows  of+       [] -> return (replicate outN [])+       _  -> return $ transpose tabSeparatedRows+   where tabSeparatedRows = ((map (unintersperse '\t')).lines) str  +         unintersperse  _ [] = [] +         unintersperse  e (c:cs) +           -- the null check makes unintersperse imposible to define with foldr+           -- or unfoldr+           | c == e = if null cs then [[],[]]  +                                 else [] : unintersperse e cs+           | otherwise = let rest = unintersperse e cs in+                         case rest of+                              [] -> [[c]]+                              (a:as) -> (c:a):as++-- | write a test bench, using a clock cycle of 10 ns+--   (Note: the initial and final CWD will be / )+writeVHDLTestBench :: Maybe Int -- ^ Number of cycles to simulate+                                --   if 'Nothing' the number will be determined+                                --   by the length of the input stimulti.+                                --   Useful when the system to simulate doesn't+                                --   have inputs or the inputs provided are +                                --   infinite+                -> [[TH.Exp]] -- ^ Input stimuli (one list per signal)+                -> VHDLM Int -- ^ Number of cycles simulated+writeVHDLTestBench mCycles stimuli = do+ sys <- gets (globalSysDef.global)+ let sysId = sid sys+     cxt = genVHDLTestBenchContext sysId+     ent = genVHDLTestBenchEntity sysId+ (arch, cycles) <- genVHDLTestBenchArch mCycles stimuli+ let design = DesignFile cxt [LUEntity ent, LUArch arch]+     tbdir = sysId </> "vhdl" </> "test"+     tbpath = tbdir </> (sysId ++ "_tb.vhd")+ liftIO $ createDirectoryIfMissing True tbdir+ liftIO $ writeDesignFile design tbpath+ return cycles++-- | Generate the Context Clause+genVHDLTestBenchContext :: SysId -- ^ Main system Id+                        -> [ContextItem]+genVHDLTestBenchContext id = commonContextClause +++  [Library libId,+   Use     $ NSelected (NSimple libId :.: SSimple typesId)  :.: All,+   Use     $ NSelected (NSimple stdId :.: SSimple textioId) :.: All]+ where libId = unsafeVHDLBasicId (id ++ "_lib")+  +-- | Generates an empty entity fot the testbench+genVHDLTestBenchEntity :: SysId -- ^ Main system Id +                       -> EntityDec+genVHDLTestBenchEntity id = EntityDec (unsafeVHDLBasicId (id ++ "_tb")) []++--------------------------+-- Test Bench Architecture+--------------------------+++-- | generate the architecture+genVHDLTestBenchArch :: Maybe Int -- ^ Maximum number of cycles+                     -> [[TH.Exp]] -- ^ Input stimuli +                     -> VHDLM (ArchBody, Int) -- ^ Number of cycles simulated+genVHDLTestBenchArch mCycles stimuli = do+ sys <- gets (globalSysDef.global)+ let sysId    = sid sys+     iface    = iIface sys+     oface    = oIface sys+     l        = logic sys+     iIds     = map fst iface+     iVHDLIds = map unsafeVHDLExtId iIds+     oIds     = map fst oface+ -- Get the signal declarations for the input signals+ iDecs <- mapM +     (\(pId, t) -> transVHDLName2SigDec (unsafeVHDLExtId pId) t Nothing) iface+ let finalIDecs = iDecs ++ +                  [SigDec clockId std_logicTM (Just $ PrimLit "'0'"),+                   SigDec resetId std_logicTM (Just $ PrimLit "'0'")]+ -- Get the component instantiation and the signal declarations for the output+ -- signals+ (mIns, outDecs) <- +     transSysIns2CompIns l+                         (unsafeVHDLBasicId "totest") +                         iVHDLIds +                         (map (\(id, t) -> (unsafeVHDLExtId id,t)) oface)+                         sysId+                         iIds+                         oIds+ -- Generate the signal assignments+ (stimuliAssigns, cycles) <- genStimuliAssigns mCycles stimuli iVHDLIds+ -- Add an assignment to turn off the reset signal after 3 ns+ -- (everything lower than 5 ns should work)+ let finalAssigns = +      (NSimple resetId :<==: +        ConWforms [] +                  (Wform [WformElem (PrimLit "'1'") (Just $ PrimLit "3 ns")])+                  Nothing) : stimuliAssigns+ -- Get the two processes (clock and output)+     clkProc = genClkProc+     outputProc = genOutputProc (map unsafeVHDLExtId oIds)+ -- return the architecture+ return $ (ArchBody +            (unsafeVHDLBasicId "test") +            (NSimple $ unsafeVHDLBasicId (sysId ++ "_tb"))+            (map BDISD (finalIDecs ++ outDecs))+            ( maybe [] (\s -> [CSISm s]) mIns ++ +             ( (CSPSm clkProc) : (CSPSm outputProc) : (map CSSASm finalAssigns) ) ),+            cycles)++-- | generate the assignments for the input stimuli+genStimuliAssigns :: Maybe Int -- ^ Maximum number of cycles+                  -> [[TH.Exp]] -- ^ Input stimuli +                  -> [VHDLId] -- ^ Input signal ids+                  -> VHDLM ([ConSigAssignSm], Int) -- ^ (Assignments,+                                                   --    number of cycles +                                                   --    simulated)+-- if the number of input signas is zero+genStimuliAssigns mCycles [] _ = return ([], maybe 0 id mCycles)++-- if the nu,ber of input signals is /= zero+genStimuliAssigns mCycles stimuli signals = do+  let genWformElem time thExp  = +         do vExp <- transExp2VHDL thExp+            return (WformElem vExp (Just $ PrimLit (show time ++ " ns")))+  wformElems <- mapM (zipWithM  genWformElem ([0,10..] :: [Int])) stimuli+  let (normWformElems, cycles) = normalize maxCycles wformElems+  if cycles == 0 +   then return ([],0)+   else return +          (zipWith +                (\s elems -> NSimple s :<==: ConWforms [] (Wform elems) Nothing)+                signals +                normWformElems,+           cycles)+ where maxCycles = maybe (-1) id mCycles +       -- FIXME: this is not efficient at all+       -- Normalize a matrix. Make sure that all the rows in a matrix have the+       -- same length, setting a maximum row length (0 establishes no limit)+       normalize :: Int     -- ^ maximum row-length to process +                 -> [[a]]   -- ^ input matrix+                 -> ([[a]], Int) -- ^ (output matrix, maximum row length)+       normalize max xss+         | any null xss || max == 0 = (replicate l [], 0)+         | otherwise = let (transres, acum) = normalize' max (transpose xss)+      	      	       in (transpose transres, acum)+        where l = length xss+              normalize' max (xs:xss)+                 | length xs == l && max /= 0 =+                     let (nextlist, nextacum) = normalize' (max-1)  xss+                     in (xs : nextlist, nextacum+1)+              normalize' _ _ = ([], 0)++-- | generates a clock process with a period of 10ns+genClkProc :: ProcSm+genClkProc = ProcSm (unsafeVHDLBasicId "clkproc") [] sms+ where sms = -- wait for 5 ns -- (half a cycle)+             [WaitFor $ PrimLit "5 ns",+              -- clk <= not clk;+              NSimple clockId `SigAssign` +                 Wform [WformElem (Not (PrimName $ NSimple clockId)) Nothing]]++-- | generate the output process+genOutputProc :: [VHDLId] -- ^ output signals+              -> ProcSm  +genOutputProc outs = +  ProcSm (unsafeVHDLBasicId "writeoutput") +         [clockId]+         [IfSm clkPred (writeOuts outs) [] Nothing]+ where clkPred = PrimName (NAttribute $ AttribName (NSimple clockId) +                                                   eventId+                                                   Nothing          ) `And` +                 (PrimName (NSimple clockId) :=: PrimLit "'1'")+       writeOuts []  = []+       writeOuts [i] = [writeOut i (PrimLit "LF")]+       writeOuts (i:is) = writeOut i (PrimLit "HT") : writeOuts is+       writeOut outSig suffix = +         genExprProcCall2 writeId +                          (PrimName $ NSimple outputId)+                          (genExprFCall1 showId (PrimName $ NSimple outSig) :&: +                           suffix)
+ src/ForSyDe/Backend/VHDL/Translate.hs view
@@ -0,0 +1,827 @@+{-# LANGUAGE TemplateHaskell, TypeOperators #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Traverse+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Functions to translate elements of the intermediate system +-- representation to elements of the VHDL AST.+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Translate where++import ForSyDe.Backend.VHDL.AST+import qualified ForSyDe.Backend.VHDL.AST as VHDL+import ForSyDe.Backend.VHDL.Constants+import ForSyDe.Backend.VHDL.Generate+import ForSyDe.Backend.VHDL.Traverse.VHDLM++import ForSyDe.Ids+import ForSyDe.AbsentExt+import ForSyDe.Signal+import ForSyDe.Bit hiding (not)+import qualified ForSyDe.Bit as B+import ForSyDe.ForSyDeErr+import ForSyDe.System.SysDef+import ForSyDe.Process.ProcFun+import ForSyDe.Process.ProcVal+import ForSyDe.Process.ProcType++import Data.Typeable.TypeRepLib (unArrowT)++import Data.Int+import Data.Char (digitToInt)+import Data.List (intersperse)+import Data.Maybe (isJust, fromJust)+import Control.Monad.State+import qualified Data.Set as S+import qualified Language.Haskell.TH as TH+import Language.Haskell.TH hiding (global)+import qualified Data.Traversable as DT+import Data.Typeable+import qualified Data.Param.FSVec as V+import Text.Regex.Posix ((=~))++import Data.TypeLevel.Num.Reps++-- | Translate a System Definition to an Entity, explicitly returning+--   the VHDL identifiers of its output signals.+transSysDef2Ent :: SysLogic -- ^ logic of the system +                -> SysDefVal -- ^ system to translate +                -> VHDLM EntityDec+transSysDef2Ent logic sysDefVal = do+ entId <- transSysId2VHDL (sid sysDefVal)+ inDecs  <- mapM (uncurry $ transPort2IfaceSigDec In)  (iIface sysDefVal) + outDecs <- mapM (uncurry $ transPort2IfaceSigDec Out) (oIface sysDefVal)+ -- clock and reset implicit declarations+ let implicitDecs = if logic == Sequential then +                     [IfaceSigDec resetId In std_logicTM, +                      IfaceSigDec clockId In std_logicTM]+                     else []+ return $ EntityDec entId (implicitDecs ++ inDecs ++ outDecs) + +-- | Translate a 'ZipwithNSY' process to a block returning a declaration of+--   the resulting signal.+transZipWithN2Block :: Label -- ^ process identifier+                    -> [VHDLId] -- ^ input signals+                    -> Loc -- ^ location of the inner function+                    -> TypedProcFunAST -- ^ AST of the inner function+                    -> VHDLId -- ^ output signal+                    -> VHDLM (BlockSm, SigDec)+transZipWithN2Block vPid ins loc ast out = do+ -- Translate the process function+ (f,fName , inFPars, inFTypes, retFType) <- +        withProcFunC ((name.tpast) ast) loc $ transProcFun2VHDL ast + -- Generate the formal parameters of the block+ let inPars = map (\n -> unsafeIdAppend vPid ("_in" ++ show n)) [1..length ins]+     outPar = unsafeIdAppend vPid "_out"+ -- Generate the port interface of the block     +     inDecs = zipWith (\par typ -> IfaceSigDec par In typ) inPars inFTypes+     outDec = IfaceSigDec outPar Out retFType+     iface = inDecs ++ [outDec]+ -- Generate the port map+     pMap = genPMap  (inPars ++ [outPar]) (ins ++ [out])+ -- Generate the function call and signal assignment+     outAssign = genFCallAssign out fName inFPars ins+ return  (BlockSm vPid iface pMap [BDISPB f] [CSSASm outAssign],+          SigDec out retFType Nothing)++ +-- | Translate a 'ZipwithxSY' process to a block returning a declaration of+--   the resulting signal.+transZipWithx2Block :: Label -- ^ process identifier+                    -> [VHDLId] -- ^ input signals+                    -> Loc -- ^ location of the inner function+                    -> TypedProcFunAST -- ^ AST of the inner function+                    -> VHDLId -- ^ output signal+                    -> VHDLM (BlockSm, SigDec)+transZipWithx2Block vPid ins loc ast out = do+ -- Translate the process function+ (f, fName, [inFPar], [inFType], retFType) <- +        withProcFunC ((name.tpast) ast) loc $ transProcFun2VHDL ast+ -- Figure out the type of the inputs from the + -- function's input vector type (horrible hack, but it works)+ let [[_,suffix]] = (fromVHDLId inFType) =~ "^fsvec_[0-9]*_(.*)$" +     inType = unsafeVHDLBasicId $ suffix+ -- Generate the formal parameters of the block+     inPars = map (\n -> unsafeIdAppend vPid ("_in" ++ show n)) [1..length ins]+     outPar = unsafeIdAppend vPid "_out"+ -- Generate the port interface of the block     +     inDecs = map (\par -> IfaceSigDec par In inType) inPars+     outDec = IfaceSigDec outPar Out retFType+     iface = inDecs ++ [outDec]+ -- Generate the port map+     pMap = genPMap  (inPars ++ [outPar]) (ins ++ [out])+ -- Generate the function call and signal assignment+     aggregate = Aggregate $+                  map (\e -> ElemAssoc Nothing (PrimName(NSimple e))) inPars +     fCall = PrimFCall $ FCall (NSimple fName) +                               [Just inFPar :=>: ADExpr aggregate]+     outAssign = genExprAssign outPar fCall+ return  (BlockSm vPid iface pMap [BDISPB f] [CSSASm outAssign],+          SigDec out retFType Nothing)+  +-- | Translate a 'UnzipNSY' process to a block returning a declaration of+--   the resulting signal.+transUnzipNSY2Block :: Label -- ^ process identifier+                    -> VHDLId -- ^ input signal+                    -> [VHDLId] -- ^ output signals+                    -> [TypeRep] -- ^ output signal types+                    -> VHDLM (BlockSm, [SigDec])+transUnzipNSY2Block vPid inSig outSigs outTRTypes = do+ -- Generate the formal parameters of the block+ let inPar = unsafeIdAppend vPid "_in"+     outPars = map (\n -> unsafeIdAppend vPid ("_out" ++ show n)) +                   [1..length outSigs]+ -- Generate the port interface of the block+     nOuts = length outSigs+     tupTyCon = mkTyCon $ replicate (nOuts-1) ','+     inTRType = tupTyCon `mkTyConApp` outTRTypes    + outTMTypes <- mapM transTR2TM outTRTypes+ inTMType <- transTR2TM inTRType+ let inDec = IfaceSigDec inPar In inTMType+     outDecs = zipWith (\par typ -> IfaceSigDec par Out typ) outPars outTMTypes+     iface = inDec : outDecs+ -- Generate the port map+     pMap = genPMap  (inPar : outPars) (inSig : outSigs)+ -- Generate the signal assignments+     genOrigExp n = (PrimName $ NSelected +                              (NSimple inPar :.: tupVHDLSuffix n))+     genOutAssign outSig n = CSSASm $ genExprAssign outSig (genOrigExp n)+     outAssigns = zipWith genOutAssign outPars [(1::Int)..]              + return  (BlockSm vPid iface pMap [] outAssigns,+          zipWith (\sig typ -> SigDec sig typ Nothing) outSigs outTMTypes)++++-- | Translate a 'UnzipxSY' process to a block returning a declaration of+--   the resulting signal.+transUnzipxSY2Block :: Label -- ^ process identifier+                    -> VHDLId -- ^ input signal+                    -> [VHDLId] -- ^ output signals+                    -> TypeRep -- ^ type of vector elements+                    -> Int -- ^ vector Size+                    -> VHDLM (BlockSm, [SigDec])+transUnzipxSY2Block vPid inSig outSigs elemTR vSize = do + -- Generate the formal parameters of the block+ let inPar = unsafeIdAppend vPid "_in"+     outPars = map (\n -> unsafeIdAppend vPid ("_out" ++ show n)) +                   [1..length outSigs]+ -- Generate the port interface of the block+     inTRType = fSVecTyCon `mkTyConApp` [transInt2TLNat vSize, elemTR]    + inTMType <- transTR2TM inTRType+ elemTM <- transTR2TM elemTR+ let inDec = IfaceSigDec inPar In inTMType+     outDecs = map (\par -> IfaceSigDec par Out elemTM) outPars +     iface = inDec : outDecs+ -- Generate the port map+     pMap = genPMap  (inPar : outPars) (inSig : outSigs)+ -- Generate the signal assignments+     genOrigExp n = +        PrimName $ NIndexed (NSimple inPar `IndexedName` [PrimLit  $ show n])+     genOutAssign outSig n = CSSASm $ genExprAssign outSig (genOrigExp n)+     outAssigns = zipWith genOutAssign outPars [(0::Int)..]              + return  (BlockSm vPid iface pMap [] outAssigns,+          map (\sig -> SigDec sig elemTM Nothing) outSigs)+++++-- | Translate a 'DelaySY' process to a block returning a declaration of+--   the resulting signal.+transDelay2Block ::  Label -- ^ process identifier+                  -> VHDLId -- ^ input signal+                  -> ProcValAST -- ^ AST of the initial value +                                -- of the delay process+                  -> VHDLId   -- ^ output signal+                  -> VHDLM (BlockSm, SigDec)+transDelay2Block vPid inS (ProcValAST exp tr enums) outS = do+ -- Add the enumerated types associated with the value to the global results+ addEnumTypes enums+ -- Get the type of the initial value+ initTR <- transTR2TM tr+ -- Translate the initial value+ initExp <- withProcValC exp $ withInitTransNameSpace $ (transExp2VHDL exp)+ -- Build the block+ let formalIn  = unsafeIdAppend vPid "_in"+     formalOut = unsafeIdAppend vPid "_out"+     iface = [IfaceSigDec resetId   In  std_logicTM,+              IfaceSigDec clockId   In  std_logicTM, +              IfaceSigDec formalIn  In  initTR,+              IfaceSigDec formalOut Out initTR] +     assocs = [Just resetId   :=>: ADName (NSimple resetId),+               Just clockId   :=>: ADName (NSimple clockId),+               Just formalIn  :=>: ADName (NSimple inS),+               Just formalOut :=>: ADName (NSimple outS)]+     sigAssign = CSSASm (NSimple formalOut :<==: +                           (ConWforms [whenElseReset] inWform (Just whenRE)))+     whenElseReset = WhenElse (Wform [WformElem initExp Nothing])+                               (PrimName (NSimple resetId) :=: PrimLit "'0'")+     inWform = Wform [WformElem (PrimName $ NSimple formalIn) Nothing]+     whenRE = When (PrimFCall $ FCall (NSimple $ unsafeVHDLBasicId "rising_edge") +                                      [Nothing :=>: ADName (NSimple clockId) ])+ return  (BlockSm vPid iface (PMapAspect assocs) [] [sigAssign],+          SigDec outS initTR Nothing)++-- | Translate a System instance into a VHDL component instantion+--   returning the declartion of the output signals+transSysIns2CompIns :: SysLogic -- ^ parent system logic+                    -> Label -- ^ instance identifier+                    -> [VHDLId] -- ^ input signals+                    -> [(VHDLId, TypeRep)] -- ^ output signals+                    -> SysId -- ^ parent system identifier+                    -> [PortId] -- ^ parent input identifiers+                    -> [PortId] -- ^ parent output identifiers+                    -> VHDLM (Maybe CompInsSm, [SigDec])+transSysIns2CompIns logic vPid ins typedOuts parentId parentInIds parentOutIds = do+ if length ins == 0 && length typedOuts == 0 +  then return (Nothing, []) +  else do+   -- Create the declarations for the signals+   decs <- mapM (\(name,typ) -> transVHDLName2SigDec name typ Nothing) typedOuts+   -- Create the portmap +   vParentId <- transSysId2VHDL parentId+   vParentInIds <- liftEProne $ mapM mkVHDLExtId parentInIds+   vParentOutIds <- liftEProne $ mapM mkVHDLExtId parentOutIds+   let implicitAssocIds = if logic == Sequential then [resetId, clockId] else []+       assocs =  genAssocElems +                   (implicitAssocIds ++ vParentInIds ++ vParentOutIds)+                   (implicitAssocIds ++ ins          ++ map fst typedOuts)+       entityName = NSelected (NSimple workId :.: SSimple vParentId)+       instantiation = CompInsSm vPid (IUEntity entityName) (PMapAspect assocs)+   return (Just instantiation, decs)+++-- | Translate a VHDL Signal to a VHDL Signal declaration+transVHDLName2SigDec ::  SimpleName -- ^ Signal name +             -> TypeRep -- ^ Type of the intermediate signal +             -> Maybe TH.Exp -- ^ Maybe an initializer expression for the signal+             -> VHDLM SigDec+transVHDLName2SigDec vId tr mExp = do+ tm <- transTR2TM tr+ mVExp <- DT.mapM (\e -> withInitTransNameSpace (transExp2VHDL e)) mExp+ return $ SigDec vId tm mVExp++++-------------------------+-- Identifier translation+-------------------------+++-- | Translate a VHDL identifier and a type to an interface signal declaration+transVHDLId2IfaceSigDec :: Mode -> VHDLId -> TypeRep -> VHDLM IfaceSigDec+transVHDLId2IfaceSigDec m vid trep = do           + tm  <- transTR2TM trep+ return $ IfaceSigDec vid m tm+ + +-- | Translate a Port to a VHDL Interface signal declaration+transPort2IfaceSigDec :: Mode -> PortId -> TypeRep -> VHDLM IfaceSigDec+transPort2IfaceSigDec m pid trep = do           + sid <- transPortId2VHDL pid+ transVHDLId2IfaceSigDec m sid trep++-- | Translate a local TH name to a VHDL Identifier+transTHName2VHDL :: TH.Name -> VHDLM VHDLId +transTHName2VHDL = transPortId2VHDL . nameBase ++-- | Translate a system identifier to a VHDL identifier+transSysId2VHDL :: SysId -> VHDLM VHDLId+transSysId2VHDL = transPortId2VHDL++-- | Translate a process identifier to a VHDL identifier+transProcId2VHDL :: ProcId -> VHDLM VHDLId+transProcId2VHDL = transPortId2VHDL++-- | translate a port identifier to a VHDL Identifier+transPortId2VHDL :: PortId -> VHDLM VHDLId+transPortId2VHDL str = liftEProne $ mkVHDLExtId str+++-------------------+-- Type translation +-------------------++-- | translate a 'TypeRep' to a VHDL 'TypeMark'+-- We don't distinguish between a type and its version nested in 'Signal'+-- since it makes no difference in VHDL+transTR2TM :: TypeRep -> VHDLM TypeMark+transTR2TM rep + -- Is it a Signal?+ | isSignal = transTR2TM  nestedTR+ -- Is it a primitive type?+ | isJust mPrimitiveTM = return $ fromJust mPrimitiveTM+ -- Non-Primitive type, try to translate it+ | otherwise = customTR2TM rep+ where (isSignal, nestedTR) = let (tc,~[tr]) = splitTyConApp rep+                              in  (tc == signalTyCon, tr)+       signalTyCon = (typeRepTyCon.typeOf) (undefined :: Signal ())+       mPrimitiveTM = lookup rep primTypeTable +++-- | Translate a custom 'TypeRep' to a VHDL 'TypeMark'+customTR2TM :: TypeRep -> VHDLM TypeMark+customTR2TM rep = do+ -- Check if it was previously translated+ mTranslated <- lookupCustomType rep+ case mTranslated of+   -- Not translated previously+   Nothing -> do+      -- translate it+      e <- doCustomTR2TM rep+      -- update the translation table and the accumulated type declarations+      addCustomType rep e+      -- return the translation+      case e of+        Left (TypeDec id _) -> return id+        Right (SubtypeDec id _) -> return id+   -- Translated previously+   Just tm -> return tm+     +-- | Really do the translation (customTR2TM deals with caching)+doCustomTR2TM :: TypeRep -> VHDLM (Either TypeDec SubtypeDec)++-- | FSVec?+--   FSVecs are translated to subtypes of unconstrained vectors.+--   All FSVec operations are translated as operations for the+--   unconstrained type.+doCustomTR2TM rep | isFSVec = do+ -- Translate the type of the elements contained in the vector+ valTM <- transTR2TM valueType+ -- Build the unconstrained vector identifier+ let vectorId = unsafeVHDLBasicId ("fsvec_"++ fromVHDLId valTM)+ -- Obtain the unconstrained vector together with its functions and add them+ -- to the global traversing-results (if this wasn't previously done):+ --  * Check if the unconstrained array was previously translated+ vecs <- gets (transUnconsFSVecs.global)+ --  * if it wasn't ...+ when (not $ elem valueType vecs) $ do+      -- create the unconstrained vector type and add it to the global+      -- results. _Only_ if we are not working with "FSVec _ Bit" becuase+      -- "type fsvec_std_logic" is already included in forsyde.vhd.+      when (valueType /= typeOf (undefined :: Bit))+           (addTypeDec $ TypeDec vectorId (TDA (UnconsArrayDef [fsvec_indexTM] valTM)))+      -- Add the default functions for the unconstrained+      -- vector type to the global results+      let funs =  genUnconsVectorFuns valTM vectorId+      mapM_ addSubProgBody funs+      -- Mark the unconstrained array as translated+      addUnconsFSVec valueType++ -- Create the vector subtype identifier+ let subvectorId = unsafeVHDLBasicId ("fsvec_" ++ show size ++ "_" +++                                     fromVHDLId valTM)+ -- Create the vector subtype declaration+ return $ Right $ +     SubtypeDec subvectorId (SubtypeIn vectorId +              (Just $ IndexConstraint [ToRange (PrimLit "0")+                                               (PrimLit (show $ size-1))]))+   where (cons, ~[sizeType,valueType]) = splitTyConApp rep+         isFSVec = cons == fSVecTyCon+         size = transTLNat2Int sizeType+++-- | Tuple?+doCustomTR2TM rep | isTuple = do+  -- Create the elements of the record+  fieldTMs <- mapM transTR2TM args+  let elems = zipWith (\fieldId fieldTM -> ElementDec fieldId fieldTM )+                      [tupVHDLIdSuffix n | n <- [1..]] fieldTMs              +  -- Create the Type Declaration identifier+      recordId = unsafeVHDLBasicId $ +              (tupStrSuffix $ length fieldTMs) ++ "_" ++ +              (concatMap fromVHDLId.intersperse (unsafeVHDLBasicId "_")) fieldTMs+  -- Add the default functions for the tuple type to the global results+      funs = genTupleFuns fieldTMs recordId+  mapM_ addSubProgBody funs+  -- Create the record+  return $ Left $ (TypeDec recordId (TDR $ RecordTypeDef elems))+ where (cons, args) = splitTyConApp rep+       conStr = tyConString cons+       isTuple = all (==',') conStr+       ++-- | AbstExt?+doCustomTR2TM rep | isAbsExt = do+  -- Create the elements of the record+  valueTM <- transTR2TM valueTR+  let elems = [ElementDec isPresentId booleanTM,+               ElementDec valueId     valueTM  ]+              +  -- Create the Type Declaration identifier+      recordId = unsafeVHDLBasicId $ +                    "abs_ext_" ++ fromVHDLId valueTM+  -- Add the default functions for the vector type to the global results+      funs =  genAbstExtFuns valueTM recordId+  mapM_ addSubProgBody funs+  -- Return the resulting the record+  return $ Left $ (TypeDec recordId (TDR $ RecordTypeDef elems))+ where (cons, ~[valueTR]) = splitTyConApp rep+       absExtTyCon = (typeRepTyCon.typeOf) (undefined :: AbstExt ())+       isAbsExt = cons == absExtTyCon ++-- | Finally, it is an Enumerated algebraic type +--   or an unkown custom type (in that case we throw an error)+--+--   NOTE: It would be cleaner to have a different clauses for each case but+--   since we need to access the state to check if it's an enumerated +--   algebraic type, we cannot do it.+doCustomTR2TM rep = do+ -- Get the accumulated Enumerated Algebraic Types+ eTys <- gets (enumTypes.global)+ -- Check if current Type representation can be found in eTys+ let equalsRep (EnumAlgTy name _) = name == (tyConString.typeRepTyCon) rep + case (S.toList.(S.filter equalsRep)) eTys of+   -- Found!+   [enumDef] -> liftM Left $ enumAlg2TypeDec enumDef +   -- Not found, unkown custom type+   _ ->  throwFError $ UnsupportedType rep++-- | Transform an enumerated Algebraic type to a VHDL+--   TypeMark adding its default function to the global results+enumAlg2TypeDec :: EnumAlgTy -- ^ Enumerated type definition+                -> VHDLM TypeDec+enumAlg2TypeDec (EnumAlgTy tn cons) = do+ -- Get the TypeMark+ tMark <- liftEProne $ mkVHDLExtId tn+ -- Get the enumeration literals+ enumLits@(firstLit:_) <- liftEProne $ mapM mkVHDLExtId cons+ -- Add the default functions for the enumeration type+ let funs = genEnumAlgFuns tMark firstLit+ mapM_ addSubProgBody funs+ -- Create the enumeration type+ return (TypeDec tMark (TDE $ EnumTypeDef enumLits))+   +-- | Translation table for primitive types+primTypeTable :: [(TypeRep, TypeMark)]+primTypeTable = [-- Commented out due to representation overflow+                 -- (typeOf (undefined :: Int64), int64TM)   ,+                 (typeOf (undefined :: Int32), int32TM)   ,+                 (typeOf (undefined :: Int16), int16TM)   ,+                 (typeOf (undefined :: Int8) , int8TM)    ,+                 (typeOf (undefined :: Bool) , booleanTM) ,+                 (typeOf (undefined :: Bit)  , std_logicTM)]++---------------------------------------+-- Translating functions and expresions+---------------------------------------++------------------------+-- Translating functions+------------------------+++-- | Throw a function error+funErr :: VHDLFunErr -> VHDLM a+funErr err = throwFError $ UntranslatableVHDLFun err++-- | Translate a typed function ast to VHDL+transProcFun2VHDL :: TypedProcFunAST  -- ^ input ast+    -> VHDLM (SubProgBody, VHDLId, [VHDLId], [TypeMark], TypeMark)+    -- ^ Function, Function name, name of inputs, type of inputs, return type   +transProcFun2VHDL (TypedProcFunAST fType fEnums fAST) = do+ -- Add the enumerated types associated with the function to the global results+ addEnumTypes fEnums+ -- Check if the procFunAST fullfils the restrictions of the VHDL Backend+ -- FIXME: translate the default arguments+ (fName, fInputPats, fBodyExp) <- checkProcFunAST fAST+ -- Get the function spec and initialize the translation namespace+ (fSpec, fVHDLName, fVHDLPars, argsTM, retTM) <- +  transProcFunSpec fName fType fInputPats+ -- Translate the function's body+ bodySm <- transFunBodyExp2VHDL fBodyExp+ let  fBody = SubProgBody fSpec [] [bodySm]+ return (fBody, fVHDLName, fVHDLPars, argsTM, retTM)+++-- | Check if a process function AST fulfils the VHDL backend restrictions.+--   It returs the function TH-name its input paterns and its body expression. +checkProcFunAST :: ProcFunAST+                -> VHDLM (Name, [Pat], Exp)+-- FIXME: translate the default arguments!+checkProcFunAST (ProcFunAST thName [Clause pats (NormalB exp) []] []) =+ return (thName, pats, exp)+checkProcFunAST (ProcFunAST _ _ (_:_)) =+ intError "ForSyDe.Backend.VHDL.Translate.checkProcFunSpec" +          (UntranslatableVHDLFun $ GeneralErr (Other "default parameters are not yet supported"))+checkProcFunAST (ProcFunAST _ [Clause _ _ whereConstruct@(_:_)] _) =  +  funErr (FunWhereConstruct whereConstruct)+checkProcFunAST (ProcFunAST _ [Clause _ bdy@(GuardedB _) _] _) =  +  funErr (FunGuardedBody bdy)+checkProcFunAST (ProcFunAST _ clauses@(_:_:_) _) =  +  funErr (MultipleClauses clauses)+-- cannot happen+checkProcFunAST (ProcFunAST _ [] _) =  + -- FIXME, use a custom error+ intError "ForSyDe.Backend.VHDL.Translate.checkProcFunSpec" +          (UntranslatableVHDLFun $ GeneralErr (Other "inconsistentency"))++++-- |  Get the spec of a VHDL function from the Haskell function name, its type +--    and its input patterns. This function also takes care of initalizing the +--    translation namespace.+transProcFunSpec :: TH.Name -- ^ Function name+                 -> TypeRep -- ^ Function type+                 -> [Pat]   -- ^ input patterns +                 -> VHDLM (SubProgSpec, VHDLId, [VHDLId], [TypeMark], TypeMark)+-- ^ translated function spec, function name, inpt parameters, input types+--   and return types+transProcFunSpec fName fType fPats = do+ -- FIXME: translate the default arguments!+ -- Get the input and output types+ let (argsTR, retTR) = unArrowT fType+ -- Check that the number of patterns equal the function parameter number+     expectedN = length argsTR+     actualN = length fPats+ when (expectedN /= actualN) (funErr $ InsParamNum actualN)+ -- Get a VHDL identifier for each input pattern and+ -- initialize the translation namespace+ fVHDLParIds <- mapM transInputPat2VHDLId fPats + -- Translate the function name+ fVHDLName <- transTHName2VHDL fName + -- Translate the types+ argsTM <- mapM transTR2TM argsTR+ retTM <- transTR2TM retTR+ -- Create the spec+ let iface = zipWith (\name typ -> IfaceVarDec  name typ) fVHDLParIds argsTM+     fSpec = Function fVHDLName iface retTM+ -- Finally, return the results+ return (fSpec, fVHDLName, fVHDLParIds, argsTM, retTM)+ +-- | Translate an input pattern to a VHDLID, +--   making the necessary changes in the translation namespace+transInputPat2VHDLId :: TH.Pat -> VHDLM VHDLId+transInputPat2VHDLId  pat = do+ -- Get the parameter identifier+ id <- case pat of+         -- if we get a variable or and @ patterm, we just translate it to VHDL+         VarP name -> transTHName2VHDL name+         AsP name _ -> transTHName2VHDL name+         -- otherwise, generate a fresh identifier+         _ -> genFreshVHDLId++ -- Prepare the namespace for the pattern+ preparePatNameSpace (NSimple id) pat+ -- Finally return the generated id+ return id +++-- | prepare the translation namespace for an input pattern+preparePatNameSpace :: Prefix -- ^ name prefix obtained so far +                    -> Pat    -- ^ pattern +                    -> VHDLM ()+-- NOTE: a good alternative to adding selected names to the+--       translation table would be declaring a variable+--       assignment. It would probably make the generated code more+--       readable but at the same time, it requires knowing the+--       pattern type, and TH's AST is unfortunately not+--       type-annotated which would make things more difficult.++-- variable pattern+preparePatNameSpace prefix (VarP name) = + addTransNamePair name 0 (\[] -> PrimName prefix)++-- '@' pattern +preparePatNameSpace prefix (AsP name pat) = do+  addTransNamePair name 0 (\[]  -> PrimName prefix)+  preparePatNameSpace prefix pat++-- wildcard pattern+preparePatNameSpace _ WildP = return ()  ++-- tuple pattern +preparePatNameSpace prefix (TupP pats) = do+  let prepTup n pat = preparePatNameSpace +                          (NSelected (prefix :.: tupVHDLSuffix n)) pat+  zipWithM_ prepTup [1..] pats++-- AbstExt patterns++-- Since we only support one clause per function+-- they are not really useful, but we accept them anyways +-- FIXME: true, they are not useful, but again, since we only support one+--        clause per function they denote a programming error. Should they+--        really be supported?+preparePatNameSpace prefix (ConP name ~[pat]) | isAbstExt name =  +  when isPrst (preparePatNameSpace (NSelected (prefix :.: valueSuffix)) pat) + where isAbstExt name = isPrst || name == 'Abst+       isPrst =  name == 'Prst++-- Unary Constructor patterns+-- We try an enumerated type patterns +-- otherwise we throw an unknown constructor pattern error+preparePatNameSpace _ pat@(ConP name []) = do+ mId <- getEnumConsId name+ case mId of +   -- it is an enumerated data constructor, however, since we only admit+   -- one clause per function there is nothing to do about it+  Just _ -> return ()+  -- it is an unknown data constructor+  Nothing -> funErr $ UnsupportedFunPat pat++-- otherwise the pattern is not supported+preparePatNameSpace _ pat = funErr $ UnsupportedFunPat pat++++--------------------------+-- Translating expressions+--------------------------++-- | Throw an expression error+expErr :: Exp -> VHDLExpErr -> VHDLM a+expErr exp err = throwFError $ UntranslatableVHDLExp exp err+++-- | Create the unique statement of a VHDL from a TH expression.+transFunBodyExp2VHDL :: TH.Exp -> VHDLM SeqSm+transFunBodyExp2VHDL  (CondE condE thenE  elseE)  = +  do condVHDLE  <- transExp2VHDL condE   +     thenVHDLSm <- transFunBodyExp2VHDL thenE +     elseVHDLSm <- transFunBodyExp2VHDL elseE +     return (IfSm condVHDLE [thenVHDLSm] [] (Just $ Else [elseVHDLSm]))+transFunBodyExp2VHDL caseE@(CaseE exp matches)  = +  do caseVHDLE  <- transExp2VHDL exp +     caseSmAlts <- mapM (transMatch2VHDLCaseSmAlt caseE) matches+     return (CaseSm caseVHDLE caseSmAlts)+-- In other case it is an expression returned directly+transFunBodyExp2VHDL  e =            +  do vHDLe <- transExp2VHDL e +     return (ReturnSm $ Just vHDLe)++-- | Translate a case alternative from Haskell to VHDL+transMatch2VHDLCaseSmAlt :: TH.Exp -> TH.Match -> VHDLM CaseSmAlt+-- FIXME: the exp passed (which contains the full case expression for+-- error reporting purposes) should be part of the context once VHDLM+-- is reworked+transMatch2VHDLCaseSmAlt contextExp (Match pat (NormalB matchExp) []) =+ do sm <- transFunBodyExp2VHDL matchExp+    case pat of+     -- FIXME: support pattern matching with tuples, AbsExt, +     -- and enumerated types+     WildP -> return $ CaseSmAlt [Others] [sm] +     LitP lit -> do vHDLExp <- transExp2VHDL (LitE lit)+                    return $ CaseSmAlt [ChoiceE vHDLExp] [sm]+     -- FIXME: check! this case introduces new names into scope+     VarP name -> do vHDLExp <- transExp2VHDL (VarE name)+                     return $ CaseSmAlt [ChoiceE vHDLExp] [sm]+     _ -> expErr contextExp $ UnsupportedCasePat pat+transMatch2VHDLCaseSmAlt contextExp (Match _ _ whereDecs@(_:_)) =+ expErr contextExp $ CaseWhereConstruct whereDecs+transMatch2VHDLCaseSmAlt contextExp (Match _ bdy@(GuardedB _) _) =+ expErr contextExp $ CaseGuardedBody bdy+++-- | Translate a Haskell expression to a VHDL expression+transExp2VHDL :: TH.Exp -> VHDLM VHDL.Expr+++-- TypeLevel-package numerical constant aliases+transExp2VHDL (VarE name) | isTypeLevelAlias = do+ let constant = nameBase name+     ([baseSym], val) = splitAt 1 constant+     basePrefix = case baseSym of+       'b' -> "2#" +       'o' -> "8#" +       'h' -> "16#"+       'd' -> ""+       _   -> error "unexpected base symbol"+ return (PrimLit $ basePrefix ++ val) + where isTypeLevelAlias = (show name =~ aliasPat)+       aliasPat = "^Data\\.TypeLevel\\.Num\\.Aliases\\.(b[0-1]+|o[0-7]+|d[0-9]+|h[0-9A-F]+)$"++++-- A FSVec generated with Template Haskell +transExp2VHDL (VarE unsafeFSVecCoerce `AppE` _ `AppE` (ConE con `AppE` ListE exps)) + | show unsafeFSVecCoerce == "Data.Param.FSVec.unsafeFSVecCoerce" &&+   show con == "Data.Param.FSVec.FSVec" = do+    vhdlExps <- mapM transExp2VHDL exps+    return $ Aggregate (map (\e -> ElemAssoc Nothing e) vhdlExps)+++-- Is it function/constructor application, a constant+-- or an unkown name.+transExp2VHDL e | isConsOrFun   =+  do -- get the symbol table (name translation table)+     nameTable <- gets (nameTable.transNameSpace.local)+     case lookup name nameTable of+       -- found name+       Just (arity, transF) -> +            if arity /= numArgs +              then expErr e $ CurryUnsupported arity numArgs+              else do exps <- mapM transExp2VHDL args+                      return $ transF exps+       -- Didn't find the name in the global table+       Nothing -> do +         -- Check if it is a user-defined enumerated data constructor +         mId <- getEnumConsId name+         case mId of+            Just id -> return $ PrimName (NSimple id)+            Nothing -> expErr e $ UnkownIdentifier name+ where (f,args,numArgs) = unApp e +       mName = getName f+       name = fromJust mName+       isConsOrFun = isJust mName +       getName (VarE n) = Just n+       getName (ConE n) = Just n+       getName _        = Nothing++++-- Literals+transExp2VHDL  (LitE (IntegerL integer))  = (return.transInteger2VHDL) integer+transExp2VHDL  (LitE (IntPrimL integer))  = (return.transInteger2VHDL) integer++-- Unsupported literal +transExp2VHDL lit@(LitE _) = expErr lit $ UnsupportedLiteral++-- Infix expressions+transExp2VHDL (InfixE (Just argl) f@(VarE _) (Just argr)) = + transExp2VHDL $ f `AppE` argl `AppE` argr++-- Sections (unsupported)+transExp2VHDL infixExp@(InfixE _ (VarE _) _) = expErr infixExp Section++-- Tuples: e.g. (1,2)+transExp2VHDL (TupE exps) = do+ vExps <- mapM transExp2VHDL exps+ return $ Aggregate $ map (\expr -> ElemAssoc Nothing expr) vExps++-- Unsupported expressions+transExp2VHDL lamE@(LamE _ _) = expErr lamE  LambdaAbstraction+transExp2VHDL condE@(CondE _ _ _) = expErr condE Conditional+transExp2VHDL letE@(LetE _ _) = expErr letE Let+transExp2VHDL caseE@(CaseE _ _) = expErr caseE Case+transExp2VHDL doE@(DoE _) = expErr doE Do	+transExp2VHDL compE@(CompE _) = expErr compE ListComprehension+transExp2VHDL arithSeqE@(ArithSeqE _) = expErr arithSeqE ArithSeq	+transExp2VHDL listE@(ListE _) = expErr listE List	+transExp2VHDL sigE@(SigE _ _) = expErr sigE Signature	+transExp2VHDL reConE@(RecConE _ _) = expErr reConE Record	+transExp2VHDL recUpE@(RecUpdE _ _) = expErr recUpE Record++-- The rest of expressions are not valid in practice and thus, not supported +-- (e.g. InfixE Nothing (RecConE _ _) _+transExp2VHDL exp = expErr exp Unsupported+  ++-- | Translate an integer to VHDL+transInteger2VHDL :: Integer -> Expr+transInteger2VHDL = PrimLit . show +++--------------------+-- Helper Functions+--------------------++-- Translate the TypeRep of a type-level natural (e.g: D1 :* D2) to a number+-- Make sure you don't supply an incorrect TypeRep or the function will break+transTLNat2Int :: TypeRep -> Int+transTLNat2Int tr+  -- Digit+  | isDigit = (digitToInt.last.tyConString) cons+  -- Connective+  | otherwise = 10 * (transTLNat2Int prefix) + (transTLNat2Int lastDigit) + where (cons, args@(~[prefix, lastDigit])) = splitTyConApp tr+       isDigit = null args+++-- Tranlate an Into to the TypeRep of a type-level natural (e.g: D1 :* D2)+transInt2TLNat :: Int -> TypeRep+transInt2TLNat n+ | n < 0 = intError fName (Other "negative index")+ | n < 10 = digit n+ | otherwise = mkTyConApp conTyCon [transInt2TLNat suffix, digit last]+ where fName = "ForSyDe.Backend.VHDL.Translate.transInt2TLNat"+       (suffix, last) = n `divMod` 10 +       digit 0 = typeOf (undefined :: D0)+       digit 1 = typeOf (undefined :: D1)+       digit 2 = typeOf (undefined :: D2)+       digit 3 = typeOf (undefined :: D3)+       digit 4 = typeOf (undefined :: D4)+       digit 5 = typeOf (undefined :: D5)+       digit 6 = typeOf (undefined :: D6)+       digit 7 = typeOf (undefined :: D7)+       digit 8 = typeOf (undefined :: D8)+       digit 9 = typeOf (undefined :: D9)+       -- Just to hush the compiler warnings+       digit _ = undefined+       conTyCon = (typeRepTyCon.typeOf) (undefined :: () :* ())++-- Type constructor of FSVec+fSVecTyCon :: TyCon+fSVecTyCon =(typeRepTyCon.typeOf) (undefined :: V.FSVec () ())++-- unApply an expression and obtain the number of arguments found+unApp :: Exp -> (Exp, [Exp], Int)+unApp e = (first, rest, n)+ where (first:rest, n) = unAppAc ([],0) e+       unAppAc (xs,n) (f `AppE` arg) = unAppAc (arg:xs, n+1) f+       unAppAc (xs,n) f = (f:xs,n)
+ src/ForSyDe/Backend/VHDL/Traverse.hs view
@@ -0,0 +1,239 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Traverse+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides specialized Netlist traversing functions aimed at+-- VHDL compilation.+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Traverse + (writeVHDLM,+  module ForSyDe.Backend.VHDL.Traverse.VHDLM) where++import ForSyDe.Backend.VHDL.Traverse.VHDLM+import ForSyDe.Backend.VHDL.Translate+import ForSyDe.Backend.VHDL.Generate+import ForSyDe.Backend.VHDL.FileIO+import ForSyDe.Backend.VHDL.AST+import ForSyDe.Backend.VHDL.Quartus (callQuartus)+import ForSyDe.Backend.VHDL.Modelsim++import ForSyDe.ForSyDeErr+import ForSyDe.System.SysDef+import ForSyDe.Process.ProcVal+import ForSyDe.Process.ProcFun+import ForSyDe.Netlist.Traverse+import ForSyDe.Netlist+import ForSyDe.OSharing++import Control.Monad.State+import System.Directory+import System.FilePath+import Data.Maybe (fromJust, isJust)++-- | Internal VHDL-Monad version of 'ForSyDe.Backend.writeVHDL'+--   (Note: the initial and final CWD will be / )+writeVHDLM :: VHDLM ()+writeVHDLM = do+   -- create and change to systemName/vhdl/work+   rootDir <- gets (sid.globalSysDef.global)+   let workDir = rootDir </> "vhdl" </> "work"+   liftIO $ createDirectoryIfMissing True workDir+   liftIO $ setCurrentDirectory workDir+   -- write the local results for the first-level entity+   writeLocalVHDLM+   -- if we are in recursive mode, also write the local results+   -- for the rest of the subsystems+   rec <- isRecursiveSet+   when rec $ do subs <- gets (subSys.globalSysDef.global)+                 let writeSub s = +                        withLocalST (initLocalST ((readURef.unPrimSysDef) s))+                                    writeLocalVHDLM +                 mapM_ writeSub subs+   -- create and change to systemName/vhdl/systemName_lib+   -- (remember we are in workDir)+   let libDir = ".." </> rootDir ++ "_lib"+   liftIO $ createDirectoryIfMissing True libDir+   liftIO $ setCurrentDirectory $ libDir+   -- write the global results+   writeGlobalVHDLM+   -- change to systemName/vhdl+   liftIO $ setCurrentDirectory ".."+   -- call quartus if necessary+   callQuartus+   -- analyze with modelsim if necessary+   compile <- isCompileModelsimSet+   when compile compileResultsModelsim+   -- go back to the original directory+   liftIO $ setCurrentDirectory (".." </> "..")+   +-- | Write the global traversing results (i.e. the library design file)+--   accumulated  in the state of the monad+writeGlobalVHDLM :: VHDLM ()+writeGlobalVHDLM = do+ gSysId <- gets (sid.globalSysDef.global)+ debugMsg $ "Generating global system library for `" ++ gSysId ++  "' ...\n"+ globalRes <- gets (globalRes.global)+ -- We can create the id unsafely because sysId was already checked in+ -- transSysDef2Ent+ let libName = gSysId ++ "_lib"+     libDesignFile = genLibDesignFile globalRes+ liftIO $ writeDesignFile libDesignFile (libName ++ ".vhd")+++-- | Traverse the netlist and write the local results (i.e. system design files)+writeLocalVHDLM :: VHDLM ()+writeLocalVHDLM = do+  gSysDefVal <- gets (globalSysDef.global)+  lSysDefVal <- gets (currSysDef.local)+  let lSysDefId =  sid lSysDefVal+  debugMsg $ "Compiling system definition `" ++ lSysDefId ++ "' ...\n"+  -- Obtain the netlist of the system definition +  let nl = netlist lSysDefVal+  -- Traverse the netlist, and get the traversing results+  intOutsInfo <- traverseVHDLM nl +  LocalTravResult decs stms <- gets (localRes.local)+  let finalLogic = logic lSysDefVal+  -- Obtain the entity declaration of the system and the VHDL identifiers+  -- of the output signals.+  entity@(EntityDec _ eIface) <- transSysDef2Ent finalLogic lSysDefVal +  -- For each output signal, we need an assigment between its intermediate+  -- signal and the final output signal declared in the entity interface.+  let outIds = mapFilter (\(IfaceSigDec id _ _) -> id) +                         (\(IfaceSigDec _  m _) -> m == Out) eIface+      outAssigns = genOutAssigns outIds intOutsInfo+      finalRes = LocalTravResult decs (stms ++ outAssigns)+  -- Finally, generate the design file+      sysDesignFile = genSysDesignFile (sid gSysDefVal) entity finalRes+  -- and write it to disk+  liftIO $ writeDesignFile sysDesignFile (lSysDefId ++ ".vhd") + where mapFilter f p = foldr (\x ys -> if p x then (f x):ys else ys) []++-- | Traverse the netlist of a System Definition, +--   returning the (implicit) final traversing state and a list+--   containing the 'IntSignalInfo' of each output of the system+traverseVHDLM :: Netlist [] -> VHDLM [IntSignalInfo]+traverseVHDLM = traverseSEIO newVHDL defineVHDL++-- | \'new\' traversing function for the VHDL backend+newVHDL :: NlNode NlSignal -> VHDLM [(NlNodeOut, IntSignalInfo)]+newVHDL node = case node of+  -- FIXME: Skip the case, basing the generation of tags on+  --        outTags +  InPort id -> do vId <- transPortId2VHDL id+                  return [(InPortOut, vId)]+  Proc pid proc -> withProcC pid $ do+   -- Obtain the VHDL id of the process+   vpid <- transProcId2VHDL pid+   -- function to create an intermediate signal out of the process+   -- identifier and a string suffix+   let procSuffSignal sigSuffix = unsafeIdAppend vpid sigSuffix+   -- Multiple output tags, add a numeric suffix specifying the output+       multOutTags =  +            zipWith (\tag n -> (tag, procSuffSignal $ outSuffix ++ show n))+                    (outTags node) [(1::Int)..]+   case proc of+    Const _ -> return [(ConstOut, procSuffSignal outSuffix)]+    ZipWithNSY _ _ -> return [(ZipWithNSYOut, procSuffSignal outSuffix)]+    ZipWithxSY _ _ -> return [(ZipWithxSYOut, procSuffSignal outSuffix)]+    UnzipNSY _ _ _ -> return multOutTags+    UnzipxSY _ _ _ _ -> return multOutTags +    DelaySY _ _ -> return [(DelaySYOut, procSuffSignal outSuffix)]+    SysIns  _ _ ->+      -- Note: Here we could use the name of the System outputs instead of+      --       instanceid_out_n but ... that could cause+      --       clashes with the oher signal names (we only check for the+      --       of the uniqueness of all process ids within a system when +      --       creating it). We could check for those clashes but it would be+      --       ineffective and ilogical.+      return multOutTags+ where outSuffix = "_out"    +       +-- | \'define\' traversing function for the VHDL backend+defineVHDL :: [(NlNodeOut, IntSignalInfo)] +             -> NlNode IntSignalInfo +             -> VHDLM ()+defineVHDL outs ins = do + case (outs,ins) of+  (_, InPort _) -> return ()+  (outs, Proc pid proc) -> withProcC pid $ do+   -- We can unsafely transform the pid to a VHDL identifier because+   -- it was checked in newVHDL+   let vPid = unsafeVHDLExtId pid+   case (outs, proc) of+    ([(ConstOut, intSig)],  Const ProcVal{valAST=ast}) -> do+     -- Generate a Signal declaration for the constant+     let cons = expVal ast+     dec  <- withProcValC cons $ transVHDLName2SigDec +                                   intSig (expTyp ast) (Just cons)+     addSigDec dec+    ([(ZipWithNSYOut, intOut)],  ZipWithNSY f intIns) -> do +     -- Translate the zipWithN process to a block+     -- and get the declaration of its output signal+     (block, dec) <- transZipWithN2Block vPid intIns (tpfloc f) (tast f) intOut+     addStm $ CSBSm block+     -- Generate a signal declaration for the resulting signal+     addSigDec dec+    ([(ZipWithxSYOut, intOut)], ZipWithxSY f intIns) -> do+     -- Translate the zipWithx process to a block+     -- and get the declaration of its output signal+     (block, dec) <- transZipWithx2Block vPid intIns (tpfloc f) (tast f) intOut+     addStm $ CSBSm block+     -- Generate a signal declaration for the resulting signal+     addSigDec dec      +    (intOuts, UnzipNSY outTypes _ intIn) -> do+     -- Translate the zipWithNSY process to a block+     -- and get the declaration of its output signal+     (block, decs) <- transUnzipNSY2Block vPid intIn (map snd intOuts) outTypes +     addStm $ CSBSm block+     -- Generate a signal declaration for the resulting signals+     mapM_ addSigDec decs+    (intOuts, UnzipxSY typ size _ intIn) -> do+     -- Translate the UnzipxSY process to a block+     -- and get the declaration of its output signal+     (block, decs) <- transUnzipxSY2Block vPid intIn (map snd intOuts) typ size +     addStm $ CSBSm block+     -- Generate a signal declaration for the resulting signals+     mapM_ addSigDec decs+    ([(DelaySYOut, intOut)],  DelaySY initExp intIn) -> do+     -- Translate the delay process to a block+     -- and get the declaration of its output signal+     (block, dec) <- transDelay2Block vPid intIn (valAST initExp) intOut+     addStm $ CSBSm block+     -- Generate a signal declaration for the resulting delayed signal+     addSigDec dec +  +    (intOuts, SysIns pSys intIns) -> do+      let parentSysRef = unPrimSysDef pSys+          parentSysVal = readURef parentSysRef+          parentLogic = logic parentSysVal+          parentInIface = iIface parentSysVal+          parentOutIface = oIface parentSysVal+          typedOuts = zipWith (\(_, t) (_, int) -> (int,t)) parentOutIface+                                                            intOuts +          parentId = sid parentSysVal +      -- Translate the instance to a component instantiation +      -- and get the declaration of the output signals+      (mCompIns, decs) <- transSysIns2CompIns parentLogic +                                             vPid +                                             intIns +                                             typedOuts +                                             parentId +                                             (map fst parentInIface) +                                             (map fst parentOutIface)+      when (isJust mCompIns) (addStm $ CSISm $ fromJust mCompIns)+      -- Generate a signal declaration for each of the resulting signals+      mapM_ addSigDec decs++-- Othewise there is a problem of inconsisten tags+    _ -> intError "ForSyDe.Backend.VHDL.Traverse.defineVHDL" InconsOutTag+++++
+ src/ForSyDe/Backend/VHDL/Traverse/VHDLM.hs view
@@ -0,0 +1,557 @@+{-# LANGUAGE FlexibleContexts #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Backend.VHDL.Traverse.VHDLM+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- 'VHDM' (VHDL Monad), related types and functions+--+-----------------------------------------------------------------------------+module ForSyDe.Backend.VHDL.Traverse.VHDLM where++import ForSyDe.Backend.VHDL.AST+import qualified ForSyDe.Backend.VHDL.AST as VHDL+import {-# SOURCE #-} ForSyDe.Backend.VHDL.GlobalNameTable (globalNameTable)++import ForSyDe.Ids+import ForSyDe.ForSyDeErr+import ForSyDe.System.SysDef (SysDefVal(..))+import ForSyDe.Netlist.Traverse (TravSEIO)+import ForSyDe.Process.ProcType (EnumAlgTy(..))++import Data.Generics (tyconModule)+import Data.Maybe (fromJust)+import qualified Data.Set as S (filter)+import Data.Set (Set, union, empty, toList)+import Control.Monad.State+import Language.Haskell.TH (nameBase, nameModule, Name, Exp)+import Data.Typeable (TypeRep)++-------------------------------------+-- How does the VHDL Backend work? --+-------------------------------------+-- FIXME: This documentation is a bit outated+-- All the types used in the the System Defintion are translated to VHDL+-- put into Package, the into a Design File and written to disk.+--+-- The System Definition itself is translated to another VHDL Design File and +-- written to disk.+--+-- This Design File will contain only two library units;+-- an Entity Declaration and an Architecture.+-- 1) The Entity Declaration can be obtained from the SysDef directly (without+--    traversing the netlist)+-- 2) The Architecture (or more specifically, its declarations  and+--    the statements) is obtained from the netlist by traversing it. +--+-- The state of the traversal is composed by +--  * list of type defintions translated during the traversal+--  * table of equivalence between Haskell types and the VHDL identifier+--    of its translated type (used to avoid translating the same type+--    multiple times)+--  * the list of declarations of the architecture+--  * the list of statements of the architecture +--  * a table of System Definition references, used to keep track of the+--    system definitions (corresponding to one or more instances in the +--    netlist) whose code was already generated.+--+-- For each process (netlist node) found during the traversal:+--    * A signal declaration is generated for each output and added to+--      the list of architecture declarations.+--    * A VHDL block including the translation of the process is generated+--      and added to the list of architecture statements.+--+-- In the special case of finding a System Instance+--      1) a port map statement is generated and added to the list of +--         architecture statements.+--      2) the System Definition table is used to check if the Design File of+--         the System Definition associated with the instance was written to +--         disk.+--      3) if the the associated System Definition wasn't in the table+--          1) generate and write to disk the corresponding Design File+--          2) add the System Definition to the table++-----------------+-- TransNameSpace+-----------------++-- | Translation namespace.+--+-- This type provides the number of fresh names already generated and+-- a tranlsation table from Template Haskell Names to VHDL Expressions (a symbol table). +-- It only makes sense in a process-function context.+data TransNameSpace = TransNameSpace +    {freshNameCount :: Int,+     nameTable      :: [(Name, (Int, [VHDL.Expr] -> VHDL.Expr ) )] }+    -- The table entries work as follows:+    -- (Template Haskell Name (table key), +    --   (Arity, function with which to construct the translated VHDL expression given its +    --           arguments already translated to VHDL                                      ))++-- | Initial trnaslation namespace for functions+initTransNameSpace :: TransNameSpace+initTransNameSpace = TransNameSpace 0 globalNameTable++-----------+-- VHDLM --+-----------++-- | VHDL backend monad+type VHDLM a = TravSEIO VHDLTravST ContextErr a++----------------+-- VHDLTravST --+----------------++-- | VHDL traversing State. (see 'ForSyDe.Netlist.Traverse.traverseSIO')+data VHDLTravST = VHDLTravST+  {local  :: LocalVHDLST, -- Local State (related to the system currently +                          -- compiled)+   global :: GlobalVHDLST}  -- Global state (related to all systems being +                            -- recursively compiled)   ++data LocalVHDLST = LocalVHDLST+   {currSysDef     :: SysDefVal, -- System definition which is currently +                                 -- being compiled+   context         :: Context,  -- Error Context+   transNameSpace  :: TransNameSpace,  -- Translation namespace for functions+                                       -- It only makes sense+                                       -- in a process-function context +   localRes        :: LocalTravResult} -- Result accumulated during the +                                       -- traversal of current System Definition +                                       -- netlist+++++-- | initialize the local state+initLocalST :: SysDefVal -> LocalVHDLST+initLocalST sysDefVal = + LocalVHDLST sysDefVal (SysDefC (sid sysDefVal) (loc sysDefVal)) +             initTransNameSpace emptyLocalTravResult++-- | Execute certain operation with a concrete local state.+--   The initial local state is restored after the operation is executed+withLocalST :: LocalVHDLST -> VHDLM a -> VHDLM a+withLocalST l' action =  do+  -- get the initial local state+  st <- get+  let l = local st+  -- set the modified state+  put st{local=l'}+  -- execute the action+  res <- action+  -- restore the initial local state+  st' <- get +  put st'{local=l}+  -- return the result+  return res++-- | Execute certain operation with the initial translation namespace+--   The initial namespace is restored after the operation is executed+withInitTransNameSpace :: VHDLM a -> VHDLM a+withInitTransNameSpace action = do+  -- get the initial name space+  st <- get+  let l = local st+      ns = transNameSpace l+  -- set the empty name space+  put st{local=l{transNameSpace=initTransNameSpace}}+  -- execute the action+  res <- action+  -- restore the initial name table+  st' <- get+  let l' = local st'+  put st'{local=l'{transNameSpace=ns}}+  -- return the result+  return res+      +            ++data GlobalVHDLST = GlobalVHDLST+  {globalSysDef :: SysDefVal, -- global system definition +                              -- (the first-level system being compiled)+   ops          :: VHDLOps,  -- Compilation options+   globalRes    :: GlobalTravResult, -- Result accumulated during the +                                     -- whole compilation+   enumTypes    :: Set EnumAlgTy, -- Set of the enumerated+                                  -- algebraic types accumulated+                                  -- by all ProcFuns and ProcVals+                                  -- in the system      +   typeTable    :: [(TypeRep, TypeMark)],  -- Type translation table+   transUnconsFSVecs :: [TypeRep]} -- Unconstrained FSVecs previously translated.+                                   -- Each unconstrained FSVec is represented by +                                   -- the 'TypeRep' of its elements+++-- | Empty initial traversing state+initGlobalVHDLST :: SysDefVal -> GlobalVHDLST+initGlobalVHDLST  sysDefVal = + GlobalVHDLST sysDefVal defaultVHDLOps emptyGlobalTravResult empty [] []++-- | Empty initial traversing state +initVHDLTravST :: SysDefVal -> VHDLTravST+initVHDLTravST sysDefVal = + VHDLTravST (initLocalST sysDefVal) (initGlobalVHDLST sysDefVal)++-------------+-- TravResult+-------------++-- | Local result accumulated during the traversal of a netlist+data LocalTravResult = LocalTravResult +  {archDecs  :: [BlockDecItem], -- generated architecture declarations +   archSms   :: [ConcSm]      } -- generated architecture statements++++-- | empty local VHDL compilation result+emptyLocalTravResult :: LocalTravResult+emptyLocalTravResult = LocalTravResult [] []+++-- | Global Results accumulated throughout the whole compilation+data GlobalTravResult = GlobalTravResult + {typeDecs      :: [TypeDec], -- Types translated during the traversal+  subtypeDecs   :: [SubtypeDec], -- Subtypes translated during the traversal+  subProgBodies :: [SubProgBody] } -- Functions or procedures generated during+                                   -- the traversal++++-- | empty global VHDL compilation result+emptyGlobalTravResult :: GlobalTravResult+emptyGlobalTravResult = GlobalTravResult [] [] []+++----------+-- VHDLOps+----------++-- | VHDL Compilation options+data VHDLOps = VHDLOps {debugVHDL :: VHDLDebugLevel, -- ^ Debug mode+                        recursivityVHDL :: VHDLRecursivity, +                        execQuartus  :: Maybe QuartusOps, -- ^ Analyze the generated code with Quartus+                        compileModelsim :: Bool -- ^ Compile the generated code with Modelsim+                                        }+ deriving (Eq, Show)++-- | Debug level+data VHDLDebugLevel = VHDLNormal | VHDLVerbose+ deriving (Eq, Ord, Show)++-- | Print a message to stdout if in verbose mode+debugMsg :: String -> VHDLM ()+debugMsg str = do+ debugLevel <- gets (debugVHDL.ops.global)+ when (debugLevel > VHDLNormal) +      (liftIO $ putStr ("DEBUG: " ++ str))++-- | Recursivity, should the parent systems of system instances be compiled as +--   well?+data VHDLRecursivity = VHDLRecursive | VHDLNonRecursive+ deriving (Eq, Show)++-------------+-- QuartusOps+-------------++-- Quartus options++-- | Options passed to Quartus II by the VHDL Backend. Most of them are optional+--   and Quartus will use a default value.+--+--   It contains:+-- +--     * What action to perform+--+--     * Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz+--+--     * FPGA family and specific device model (both are independently optional).+--+--     * Pin assignments, in the form (VHDL Pin, FPGA Pin). Note+--       that Quartus will automatically split composite VHDL ports +---      (arrays and records) in various pins with different logical names. +data QuartusOps = +     QuartusOps {action :: QuartusAction,+                 fMax   :: Maybe Int,+                 fpgaFamiliyDevice :: Maybe (String, Maybe String),+                 pinAssigs :: [(String,String)] }+ deriving (Eq, Show)++-- | Action to perform by Quartus+data QuartusAction = AnalysisAndElaboration  -- ^ Analysis and eleboration flow+                   | AnalysisAndSynthesis -- ^ Call map executable +                   | FullCompilation -- ^ Compile flow+ deriving (Eq, Show)++-- | Options to check if the model is synthesizable, all options except+--   the action to take are set to default. +checkSynthesisQuartus :: QuartusOps+checkSynthesisQuartus = QuartusOps AnalysisAndSynthesis Nothing Nothing [] +++-- | Check if we are in recursive mode+isRecursiveSet :: VHDLM Bool+isRecursiveSet = do +  recOp <- gets (recursivityVHDL.ops.global)+  return $ recOp == VHDLRecursive++-- | Check if we want to compile the results with modelsim+isCompileModelsimSet :: VHDLM Bool+isCompileModelsimSet = gets (compileModelsim.ops.global)++-- | Default traversing options+defaultVHDLOps :: VHDLOps+defaultVHDLOps =  VHDLOps VHDLNormal VHDLRecursive Nothing False+++-- | Set VHDL options inside the VHDL monad+setVHDLOps :: VHDLOps -> VHDLM ()+setVHDLOps options =  modify (\st -> st{global=(global st){ops=options}})+++-------------------------------------+-- Useful functions in the VHDL Monad+-------------------------------------+++-- | Add a signal declaration to the 'LocalTravResult' in the State+addSigDec :: SigDec -> VHDLM ()+addSigDec dec = modify addFun + -- FIXME: use a queue for the declarations+  where addFun st = st{local=l{localRes=r{archDecs=ads ++ [BDISD dec]}}}+         where l  = local st+               r  = localRes l+               ads = archDecs r +++-- | Add a statement to the 'LocalTravResult' in the State+addStm :: ConcSm -> VHDLM ()+addStm sm = modify addFun+ -- FIXME: use a queue for the statements+  where addFun st = st{local=l{localRes=r{archSms=aSms ++ [sm]}}}+         where l  = local st+               r  = localRes l+               aSms = archSms r ++ +-- | Find a previously translated custom type+lookupCustomType :: TypeRep -> VHDLM (Maybe SimpleName)+lookupCustomType rep = do+ transTable <- gets (typeTable.global)+ return $ lookup rep transTable+++-- | Add enumerated types to the global state+addEnumTypes :: Set EnumAlgTy -> VHDLM ()+addEnumTypes newETs = do+ globalST <- gets global + let oldETs = enumTypes globalST+ modify (\st -> st{global = globalST {enumTypes = oldETs `union` newETs}})+ +-- | Check if a Template haskell 'Name' corresponding to+--   a Enumerated-type data constructor is present in the enumerated+--   types accumulated in the global state and return the corresponding+--   VHDL identifier.+getEnumConsId :: Name -> VHDLM (Maybe VHDLId)+getEnumConsId consName = do+ let consModule = (fromJust.nameModule) consName+     consBase = nameBase consName+ enums <- gets (enumTypes.global)+ let matchesName (EnumAlgTy dataName enums) = +                 tyconModule dataName == consModule && elem consBase enums+ case (toList.(S.filter matchesName)) enums of+   []  -> return Nothing+   [_] -> liftM Just (liftEProne $ mkVHDLExtId consBase) +   -- _ -> this shouldn't happen since the enumerated types stored are unique+   _ ->  intError "ForSyDe.Backend.VHDL.Traverse.VHDLM.getEnum" +          (UntranslatableVHDLFun $ GeneralErr (Other "pattern match inconsistency"))+++-- | Add a cutom type to the global results and type translation table+addCustomType :: TypeRep -> Either TypeDec SubtypeDec -> VHDLM ()+addCustomType rep eTD = do+ globalST <- gets global + let transTable = typeTable globalST+     gRes = globalRes globalST +     tDecs =  typeDecs gRes+     stDecs = subtypeDecs gRes+ -- FIXME: use queues+ modify (\st -> st{global = +                    case eTD of+                     Left td@(TypeDec id _) -> +                        globalST+                             {typeTable = transTable ++ [(rep, id)],+                              globalRes = gRes{typeDecs = tDecs ++ [td]}}+                     Right std@(SubtypeDec id _) -> +                        globalST+                             {typeTable = transTable ++ [(rep, id)],+                              globalRes = gRes{subtypeDecs = stDecs ++ [std]}}+                   })++-- | Add type declaration to the global results+addTypeDec :: TypeDec  -> VHDLM ()+addTypeDec td = do+ globalST <- gets global + let gRes = globalRes globalST +     tDecs =  typeDecs gRes+ -- FIXME: use queues+ modify (\st -> st{global = globalST{globalRes = gRes{typeDecs = tDecs ++ [td]}}})+++-- | Add subtype declaration to the global results+addSubtypeDec :: SubtypeDec  -> VHDLM ()+addSubtypeDec std = do+ globalST <- gets global + let gRes = globalRes globalST +     stDecs =  subtypeDecs gRes+ -- FIXME: use queues+ modify (\st -> st{global = globalST{+                              globalRes = gRes{subtypeDecs = stDecs ++ [std]}}})+++-- | Add an unconstrained FSVec to the global results+addUnconsFSVec :: TypeRep -> VHDLM ()+addUnconsFSVec trep = do+ globalST <- gets global + -- FIXME: use queues+ modify (\st -> st{global = +                    globalST{+                     transUnconsFSVecs = (transUnconsFSVecs globalST) ++ [trep]}})++-- | Add a subprogram to the global results+addSubProgBody :: SubProgBody -> VHDLM ()+addSubProgBody newBody = do+ globalST <- gets global + let gRes = globalRes globalST +     bodies = subProgBodies gRes+ -- FIXME: use queues+ modify (\st -> st{global = globalST+                       {globalRes = gRes{subProgBodies = bodies ++ [newBody]}}})+++-- | Add a TH-name (arity, VHDL expression construtor fucntion)  pair to the translation namespace table+addTransNamePair :: Name -> Int -> ([Expr] -> Expr) -> VHDLM ()+addTransNamePair thName arity vHDLFun = do+ lState <- gets local+ let ns = transNameSpace lState+     table = nameTable ns+ modify (\st -> st{local=lState{transNameSpace=ns{+                                       nameTable=(thName,(arity,vHDLFun)):table}}})++-- | Get a fresh VHDL Identifier and increment the+--   tranlation-namespace-count of freshly generated identifiers.+--+--   Note that all user-supplied identifiers (process ids, port ids,+--   and function parameters) are translated to extended VHDL+--   identifiers. That, together with the fact that basic and extended+--   VHDL identifers live in different namespaces, guarantees that+--   freshly generated basic VHDL identifiers cannot clash with the+--   ones supplied by the frontend.+genFreshVHDLId :: VHDLM VHDLId+genFreshVHDLId = do+ lState <- gets local+ let ns = transNameSpace lState+     count = freshNameCount ns+ modify (\st -> st{local=lState{transNameSpace=ns{freshNameCount=count+1}}})+ return $ unsafeVHDLBasicId ("fresh_" ++ show count) ++-- | Lift an 'EProne' value to the VHDL monad setting current error context+--   for the error+-- liftEProne :: EProne a -> VHDLM a+liftEProne :: EProne a -> VHDLM a+liftEProne ep = do+ cxt <- gets (context.local)+ either (throwError.(ContextErr cxt)) return ep++-- | Throw a ForSyDe error, setting current error context+throwFError :: ForSyDeErr -> VHDLM a+throwFError = liftEProne.Left++++-- | Execute certain operation with a concrete process context.+--   The initial context is restored after the operation is executed+--   Note: the initial context must be a system context or 'InconsistenContexts'+--         will be raised.+withProcC :: ProcId -> VHDLM a -> VHDLM a+withProcC pid action = do+  -- get the initial context+  st <- get+  let l = local st+      c = context l+  -- set the modified name context+  put st{local=l{context=setProcC pid c}}+  -- execute the action+  res <- action+  -- restore the initial name context+  st' <- get+  let l' = local st'+  put st'{local=l'{context=c}}+  -- return the result+  return res++++-- | Execute certain operation with a concrete process function context.+--   The initial context is restored after the operation is executed+--   Note: the initial context must be a process context or +--         'InconsistenContexts' will be raised.+withProcFunC :: Name -> Loc -> VHDLM a -> VHDLM a+withProcFunC name loc action = do+  -- get the initial context+  st <- get+  let l = local st+      c = context l+  -- set the modified context+  put st{local=l{context=setProcFunC name loc c}}+  -- execute the action+  res <- action+  -- restore the initial context+  st' <- get+  let l' = local st'+  put st'{local=l'{context=c}}+  -- return the result+  return res++++-- | Execute certain operation with a concrete process function context.+--   The initial context is restored after the operation is executed+--   Note: the initial context must be a process context or +--         'InconsistenContexts' will be raised.+withProcValC :: Exp -> VHDLM a -> VHDLM a+withProcValC exp action = do+  -- get the initial context+  st <- get+  let l = local st+      c = context l+  -- set the modified context+  put st{local=l{context=setProcValC exp c}}+  -- execute the action+  res <- action+  -- restore the initial context+  st' <- get+  let l' = local st'+  put st'{local=l'{context=c}}+  -- return the result+  return res+++----------------+-- IntSignalInfo+----------------++-- | Intermediate signal information. Tag generated for each output of each+--   node found during the traversal. +-- (see ForSyDe.Netlist.Traverse.traverseSIO).+--   It contains the VHDL intemediate signal name associated with the process +--   output.+type IntSignalInfo = SimpleName+
+ src/ForSyDe/Bit.hs view
@@ -0,0 +1,169 @@+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable, MultiParamTypeClasses,+             FunctionalDependencies, TypeSynonymInstances #-}  +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Bit+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- 'Bit' Datatype. Note that the 'Num' instance is phony and shouldn't be used+-- +-----------------------------------------------------------------------------+module ForSyDe.Bit (Bit(..), +                    not, +                    bitToBool, +                    boolToBit,+                    toBitVector8,+                    fromBitVector8,+                    toBitVector16,+                    fromBitVector16,+                    toBitVector32,+                    fromBitVector32,+                    toBitVector64,+                    fromBitVector64) where++import Language.Haskell.TH.Lift+import Data.Int+import Data.Bits+import Data.Generics (Data, Typeable)+import Prelude hiding (not)++import Data.Param.FSVec (FSVec, reallyUnsafeVector)+import qualified Data.Param.FSVec as V+import Data.TypeLevel.Num (D8,D16,D32,D64,Nat)++data Bit = H -- ^ High value +         | L -- ^ Low value+ deriving (Eq, Show, Data, Typeable)++$(deriveLift1 ''Bit)++-- | Not operation over bits+not :: Bit -> Bit+not = complement+++instance Bits Bit where+ H .&. x = x+ L .&. _ = L+ H .|. _ = H+ L .|. x = x+ xor H L = H+ xor L H = H+ xor _ _ = L+ complement L = H+ complement H = L+ shift x 0 = x+ shift _ _ = L+ rotate x _ = x+ bitSize _ = 1+ isSigned _ = False+++-- Phony instance of Num+instance Num Bit where+ H + L = H+ H + H = L+ L + x = x+ -- since they are unsigned and there are only two elements, (-) == (+)+ (-) = (+)+ -- multiplication is equivalent to (.&.)+ (*) = (.&.)+ -- since a bit is unsigned, it is equivalent to identity+ abs = id+ signum _ = L+ fromInteger n = if n<=0 then L else H++-- | Convert a bit to a boolean+bitToBool :: Bit -> Bool+bitToBool H = True+bitToBool L = False++-- | Convert a boolean to a bit+boolToBit :: Bool -> Bit+boolToBit True = H+boolToBit False = L++toBitVector8 :: Int8 -> FSVec D8 Bit+toBitVector8 = reallyUnsafeToBitVector+  +fromBitVector8 :: FSVec D8 Bit -> Int8+fromBitVector8 = fromBitVectorDef 0+++toBitVector16 :: Int16 -> FSVec D16 Bit+toBitVector16 = reallyUnsafeToBitVector+  +fromBitVector16 :: FSVec D16 Bit -> Int16+fromBitVector16 = fromBitVectorDef 0+++toBitVector32 :: Int32 -> FSVec D32 Bit+toBitVector32 = reallyUnsafeToBitVector+  +fromBitVector32 :: FSVec D32 Bit -> Int32+fromBitVector32 = fromBitVectorDef 0+++toBitVector64 :: Int64 -> FSVec D64 Bit+toBitVector64 = reallyUnsafeToBitVector+  +fromBitVector64 :: FSVec D64 Bit -> Int64+fromBitVector64 = fromBitVectorDef 0+++{- This would have been much more convenient+   But it makes things really complicated int he VHDL+   backend++-- | Datatypes  which can be converted to and from+--   vectors of bits+class BitStream d s | d -> s where+ -- | convert a data type to a bit vector+ toBitVector :: d -> FSVec s Bit+ -- | get a datatype from a bit vector+ fromBitVector :: FSVec s Bit -> d++instance BitStream Int8 D8 where+  toBitVector = reallyUnsafeToBitVector+  fromBitVector = fromBitVectorDef 0+++instance BitStream Int16 D16 where+  toBitVector = reallyUnsafeToBitVector+  fromBitVector = fromBitVectorDef 0+++instance BitStream Int32 D32 where+  toBitVector = reallyUnsafeToBitVector+  fromBitVector = fromBitVectorDef 0+++instance BitStream Int64 D64 where+  toBitVector = reallyUnsafeToBitVector+  fromBitVector = fromBitVectorDef 0+-}++-------------------+-- Helper functions+-------------------+reallyUnsafeToBitVector :: Bits a => a -> FSVec s Bit+reallyUnsafeToBitVector x = +  reallyUnsafeVector $ map (boolToBit.(testBit x)) [size-1,size-2..0]+ where size = bitSize x++-- | version of fromBitVector supplying a default initial value from which to +--   start working+fromBitVectorDef :: (Bits a, Nat s) => a -> FSVec s Bit -> a+fromBitVectorDef def vec = fst $ V.foldr f (def, 0) vec+  where f e (ac, pos)  = (copyBit e ac pos, pos+1)+        copyBit H = setBit+        copyBit L = clearBit+ ++ +
+ src/ForSyDe/Config.hs view
@@ -0,0 +1,23 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Config+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Configuration values of ForSyDe+--+-----------------------------------------------------------------------------+module ForSyDe.Config (maxTupleSize, module Paths_ForSyDe) where++import Paths_ForSyDe ++-- | Maximum tuple size+maxTupleSize :: Int+-- 62: this is the GHC-hardcoded value as of version 6.8.2+--     in the future there will be a way to avoid hardcoding this value.+--     See: http://hackage.haskell.org/trac/ghc/ticket/2364+maxTupleSize = 62
+ src/ForSyDe/DFT.hs view
@@ -0,0 +1,79 @@+{-# LANGUAGE ScopedTypeVariables, FlexibleContexts #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.DFT+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module includes the standard Discrete Fourier Transform (DFT)+-- function, and a fast Fourier transform (FFT) algorithm, for+-- computing the DFT, when the input vectors' length is a power of 2.+-----------------------------------------------------------------------------+module ForSyDe.DFT(dft, fft) where+++import qualified Data.Param.FSVec as V+import Data.Param.FSVec +import Data.TypeLevel (Nat, IsPowOf, D2)+import Data.Complex+++-- | The function 'dft' performs a standard Discrete Fourier Transformation+dft :: forall s . Nat s => FSVec s (Complex Double) -> FSVec s (Complex Double)+dft v = V.map (bigX_k v) nVector+   where+     lT = V.lengthT v+     lV = V.genericLength v+     -- FIXME: dft does not type-check without this type signature:+     --        learn why!+     nVector :: Num a => FSVec s a+     nVector = kVector lT+     fullCircle = V.map (\n -> -2*pi*n/lV) nVector+     bigX_k v k = sumV (V.zipWith (*) v (bigW k))+     bigW k = V.map (** k) (V.map cis fullCircle)+     sumV = V.foldl (+) (0:+ 0)+++-- | The function 'fft' implements a fast Fourier transform (FFT) algorithm, +--   for computing the DFT, when the size N is a power of 2.+fft :: (Nat s, IsPowOf D2 s) => +       FSVec s (Complex Double) -> FSVec s (Complex Double)+fft v = V.map (bigX v) (kVector lT)+   where lT = V.lengthT v++kVector :: (Num a, Nat s) => s -> FSVec s a      +kVector s = V.iterate s (+1) 0 +++bigX :: (Nat s, IsPowOf D2 s) => +        FSVec s (Complex Double) -> Integer ->  Complex Double+-- since there are no output length constraints (no vector is being returned)+-- we can simply obtain the list inside the vector and work with it directly+bigX v k = bigX' (V.genericLength v) (V.fromVector v) k+ where bigX' :: Integer -> [Complex Double] -> Integer ->  Complex Double+       -- The first argument is the length of the list (bigN)+       bigX' _ (x0:[x1]) k | even k = x0 + x1 * bigW 2 0+                           | odd k  = x0 - x1 * bigW 2 0+       bigX' l xs k = bigF_even + bigF_odd * bigW l k+           where bigF_even = bigX' halfl (evens xs) k+	         bigF_odd  = bigX' halfl (odds xs) k+                 halfl = l `div` 2++bigW :: Integer -> Integer -> Complex Double+bigW bigN k = cis (-2 * pi * (fromInteger k) / (fromInteger bigN))++evens :: [a] -> [a]+evens []  = []+evens [v1] = [v1] +evens (v1:_:v) = v1 : evens v++odds :: [a] -> [a]+odds [] = []+odds [_] = []+odds (_:v2:v) = v2 : odds v++
+ src/ForSyDe/FIR.hs view
@@ -0,0 +1,63 @@+{-# LANGUAGE TemplateHaskell, RelaxedPolyRec, PatternGuards #-}+-- The PatternGuards are used to hush innapropiate compiler warnings+-- see http://hackage.haskell.org/trac/ghc/ticket/2017+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.FIR+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module implements FIR filters for the synchronous computational model.+-----------------------------------------------------------------------------+module ForSyDe.FIR (fir) where++import ForSyDe.Ids+import ForSyDe.Signal+import ForSyDe.Process++import Data.TypeLevel.Num (Nat, Pos)+import Data.Param.FSVec hiding ((++))+import qualified Data.Param.FSVec as V+import Data.Typeable++-- | +-- All kinds of FIR-filters can now be modeled by means of 'fir'. The+-- only argument needed is the list of coefficients, which is given as+-- a vector of any size. To illustrate this, an 8-th order band pass+-- filter is modeled as follows.+--+-- > bp = fir "fir Id" $(vectorTH [0.06318761339784, 0.08131651217682, 0.09562326700432, +-- >                               0.10478344432968, 0.10793629404886, 0.10478344432968, +-- >                               0.09562326700432, 0.08131651217682, 0.06318761339784 ])+-- ++fir :: (Fractional b, ProcType b, Pos s, Typeable s) => +       ProcId -> FSVec s b -> Signal b -> Signal b+fir id h = innerProd (id ++ "_innerProd") h . sipo (id ++ "_sipo") k 0.0+    where k = V.lengthT h++sipo :: (Pos s, Typeable s, Fractional a, ProcType a) =>+        ProcId -> s -> a -> Signal a -> FSVec s (Signal a)+sipo id n s0 = unzipxSY (id ++ "_unzipxSY") . scanldSY (id ++ "_scanldSY") srV initState+    where initState = V.copy n s0+          srV = $(newProcFun [d| srV :: Pos s => FSVec s a -> a -> FSVec s a+                                 srV v a = V.shiftr v a |])++innerProd :: (Fractional a, ProcType a, Nat s, Typeable s) =>+             ProcId -> FSVec s a -> FSVec s (Signal a) -> Signal a+innerProd id h = zipWithxSY id (ipV `defArgVal` h)+   where ipV = $(newProcFun +                  -- We could make the inner product in one traverse +                  -- but FSVecs don't allow recursive calls+                  -- (they don't allow to check the constraints statically)+                  -- Thus, we traverse the vector twice+                  [d| ipV :: (Nat s, Num a) => FSVec s a -> FSVec s a -> a+                      ipV v1 v2 = +                          V.foldl (+) 0 $ V.zipWith (*) v1 v2 |])+++
+ src/ForSyDe/ForSyDeErr.hs view
@@ -0,0 +1,457 @@+{-# LANGUAGE FlexibleContexts #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.ForSyDeErr+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- ForSyDe error-related types and functions.+--+-----------------------------------------------------------------------------+module ForSyDe.ForSyDeErr + (ForSyDeErr(..),+  ContextErr(..),+  VHDLFunErr(..),+  VHDLExpErr(..),+  Context(..),+  setProcC,+  setProcFunC,+  setProcValC,+  Loc,+  EProne,+  liftEither,+  uError,+  intError,+  qError,+  qGiveUp,+  qPutTraceMsg,+  printError,+  printVHDLError,+  printGraphMLError,+  module Control.Monad.Error,+  module Debug.Trace) where+++import ForSyDe.Ids++import Data.Maybe (fromMaybe)+import Debug.Trace+import Control.Monad.Error +import Data.Dynamic+import Data.Typeable+import Language.Haskell.TH.Syntax +import Language.Haskell.TH.Ppr+import Language.Haskell.TH.PprLib+import Text.PrettyPrint.HughesPJ (render)++-------------+-- ForSyDeErr+-------------++-- | All Errors thrown or displayed in ForSyDe+data ForSyDeErr = +  -- Used in ForSyDe.ForSyDeErr              +  InconsistentContexts                       |+  -- Used in ForSyDe.Netlist+  EvalErr String                             |++  -- Used in ForSyDe.System.*+  -- | Not a variable name+  NonVarName Name                            | +  -- | Incompatible system function+  IncomSysF  Name Type                       | +  -- | Incompatible input interface length                +  InIfaceLength   (SysId,Int) ([String],Int)  | +  -- | Incompatible output interface length+  OutIfaceLength  (SysId,Int) ([String],Int)  |+  -- | Multiply defined port identifier                +  MultPortId  PortId                         |+  -- | Multiply defined process identifier                +  MultProcId  ProcId                         |+  -- | The system contains components from different subsystems with+  --   the same Identifiers                +  SubSysIdClash SysId (Maybe Loc) (Maybe Loc) |+  -- | Not a SysDef variable+  NonSysDef Name Type                        |++  -- Used in ForSyDe.Proc.ProcFun +  -- | Incorrect Declarations provided to create a ProcFun+  IncorrProcFunDecs [Dec]                    |++  -- Used in ForSyDe.Netlist.Traversable     +  -- | Inconsistent output tag+  InconsOutTag                               |++  -- Used in ForSyDe.Backend.Simulate+  -- | Inconsistent System Definition Port+  InconsSysDefPort PortId                    | +  -- | Dynamic type mismatch+  DynMisMatch Dynamic TypeRep                |+  -- | Signature mismatch+  SigMisMatch Type                           |+  -- | Simulation input signals length mismatch+  InLengthMisMatch Int Int                   | ++  -- Used in ForSyDe.Backend.VHDL.*+  -- | Empty VHDL identifier+  EmptyVHDLId                                |+  -- | Incorrect Basic VHDL Identifier+  IncVHDLBasId String                        |+  -- | Incorrect Extended VHDL Identifier+  IncVHDLExtId String                        |+  -- | Function untranslatable to VHDL (function name and error raised)+  UntranslatableVHDLFun VHDLFunErr           |+  -- | Expresion untranslatable to VHDL+  UntranslatableVHDLExp Exp VHDLExpErr       |+  -- Common Backend errors              +  -- | UnsUpported type+  UnsupportedType TypeRep                    |+  -- | Reserved identifier+  ReservedId String                          |+  -- | Unsupported process+  UnsupportedProc                            |+  -- | Quartus Failed+  QuartusFailed                              |+  -- | Modelsim Failed+  ModelsimFailed                             |++  -- | Other Errors+  Other String           ++-- | Function translation errors in the VHDL backend+data VHDLFunErr =+  -- | Insufficient number of parameters +  InsParamNum Int              |+  -- | Unsupported input pattern in function +  UnsupportedFunPat Pat        |+  -- | Multiple clauses+  MultipleClauses [Clause]     |+  -- | Guards in case alternatives are not supported+  FunGuardedBody Body          |+  -- | Where constructs in case alternatives are not supported+  FunWhereConstruct [Dec]      |+  -- | A general Error which applies to a function+  --   (e.g. its name or parameters are not a VHDL identifier,+  --         an error in an inner expression ... )+  GeneralErr ForSyDeErr+++instance Show VHDLFunErr where+  show (FunGuardedBody body) = "guards are not supported in functions:\n" +++                               (render.to_HPJ_Doc.(pprBody True)) body+  show (FunWhereConstruct decs) = +   "where constructs are not supported in functions:\n" +++   (render.to_HPJ_Doc.where_clause) decs +  show (InsParamNum n) = "insufficient number of parameters (" ++ show n ++ ")"+  show (UnsupportedFunPat pat) = +      "input pattern `" ++ pprint pat ++ "' is not supported"+  show (MultipleClauses cs) = "multiple clauses (" ++ +                              (show.length) cs ++ "):\n" ++ pprint cs+  show (GeneralErr err) = show err++-- | Expression translation errors in the VHDL backend+data VHDLExpErr =+  -- | Guards in case alternatives are not supported+  CaseGuardedBody Body     |+  -- Unsupported case pattern +  UnsupportedCasePat Pat   |+  -- | Where constructs in case alternatives are not supported+  CaseWhereConstruct [Dec] |+  -- | Currification not supported function arguments must be fully supplied+  CurryUnsupported Int Int |+  -- | Unkown identifier+  UnkownIdentifier Name    |+  -- Unsupported literal+  UnsupportedLiteral       |+  -- Sections are not supported+  Section                  |+  -- Lambda Abstractions are not supported+  LambdaAbstraction        |+  -- Conditional expressions are only supported in a function body+  Conditional              |+  -- Let expressions are not supported+  Let                      |+  -- Case expressions are only supported in a function body+  Case                     |+  -- Do expressions are not supported+  Do                       |+  -- List comprehensions are not supported+  ListComprehension        |+  -- Arithmetic sequences are not supported+  ArithSeq                 |+  -- Lists are not supported+  List                     |+  -- Signature expressiosn are not supported+  Signature                |+  -- Record expressions are not supported+  Record                   |+  -- Unsupported expression generic error+  -- it shouldn't be raised, just for pattern completeness+  Unsupported++instance Show VHDLExpErr where+ show (CaseGuardedBody body) = +  "guards are not supported in case alternatives:\n" +++  (render.to_HPJ_Doc.(pprBody True)) body+ show (UnsupportedCasePat pat) = "unsupported case pattern: `" ++ +                                 pprint pat ++ "'"+ show (CaseWhereConstruct decs) = +   "where constructs are not supported in case alternatives:\n" +++   (render.to_HPJ_Doc.where_clause) decs + show (CurryUnsupported expected real) =+    "Currification is not supported, all arguments must be fully supplied\n"+++    "  Expected arguments: " ++ show expected ++ " Provided arguments: " ++ +    show real + show (UnkownIdentifier name) = "unkown identifier `" ++ pprint name ++ "'"+ show UnsupportedLiteral = "unsupported literal"+ + show Section            = "sections are not supported"+ show LambdaAbstraction  = "lambda abstractions are not supported"+ show Conditional        = "conditional expressions are only supported within" +                           ++ " a function body"+ show Let                = "let expressions are not supported"+ show Case               = "case expressions are only supported within" +                           ++ " a function body"+ show Do                 = "do expressions are not suupported"+ show ListComprehension  = "list comprehensions are not supported"+ show ArithSeq           = "arithmetic sequences are not supported"+ show List               = "lists are not supported" + show Signature          = "signature expressions are not supported"+ show Record             = "record expressions are not supported"+ show Unsupported        = "unsupported expression"++-- | Show errors+instance Show ForSyDeErr where+ show InconsistentContexts = "Inconsistent contexts"+ show (EvalErr str) = "Non evaluable node (" ++ show str ++ ")"+ show (NonVarName name) = show name ++ " is not a variable name."+ show (IncomSysF fName inctype) = +   "Incompatible system function type\n"+++   show strFName ++ " was expected to have type:\n" +++   "  Signal i1 -> Signal i2 -> ..... -> Signal in ->\n" +++   "  (Signal o1, Signal o2, ... , Signal om)\n" +++   "  with n <- |N U {0} and m <- |N U {0}\n"  ++ +   "       i1 .. in, o1 .. im monomorphic types\n" +++   "However " ++ strFName ++ " has type\n  " +++   "  " ++ pprint inctype+  where strFName = show fName+ show (InIfaceLength sysInInfo portIdsInInfo) =+    showIfaceLength "input interface" sysInInfo portIdsInInfo+ show (OutIfaceLength sysOutInfo portIdsOutInfo) =+    showIfaceLength "output interface" sysOutInfo portIdsOutInfo+ show (MultPortId  portId) = +   "Multiply defined port identifier " ++ show portId+ show (MultProcId procId) = +   "Multiply defined process identifier " ++ show procId+ show (SubSysIdClash subSysId mLoc1 mLoc2) =+   "System contains components of different subsystems " ++ +   "(defined at locations " ++ finalLoc1 ++ " and " ++ finalLoc2 ++ ") " +++   "which share the same system identifier (`"++subSysId++")"+  where finalLoc1 = fromMaybe "<unkown>" mLoc1+        finalLoc2 = fromMaybe "<unkown>" mLoc2 + show (NonSysDef name t) = +   "A variable with SysDef type was expected\n" +++   "However " ++ show name ++ " has type " ++ pprint t+ show (IncorrProcFunDecs decs) =+  "Only a function declaration (possibly precedeeded by a signature)" ++ +  "is accepted\n"++ +  "The specific, incorrect declarations follow:\n" +++  pprint decs+ show InconsOutTag = "Inconsistent output tag"+ show (InconsSysDefPort id) = "Inconsistent port in SysDef: " ++ show id+ show (DynMisMatch dyn rep) = +   "Type matching error in dynamic value with typerep " ++ +   show (dynTypeRep dyn) +++   "\n(Expected type: " ++ show rep ++ " )."+ show (SigMisMatch t) = +  "Signal mismatch:  expected a Signal type but got " ++ pprint t + show (InLengthMisMatch l1 l2) = +   "Cannot simulate: simulation arguments length-mismatch: " ++ +     show l1 ++ " /= " ++ show l2+ show EmptyVHDLId = "Empty VHDL identifier"+ show (IncVHDLBasId id)  = "Incorrect VHDL basic identifier " ++ +                           "`" ++ id ++ "'"+ show (IncVHDLExtId id)  = "Incorrect VHDL extended identifier " ++ +                           "`" ++ id ++ "'"+ show (UnsupportedType tr) = "Unsupported type " ++ show tr+ show (ReservedId str)  = "Identifier `" ++ str ++ "' is reserved"+ show UnsupportedProc = "Unsupported process"+ show (UntranslatableVHDLFun err) = +    "Untranslatable function: " ++ show err     + show (UntranslatableVHDLExp exp err) = +    "Untranslatable expression `" ++ pprint exp ++ "': " ++ show err     + show QuartusFailed = "Quartus failed"+ show ModelsimFailed = "Modelsim failed"+ show (Other str) = str ++-- | help function for the show instance+showIfaceLength :: String -> (SysId, Int) -> ([String],Int) -> String+showIfaceLength ifaceMsg  (sysName, sysIfaceL) (ifaceIds, ifaceL) = +   "Incorrect length of " ++ ifaceMsg  ++ " (" ++ show ifaceL ++ ")\n" +++   "  " ++ show ifaceIds ++ "\n" ++    +   sysName ++ " expects an " ++ show ifaceMsg ++ " length of " +++   show sysIfaceL ++-----------------+-- Context Error+-----------------++-- | A context error: a 'ForSyDeErr' with context information (indicating where+--   the error ocurred)+data ContextErr = ContextErr Context ForSyDeErr++-- | A context: it indicates where an error ocurred.+data Context =+ -- | Empty context + EmptyC | + -- | In a System definition + SysDefC SysId (Maybe Loc) | + -- | In a Process+ ProcC   SysId (Maybe Loc) ProcId | + -- | In a Proces Function+ ProcFunC SysId (Maybe Loc) ProcId Name Loc | + -- | In  a Process value+ ProcValC SysId (Maybe Loc) ProcId Exp++-- | type indicating a location in the user's source+--   code+type Loc = String++-- | Set a process context from a system context+setProcC :: ProcId -- ^ Identifier of the process+        -> Context -- ^ system context+        -> Context+setProcC pid (SysDefC sysid mSysloc) = ProcC sysid mSysloc pid +setProcC _ _ = intError funName InconsistentContexts+ where funName = "ForSyDe.ForSyDeErr.setProcC" ++-- | Set a process function context from a process context +setProcFunC :: Name -- ^ Function name+        -> Loc -- ^ Function location+        -> Context -- ^ system context+        -> Context+setProcFunC name loc (ProcC sysid sysloc pid) = + ProcFunC sysid sysloc pid name loc+setProcFunC _ _ _ = intError funName InconsistentContexts+ where funName = "ForSyDe.ForSyDeErr.setProcFunC" ++-- | Set a process value context from a process context +setProcValC :: Exp -- ^ Expression value+        -> Context -- ^ system context+        -> Context+setProcValC exp (ProcC sysid sysloc pid) = ProcValC sysid sysloc pid exp+setProcValC _ _ = intError funName InconsistentContexts+ where funName = "ForSyDe.ForSyDeErr.setProcValC" ++instance Show Context where+ show EmptyC = ""+ show (SysDefC id mLoc)   = "system definition `" ++ id ++ +                           "' (created in " ++ finalLoc ++ ")"+  where finalLoc = fromMaybe "<unkown>" mLoc+ show (ProcC sysid sysloc pid) = "process `" ++ pid ++ "' belonging to " ++ +                      show (SysDefC sysid sysloc)+ show (ProcFunC sysid sysloc pid fName fLoc) = +   "process function `" ++ pprint fName ++ "' (created in " ++ fLoc ++ ") " +++   " used by  " ++  show (ProcC sysid sysloc pid)+ show (ProcValC sysid sysloc pid valExp) =+   "process argument `" ++ pprint valExp ++ "' used by  "+   ++ show (ProcC sysid sysloc pid)+ ++instance Show ContextErr where+ show (ContextErr cxt err) = case cxt of+  EmptyC -> show err+  _ -> show err ++ "\nin " ++ show cxt++--------------+-- Error Monad+--------------++-- | We make ForSyDeErr an instance of the Error class to be able to throw it+-- as an exception.+instance Error ForSyDeErr where+ noMsg  = Other "An Error has ocurred"+ strMsg = Other+++instance Error ContextErr where+ noMsg = ContextErr EmptyC noMsg+ strMsg = \str ->  ContextErr EmptyC (strMsg str)++-- | 'EProne' represents failure using Left ForSyDeErr  or a successful +--   result of type a using Right a+-- +--  'EProne' is implicitly an instance of +--   ['MonadError']  (@Error e => MonadError e (Either e)@)+--   ['Monad']       (@Error e => Monad (Either e)@)+type EProne = Either ForSyDeErr+-- FIXME: Rethink Eprone so that it takes contexts in account++-------------------+-- Helper functions+-------------------++-- | Throws a an error caused by improper use of a user-exported function+uError :: String -- ^ User-exported function which cuased the error +          -> ForSyDeErr -- ^ Error to show+          -> a+uError funName err = error $ "User error in " ++ funName ++ ": " ++ +                             show err ++ "\n"+++-- | Throws an internal error+intError :: String     -- ^ Function which caused the internal error +         -> ForSyDeErr -- ^ Error to show+         -> a+intError funName err = error $ "Internal error in " ++ funName ++ ": " ++ +                               show err ++ "\n" +++                               "Please report!"++-- | lift an Either expression to an Error Monad+liftEither :: MonadError e m => Either e a  -> m a+liftEither = either throwError return++++-- | An error reporting function for Quasi monads+--   Executing in the monad will stop inmideately after calling qError+-- Note, it does not work for GHC<6.8+-- see <http://hackage.haskell.org/trac/ghc/ticket/1265>+qError :: Quasi m => String      -- ^ The name of the function  +                                 --   called in the splice +                     -> ForSyDeErr  -- ^ Error to show+                     -> m a+qError fname err =  fail $ "Error when calling " ++ fname ++ ":\n"  ++ +                           show err+++-- | Stop execution, find the enclosing qRecover+--   if a recover is not found, it is considered as an internal error+--   and the string provided will used as a reference to +--   the origin of the error.+-- Note, it does not work for GHC<6.8+-- see <http://hackage.haskell.org/trac/ghc/ticket/1265>+qGiveUp :: Quasi m  =>  String -> m a+qGiveUp name = fail $ "qGiveUp: Internal error in " ++ name ++ +                      ", please report."++-- | Output a trace message in a quasi monad (similar to 'putTraceMsg')+qPutTraceMsg :: Quasi m => String -> m ()+qPutTraceMsg msg = qRunIO (putTraceMsg msg)+++-- | Print an Error+printError :: Show a => a -> IO ()+printError = putStrLn.("Error: "++).show++-- | Print a VHDL compilation error+printVHDLError :: Show a => a -> IO b+printVHDLError = error.("VHDL Compilation Error: "++).show++-- | Print a GraphML compilation error+printGraphMLError :: Show a => a -> IO ()+printGraphMLError = putStrLn.("VHDL Compilation Error: "++).show
+ src/ForSyDe/Ids.hs view
@@ -0,0 +1,23 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Ids+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- ForSyDe  identifier types+--+-----------------------------------------------------------------------------+module ForSyDe.Ids where++-- | A process identifier+type ProcId = String++-- | A Port identifier+type PortId = String++-- | A System identifier+type SysId = String
+ src/ForSyDe/Netlist.hs view
@@ -0,0 +1,251 @@+{-# LANGUAGE DeriveDataTypeable, GeneralizedNewtypeDeriving #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Netlist+-- Copyright   :  (c) Sam Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides a definition for the netlist of a system description, +-- which is used as the intermediate representation of the embedded compiler.+-- +-- The netlist is modelled as a directed cyclic graph whose nodes +-- are shared using Observable Sharing ("ForSyDe.OSharing").+--+-- /This module is based on Lava2000/: <http://www.cs.chalmers.se/~koen/Lava/>+-- +-----------------------------------------------------------------------------++module ForSyDe.Netlist  where+++import ForSyDe.Ids+import ForSyDe.OSharing (URef, newURef, readURef)+import {-# SOURCE #-} ForSyDe.System.SysDef + (SysDef(..), PrimSysDef(..), oIface)+import ForSyDe.Process.ProcFun (TypedProcFun(..))+import ForSyDe.ForSyDeErr+import ForSyDe.Process.ProcVal (ProcVal(..))++import Data.Dynamic+++-----------+-- Netlist+-----------+++-- | The netlist of a system is modelled as a directed cyclic graph but is+-- really equivalently implemented as a set of (possibly overlapping) trees+-- capable of sharing nodes between them.+--+-- There is no specific data structure for the netlist itself. Instead, a+-- netlist is simply represented by its outputs. Each output is the root node+-- of a tree ('NlTree'). The NlTrees can (and probably will) have common nodes.+--+-- It is important to note that, due to the use of trees, the only way to+-- traverse a 'Netlist' is from its outputs to its inputs.++newtype Netlist container = Netlist {netlistOuts :: (container NlTree)}++++----------+-- NlNode+----------++-- | A node of the netlist can be either a process, component instances or+-- special nodes to help traversing the graph.  +--+-- Since the netlist graph is implemented with trees, they only store+-- information about their inputs (which are their child nodes in the tree).++data  NlNode inputi =+             -- Ports+             InPort  PortId               | -- ^ Input Ports of the system +             -- Processes+             Proc ProcId (NlProc inputi)+++-- | A process node+--   Note that vectors and transformed to lists puls an Int parameter +--   indicating its size+data NlProc inputi =+ -- Constant signal + Const ProcVal  | -- ^ A signal with constant value+                  --   During all its periods        +              + -- | mapSY and zipWithSY processes+ ZipWithNSY (TypedProcFun Dynamic) -- Process function in dynamic form+            [inputi]                                | + + -- | Vector version of zipWithNSY+ ZipWithxSY (TypedProcFun ([Dynamic] -> Dynamic))     -- Process function +                                                      -- with dynamic arguments +             [inputi]                               | + + -- ^ Inverse of ZipWithNSY+ UnzipNSY [TypeRep] -- Type of the elements in the input tuple+                    -- (type of outputs)+          (Dynamic -> [Dynamic]) -- Dynamic version of the unzipping function+                                 -- for the concrete, monomorphic types+                                 -- of the process+          inputi                                    | + + -- | Vector version of UnzipSY+ UnzipxSY TypeRep -- Type of elements in the input vector+                  -- (and type of the outputs)+          Int -- Size of output vector (Number of output signals)+          (Dynamic -> [Dynamic])             +          inputi                                    |  ++ -- | delaySY process+ DelaySY    ProcVal    inputi                       | + + -- A System Instance is considered a special process+ + -- | System Instance+ SysIns PrimSysDef [inputi]                 + +         ++---------+-- NlEdge+---------++-- FIXME: The NLNodeOut should merely be an integer++-- | The node connection is carried out by directed edges modelled as +--   Unsafe Unmutable References (allowing to share nodes) connected +--   in the output->input direction (remember we are using trees). +--   Since the node to which the edge is directed can have various outputs +--   (e.g a system instance) the edge is tagged to indicate to what +--   output it refers to.+data NlEdge node = NlEdge (ForSyDe.OSharing.URef node) NlNodeOut+                           ++-- FIXME: output tags are ugly, create a variant of NlNode which takes outputs in account++-- | The different outputs which the different nodes can have+data NlNodeOut = InPortOut        |+                 ConstOut         |+                 ZipWithNSYOut    |+                 ZipWithxSYOut    |+                 UnzipNSYOut Int  |+                 UnzipxSYOut Int  |+                 DelaySYOut       |+                 SysInsOut PortId + deriving (Show, Eq)                ++-- | Get the output tags of a node+outTags :: NlNode a -> [NlNodeOut]+outTags (InPort  _) = [InPortOut]+outTags (Proc _ proc) =+ case proc of+   Const _ -> [ConstOut]+   ZipWithNSY _ _ -> [ZipWithNSYOut]+   ZipWithxSY _ _ -> [ZipWithxSYOut] +   UnzipNSY types _ _  -> map UnzipNSYOut [1..length types]+   UnzipxSY _ nout _ _  -> map UnzipxSYOut [1..nout]+   DelaySY    _ _  -> [DelaySYOut]+   SysIns primSysDefRef _ -> +       map (SysInsOut . fst) ((oIface . readURef . unPrimSysDef) primSysDefRef)++ ++------------+-- NlTree+------------++-- | We tie the knot to connect nodes through 'NlEdge's, building a Tree which+--   can have shared nodes.  +--+-- That is done by storing 'NlTree's as the the input information of each node+-- of the tree. Child nodes of the tree are closer to the inputs of the system+-- and parents are closer to the outputs.++newtype NlTree = NlTree  {rootEdge :: (NlEdge (NlNode NlTree))}++-----------+-- NlSignal+-----------++-- | A 'NlTree', or more preciselly its root 'NlEdge', is after all, how+-- signals are implemented in the netlist.+type NlSignal = NlTree++-- | Get the tag of a signal+nlSignalNlOut :: NlSignal -> NlNodeOut+nlSignalNlOut (NlTree (NlEdge _ tag)) = tag++---------+-- Signal+---------+++-- | A signal can be seen as wire which carries values of certain type +--   and which can be connected and processed by the two computational +--   entities of a ForSyDe system: processes and block instances.+--++--   A Signal is internally represented as an edge of the graph representing+--   the system netlist.  +--   The phantom type parameter ensures type-consistency for the signal+--   processing functions.  ++newtype Signal a = Signal {unSignal :: NlSignal}+ deriving Typeable+++-------------------+-- Helper functions+-------------------++-- FIXME: All these newWhatever functions probably shouldn't be here++-- | Generate a signal pointing to an 'InPort' node+newInPort :: PortId -> NlSignal+newInPort id = NlTree (NlEdge (newURef (InPort id)) InPortOut)+++-- | Generate a reference to a new 'SysIns' node+newSysIns :: ProcId -> SysDef a -> [NlSignal] +             -> URef (NlNode NlSignal)+newSysIns id (SysDef primSysDef) inputInfo = +    newURef (Proc id (SysIns primSysDef inputInfo))   ++-- | Generate the output signal of a node+newNodeOutSig :: URef (NlNode NlSignal)  -- ^ Reference to the node +              -> NlNodeOut               -- ^ Output tag+              -> NlSignal+newNodeOutSig ref mTag  = NlTree (NlEdge ref mTag)+++-- | Evaluate the output of a process within a synchronous period+--   The inputs and outputs are given in dynamic form+eval :: NlNode Dynamic -> [(NlNodeOut, Dynamic)]+eval node = case node of+ InPort _ -> intError evalStr (EvalErr "InPort")+ Proc _ proc -> case proc of+    Const pv -> [(ConstOut, dyn pv)]+    ZipWithNSY fun dynArgs+      -> [(ZipWithNSYOut, foldl1 dynApp ((tval fun) : dynArgs))]  +    ZipWithxSY fun dynListArg+      -> [(ZipWithxSYOut, (tval fun) dynListArg)]+    UnzipNSY _ fun dynArg+      -> zipWith (\n dyn -> (UnzipNSYOut n, dyn))+                 [1..] +                 (fun dynArg) +    UnzipxSY _ _ fun dynArg+      -> zipWith (\n dyn -> (UnzipxSYOut n, dyn))+                 [1..] +                 (fun  dynArg) +    DelaySY _ _                   +      -> intError evalStr (EvalErr "DelaySY")+    SysIns  _ _                   +      -> intError evalStr (EvalErr "SysIns")+ + where evalStr = "ForSyDe.Netlist.eval"
+ src/ForSyDe/Netlist/Traverse.hs view
@@ -0,0 +1,194 @@+{-# LANGUAGE ScopedTypeVariables #-} +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Netlist.Traverse+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (LSTV)+--+-- This module provides traversing operations for 'ForSyDe.Netlist'+--+--+-- /This module is based on Lava2000/: <http://www.cs.chalmers.se/~koen/Lava/>+-- +-----------------------------------------------------------------------------+module ForSyDe.Netlist.Traverse  where+++import ForSyDe.Netlist+import ForSyDe.OSharing+import ForSyDe.ForSyDeErr+++import Data.Maybe (fromMaybe)+-- qualified to avoid nameclash+import qualified Data.Foldable  as DF (Foldable(foldMap), toList)+import Data.Monoid (mempty)+-- qualified to avoid nameclash+import qualified Data.Traversable as DT (Traversable(traverse,mapM)) +import Control.Applicative (pure, (<$>))+import Control.Monad.State+import Data.List (lookup)+import Control.Monad.ST (ST)++-- Instances to traverse a netlist Node (and implicitly the whole netlist)++instance DF.Foldable NlProc where+ foldMap _ (Const _)  = mempty + foldMap f (ZipWithNSY _ is)   = DF.foldMap f is+ foldMap f (ZipWithxSY _ is) = DF.foldMap f is+ foldMap f (UnzipNSY _ _ i)    = f i+ foldMap f (UnzipxSY _ _ _ i)  = f i                                  + foldMap f (DelaySY _ i)       = f i+ foldMap f (SysIns  _ i)       = DF.foldMap f i++++instance DF.Foldable NlNode where+ foldMap _ (InPort  _)   = mempty+ foldMap f (Proc _ proc) = DF.foldMap f proc++instance Functor NlProc where+ fmap _ (Const val)          = Const val+ fmap f (ZipWithNSY pf is)  = ZipWithNSY pf (fmap f is)+ fmap f (ZipWithxSY pf is)  = ZipWithxSY  pf (fmap f is)+ fmap f (UnzipNSY ts pf i)  = UnzipNSY ts pf (f i)+ fmap f (UnzipxSY t n pf i) = UnzipxSY t n pf (f i)                       + fmap f (DelaySY c i)       = DelaySY c (f i)+ fmap f (SysIns def is)     = SysIns def (fmap f is)++++instance Functor NlNode where+ fmap _ (InPort  id)         = InPort  id+ fmap f (Proc id proc)       = Proc id (fmap f proc) ++instance DT.Traversable NlProc where+ traverse _ (Const val) = pure (Const val) + traverse f (ZipWithNSY pf is)  = ZipWithNSY pf <$> DT.traverse f is+ traverse f (ZipWithxSY pf is)  = ZipWithxSY pf <$> DT.traverse f is+ traverse f (UnzipNSY ts pf i)  = UnzipNSY ts pf <$> f i+ traverse f (UnzipxSY t n pf i) = UnzipxSY t n pf <$> f i+ traverse f (DelaySY c i)       = DelaySY c <$> f i+ traverse f (SysIns def is)     = SysIns def <$> DT.traverse f is+++++instance DT.Traversable NlNode where+ traverse _ (InPort  id)   = pure (InPort id)+ traverse f (Proc id proc) = Proc id <$> DT.traverse f proc +++-- | Traversing monad, stacking state and error transformers over IO+type TravSEIO s e a = (StateT s (ErrorT e IO)) a++++-- | traverseSIO traverses a netlist and returns a final user-defined +--   traversing state (@s@) given:+--  new: generates a new (and normally unique) tag for the outputs of each +--       netlist node given the traversing state (which is possibly updated +--       as well).+--  define: given the output tags of a node, current iteration state, +--          and the output tags of its children, @define@+--          generates the netlist of that node, possibly updating +--          the traversing state+-- FIXME: shoudn't the arguments of define go the other way around?+--        first inputs then outputs.+-- FIXME: why are tags needed in define? [oinfo] should be enough.+--        tags are ugly in general (see the pattern matches) fix this problem.+traverseSEIO :: (DT.Traversable container, Error e) => +         (NlNode NlSignal -> TravSEIO s e [(NlNodeOut, oinfo)]) -- ^ new+      -> ([(NlNodeOut, oinfo)] -> NlNode oinfo -> TravSEIO s e ()) -- ^ define+      -> Netlist container +      -> TravSEIO s e (container oinfo)+traverseSEIO new define (Netlist rootSignals) =+  do uRefTable <- liftIO $ newURefTableIO++     let gather (NlTree (NlEdge nodeRef tag)) =+           do visited <- liftIO $ queryIO uRefTable nodeRef+              case visited of+                Just infoPairs  -> return (specifyOut tag infoPairs)+                Nothing -> do +                  let node = readURef nodeRef+                  infoPairs <- new node+                  liftIO $ addEntryIO uRefTable nodeRef infoPairs+                  childInfo <- DT.mapM gather node+                  define infoPairs childInfo+                  return (specifyOut tag infoPairs)++         specifyOut :: NlNodeOut -> [(NlNodeOut, a)] -> a+         specifyOut tag pairs = fromMaybe err maybeOut+             where funName = "ForSyDe.NetList.Traverse.traverseIO"+                   err = intError funName InconsOutTag+                   maybeOut = lookup tag pairs++     DT.mapM gather rootSignals++-- | Traversing monad, stacking state and error transformers over ST+type TravSEST s e st a = (StateT s (ErrorT e (ST st))) a++-- | 'ST'-monad  version of 'traverseSEIO'+traverseSEST :: (DT.Traversable container, Error e) => +         (NlNode NlSignal -> TravSEST s e st [(NlNodeOut, oinfo)]) -- ^ new+      -> ([(NlNodeOut, oinfo)] -> NlNode oinfo -> TravSEST s e st ()) -- ^ define+      -> Netlist container +      -> TravSEST s e st (container oinfo)+traverseSEST new define (Netlist rootSignals) =+  do let lift2 = lift.lift+     uRefTable <- lift2 $ newURefTableST+     let gather (NlTree (NlEdge nodeRef tag)) =+           do visited <- lift2 $ queryST uRefTable nodeRef+              case visited of+                Just infoPairs  -> return (specifyOut tag infoPairs)+                Nothing -> do +                  let node = readURef nodeRef+                  infoPairs <- new node+                  lift2 $ addEntryST uRefTable nodeRef infoPairs+                  childInfo <- DT.mapM gather node+                  define infoPairs childInfo+                  return (specifyOut tag infoPairs)++         specifyOut :: NlNodeOut -> [(NlNodeOut, a)] -> a+         specifyOut tag pairs = fromMaybe err maybeOut+             where funName = "ForSyDe.NetList.Traverse.traverseIO"+                   err = intError funName InconsOutTag+                   maybeOut = lookup tag pairs++     DT.mapM gather rootSignals++-- deprecated, do not use+traverseST :: DT.Traversable container => +             (NlNode NlSignal -> ST s [(NlNodeOut, oinfo)]) +          -> ([(NlNodeOut, oinfo)] -> NlNode oinfo -> ST s ()) +          -> Netlist container +          -> ST s (container oinfo)+traverseST new define (Netlist rootSignals) =+  do uRefTable <- newURefTableST++     let gather (NlTree (NlEdge nodeRef tag)) =+           do visited <- queryST uRefTable nodeRef+              case visited of+                Just infoPairs  -> return (specifyOut tag infoPairs)+                Nothing -> do let node = readURef nodeRef+                              infoPairs <- new node+                              addEntryST uRefTable nodeRef infoPairs+                              childInfo <- DT.mapM gather node+                              define infoPairs childInfo+                              return (specifyOut tag infoPairs)++         specifyOut :: NlNodeOut -> [(NlNodeOut, a)] -> a+         specifyOut tag pairs = fromMaybe err maybeOut+             where funName = "ForSyDe.NetList.Traverse.traverseST"+                   err = intError funName InconsOutTag+                   maybeOut = lookup tag pairs++     DT.mapM gather rootSignals++-- | Obtain the arguments of a node+arguments :: NlNode a -> [a]+arguments = DF.toList
+ src/ForSyDe/OSharing.hs view
@@ -0,0 +1,207 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.OSharing+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides support for Observable Sharing: <http://www.cs.chalmers.se/~koen/pubs/entry-asian99-lava.html>+-- +-- It provides:+--+--   * 'URef': Unsafe Unmutable references, using them causes side effects.+--+--   * 'URefTable': a table were 'URef's are used as key and can store+--     any value.+--    +-- /This Module was taken from Lava2000's/ @Ref.hs@ /module/:+--   <http://www.cs.chalmers.se/~koen/Lava/>+-- +-- IMPORTANT WARNING: Even if all the functions causing side effects+--                    are set as NOINLINE and that all currently known+--                    Haskell compilers are based in graph reduction+--                    (i.e. referential transparency will be preserved if +--                    sharing is), there are other optimisations than inlining+--                    that can break Observable Sharing, e.g. Common +--                    Subexpression Elimination (CSE).+-----------------------------------------------------------------------------+module ForSyDe.OSharing+  ( -- Unsafe references+    URef, +    newURef,       +    readURef,     +    -- Tables of Unsafe References (IO version)+    URefTableIO,   +    newURefTableIO,   +    addEntryIO,  +    queryIO,+    -- Tables of Unsafe References (IO version)+    URefTableST,+    newURefTableST,+    addEntryST,+    queryST,+    -- Memoizating functions+    memoURef,+    memoURefIO,+    memoURefST)+ where++import ForSyDe.OSharing.UDynamic++import System.IO (fixIO)+import System.IO.Unsafe (unsafePerformIO)+import Data.IORef (IORef, newIORef, readIORef, writeIORef)+import Control.Monad.ST++++-- | An Unsafe Unmutable Reference to a value of type a +--+-- An 'URef' is implemented as follows: it has two pieces of information. The+-- first one is an updatable list of entries for each table it is a member in.+-- Since the types of the Tables vary, the URef has no idea what type of+-- values it is supposed to store. So we use dynamic types.+--+-- Since it is an updatable list, it is an IORef, which we also use to compare+-- two 'URef's. The second part is just the value the URef is pointing at (this+-- can never change anyway since references are unmutable).+--+-- FIXME: why IORef? it should maybe be STRef?+--        Besides: Is it guaranteed that the values of an IORef+--        are not changed by the garbage collector?+data URef a+  = URef (IORef [(URefTableTag, UDynamic)]) a++instance Eq (URef a) where+  URef r1 _ == URef r2 _ = r1 == r2++instance Show a => Show (URef a) where+  showsPrec _ (URef _ a) = showChar '{' . shows a . showChar '}'+++-- | Create a new Unsafe Unmutable Reference to a Haskell object+--+--   This operation, as explained in the Observable sharing paper, can cuase+--   side-effects, since the value returned (the 'URef') is not determined by+--   the arguments of the function (i.e. different calls to 'newURef' with+--   the same argument return different 'URef's). +newURef :: a -> URef a+newURef a = unsafePerformIO $+  do r <- newIORef []+     return (URef r a)+{-# NOINLINE newURef #-}++-- | Read the value pointed by the 'URef'.+readURef :: URef a -> a+readURef (URef _ a) = a++--------------+-- URefTableIO +--------------++-- | A unique identifier which univocally designates a table +type URefTableTag+  = IORef ()+++-- | A 'URefTable' a b +-- +-- * Unsafe References to a value of type "a" (key of the table)+-- * Values of type "b" associated to each key+-- +-- Here is how we implement Tables of URefs:+--+-- A Table is nothing but a unique tag, of type TableTag.  TableTag can be+-- anything, as long as it is easy to create new ones, and we can compare them+-- for equality. (I chose IORef ()).+--+-- So how do we store URefs in a Table? We do not want the Tables keeping+-- track of their URefs (which would be disastrous when the table becomes big,+-- and we would not have any garbage collection).+--+-- Instead, every URef keeps track of the value it has in each table it is+-- in. This has the advantage that we have a constant lookup time (if the+-- number of Tables we are using is small), and we get garbage collection of+-- table entries for free.+newtype URefTableIO a b+  = URefTableIO URefTableTag+ deriving Eq++-- | Create a new table+newURefTableIO :: IO (URefTableIO a b)+newURefTableIO = URefTableIO `fmap` newIORef ()++-- | Query the value corresponding to an 'URef' +queryIO :: URefTableIO a b -> URef a -> IO (Maybe b)+queryIO (URefTableIO t) (URef r _) =+  do list <- readIORef r+     return (unsafeFromUDyn `fmap` lookup t list)++-- | Add an ('URef' a, b) pair entry to the table +addEntryIO ::  URefTableIO a b -- ^ key of the entry  +         -> URef a +         -> b             -- ^ value of the entry +         -> IO () +addEntryIO (URefTableIO t) (URef r _) b =+  do list <- readIORef r+     writeIORef r ((t, unsafeToUDyn b) : filter ((/= t) . fst) list)++--------------+-- URefTableST+--------------++-- | 'ST' version of 'URefTableIO'+newtype URefTableST s a b+  = URefTableST (URefTableIO a b)+ deriving Eq++-- | 'ST' version of 'newURefTableIO'+newURefTableST :: ST s (URefTableST s a b)+newURefTableST = unsafeIOToST (URefTableST `fmap` newURefTableIO)++-- | 'ST' version of 'queryIO'+queryST :: URefTableST s a b -> URef a -> ST s (Maybe b)+queryST (URefTableST tab) r = unsafeIOToST (queryIO tab r)++-- | 'ST' version of 'addEntryIO'+addEntryST :: URefTableST s a b -> URef a -> b -> ST s ()+addEntryST (URefTableST tab) r b = unsafeIOToST (addEntryIO tab r b)++--------------------------------+-- Memoization of URef functions+--------------------------------++-- | Generates a memoizated version of a function taking 'URef' values +memoURef :: (URef a -> b) -> (URef a -> b)+memoURef f = unsafePerformIO . memoURefIO (return . f)+{-# NOINLINE memoURef #-}++-- | 'IO' version of 'memoURef'+memoURefIO :: (URef a -> IO b) -> (URef a -> IO b)+memoURefIO f = unsafePerformIO $+  do tab <- newURefTableIO+     let f' r = do mb <- queryIO tab r+                   case mb of+                     Just b  -> do return b+                     Nothing -> fixIO $ \b ->+                                  do addEntryIO tab r b+                                     f r+     return f'+{-# NOINLINE memoURefIO #-}++-- | 'ST' version of 'memoURef'+memoURefST :: (URef a -> ST s b) -> (URef a -> ST s b)+memoURefST f = unsafePerformST $+  do tab <- newURefTableST+     let f' r = do mb <- queryST tab r+                   case mb of+                     Just b  -> do return b+                     Nothing -> fixST $ \b ->+                                  do addEntryST tab r b+                                     f r+     return f'+ where unsafePerformST = unsafePerformIO . unsafeSTToIO+{-# NOINLINE memoURefST #-}
+ src/ForSyDe/OSharing/UDynamic.hs view
@@ -0,0 +1,54 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.OSharing+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (GHC libraries)+--+-- This module provides support for unsafe dynamic typing.+--+--  Use with care. Normally, "Data.Dynamic" is preferred since it provides a+-- safe casting operation thanks to the use of "Data.Typeable". +--+-- /This module is based on Lava2000/: <http://www.cs.chalmers.se/~koen/Lava/>+-- +-----------------------------------------------------------------------------+module ForSyDe.OSharing.UDynamic + (UDynamic, +  unsafeToUDyn,+  unsafeFromUDyn)+  + where++import Unsafe.Coerce (unsafeCoerce)+import GHC.Base (Any)++-- | A value of type 'UDynamic' (from Unsafe Dynamic) can+--   implicitly any Haskell value. +--+--   It is unsafe because, as opposed to 'Data.Dynamic', +---  it does not encapsule type information and does+--   it makes unsafe to cast a 'UDynamic' back to its original Haskell type.+data UDynamic = UDynamic Any++-- | Converts an arbitrary value into an object of type 'UDynamic'.+--   It is unsafe because it does not provide type information during the +--   transformation+unsafeToUDyn :: a -> UDynamic+unsafeToUDyn a = UDynamic (unsafeCoerce a)++-- | Converts a 'UDynamic' object back into an ordinary Haskell value.+--   It is unsafe because there is no way to unsure converting+--   back to the correct original Haskell type. Thus, this+--   function should be used with care since it can cuase disastrous errors.+-- +--   e.g. disastrousCast :: a -> b+--        disastrousCast = unsafeToDyn . unsafeFromDyn+--+--        The following program would coredump+--          main = putStr (disastrousCast 1 :: String) +unsafeFromUDyn :: UDynamic -> a+unsafeFromUDyn (UDynamic obj) = unsafeCoerce obj
+ src/ForSyDe/Process.hs view
@@ -0,0 +1,24 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Process+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Publicly usable functions to create primitive processes. (Reexports +--  "ForSyDe.Process.SynchProc")+-- +-----------------------------------------------------------------------------+module ForSyDe.Process + (ProcFun, newProcFun, defArgVal, defArgPF,+  ProcType,+  module ForSyDe.Process.SynchProc) where++import ForSyDe.Process.ProcFun (ProcFun, newProcFun, defArgVal, defArgPF)++import ForSyDe.Process.SynchProc +import ForSyDe.Process.ProcType (ProcType)+import ForSyDe.Process.ProcType.Instances ()
+ src/ForSyDe/Process/ProcFun.hs view
@@ -0,0 +1,163 @@+{-# LANGUAGE TemplateHaskell #-} +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Process.ProcFun+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides a type ('ProcFun') to store the functions  passed+-- to process constructors.+--+----------------------------------------------------------------------------- +module ForSyDe.Process.ProcFun + (ProcFun(..),+  ProcFunAST(..),+  newProcFun, +  defArgVal,+  defArgPF,+  TypedProcFun(..),+  TypedProcFunAST(..),+  procFun2Dyn,+  contProcFun2Dyn,+) where++import ForSyDe.Process.ProcType+import ForSyDe.Process.ProcVal (ProcValAST, mkProcValAST)+import ForSyDe.ForSyDeErr++import Language.Haskell.TH+import Language.Haskell.TH.Syntax+import Language.Haskell.TH.LiftInstances ()+import Data.Dynamic+import Data.Maybe (fromJust)+import Data.Set (Set)+-----------+-- ProcFun+-----------++-- | A Process Function +data ProcFun a = +   ProcFun {val  :: a,          -- ^ Value of the function+            pfloc :: Loc, -- ^ where was it created+            ast  :: ProcFunAST} -- ^ AST of the function++++-- | A process Function AST+data ProcFunAST = +  ProcFunAST {name  :: Name,     -- ^ Function Name +                                    -- (FIXME: maybe just a String?) +              cls   :: [Clause], -- ^ Function clauses +              pars  :: [DefArg]} -- ^ Default parameters+++-- | A process Function default argument+--   Either a process function AST or a value AST+data DefArg = FunAST ProcFunAST | ValAST ProcValAST++++-- | Sets a default value for an argument of the process function+defArgVal :: (Lift a, ProcType a) => ProcFun (a -> b) -> a -> ProcFun b+-- FIXME: inneficient, use a queue data structure+defArgVal pf v = +   pf{ ast = astPF {pars = ((pars astPF) ++ [ValAST (mkProcValAST v)])}, +       val = (val pf) v}                    +  where astPF = ast pf++-- | Sets a default value for an argument of the process function +--   when the argument is a process function itself+defArgPF :: ProcFun (a -> b) -> ProcFun a -> ProcFun b+defArgPF pf v = pf{ ast = astPF {pars = ((pars astPF) ++ [FunAST (ast v)])}, +                    val = (val pf) (val v)}                    +  where astPF = ast pf +                   +-- | Template Haskell constructor for 'ProcFun', here is an example on how to use it+--+-- @+--  plus1Fun :: ProcFun (Int -> Int)+--  plus1Fun = $(newProcFun [d| plus1 :: Int -> Int+--                              plus1 n = n + 1     |])+-- @+newProcFun :: Q [Dec] -> ExpQ+newProcFun fDecQs = do +      fDecs <- fDecQs   +      -- Check for the declarations to be correct+      (name, cls) <- recover (currErr $ IncorrProcFunDecs fDecs) +                             (checkDecs fDecs)+      -- Generate the main expression+      errInfo <- qCurrentModule+      exp <-  [| let  fName    = name+                      fClauses = cls +                 in ProcFun $(varE name)+                            errInfo +                            (ProcFunAST fName fClauses []) |]+      -- Add the function declarations to the expression+      return $ LetE fDecs exp  + where currErr = qError "newProcFun"++----------------+-- TypedProcFun+----------------+++-- | A ProcFun bundled with its type representation. This type is not+--   exported to the end user. Only used internally.+data TypedProcFun a =    +   TypedProcFun {tval   :: a,          -- ^ Value of the function+                 tpfloc :: Loc,+                 tast   :: TypedProcFunAST} -- ^ AST of the function+++-- | A ProcFunAST bundled with its type representation:+--   Why a TypeRep and not the Type provided by Template Haskell?+--    We could use the type signature provided by TH but ...+--     1) We don't want to force the user to provide a signature+--     2) We don't want to handle polymorphic types. We just want the+--        monomorphic type used by the process using the procfun.+--   Why not just including the 'TypeRep' in ProcFunAST?+--     We need the context of the process to know what monomorphic types are +--     going to be used. Thus it is imposible to guess the TypeRep within+--     the code of newProcFun.+data TypedProcFunAST = +     TypedProcFunAST {tptyp   :: TypeRep,        -- function type+                      tpEnums :: Set EnumAlgTy,  -- enumerated types associated +                                                 -- with the function+                      tpast   :: ProcFunAST}++-- | transform a ProcFun into a Dynamic TypedProcFun+procFun2Dyn :: Typeable a => Set EnumAlgTy -> ProcFun a -> TypedProcFun Dynamic+procFun2Dyn s (ProcFun v l a) = +  TypedProcFun (toDyn v) l (TypedProcFunAST (typeOf v) s a)++-- FIXME: probably not needed+-- | tranform the arguments and return value of+--   a ProcFun to dynamic+contProcFun2Dyn :: (Typeable1 container,+                    Typeable b,+                    Functor container, +                    Typeable a) =>+                   Set EnumAlgTy ->+                   ProcFun (container a -> b) -> +                   TypedProcFun (container Dynamic -> Dynamic)+contProcFun2Dyn s (ProcFun v l a) = +     TypedProcFun (fmapDyn v) l (TypedProcFunAST (typeOf v) s a)+       where  fmapDyn f cont = toDyn (f (fmap (fromJust.fromDynamic) cont)) +++----------------------------+-- Internal Helper Functions+----------------------------++-- | Check the decarations passed to newProcFun to be correct+checkDecs :: [Dec] -> Q (Name, [Clause])+checkDecs [FunD name2 cls] = return (name2, cls) +-- in case a signature is provided+checkDecs [SigD name1 _, FunD name2 cls] | name1 == name2 = +  return (name1, cls) +checkDecs _                  = qGiveUp name+  where name = "ForSyDe.Process.ProcFun.checkDecs"
+ src/ForSyDe/Process/ProcType.hs view
@@ -0,0 +1,196 @@+{-# LANGUAGE TemplateHaskell #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Process.ProcType+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (non-standard instances)+--+-- This module includes and exports, the internal definition, instantiations+-- and related types of 'ProcType', a class used to constrain the arguments+-- taken by process constructors.+----------------------------------------------------------------------------- +module ForSyDe.Process.ProcType (+ EnumAlgTy(..), + ProcType(..), + genTupInstances) where++import Control.Monad (replicateM)+import Data.List (intersperse)+import Data.Generics+import Data.Set (Set, union)+import Language.Haskell.TH+import Language.Haskell.TH.Syntax (Lift(..))+import Text.ParserCombinators.ReadP++-- | Data type describing an algebraic enumerated type (i.e. an algrebraic +--   type whose data constructors have arity zero)+data EnumAlgTy = EnumAlgTy String [String] + deriving Show++instance Eq EnumAlgTy where+ (EnumAlgTy d1 _) == (EnumAlgTy d2 _) = d1 == d2++instance Ord EnumAlgTy where+ (EnumAlgTy d1 _) `compare` (EnumAlgTy d2 _) = d1 `compare` d2++-- | Class used to constrain the arguments (values and 'ProcFun's) taken by+--   process constructors+class (Data a, Lift a) => ProcType a where+ -- | Get the associated enumerated type-definitions of certain value, + --   taking nesting in account.  + -- + --   For example:  + --+ -- + -- >  module MyMod where+ -- >+ -- >  data Colour = Blue | Red+ -- >   deriving (Data, Typeable)+ -- >  data Shapes = Circle | Square+ -- >   deriving (Data, Typeable)+ -- >+ -- >  getEnums (Prst Blue, Circle) =                 + -- >   fromList [EnumAlgTy "MyMod.Colour" ["Blue", "Red"],+ -- >             EnumAlgTy "MyMod.Shapes" ["Circle", "Square"]]+ getEnums :: a -> Set EnumAlgTy+ -- | Read a process type+ readProcType :: ReadP a++-- Function to automatically generate ProcType, Data, Lift and+-- Typeable instances for tuples (with 2 or more elements) with+-- Template Haskell. For example, in the case of 2 elements, the code+-- generated would be:+--+-- @+-- instance (ProcType o1, ProcType o2) => ProcType (o1, o2) where+--  getEnums _ = getEnums (undefined :: a) `union` getEnums (undefined :: b) +--  readProcType = do+--            skipSpaces >> char '('+--            o1 <- readProcType+--            skipSpaces >> char ','+--            o2 <- readProcType+--            skipSpaces >> char ')'+--            return (o1,o2)+--+-- The next two are only necessary for tuples with more than 7 elements+--+-- instance (Typeable o1, Typeable o2) => Typeable (o1, o2) where+--  typeOf _ = mkTyCon "," `mkTyConApp` +--               [typeOf (undefined :: o1), typeOf (undefined :: o2)]+--+-- instance (Data o1, Data o2) => Data (o1, o2) where+--  gfoldl k z (o1, o2) = z (,) `k` o1 `k` o2+--  gunfold k z _ = k (k (z (,) ))+--  toConstr a = mkConstr (dataTypeOf a) "(,)" [] Prefix+--  dataTypeOf a = mkDataType "Data.Tuple.(,)" [toConstr a]+--+-- FIXME: This won't be necessary once the Data a => Lift a instance is created+--+-- instance (Lift o1, Lift o2) => Lift (o1, o2) where+--  lift (o1, o2) = tupE [lift o1, lift o2]+-- @+genTupInstances :: Int -- ^ number of outputs to generate+             -> Q [Dec]+genTupInstances n = do+  -- Generate N o names+  outNames <- replicateM n (newName "o")+  let tupType = foldl accumApp (tupleT n) outNames+      accumApp accumT vName = accumT `appT` varT vName +  if n <= 7 +     then sequence [genProcTypeIns outNames tupType]+     else sequence [genTypeableIns outNames tupType,+                    genDataIns outNames tupType]+                    -- genLiftIns outNames tupType,+                    --genProcTypeIns outNames tupType]++ where +  undef t = sigE [| undefined |] (varT t)+  genProcTypeIns :: [Name] -> Q Type -> Q Dec+  genProcTypeIns names tupType = do+    let getEnumsExpr =  +            foldr1 (\e1 e2 -> infixE (Just e1) +                                     (varE 'union)+                                     (Just e2) )+                   (map (\n -> varE  'getEnums `appE` undef n) names)     +        getEnumsD = funD 'getEnums [clause [wildP]  (normalB getEnumsExpr) []] +        readProcTypeExpr = doE $ +            noBindS [| skipSpaces >> char '(' |] : +            (intersperse (noBindS [| skipSpaces >> char ',' |]) +                        (map (\n -> bindS (varP n) [| readProcType |]) names) +++             [noBindS [| skipSpaces >> char ')' |],+              noBindS [| return $(tupE $ map varE names) |] ] )+        readProcTypeD = funD 'readProcType +                             [clause []  (normalB readProcTypeExpr) []]+        procTypeCxt = map (\vName -> conT ''ProcType `appT` varT vName) names +++                      map (\vName -> conT ''Data `appT` varT vName) names +++                      map (\vName -> conT ''Lift `appT` varT vName) names+    instanceD (cxt procTypeCxt) +                     (conT ''ProcType `appT` tupType) +                     [getEnumsD, readProcTypeD]+  genDataIns :: [Name] -> Q Type -> Q Dec+  genDataIns names tupType = do+   k <- newName "k"+   c <- newName "c"+   z <- newName "z"+   a <- newName "a"+   let tupCons = conE tupName+       tupName = tupleDataName n+       gfoldlExpr = foldl (\acum n -> infixE (Just acum)+                                             (varE k)+                                             (Just $ varE n))+                           (varE z`appE` tupCons) +                           names                    +       gfoldlD = funD 'gfoldl +                       [clause [varP k, varP z, tupP (map varP names)] +                               (normalB gfoldlExpr) []] +       gunfoldExpr = let nKs 0 = (varE z `appE` tupCons)+                         nKs n = varE k `appE` (nKs (n-1))+                     in nKs n+       gunfoldD = funD 'gunfold +                      [clause [varP k, varP z, wildP] (normalB gunfoldExpr) []] +       toConstrExpr = [| mkConstr (dataTypeOf $(varE a))+                                  $(litE $ stringL (nameBase tupName))+                                  [] +                                  Prefix  |]+       toConstrD = funD 'toConstr+                        [clause [varP a] (normalB toConstrExpr) []]+       dataTypeOfExpr = [| mkDataType $(litE $ stringL (show tupName)) +                                      [toConstr $(varE a)] |] +       dataTypeOfD = funD 'dataTypeOf+                          [clause [varP a] (normalB dataTypeOfExpr) []]+       dataCxt = map (\vName -> conT ''Data `appT` varT vName) names +   instanceD (cxt dataCxt) +             (conT ''Data `appT` tupType) +             [gfoldlD, gunfoldD, toConstrD, dataTypeOfD]+  genTypeableIns :: [Name] -> Q Type -> Q Dec+  genTypeableIns names tupType = do+   -- generate n-1 commas to be consistent with the (faulty) instances+   -- of tuples from 2 to 7 elements+   let strRep = replicate (n-1) ','+       typeOfExpr = [| mkTyCon +                        $(litE $ stringL strRep)+                        `mkTyConApp`+                        $(listE $ map (\n -> varE 'typeOf `appE` undef n) names)+                     |]+       typeOfD = funD 'typeOf+                      [clause [wildP] (normalB typeOfExpr) []]+       typeableCxt = map (\vName -> conT ''Typeable `appT` varT vName) names+   instanceD (cxt typeableCxt) +             (conT ''Typeable `appT` tupType) +             [typeOfD]+  genLiftIns :: [Name] -> Q Type -> Q Dec+  genLiftIns names tupType = do+   let liftExpr = +           varE 'tupE `appE` listE (map (\n -> varE 'lift `appE` varE n) names)+       liftD = funD 'lift +                 [clause [tupP (map varP names)] (normalB liftExpr) []]+       liftCxt = map (\vName -> conT ''Lift `appT` varT vName) names+   instanceD (cxt liftCxt) +             (conT ''Lift `appT` tupType) +             [liftD]++
+ src/ForSyDe/Process/ProcType/Instances.hs view
@@ -0,0 +1,116 @@+{-# LANGUAGE ScopedTypeVariables, FlexibleInstances,+             UndecidableInstances, OverlappingInstances, TemplateHaskell #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System.SysFun.Instances+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides the 'ProcType' instances (and 'Data',+-- 'Typeable' and 'Lift' when necessary) . It cannot be included in+-- "ForSyDe.Process.ProcType" directly due to a Template Haskell bug+-- which prevents Template Haskell from executing functions defined in+-- the same module: <http://hackage.haskell.org/trac/ghc/ticket/1800>+--+----------------------------------------------------------------------------- +module ForSyDe.Process.ProcType.Instances where++import ForSyDe.Config (maxTupleSize)+import ForSyDe.Process.ProcType+import ForSyDe.AbsentExt++import Data.TypeLevel.Num.Sets (Nat, toInt)+import Data.Param.FSVec (FSVec, reallyUnsafeVector)+++import Data.Generics+import Control.Monad (liftM, liftM2, mzero)+import Text.ParserCombinators.ReadP+import Data.Set (empty, singleton)+import Language.Haskell.TH.Syntax (Lift(..), runIO)++-------------------------------------------------------------+-- Checking if a member of Data belongs to an enumerated type+-------------------------------------------------------------++-- | Phony type used to check if a data constructor is enumerate (has )+newtype IsConsEnum a = IsConsEnum {unIsConsEnum :: Bool}++-- | Tell if a member of "Data" belongs to an enumerated type+isConsEnum :: Data a => Constr -> IsConsEnum a+isConsEnum = gunfold  (\_ -> IsConsEnum False) (\_ -> IsConsEnum True) ++-- | Tell if a member of "Data" belongs to an enumerated type+--   and return its description.+getEnumAlgTy :: forall a . Data a => a -> Maybe EnumAlgTy+getEnumAlgTy a = case dataTypeRep dt of+  AlgRep cons -> do +   strs <- mapM (\c -> toMaybe (unIsConsEnum (isConsEnum c :: IsConsEnum a)) +                               (showConstr c)) cons +   return (EnumAlgTy dn strs)+  _ -> Nothing+ where dt = dataTypeOf a+       dn = dataTypeName dt+       toMaybe bool c = if bool then Just c else Nothing++-------------+-- Instances+-------------++instance (Lift a, Data a) => ProcType a where+ getEnums _ = maybe empty singleton (getEnumAlgTy (undefined :: a))+ -- We add parenthesis and try to use gread. + -- In addition, since gread is broken for unit (), we create or own parser+ readProcType = do skipSpaces+                   -- get all the input while no separator is found+                   str <- munch1 (\c -> not (elem c " ,()<>" )) +                   gReadUnaryCons str+  where -- Generically read a unary constructor (possibly an integer, float etc .. )+        gReadUnaryCons :: forall a . Data a => String -> ReadP a+        gReadUnaryCons str = do +              cons <- maybe mzero return $ readConstr (dataTypeOf (undefined :: a)) str+              fromConstrM (fail "readProcType: non-unary constructor found") cons++++instance (Typeable s, Nat s, ProcType a) => ProcType (FSVec s a) where+ getEnums _ = getEnums (undefined :: a)+ readProcType = do+          skipSpaces  +          char '<'+          elems <- countSepBy (toInt (undefined :: s))+                              readProcType +                              (skipSpaces >> char ',' >> skipSpaces)+          char '>'+          return (reallyUnsafeVector elems)+   where countSepBy n p sep = +            if n == 0 +               then return []+               else liftM2 (:) p (sequence (replicate (n-1) (sep >> p))) +  ++instance ProcType a =>  ProcType (AbstExt a) where+ getEnums _ = getEnums (undefined :: a)+ readProcType = skipSpaces >> (absP <++ prstP)+   where absP = do string "Abst" +                   return Abst+         prstP = do string "Prst"+                    skipSpaces+                    v <- readProcType+                    return $ Prst v++-- Tuple instances+$(let concatMapM f xs = liftM concat (mapM f xs) +      msg = "Generating and compiling " ++ show (maxTupleSize -2) ++ +            " tuple instances of " +++            show ''ProcType ++  +            ", this might take some time ... \n"+  in runIO (putStrLn $ msg) >>+     concatMapM genTupInstances [2..maxTupleSize])+++
+ src/ForSyDe/Process/ProcVal.hs view
@@ -0,0 +1,48 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Process.ProcVal+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides a type ('ProcVal') to store the value arguments passed+-- to process constructors.+--+----------------------------------------------------------------------------- +module ForSyDe.Process.ProcVal where+++import ForSyDe.Process.ProcType++import Data.Typeable (Typeable(..), TypeRep)+import Data.Dynamic (toDyn, Dynamic)+import Data.Set+import Language.Haskell.TH (Exp, runQ)+import Language.Haskell.TH.Syntax (Lift(..))+import System.IO.Unsafe (unsafePerformIO)+++data ProcVal = ProcVal +                  {dyn     :: Dynamic,    --  Dynamic value +                   valAST  :: ProcValAST} --  its AST++data ProcValAST = ProcValAST+                    {expVal   :: Exp,           -- Its AST representation+                     expTyp   :: TypeRep,       -- Type of the expression +                     expEnums :: Set EnumAlgTy} -- Enumerated types associated+                                                -- with the expression++-- | 'ProcVal' constructor+mkProcVal :: (Lift a, ProcType a) => a -> ProcVal+-- FIXME: would unsafePerformIO cause any harm to get the exp out of the+--        Q monad in this context?+mkProcVal val = ProcVal (toDyn val) (mkProcValAST val) ++mkProcValAST :: (Lift a, ProcType a) => a -> ProcValAST +-- FIMXE: the unsafePerformIO won't be needed once the Data a => Lift a+--        instance is created+mkProcValAST val = ProcValAST (unsafePerformIO.runQ.lift $ val) (typeOf val) +                              (getEnums val)
+ src/ForSyDe/Process/SynchProc.hs view
@@ -0,0 +1,875 @@+{-# LANGUAGE TemplateHaskell, ScopedTypeVariables, RelaxedPolyRec,+             PatternGuards #-}+-- The PatternGuards are used to hush innapropiate compiler warnings+-- see http://hackage.haskell.org/trac/ghc/ticket/2017+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Process.SynchProc+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides the synchronous process constructors of+-- ForSyDe and some useful synchronous processes.+--+----------------------------------------------------------------------------- +module ForSyDe.Process.SynchProc (+ -- * Combinational process constructors+ -- | Combinational process constructors are used for processes that do not + --   have a state.+ constSY, mapSY, zipWithSY, zipWith3SY, + zipWith4SY, zipWith5SY, zipWith6SY, zipWithxSY, + -- * Sequential process constructors+ -- | Sequential process constructors are used for processes that have a state.+ --   One of the input parameters is the initial state.+ delaySY, delaynSY,+ scanlSY, scanl2SY, scanl3SY, scanldSY, scanld2SY,+ scanld3SY, mooreSY, moore2SY, moore3SY, mealySY,+ mealy2SY, mealy3SY, sourceSY, + filterSY, fillSY, holdSY,+ -- * Synchronous Processes+ -- | The library contains a few simple processes that are applicable to many + -- cases.+ whenSY, zipSY, zip3SY, zip4SY, zip5SY, zip6SY, + unzipSY, unzip3SY, unzip4SY, unzip5SY, unzip6SY,+ zipxSY, unzipxSY, mapxSY, + fstSY, sndSY, groupSY) where+++import ForSyDe.Ids+import ForSyDe.System+import ForSyDe.Process.ProcType+import ForSyDe.Process.ProcType.Instances()+import ForSyDe.Process.ProcFun+import ForSyDe.Process.ProcVal+import ForSyDe.OSharing+import ForSyDe.Netlist+import ForSyDe.AbsentExt++import qualified Data.Param.FSVec as V+import Data.Param.FSVec hiding ((++), map)+import Data.TypeLevel (Nat, toInt)++import Data.Set (union)+import Data.Maybe+import Data.Dynamic+import Data.Typeable++-----------------------------------+-- Synchronous Process Constructors+-----------------------------------++----------------------------------------                                      +--                                    --                                      +-- COMBINATIONAL PROCESS CONSTRUCTORS --                                      +--                                    --                                      +----------------------------------------+++-- | Creates a constant process. A process which outputs the +--   same signal value in every clock cycle.+constSY :: ProcType a => +            ProcId   -- ^ Identifier of the process+         -> a        -- ^ Value to output+         -> Signal a -- ^ Resulting output signal+constSY id v = Signal (newNodeOutSig nodeRef ConstOut) +  where nodeRef = newURef $ Proc id $ Const (mkProcVal v)+++++-- | The process constructor 'mapSY' takes an identifier and a +--   combinational function as arguments and returns a process with one +--   input signal and one output signal.         +mapSY :: forall a b . (ProcType a, ProcType b) =>+         ProcId           -- ^ Identifier of the process +      -> ProcFun (a -> b) -- ^ Function applied to the input signal +                          --   in every cycle+      -> Signal a         -- ^ Input 'Signal' +      -> Signal b         -- ^ Output 'Signal'+mapSY id  f s = Signal (newNodeOutSig nodeRef ZipWithNSYOut) +  where nodeRef = newURef $ Proc id $ ZipWithNSY dynPF [unSignal s]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b)) +                            f ++-- | The process constructor 'zipWithSY' takes an identifier and a +--  combinational function as arguments and returns a process with +--  two input signals and one output signal.+zipWithSY :: forall a b c . (ProcType a, ProcType b, ProcType c) => +             ProcId                -- ^ Identifier of the process+          -> ProcFun (a -> b -> c) -- ^ Function applied to the input signals +                                   --   in every cycle+          -> Signal a              -- ^ First input 'Signal'+          -> Signal b              -- ^ Second input 'Signal'+          -> Signal c              -- ^ Output Signal +zipWithSY id f s1 s2 = Signal (newNodeOutSig nodeRef ZipWithNSYOut)+  where nodeRef = newURef $ Proc id $ +                     ZipWithNSY dynPF [unSignal s1,unSignal s2]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b) `union`+                             getEnums (undefined ::c) ) +                            f         ++-- | The process constructor 'zipWith3SY' takes an identifier and a +--   combinational function as arguments and returns a process with +--   three input signals and one output signal. +zipWith3SY :: forall a b c d.+              (ProcType a, ProcType b, ProcType c, ProcType d) => +              ProcId                -- ^ Identifier of the process+           -> ProcFun (a -> b -> c -> d) -- ^ Function applied to the input +                                         -- signals in every cycle+           -> Signal a              -- ^ First input 'Signal'+           -> Signal b              -- ^ Second input 'Signal'+           -> Signal c              -- ^ Third input 'Signal'+           -> Signal d              -- ^ Output Signal +zipWith3SY id f s1 s2 s3 = Signal (newNodeOutSig nodeRef ZipWithNSYOut)+  where nodeRef = newURef $ Proc id $ +                    ZipWithNSY dynPF +                                   [unSignal s1, +                                    unSignal s2, +                                    unSignal s3]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b) `union`+                             getEnums (undefined ::c) `union`+                             getEnums (undefined ::d)) +                            f +++-- | The process constructor 'zipWith4SY' takes an identifier and a +--   combinational function as arguments and returns a process with +--   four input signals and one output signal. +zipWith4SY ::forall a b c d e. +             (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e) => +              ProcId                -- ^ Identifier of the process+           -> ProcFun (a -> b -> c -> d -> e) -- ^ Function applied to the  +                                              --   input signals in every cycle+           -> Signal a              -- ^ First input 'Signal'+           -> Signal b              -- ^ Second input 'Signal'+           -> Signal c              -- ^ Third input 'Signal'+           -> Signal d              -- ^ Fourth input 'Signal'+           -> Signal e              -- ^ Output Signal +zipWith4SY id f s1 s2 s3 s4 = Signal (newNodeOutSig nodeRef ZipWithNSYOut)+  where nodeRef = newURef $ Proc id $ +                    ZipWithNSY dynPF +                                   [unSignal s1, +                                    unSignal s2, +                                    unSignal s3,+                                    unSignal s4]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b) `union`+                             getEnums (undefined ::c) `union`+                             getEnums (undefined ::d) `union`+                             getEnums (undefined ::e) ) +                            f +-- | The process constructor 'zipWith5SY' takes an identifier and a +--   combinational function as arguments and returns a process with +--   five input signals and one output signal. +zipWith5SY :: forall a b c d e f.+              (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e,+               ProcType f) => +              ProcId                -- ^ Identifier of the process+           -> ProcFun (a -> b -> c -> d -> e -> f) +                                              -- ^ Function applied to the  +                                              --   input signals in every cycle+           -> Signal a              -- ^ First input 'Signal'+           -> Signal b              -- ^ Second input 'Signal'+           -> Signal c              -- ^ Third input 'Signal'+           -> Signal d              -- ^ Fourth input 'Signal'+           -> Signal e              -- ^ Fifth input 'Signal'+           -> Signal f              -- ^ Output Signal +zipWith5SY id f s1 s2 s3 s4 s5 = Signal (newNodeOutSig nodeRef ZipWithNSYOut)+  where nodeRef = newURef $ Proc id $ +                    ZipWithNSY dynPF +                                   [unSignal s1, +                                    unSignal s2, +                                    unSignal s3,+                                    unSignal s4,+                                    unSignal s5]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b) `union`+                             getEnums (undefined ::c) `union`+                             getEnums (undefined ::d) `union`+                             getEnums (undefined ::e) `union`+                             getEnums (undefined ::f)  ) +                            f +++-- | The process constructor 'zipWith6SY' takes an identifier and a +--   combinational function as arguments and returns a process with +--   five input signals and one output signal. +zipWith6SY :: forall a b c d e f g.+              (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e,+               ProcType f, ProcType g) => +              ProcId                -- ^ Identifier of the process+           -> ProcFun (a -> b -> c -> d -> e -> f -> g) +                                              -- ^ Function applied to the  +                                              --   input signals in every cycle+           -> Signal a              -- ^ First input 'Signal'+           -> Signal b              -- ^ Second input 'Signal'+           -> Signal c              -- ^ Third input 'Signal'+           -> Signal d              -- ^ Fourth input 'Signal'+           -> Signal e              -- ^ Fifth input 'Signal'+           -> Signal f              -- ^ Sixth input 'Signal'+           -> Signal g              -- ^ Output Signal +zipWith6SY id f s1 s2 s3 s4 s5 s6 = Signal (newNodeOutSig nodeRef ZipWithNSYOut)+  where nodeRef = newURef $ Proc id $ +                    ZipWithNSY dynPF +                                   [unSignal s1, +                                    unSignal s2, +                                    unSignal s3,+                                    unSignal s4,+                                    unSignal s5,+                                    unSignal s6]+        dynPF = procFun2Dyn (getEnums (undefined ::a) `union`+                             getEnums (undefined ::b) `union`+                             getEnums (undefined ::c) `union`+                             getEnums (undefined ::d) `union`+                             getEnums (undefined ::e) `union`+                             getEnums (undefined ::f) `union`+                             getEnums (undefined ::g) ) +                            f ++-- | The process constructor 'mapxSY' creates a process network that maps a +-- function onto all signals in a vector of signals. The identifier is used +-- as the identifier prefix of the processes created (a number starting with 1+-- will be appended to each identifier)+mapxSY  :: (Nat s, ProcType a, ProcType b) => +           ProcId+        -> ProcFun (a -> b) +        -> FSVec s (Signal a) +        -> FSVec s (Signal b)+mapxSY id f = V.zipWith (\n s -> mapSY (id ++ show n) f s) +                        (V.reallyUnsafeVector [(1::Int)..]) ++-- | The process constructor 'zipWithxSY' works as 'zipWithSY', but takes a +--   vector of signals as input.                                             +zipWithxSY      :: forall s a b . +                   (Nat s, Typeable s, ProcType a, ProcType b) => +                   ProcId+                -> ProcFun (FSVec s a -> b) +                -> FSVec s (Signal a) +                -> Signal b+zipWithxSY id f sv = Signal (newNodeOutSig nodeRef ZipWithxSYOut)+  where nodeRef = newURef $ Proc id $ +                    ZipWithxSY (vecProcFun2List dynPF) +                               (map unSignal (V.fromVector sv)) +        -- Transform the vector argument of a procfun into a list+        vecProcFun2List :: TypedProcFun (FSVec s' a' -> b') -> +                           TypedProcFun ([a'] -> b')+        vecProcFun2List f = f{tval = \x -> (tval f) (reallyUnsafeVector x)}+        dynPF = contProcFun2Dyn (getEnums (undefined ::a) `union`+                                 getEnums (undefined ::b) )+                                f+                                   ++-------------------------------------+--                                 --+-- SEQUENTIAL PROCESS CONSTRUCTORS --+--                                 --+-------------------------------------                                   ++-- | The process constructor 'delaySY' delays the signal one event cycle      +--   by introducing an initial value at the beginning of the output signal.   +--   Note, that this implies that there is one event (the first) at the       +--   output signal that has no corresponding event at the input signal.       +--   One could argue that input and output signals are not fully synchronized,+--   even though all input events are synchronous with a corresponding output +--   event. However, this is necessary to initialize feed-back loops.+delaySY :: ProcType a => +           ProcId      -- ^ Identifier of the process+        -> a           -- ^ Initial value+        -> Signal a    -- ^ 'Signal' to be delayed         +        -> Signal a    -- ^ Resulting delayed 'Signal'+delaySY id v s = Signal (newNodeOutSig nodeRef DelaySYOut)+  where procVal = mkProcVal v+        nodeRef = newURef $ Proc id $ DelaySY procVal (unSignal s)+++-- | The process constructor 'delaynSY' delays the signal n events by +--   introducing n identical default values. It creates a chain of 'delaySY'+--   processes.+delaynSY :: ProcType a =>+            ProcId    -- ^ Identifier+         -> a         -- ^Initial state+	 -> Int       -- ^ Number of Delay cycles +	 -> Signal a  -- ^Input signal+	 -> Signal a  -- ^Output signal+delaynSY id e n = instantiate id delaynSys+ where delaynSys = newSysDef delaynSysF ("delay"++show n++"SY_"++id) +                                        ["in1"] ["out1"]+       delaynSysF s =  (\(a,_,_) -> a) $ delaynSYacum (s, 1, n)+       delaynSYacum acum@(lastSig, curr, max)+        | curr > max = acum+        | otherwise  = +           delaynSYacum (delaySY ("delay" ++ show curr) e lastSig, curr+1, max)+         +++-- | The process constructor 'scanlSY' is used to construct a finite state +--   machine process without output decoder. It takes an initial value and +--   a function for the next state decoder. The process constructor behaves +--   similar to the Haskell prelude function 'scanlSY' and has the value of +--   the new state as its output value as illustrated by the +--   following example.  +-- +--   This is in contrast to the function 'scanldSY', which has its current +--   state as its output value. +scanlSY	:: (ProcType a, ProcType b) =>+           ProcId -- ^Process Identifier+        -> ProcFun (a -> b -> a) -- ^Combinational function for next +                                 -- state decoder+        -> a -- ^Initial state+	-> Signal b -- ^ Input signal +	-> Signal a -- ^ Output signal+scanlSY id f mem = instantiate id scanlSys+    where scanlSys = newSysDef scanlSysF ("scanlSY_"++id) ["in1"] ["out1"]+          scanlSysF s = s'+            where s' = zipWithSY "zipWith" f (delaySY "delay" mem s') s +++-- | The process constructor 'scanl2SY' behaves like 'scanlSY', but has two +--   input signals.+scanl2SY :: (ProcType a, ProcType b, ProcType c) =>+           ProcId -- ^Process Identifier+        -> ProcFun (a -> b -> c -> a) -- ^Combinational function for next +                                      -- state decoder+        -> a -- ^Initial state+	-> Signal b -- ^ First Input signal +        -> Signal c -- ^ Second Input signal+	-> Signal a -- ^ Output signal+scanl2SY id f mem = instantiate id scanl2Sys+    where scanl2Sys = newSysDef scanl2SysF ("scanl2SY_"++id) +                                           ["in1", "in2"] ["out1"]+          scanl2SysF s1 s2 = s'+           where s' = zipWith3SY "zipWith" f (delaySY "delay" mem s') s1 s2 ++++-- | The process constructor 'scanl2SY' behaves like 'scanlSY', but has two +--   input signals.+scanl3SY :: (ProcType a, ProcType b, ProcType c, ProcType d) =>+           ProcId -- ^Process Identifier+        -> ProcFun (a -> b -> c -> d -> a) -- ^Combinational function for next +                                           -- state decoder+        -> a -- ^Initial state+	-> Signal b -- ^ First Input signal +        -> Signal c -- ^ Second Input signal+        -> Signal d -- ^ Third Input signal+	-> Signal a -- ^ Output signal+scanl3SY id f mem = instantiate id scanl3Sys+    where scanl3Sys = newSysDef scanl3SysF ("scanl3SY_"++id) +                                           ["in1", "in2", "in3"] ["out1"]+          scanl3SysF s1 s2 s3 = s'+            where s' = zipWith4SY "zipWith" f (delaySY "delay" mem s') s1 s2 s3++++-- | The process constructor 'scanldSY' is used to construct a finite state+--  machine process without output decoder. It takes an initial value and a+--  function for the next state decoder. The process constructor behaves+--  similarly to the Haskell prelude function 'scanlSY'. In contrast to the+--  process constructor 'scanlSY' here the output value is the current state+--  and not the one of the next state.+scanldSY :: (ProcType a, ProcType b) => +           ProcId+        -> ProcFun (a -> b -> a) -- ^Combinational function +                                 -- for next state decoder+        -> a -- ^Initial state+        -> Signal b -- ^ Input signal +        -> Signal a -- ^ Output signal+scanldSY id f mem = instantiate id scanldSys+    where scanldSys = newSysDef scanldSysF ("scanlSY_"++id) ["in1"] ["out1"]+          scanldSysF s = s'+            where s' = delaySY "delay" mem $ zipWithSY "zipWith" f s' s +++-- | The process constructor 'scanld2SY' behaves like 'scanldSY', but has +--   two input signals.+scanld2SY :: (ProcType a, ProcType b, ProcType c) => +            ProcId+         -> ProcFun (a -> b -> c -> a) -- ^Combinational function +                                       -- for next state decoder+         -> a -- ^Initial state+         -> Signal b -- ^ First Input signal+         -> Signal c -- ^ Second Input signal+         -> Signal a -- ^ Output signal+scanld2SY id f mem = instantiate id scanld2Sys+    where scanld2Sys = newSysDef scanld2SysF ("scanld2SY_"++id) +                                             ["in1", "in2"] ["out1"]+          scanld2SysF s1 s2 = s'+            where s' = delaySY "delay" mem $ zipWith3SY "zipWith" f s' s1 s2 ++++-- | The process constructor 'scanld2SY' behaves like 'scanldSY', but has +--   two input signals.+scanld3SY :: (ProcType a, ProcType b, ProcType c, ProcType d) => +            ProcId+         -> ProcFun (a -> b -> c -> d -> a) -- ^Combinational function +                                       -- for next state decoder+         -> a -- ^Initial state+         -> Signal b -- ^ First Input signal+         -> Signal c -- ^ Second Input signal+         -> Signal d -- ^ Second Input signal+         -> Signal a -- ^ Output signal+scanld3SY id f mem = instantiate id scanld3Sys+    where scanld3Sys = newSysDef scanld3SysF ("scanld3SY_"++id) +                                            ["in1", "in2", "in3"] ["out1"]+          scanld3SysF s1 s2 s3 = s' +            where s' = delaySY "delay" mem $ zipWith4SY "zipWith" f s' s1 s2 s3 ++++-- | The process constructor 'mooreSY' is used to model state machines+-- of \"Moore\" type, where the output only depends on the current+-- state. The process constructor is based on the process constructor+-- 'scanldSY', since it is natural for state machines in hardware, that+-- the output operates on the current state and not on the next+-- state. The process constructors takes a function to calculate the+-- next state, another function to calculate the output and a value for+-- the initial state.+--+-- In contrast the output of a process created by the process constructor+-- 'mealySY' depends not only on the state, but also on the input values.+mooreSY :: (ProcType a, ProcType b, ProcType c) =>+           ProcId+        -> ProcFun (a -> b -> a) -- ^ Combinational function for+                                 --   next state decoder+        -> ProcFun (a -> c) -- ^Combinational function for output decoder+        -> a -- ^Initial state+        -> Signal b -- ^Input signal+        -> Signal c -- ^Output signal+mooreSY id nextState output initial = instantiate id mooreSys+ where mooreSys = newSysDef mooreSysF ("mooreSY_"++id)+                                      ["in1"] ["out1"] +       mooreSysF = mapSY "map" output . scanldSY "mooreScan" nextState initial+++-- | The process constructor 'moore2SY' behaves like 'mooreSY', but has two +--   input signals.+moore2SY :: (ProcType a, ProcType b, ProcType c, ProcType d) =>+            ProcId+         -> ProcFun (a -> b -> c -> a) -- ^ Combinational function for+                                       --   next state decoder+         -> ProcFun (a -> d) -- ^Combinational function for output decoder+         -> a -- ^Initial state+         -> Signal b -- ^First Input signal+         -> Signal c -- ^Second Input signal+         -> Signal d -- ^Output signal+moore2SY id nextState output initial = instantiate id moore2Sys+ where moore2Sys = newSysDef moore2SysF ("moore2SY_"++id)+                                        ["in1", "in2"] ["out1"] +       moore2SysF i1 i2 = +         mapSY "map" output $ scanld2SY "mooreScan" nextState initial i1 i2+++++-- | The process constructor 'moore2SY' behaves like 'mooreSY', but has two +--   input signals.+moore3SY :: (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e) =>+            ProcId+         -> ProcFun (a -> b -> c -> d -> a) -- ^ Combinational function for+                                            --   next state decoder+         -> ProcFun (a -> e) -- ^Combinational function for output decoder+         -> a -- ^Initial state+         -> Signal b -- ^First Input signal+         -> Signal c -- ^Second Input signal+         -> Signal d -- ^Third Input signal+         -> Signal e -- ^Output signal+moore3SY id nextState output initial = instantiate id moore3Sys+ where moore3Sys = newSysDef moore3SysF ("moore3SY_"++id)+                                        ["in1", "in2", "in3"] ["out1"] +       moore3SysF i1 i2 i3 = +         mapSY "map" output $ scanld3SY "mooreScan" nextState initial i1 i2 i3+++-- | The process constructor 'melaySY' is used to model state machines of+-- \"Mealy\" type, where the output only depends on the current state and+-- the input values. The process constructor is based on the process+-- constructor 'scanldSY', since it is natural for state machines in+-- hardware, that the output operates on the current state and not on the+-- next state. The process constructors takes a function to calculate the+-- next state, another function to calculate the output and a value for the+-- initial state.+--+-- In contrast the output of a process created by the process constructor +-- 'mooreSY' depends only on the state, but not on the input values.+mealySY :: (ProcType a, ProcType b, ProcType c) => +           ProcId+        -> ProcFun (a -> b -> a) -- ^Combinational function for next +                                 -- state decoder  +        -> ProcFun (a -> b -> c) -- ^Combinational function for output decoder+        -> a -- ^Initial state+        -> Signal b -- ^Input signal +        -> Signal c -- ^Output signal+mealySY id nextState output initial = instantiate id mealySys+  where mealySys = newSysDef mealySysF ("mealySY_"++id) ["in1"] ["out1"]+        mealySysF i = zipWithSY "zipWith" output state i+           where state = scanldSY "scanld" nextState initial i++-- | The process constructor 'mealy2SY' behaves like 'mealySY', but has +--   two input signals.+mealy2SY :: (ProcType a, ProcType b, ProcType c, ProcType d) => +           ProcId+        -> ProcFun (a -> b -> c -> a) -- ^Combinational function for next +                                      -- state decoder  +        -> ProcFun (a -> b -> c -> d) -- ^Combinational function for output +                                      -- decoder+        -> a -- ^Initial state+        -> Signal b -- ^First Input signal+        -> Signal c -- ^Second Input signal +        -> Signal d -- ^Output signal+mealy2SY id nextState output initial = instantiate id mealy2Sys+  where mealy2Sys = newSysDef mealy2SysF ("mealySY_"++id) +                                         ["in1", "in2"] ["out1"]+        mealy2SysF i1 i2 = zipWith3SY "zipWith" output state i1 i2+           where state = scanld2SY "scanld" nextState initial i1 i2+ +++-- | The process constructor 'mealy2SY' behaves like 'mealySY', but has +--   two input signals.+mealy3SY :: (ProcType a, ProcType b, ProcType c, ProcType d, +             ProcType e) => +           ProcId+        -> ProcFun (a -> b -> c -> d -> a) -- ^Combinational function for next +                                           -- state decoder  +        -> ProcFun (a -> b -> c -> d -> e) -- ^Combinational function for +                                           -- output decoder+        -> a -- ^Initial state+        -> Signal b -- ^First Input signal+        -> Signal c -- ^Second Input signal +        -> Signal d -- ^Third Input signal +        -> Signal e -- ^Output signal+mealy3SY id nextState output initial = instantiate id mealy3Sys+  where mealy3Sys = newSysDef mealy3SysF ("mealySY_"++id) +                                         ["in1", "in2", "in3"] ["out1"]+        mealy3SysF i1 i2 i3 = zipWith4SY "zipWith" output state i1 i2 i3+           where state = scanld3SY "scanld" nextState initial i1 i2 i3+ +++-- | The process constructor 'filterSY' discards the values who do not fulfill a predicate given by a predicate function and replaces them with absent events.+filterSY       :: ProcType a =>+                  ProcId+               -> ProcFun (a -> Bool) -- ^ Predicate function+               -> Signal a -- ^ Input signal+               -> Signal (AbstExt a) -- ^ Output signal+filterSY id pred = mapSY id (filterer `defArgPF` pred) + where filterer = +        $(newProcFun [d| filterer :: (a -> Bool) -> a -> AbstExt a+                         filterer pred val = +                              if pred val then Prst val +                                          else Abst  |])++-- | The process 'sourceSY' takes a function and an initial state and generates+--   an infinite signal starting with the initial state as first output +--   followed by the recursive application of the function on the current +--   state. The state also serves as output value.             +--                                                                            +-- The process that has the infinite signal of natural numbers as output is +-- con structed by                                                            +--                                                                           +-- sourceSY \"naturals\" (+1) 0+sourceSY :: ProcType a =>+            ProcId +         -> ProcFun (a -> a) +         -> a +         -> Signal a+sourceSY id f s0 = instantiate id sourceSys+ where sourceSys = newSysDef sourceSysF ("sourceSY_"++id) +                                        [] ["out1"]+       sourceSysF = o  +         where o = delaySY "delay" s0 s+               s = mapSY  "map" f o+++++-- | The process constructor 'fillSY' creates a process that 'fills' a signal +--   with present values by replacing absent values with a given value. The +--   output signal is not any more of the type 'AbstExt'.        +fillSY :: ProcType a =>+          ProcId+       -> a                  -- ^Default value                                +       -> Signal (AbstExt a) -- ^Absent extended input signal             +       -> Signal a           -- ^Output signal                                +fillSY id v s = mapSY id (replaceAbst `defArgVal` v)  s+  where replaceAbst :: ProcFun (a -> AbstExt a -> a)+        replaceAbst = $(newProcFun +                          [d| replaceAbst :: a -> AbstExt a -> a+                              replaceAbst x y = fromAbstExt x y |])     ++-- | The process constructor 'holdSY' creates a process that 'fills' a signal +--   with values by replacing absent values by the preceding present value. +--   Only in cases, where no preceding value exists, the absent value is +--   replaced by a default value. The output signal is not any more of the +--   type 'AbstExt'.+holdSY :: ProcType a => +          ProcId -- ^Default value +       -> a+       -> Signal (AbstExt a) -- ^Absent extended input signal +       -> Signal a -- ^Output signal+holdSY id a s = scanlSY id hold a s+ where hold = $(newProcFun [d| hold :: a -> AbstExt a -> a+                               hold a abs = fromAbstExt a abs |])++---------------------------+--                       --+-- SYNCHRONOUS PROCESSES --+--                       --+---------------------------+++-- | The process constructor 'whenSY' creates a process that synchronizes a +--   signal of absent extended values with another signal of absent extended +--   values. The output signal has the value of the first signal whenever an +--   event has a present value and 'Abst' when the event has an absent value.+whenSY :: (ProcType a, ProcType b) => +           ProcId+        -> Signal (AbstExt a) -> Signal (AbstExt b) -> Signal (AbstExt a)+whenSY id = zipWithSY id whenF +  where whenF = $(newProcFun [d| whenF :: AbstExt a -> AbstExt b -> AbstExt a+                                 whenF v1 v2 = if isAbsent v2+                                                  then Abst+                                                  else v1 |])+++-- | The process 'zipSY' \"zips\" two incoming signals into one signal of +--   tuples.+zipSY :: (ProcType a, ProcType b) => +         ProcId+      -> Signal a +      -> Signal b +      -> Signal (a,b)+zipSY id = zipWithSY id tup2+  where tup2 :: ProcFun (a -> b -> (a,b))+        tup2 = $(newProcFun [d| tup2 :: a -> b -> (a,b)+                                tup2 a b = (a,b) |])++-- | The process 'zip3SY' works as 'zipSY', but takes three input signals.+zip3SY :: (ProcType a, ProcType b, ProcType c) => +          ProcId ->+          Signal a -> +          Signal b -> +          Signal c ->+          Signal (a,b,c)+zip3SY id = zipWith3SY id tup3+  where tup3 :: ProcFun (a -> b -> c -> (a,b,c))+        tup3 = $(newProcFun [d| tup3 :: a -> b -> c -> (a,b,c)+                                tup3 a b c = (a,b,c) |])+++-- | The process 'zip4SY' works as 'zipSY', but takes four input signals.+zip4SY :: (ProcType a, ProcType b, ProcType c, ProcType d) => +          ProcId -> +          Signal a -> +          Signal b -> +          Signal c ->+          Signal d ->+          Signal (a,b,c,d)+zip4SY id = zipWith4SY id tup4+  where tup4 :: ProcFun (a -> b -> c -> d -> (a,b,c,d))+        tup4 = $(newProcFun [d| tup4 :: a -> b -> c -> d -> (a,b,c,d)+                                tup4 a b c d = (a,b,c,d) |])+++-- | The process 'zip5SY' works as 'zipSY', but takes five input signals.+zip5SY :: (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e) => +          ProcId ->+          Signal a -> +          Signal b -> +          Signal c ->+          Signal d ->+          Signal e ->+          Signal (a,b,c,d,e)+zip5SY id = zipWith5SY id tup5+  where tup5 :: ProcFun (a -> b -> c -> d -> e -> (a,b,c,d,e))+        tup5 = $(newProcFun [d| tup5 :: a -> b -> c -> d -> e -> (a,b,c,d,e)+                                tup5 a b c d e = (a,b,c,d,e) |])+++-- | The process 'zip6SY' works as 'zipSY', but takes six input signals.+zip6SY :: (ProcType a, ProcType b, ProcType c, ProcType d, ProcType e, +           ProcType f) =>+          ProcId -> +          Signal a -> +          Signal b -> +          Signal c ->+          Signal d ->+          Signal e ->+          Signal f ->+          Signal (a,b,c,d,e,f)+zip6SY id = zipWith6SY id tup6+  where tup6 :: ProcFun (a -> b -> c -> d -> e -> f -> (a,b,c,d,e,f))+        tup6 = $(newProcFun [d| tup6 :: a -> b -> c -> d -> e -> f -> +                                        (a,b,c,d,e,f)+                                tup6 a b c d e f = (a,b,c,d,e,f) |])+++-- | The process 'unzipSY' \"unzips\" a signal of tuples into two signals.+unzipSY :: forall a b . (ProcType a, ProcType b) =>  +          ProcId+       -> Signal (a,b) +       -> (Signal a,Signal b)+unzipSY id s = (Signal (newNodeOutSig nodeRef (UnzipNSYOut 1)),+                Signal (newNodeOutSig nodeRef (UnzipNSYOut 2)))+  where ts = [typeOf (undefined :: a), typeOf (undefined :: b)]+        nodeRef = newURef $ Proc id $ +                     UnzipNSY ts untup (unSignal s)+        untup :: Dynamic -> [Dynamic]+        untup i = let (t1,t2) = ((fromJust.fromDynamic) i) :: (a,b)    +                  in [toDyn t1, toDyn t2]++++-- | The process 'unzip3SY' \"unzips\" a signal of tuples into three signals.+unzip3SY :: forall a b c . (ProcType a, ProcType b, ProcType c) =>  +           ProcId +        -> Signal (a,b,c) +        -> (Signal a, Signal b, Signal c)+unzip3SY id s = (Signal (newNodeOutSig nodeRef (UnzipNSYOut 1)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 2)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 3)))+  where ts = [typeOf (undefined :: a), typeOf (undefined :: b),+              typeOf (undefined :: c)]+        nodeRef = newURef $ Proc id $ +                     UnzipNSY ts untup3 (unSignal s)+        untup3 :: Dynamic -> [Dynamic]+        untup3 i = let (t1,t2,t3) = ((fromJust.fromDynamic) i) :: (a,b,c)    +                   in [toDyn t1, toDyn t2, toDyn t3]+++-- | The process 'unzip4SY' \"unzips\" a signal of tuples into four signals.+unzip4SY :: forall a b c d . (ProcType a, ProcType b, ProcType c, +                              ProcType d) => +           ProcId   +        -> Signal (a,b,c,d) +        -> (Signal a, Signal b, Signal c, Signal d)+unzip4SY id s = (Signal (newNodeOutSig nodeRef (UnzipNSYOut 1)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 2)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 3)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 4)))+  where ts = [typeOf (undefined :: a), typeOf (undefined :: b),+              typeOf (undefined :: c), typeOf (undefined :: d)]+        nodeRef = newURef $ Proc id $ +                     UnzipNSY ts untup4 (unSignal s)+        untup4 :: Dynamic -> [Dynamic]+        untup4 i = let (t1,t2,t3,t4) = ((fromJust.fromDynamic) i) :: (a,b,c,d)+                   in [toDyn t1, toDyn t2, toDyn t3, toDyn t4]+++-- | The process 'unzip5SY' \"unzips\" a signal of tuples into five signals.+unzip5SY :: forall a b c d e . (ProcType a, ProcType b, ProcType c, +                                ProcType d, ProcType e) => +           ProcId +        -> Signal (a,b,c,d,e) +        -> (Signal a, Signal b, Signal c, Signal d, Signal e)+unzip5SY id s = (Signal (newNodeOutSig nodeRef (UnzipNSYOut 1)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 2)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 3)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 4)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 5)))+  where ts = [typeOf (undefined :: a), typeOf (undefined :: b),+              typeOf (undefined :: c), typeOf (undefined :: d),+              typeOf (undefined :: e)]+        nodeRef = newURef $ Proc id $ +                     UnzipNSY ts untup5 (unSignal s)+        untup5 :: Dynamic -> [Dynamic]+        untup5 i = let (t1,t2,t3,t4,t5) +                        = ((fromJust.fromDynamic) i) :: (a,b,c,d,e)+                   in [toDyn t1, toDyn t2, toDyn t3, toDyn t4, toDyn t5]+++-- | The process 'unzip6SY' \"unzips\" a signal of tuples into six signals.+unzip6SY :: forall a b c d e f . (ProcType a, ProcType b, ProcType c, +                                  ProcType d, ProcType e, ProcType f) =>  +           ProcId +        -> Signal (a,b,c,d,e,f) +        -> (Signal a, Signal b, Signal c, Signal d, Signal e, Signal f)+unzip6SY id s = (Signal (newNodeOutSig nodeRef (UnzipNSYOut 1)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 2)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 3)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 4)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 5)),+                 Signal (newNodeOutSig nodeRef (UnzipNSYOut 6)))+  where ts = [typeOf (undefined :: a), typeOf (undefined :: b),+              typeOf (undefined :: c), typeOf (undefined :: d),+              typeOf (undefined :: e), typeOf (undefined :: f)]+        nodeRef = newURef $ Proc id $ +                     UnzipNSY ts untup6 (unSignal s)+        untup6 :: Dynamic -> [Dynamic]+        untup6 i = let (t1,t2,t3,t4,t5,t6) +                        = ((fromJust.fromDynamic) i) :: (a,b,c,d,e,f)+                   in [toDyn t1, toDyn t2, toDyn t3, toDyn t4, toDyn t5, +                       toDyn t6]++-- | The process 'zipxSY' \"zips\" a signal of vectors into a vector of signals.+zipxSY :: (Nat s, Typeable s, ProcType a) =>+          ProcId+       -> FSVec s (Signal a) +       -> Signal (FSVec s a)+zipxSY id = zipWithxSY id vectId +  where vectId = $(newProcFun [d| vectId :: FSVec s a -> FSVec s a+                                  vectId v = v |]) ++-- | The process 'unzipxSY' \"unzips\" a vector of n signals into a signal of +--   vectors.+unzipxSY :: forall s a . (Typeable s, Nat s, ProcType a) => +            ProcId+         -> Signal (FSVec s a) +         -> FSVec s (Signal a)+unzipxSY id vs = V.map (\tag -> Signal (newNodeOutSig nodeRef tag) )+                        (reallyUnsafeVector [UnzipxSYOut i | i <- [1..n]])+  where n = toInt (undefined :: s)+        t = typeOf (undefined :: a)+        nodeRef = newURef $ Proc id $+                    UnzipxSY t n unvector (unSignal vs)+        unvector :: Dynamic -> [Dynamic]+        unvector i = let v = ((fromJust.fromDynamic) i) :: FSVec s a+                     in map toDyn (V.fromVector v)++-- | The process 'fstSY' selects always the first value from a signal of pairs+fstSY :: (ProcType a, ProcType b) => ProcId -> Signal (a,b) -> Signal a+fstSY id = mapSY id  first+  where first = $(newProcFun [d| first :: (a,b) -> a+                                 first (a,_) = a |])+++-- | The process 'sndSY' selects always the second value from a signal of pairs+sndSY :: (ProcType a, ProcType b) => ProcId -> Signal (a,b) -> Signal b+sndSY id = mapSY id second+  where second = $(newProcFun [d| second :: (a,b) -> b+                                  second (_,b) = b |])++++-- | The function 'groupSY' groups values into a vector of size n, which takes +--   n cycles. While the grouping takes place the output from this process +--   consists of absent values.+groupSY :: forall k a . (Nat k, Typeable k, ProcType a) => +           ProcId -> k -> Signal a -> Signal (AbstExt (FSVec k a))+groupSY id k = mooreSY id (f `defArgVal` kV)  (g `defArgVal` kV) s0 +  where+   kV = toInt k+   -- FIXME, FIXME, this won't work in th VHDL backend+   --               due to the undefined and probably unsafeReplace+   s0 = (0, V.copy k (undefined :: a)) +   f = $(newProcFun [d| f :: Nat k' => Int -> (Int, FSVec k' a') -> a' -> +                             (Int, FSVec k' a')+                        f k (count,v)  a =+                           (count+1 `mod` k, unsafeReplace v count a) |])+   g = $(newProcFun [d| g :: Nat k' => Int -> (Int, FSVec k' a') -> AbstExt (FSVec k' a') +                        g k (count,v) = if  k-1 == count then Prst v else Abst |])+   unsafeReplace :: Nat s => FSVec s a' -> Int -> a' ->FSVec s a'+   unsafeReplace v i a = +      reallyUnsafeVector $ unsafeReplace' (fromVector v) i a+     where unsafeReplace' []     _ _ = []+           unsafeReplace' (_:xs) 0 y = (y:xs)+           unsafeReplace' (x:xs) n y = x : (unsafeReplace' xs (n - 1) y)+
+ src/ForSyDe/Shallow.hs view
@@ -0,0 +1,43 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+--+-- Shallow-embedded implementation of ForSyDe (see "ForSyDe.Shallow.Signal"). +--+-- Unlike systems built using the deep-embedded Signal type of ForSyDe+-- (see 'ForSyDe.Signal'), systems built with 'ForSyDe.Shallow.Signal'+-- can make use of new and experimental features such as multiple,+-- heterogeneous MoCs (Models of Computation) other than the Synchronous+-- MoC (the only Model of Computation currently supported by deep-embdded+-- ForSyDe). However, as an important tradeoff, 'ForSyDe.Shallow.Signal'+-- is unaware of the resulting system structure, only allowing simulation +-- (i.e. a VHDL or GraphML backend is impossible to implement).+-- +-- The shallow implementation of ForSyDe consists of three main libraries:+-- +-- * "ForSyDe.Shallow.CoreLib" contains the basic definitions and+--   functions such as events and signals.+--+-- * "ForSyDe.Shallow.MoCLib" defines the models of computations+--   included in ForSyDe.+--+-- * "ForSyDe.Shallow.UtilityLib" provides several additional modules+--   that are useful and convenient in practice. Their status is+--   experimental.+--+-----------------------------------------------------------------------------+module ForSyDe.Shallow(module ForSyDe.Shallow.CoreLib+              , module ForSyDe.Shallow.MoCLib+              , module ForSyDe.Shallow.UtilityLib+	      ) where++import ForSyDe.Shallow.CoreLib+import ForSyDe.Shallow.MoCLib+import ForSyDe.Shallow.UtilityLib
+ src/ForSyDe/Shallow/AbsentExt.hs view
@@ -0,0 +1,88 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.AbsentExt+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The 'AbstExt' is used to extend existing data types with the value+--  \'absent\', which models the absence of a value.+-- +-----------------------------------------------------------------------------+module ForSyDe.Shallow.AbsentExt( +		  AbstExt (Abst, Prst), fromAbstExt, abstExt, psi, +	          isAbsent, isPresent, abstExtFunc)+	        where+++++-- |The data type 'AbstExt' has two constructors. The constructor 'Abst' is used to model the absence of a value, while the constructor 'Prst' is used to model present values.+data AbstExt a		       =  Abst   +			       |  Prst a deriving (Eq)++++-- |The function 'fromAbstExt' converts a value from a extended value.+fromAbstExt	       :: a -> AbstExt a -> a+-- |The functions 'isPresent' checks for the presence of a value.+isPresent	       :: AbstExt a -> Bool+-- |The functions 'isAbsent' checks for the absence of a value.+isAbsent	       :: AbstExt a -> Bool+-- |The function 'abstExtFunc' extends a function in order to process absent extended values. If the input is (\"bottom\"), the output will also be  (\"bottom\").+abstExtFunc	       :: (a -> b) -> AbstExt a -> AbstExt b+-- | The function 'psi' is identical to 'abstExtFunc' and should be used in future.+psi :: (a -> b) -> AbstExt a -> AbstExt b+-- | The function 'abstExt' converts a usual value to a present value. +abstExt :: a -> AbstExt a+++++++-- Implementation of Library Functions++-- | The data type 'AbstExt' is defined as an instance of 'Show' and 'Read'. \'_\' represents the value 'Abst' while a present value is represented with its value, e.g.  'Prst' 1 is represented as \'1\'.+instance Show a => Show (AbstExt a) where+	 showsPrec _ x	       = showsAbstExt x++showsAbstExt :: Show a => AbstExt a -> [Char] -> [Char]+showsAbstExt Abst	       = (++) "_"       +showsAbstExt (Prst x)	       = (++) (show x)++instance Read a => Read (AbstExt a) where+ 	 readsPrec _ x	       =  readsAbstExt x ++readsAbstExt		       :: (Read a) => ReadS (AbstExt a)+readsAbstExt s		       =     [(Abst, r1)    | ("_", r1) <- lex s]+                                  ++ [(Prst x, r2)  | (x, r2) <- reads s]++abstExt v		       =  Prst v++fromAbstExt x Abst	       =  x   +fromAbstExt _ (Prst y)	       =  y   ++isPresent Abst		       =  False+isPresent (Prst _)	       =  True++isAbsent		       =  not . isPresent++abstExtFunc f		       = f' +  where f' Abst		       = Abst+	f' (Prst x)	       = Prst (f x)+++psi			       = abstExtFunc+++++++++
+ src/ForSyDe/Shallow/AdaptivityLib.hs view
@@ -0,0 +1,26 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.AdaptivityLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Adaptivity Library, yet to be completed.+-- +-----------------------------------------------------------------------------+module ForSyDe.Shallow.AdaptivityLib (applyfSY, applyfU) where++import ForSyDe.Shallow.Signal+import ForSyDe.Shallow.SynchronousLib+import ForSyDe.Shallow.UntimedLib++applyfSY :: Signal (a -> b) -> Signal a -> Signal b+applyfSY = zipWithSY apply+           where apply f x = f x++applyfU :: Int -> Signal ([a] -> [b]) -> Signal a -> Signal b+applyfU tokenNum = comb2UC tokenNum apply+      where apply f x = f x
+ src/ForSyDe/Shallow/BitVector.hs view
@@ -0,0 +1,122 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.BitVector+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- It defines the bit vector operations from\/to integer.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.BitVector(+    -- *Polynomial data type+    BitVector, Parity(..),+    -- *Bit-vector and integer transformations+    intToBitVector, bitVectorToInt,+    -- *Add even\/odd parity bit+    addEvenParityBit, addOddParityBit, addParityBit,+    -- *Remove parity bit+    removeParityBit,+    -- *Check the even\/odd parity of the bit-vector+    isEvenParity, isOddParity,+    -- *Judge the form sanity of the bit-vector+    isBitVector+  )+  where++import ForSyDe.Shallow.Vector++type BitVector = Vector Integer++-- |To judge whether the input bit-vector is in a proper form.+isBitVector :: (Num t) =>+          Vector t  -- ^Input bit-vector+       -> Bool      -- ^Output boolean value+isBitVector NullV = True+isBitVector (x:>xs) = (x == 0 || x == 1) && isBitVector xs++-- |To transform the input integer to a bit-vector with specified number of+-- bits.+intToBitVector :: Int  -- ^Num of the bits+               -> Integer  -- ^The input integer+               -> BitVector -- ^The output bit-vector+intToBitVector bits n | n >= 0 && n < 2^(bits-1) +			   = intToBitVector' bits n+intToBitVector bits n | n < 0 && abs n <= 2^(bits-1) +			   = intToBitVector' bits (n + 2^bits)+intToBitVector _    _ | otherwise = +          error "intToBitvector : Number out of range!" ++-- |Helper function of 'intToBitVector'.+intToBitVector' :: (Num a, Ord a1, Num a1, Integral t) => +                   t -> a1 -> Vector a+intToBitVector' 0    _ = NullV+intToBitVector' bits n = if (n >= 2^(bits-1)) then+			     1 :> intToBitVector' (bits-1) (n - 2^(bits-1))+			 else  +			     0 :> intToBitVector' (bits-1) n++-- |To transform the input bit-vecotr to an integer.+bitVectorToInt :: BitVector -> Integer+bitVectorToInt (1:>xv) | isBitVector xv +               = bitVectorToInt' xv (lengthV xv) - 2^(lengthV xv) +bitVectorToInt (0:>xv) | isBitVector xv +               = bitVectorToInt' xv (lengthV xv)+bitVectorToInt _ = error "bitVectorToInt: Vector is not a BitVector!"+++-- |Helper function of 'bitVectorToInt'.+bitVectorToInt' :: (Integral a, Num t) => Vector t -> a -> t+bitVectorToInt' NullV   _   = 0+bitVectorToInt' (x:>xv) bit = x * 2^(bit-1) + bitVectorToInt' xv (bit-1)++data Parity = Even | Odd deriving (Show, Eq)++-- |To add even parity bit on the bit-vector in the tail.+addEvenParityBit :: Num a => Vector a -> Vector a+addEvenParityBit = addParityBit Even+-- |To add odd parity bit on the bit-vector in the tail.+addOddParityBit :: Num a => Vector a -> Vector a+addOddParityBit  = addParityBit Odd++addParityBit :: Num a => Parity -> Vector a -> Vector a+addParityBit p v +  | isBitVector v = case p of+                     Even -> resZero even+                     Odd -> resZero (not even)+  | otherwise =  error "addParity: Vector is not a BitVector"  + where even = evenNumber v +       resZero b = v <+> unitV (if b then 0 else 1)+++-- |To remove the parity bit in the tail.+removeParityBit :: Num t => Vector t -> Vector t+removeParityBit v + | isBitVector v = takeV (lengthV v - 1) v+ | otherwise = error "removeParityBit: Vector is not a BitVector "++-- |To check the even parity of the bit-vector.+isEvenParity :: Num t => Vector t -> Bool+isEvenParity = isParityCorrect Even++-- |To check the odd parity of the bit-vector.+isOddParity :: Num t => Vector t -> Bool+isOddParity = isParityCorrect Odd++isParityCorrect :: Num t => Parity -> Vector t -> Bool +isParityCorrect Even xv = evenNumber xv+isParityCorrect Odd xv  = not $ evenNumber xv ++evenNumber :: Num t => Vector t -> Bool+evenNumber NullV   = True+evenNumber (0:>xv) = xor False (evenNumber xv)+evenNumber (1:>xv) = xor True (evenNumber xv)+evenNumber (_:>_) = error "evenNumber: Vector is not a BitVector "+                     +xor :: Bool -> Bool -> Bool+xor True  False = True+xor False True  = True+xor _     _     = False +
+ src/ForSyDe/Shallow/CTLib.hs view
@@ -0,0 +1,1040 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.CTLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This is the ForSyDe library for continuous time MoC (CT-MoC).+-- Revision: $Revision: 1.7 $+-- Id: $Id: CTLib.hs,v 1.7 2007/07/11 08:38:34 axel Exp $+-- It is still experimental.+-- Right now there are only constructors 'combCT', 'combCT2', 'delayCT', +-- 'shiftCT', 'mealyCT', 'mooreCT', 'scaleCT', 'addCT', 'multCT' and 'absCT'.+--+-- The main idea is to represent continuous time signals as functions+-- @Real --> a@ with @a@ being a numerical type. This allows us to represent a +-- continuous time signal without loss of information because no sampling or +-- ADC is required. The sampling occurs only when a signal is evaluated, +-- for instance when it is plotted. +-- +-- Thus, a /signal/ is represented as a sequence of functions and intervals. For+-- instance a signal +-- +-- @s = \<(sin,[0,100])\>@ +--+-- represents a sinus signal in the interval between 0 and 100. The signal +--+-- @s2 = \<(f1(x)=2x, [0,2]), (f2(x)=3+x,[2,4])\>@+--+-- defines a signal that is defined by function @f1@ in the interval @[0,2]@ +-- and by function @f2@ in the interval @[2,4]@. +--+-- A /process/ transforms the incoming functions into outgoing functions. +-- The approach is described in more detail in the ANDRES deliverable D1.1a.+-- Here we only briefly comment the main functions and constructors.+----------------------------------------------------------------------------+module ForSyDe.Shallow.CTLib (+--	      module ForSyDe.Shallow.CoreLib,+              -- * The signal data type+              SubsigCT(..), +              timeStep,+              -- * Primary process constructors+              combCT, combCT2, mooreCT, mealyCT, delayCT, shiftCT, initCT,+              -- * Derived process constructors+              -- | These constructors instantiate very useful processes.+              -- They could be defined in terms of the basic constructors+              -- but are typically defined in a more direct way for +              -- the sake of efficieny.+	      scaleCT, addCT, multCT, absCT,+              -- * Convenient functions and processes+              -- | Several helper functions are available to obtain parts+              -- of a signal, the duration, the start time of a signal, and+              -- to generate a sine wave and constant signals.+              takeCT, dropCT, duration, startTime, sineWave, constCT, zeroCT,+              -- * AD and DA converters+              DACMode(..), a2dConverter, d2aConverter,+              -- * Some helper functions+              applyF1, applyF2, applyG1, cutEq, +              -- * Sampling, printing and plotting+              -- $plotdoc+              plot, plotCT, plotCT' ,showParts, vcdGen)+    where++import ForSyDe.Shallow.CoreLib+import System.Cmd+import System.Time+import System.IO+import System.Directory+--import Control.Exception+import Data.Ratio+import Numeric()++-- The revision number of this file:+revision :: String+revision=filter (\ c -> (not (c=='$'))) "$Revision: 1.7 $, $Date: 2007/07/11 08:38:34 $"++-- |The type of a sub-signal of a continuous signal. It consisits of the +--  function and the interval on which the function is defined.+-- The continuous time signal is then defined as a sequence of SubsigCT +-- elements: Signal SubsigCT+data (Num a) => +    SubsigCT a = SubsigCT ((Rational -> a),     -- The function Time -> Value+                           (Rational,Rational)) -- The interval on which the+                                                --  function is defined++instance (Num a) => Show (SubsigCT a) where+    show ss = show (sampleSubsig timeStep ss)++--unit :: String -- all time numbers are in terms of this unit.+--unit = "sec" ++-- | This constant gives the default time step for sampling and plotting.+-- Its value is 10ns.+timeStep :: Rational +timeStep = 10.0e-9++-----------------------------------------------------------------------+-- |'combCT' is a process constructor with one input and one output signal.+-- It instantiates a combinatorial, stateless process.+combCT :: (Num a) =>+          Rational -- ^The partitioning of the input signal. In other words+                   -- this gives the time period which is consumed by the+                   -- process during each evaluation cycle.+       -> ((Rational -> a) -> (Rational -> a)) -- ^The function that +                                                      -- defines the process +                                                      -- behaviour+	->Signal (SubsigCT a)   -- ^The input signal+        -> Signal (SubsigCT a)  -- ^The output signal of the process.+combCT _ _ NullS = NullS+combCT c f s | (duration (takeCT c s)) < c = NullS+	      | otherwise = applyF1 f (takeCT c s) +-+ combCT c f (dropCT c s)++-- |'combCT2' is a process constructor just like 'combCT' but operates on+-- two input signals.+combCT2 :: (Num a) =>+           Rational -- ^The partitioning of both input signals+	-> ((Rational -> a) -> (Rational -> a) -> (Rational->a)) +           -- ^The function defining the process behaviour.+	-> Signal (SubsigCT a) -- ^The first input signal+        -> Signal (SubsigCT a) -- ^The second input signal+        -> Signal (SubsigCT a) -- ^The output signal of the process+combCT2 _ _ NullS _ = NullS+combCT2 _ _ _ NullS = NullS+combCT2 c f s1 s2 | (duration (takeCT c s1)) < c+		      || (duration (takeCT c s2)) < c = NullS+		  | startTime s1 /= startTime s2 +                      && abs(startTime s1 - startTime s2) > 0+		      = error ("combCT2: s1 and s2 have not identical start"+			       ++ " times: startTime s1 = "+			       ++ (show (startTime s1)) ++ ", startTime s2 = "+			       ++ (show (startTime s2)) ++ ";")+		  | otherwise = applyF2 f s1' s2'+				+-+ combCT2 c f (dropCT c s1) (dropCT c s2)+		  where (s1',s2') = cutEq (takeCT c s1) (takeCT c s2)++---+-- |'delayCT' is a delay process which simply delays the+-- output but does not buffer it. The value at each time t is the same as +-- for the input signal, after the initial delay.+delayCT :: (Num a) =>+           Rational           -- ^ The delay+        -> Signal (SubsigCT a) -- ^ The input signal+        -> Signal (SubsigCT a) -- ^ The output signal+delayCT _     NullS = NullS+delayCT delay (SubsigCT (f,(a,b)) :- s) +              = SubsigCT (f,(a+delay, b+delay)) :- delayCT delay s+++----+-- |'shiftCT'  shifts the shape of the input signal by delay +-- to the right.+shiftCT :: (Num a) =>+           Rational          -- ^ The delay+        -> Signal (SubsigCT a) -- ^ The input signal+        -> Signal (SubsigCT a) -- ^ The output signal+shiftCT _     NullS = NullS+shiftCT 0     s     = s+shiftCT delay s     = shiftCT' delay (dropCT delay s) -- The new signal shall+                                                      --  only start delay +                                                      -- seconds later.+    where +      shiftCT' _      NullS = NullS+      shiftCT' delay (SubsigCT (f,(a,b)) :- s) +          = SubsigCT (f',(a,b)) :- (shiftCT' delay s)+          where f' x = f (x-delay)++----+-- | initCT takes an initial signal, outputs it and then copies its second +-- input signal, which is delayed by the duration of the initial signal.+-- The delay is realized by 'delayCT' +initCT :: (Num a) => +          Signal (SubsigCT a) -- ^ The initial signal output first.+       -> Signal (SubsigCT a) -- ^ Then this signal is output, but delayed.+       -> Signal (SubsigCT a) -- ^ The concatation of the two inputs.+initCT s0 s1 = s0 +-+ (delayCT (duration s0) s1)++-----------------------------------------------------------------------------+-- |The state-full constructor 'mealyCT' resembles a Mealy machine.+mealyCT :: (Num b, Num c) =>+           (a -> Rational)                  -- ^The gamma function which defines+                                           -- the partitioning of the input+                                           -- signal. +	 -> (a -> (Rational -> b) -> a) -- ^The next state function g+	 -> (a -> (Rational -> b) -> (Rational -> c))+	                                   -- ^The output encoding function f +	 -> a                              -- ^The initial state+	 -> Signal (SubsigCT b)                -- ^The input signal+	 -> Signal (SubsigCT c)                -- ^The output signal+mealyCT _     _ _ _ NullS = NullS+mealyCT gamma g f w s+    | (duration (takeCT c s)) < c = NullS+    | otherwise = applyF1 (f w) (takeCT c s) +		  +-+ mealyCT gamma g f w' (dropCT c s)+    where c = gamma w+	  w' = applyG1 g w (takeCT c s)++-- |The state-full constructor 'mooreCT' resembles a Moore machine.+mooreCT :: (Num b, Num c) =>+           (a -> Rational)                  -- ^The gamma function which defines+                                           -- the partitioning of the input+                                           -- signal. +	 -> (a -> (Rational -> b) -> a) -- ^The next state function g+	 -> (a -> (Rational -> c))+	                                   -- ^The output encoding function f +	 -> a                              -- ^The initial state+	 -> Signal (SubsigCT b)                -- ^The input signal+	 -> Signal (SubsigCT c)                -- ^The output signal+mooreCT _     _ _ _ NullS = NullS+mooreCT gamma g f w s+    | (duration (takeCT c s)) < c = NullS+    | otherwise = (SubsigCT ((f w),(a,b))) +                  :- mooreCT gamma g f w' (dropCT c s)+    where c = gamma w+          a = startTime s+          b = a + c+	  w' = applyG1 g w (takeCT c s)++-------------------------------------------------------------------------+-- Some useful process constructors:+-- +-- |'scaleCT' amplifies an input by a constant factor:+scaleCT :: (Num a) =>+           a                   -- ^The scaling factor+        -> Signal (SubsigCT a) -- ^The input signal+        -> Signal (SubsigCT a) -- ^The output signal of the process+scaleCT k = applyF1 f'+    where f' f x = k * (f x)++-- scaleCT' has the same functionality as scaleCT but operates with a+-- given signal partitioning rather than on the +-- SubsigCT elements.+--scaleCT' :: (Num a) =>+--            Rational -- The sampling period+--         -> a        -- The scaling factor+--         -> Signal (SubsigCT a) -> Signal (SubsigCT a)+--scaleCT' step k = combCT step f+--    where f g = f'+--	      where f' x = k * (g x)++-- |'addCT' adds two input signals together.+addCT :: (Num a) =>+         Signal (SubsigCT a) -- ^The first input signal+      -> Signal (SubsigCT a) -- ^The second input signal+      -> Signal (SubsigCT a) -- ^The output signal+addCT s1 s2 = applyF2 f s1' s2'+    where (s1',s2') = cutEq s1 s2+          f g1 g2 = f'+              where f' x = (g1 x) + (g2 x)+	      +-- addCT' has the same functionality as addCT but operates with a+-- given signal partitioning rather than on the SubsigCT elements.+-- addCT' :: (Num a) =>+--           Rational          -- The sampling period+--        -> Signal (SubsigCT a) -- The first input signal+--        -> Signal (SubsigCT a) -- The second input signal+--        -> Signal (SubsigCT a) -- The output signal+-- addCT' step = combCT2 step f+--     where f g1 g2 = f'+-- 	      where f' x = (g1 x) + (g2 x)+	      +-- |'multCT' multiplies two input signals together.+multCT :: (Num a) =>+          Signal (SubsigCT a) -- ^The first input signal+       -> Signal (SubsigCT a) -- ^The second input signal+       -> Signal (SubsigCT a) -- ^The output signal+multCT s1 s2 = applyF2 f s1' s2'+    where (s1',s2') = cutEq s1 s2+          f g1 g2 = f'+              where f' x = (g1 x) * (g2 x)++-- multCT' has the same functionality as multCT but operates with a+-- given signal partitioning rather than on the SubsigCT elements.+-- multCT' :: (Num a) =>+--            Rational          -- The sampling period+--         -> Signal (SubsigCT a) -- The first input signal+--         -> Signal (SubsigCT a) -- The second input signal+--         -> Signal (SubsigCT a) -- The output signal+-- multCT' step = combCT2 step f+--     where f g1 g2 = f'+--               where f' x = (g1 x) * (g2 x)++-- |'absCT' takes the absolute value of a signal.+absCT :: (Num a,Ord a) =>+         Signal (SubsigCT a) -- ^The input signal+      -> Signal (SubsigCT a) -- ^The output signal+absCT = applyF1 f+    where f g = f'+	      where f' x | (g x) <= 0 = (-1) * (g x)+                         | otherwise  = (g x)++-- | 'sineWave' generates a sinus signal with the given frequency defined+-- over  a given period. The function is defined as @f(x)=sin(2*pi*freq*x)@.+sineWave :: (Floating a) =>+            Rational          -- ^The frequency+         -> (Rational,Rational) -- ^The interval of the signal+         -> Signal (SubsigCT a) -- ^The generated signal+sineWave freq timeInterval +    = signal [SubsigCT (sineFunction, timeInterval)]+      where +        sineFunction :: (Floating a) => Rational -> a+        --sineFunction t = sin (2*pi * freq * t)+        sineFunction t = (sin (2*pi * (fromRational (freq * t))))+-- | constCT generates a constant signal for a given time duration.+constCT :: (Num a) => +           Rational -- ^ The time duration of the generated signal.+        -> a        -- ^ The constant value of the signal.+        -> Signal (SubsigCT a) -- ^ The resulting signal.+constCT t c = signal [SubsigCT ((\_->c), (0,t))]++-- | zeroCT generates a constant 0 signal for the given time duration.+zeroCT :: (Num a) => +          Rational            -- ^ The time duration+       -> Signal (SubsigCT a) -- ^ The generated signal.+zeroCT t = constCT t 0++-----------------------------------------------------------------------------+-- DA and AD converter processes:+--+-- |For the digital-analog conversion we have two different possibilities+-- which is determined by this data type 'DACMode'.+data DACMode = DAlinear -- ^linear interpolation+             | DAhold   -- ^the last digital value is frozen+  deriving (Show, Eq)++{- |'d2aConverter' converts an untimes or synchronous signal into a + continuous time signal.+ The process 'd2aConverter' converts a signal of the digital domain+ into a continuous time signal. There are two modes, 'DAlinear',+ which makes a smooth transition between adjacent digital values and+ 'DAhold', where the analog value directly follows the digital+ value. This means that in 'DAhold'-mode a staircase function+ remains a staircase function, while in 'DAlinear' the staircase+ function would resemble at least partially a /saw tooth/-curve. ++ The resolution of the converter is given by the parameter+ 'timeStep'.++ Note, that the process 'd2aConverter' is an ideal component, i.e. there+ are no losses due to a limited resolution due to a fixed number of bits. +-}+d2aConverter :: (Fractional a) =>+                DACMode           -- ^Mode of conversion+              -> Rational           -- ^Duration of input signal+              -> Signal a             -- ^Input signal (untimed MoC)+              -> Signal (SubsigCT a)  -- ^Output signal (continuous time MoC)+d2aConverter mode c xs+        | mode == DAlinear = d2aLinear c 0.0 xs+        | otherwise = d2aHolder c 0.0 xs+  where+    d2aHolder :: (Num a) => +                 Rational -> Rational -> Signal a -> Signal (SubsigCT a)+    d2aHolder _ _ NullS = NullS+    d2aHolder c holdT (x:-xs) = (SubsigCT (constRationalF x,(holdT,holdT+c)) )+                                :- d2aHolder c (holdT+c) xs++    d2aLinear :: (Fractional a) =>+                 Rational -> Rational -> Signal a -> Signal (SubsigCT a)+    d2aLinear _ _ NullS = NullS+    d2aLinear _ _ (_:-NullS) = NullS+    d2aLinear c holdT (x:-y:-xs) = +                      (SubsigCT (linearRationalF c holdT x y,(holdT,holdT+c)) )+                                  :- d2aLinear c (holdT+c) (y:-xs)+++constRationalF :: (Num a) => a -> Rational -> a+constRationalF = (\x _->x)++linearRationalF :: (Fractional a) =>+                   Rational -> Rational -> a -> a -> Rational -> a+linearRationalF c holdT m n x = (1-alpha)*m + alpha*n+  where alpha :: (Fractional a) => a+        alpha = fromRational ((x-holdT)/c)++{- | The process 'a2dConverter' converts a continuous time signal to+   an untimed or synchronous signal. The first parameter gives the+   sampling period of the converter.++   Note, that the process 'a2dConverter' is an ideal component,+   i.e. there are no losses due to a limited resolution due to a fixed+   number of bits.  +-}+a2dConverter :: (Num a) =>+                Rational            -- ^Sampling Period+             -> Signal (SubsigCT a) -- ^Input signal (continuous time)+	     -> Signal a            -- ^Output signal (untimed)+a2dConverter _ NullS = NullS+a2dConverter c s | (duration (takeCT c s)) < c = NullS+                 | otherwise = f (takeCT c s)+                               +-+ a2dConverter c (dropCT c s)+    where f :: (Num a ) => Signal (SubsigCT a) -> Signal a+          f NullS = NullS+          f (SubsigCT (g,(a,_)) :- _) = signal [g a]++--------------------------------------------------------------------+-- Helpter functions for the CT MoC:+-- | applyF1 applies a function on a sub-signal, which means the function of +-- the subsignal is transformed to another function:+applyF1 :: (Num a, Num b) =>+           ((Rational -> a) -> (Rational -> b)) -- The transformer+        -> Signal (SubsigCT a)                            -- The input signal+        -> Signal (SubsigCT b)                            -- The output signal+applyF1 _ NullS = NullS+applyF1 f (ss :- s) = (applyF' f ss) :- (applyF1 f s)+    where applyF' :: (Num a, Num b) =>+                     ((Rational -> a) -> (Rational -> b)) +                  -> (SubsigCT a) -> (SubsigCT b)+          applyF' f (SubsigCT (f',(a,b))) = SubsigCT ((f f'), (a,b))++-- | applyF2 works just like applyF1 but operates on two incoming signals.+applyF2 :: (Num a, Num b, Num c) =>+           ((Rational -> a) -> (Rational->b) -> (Rational -> c))+        -> Signal (SubsigCT a) +        -> Signal (SubsigCT b) +        -> Signal (SubsigCT c) +applyF2 _ NullS _ = NullS+applyF2 _ _ NullS = NullS+applyF2 f (ss1 :- s1) (ss2 :- s2) = (applyF' f ss1 ss2) :- (applyF2 f s1 s2)+    where applyF' f (SubsigCT (f1,(a,b))) (SubsigCT (f2,(c,d))) +              | (a==c) && (b==d) +	        || (abs (a-c)< 0)+		|| (abs (b-d)< 0)+	        = SubsigCT ((f f1 f2), (a,b))+	        +              | otherwise    = error ("applyF2: The two subintervals are"+                                      ++ " not identical: (a,b) = ("+                                      ++ (show a) ++ ", "+                                      ++ (show b) ++ "); (c,d) = ("+                                      ++ (show c) ++ ", "+                                      ++ (show d) ++ ").")++-- | applyG1 is used to apply a next-state function. A very interesting+-- question is, what should be an argument to the next-state function: +-- the incoming function, defining the value of the input signal?+-- or the incoming function and the incoming interval?+-- or the value of the incoming signal at a particular point, e.g. at the +-- left most point of the interval?+-- To give the next-state function the interval itself as argument, would mean+-- that the process becomes time variant process, i.e. its behaviour is +-- dependent on the absolute time values. This is not a good thing to have!+-- Another possibility may be to give a sub-signal that is relative to the +-- current evaluation, i.e. the left most point is always 0. Would that make+-- sense?+applyG1 :: (Num b) =>+           (a -> (Rational -> b) -> a) -> a -> Signal (SubsigCT b) -> a+applyG1 _ w NullS = w+applyG1 g w (ss :- _) = applyG1' g w ss+    where +    applyG1' :: (Num b) =>+                (a -> (Rational -> b) -> a) -> a -> (SubsigCT b) -> a+    applyG1' g w (SubsigCT (f, (_,_))) = g w f++-- | cutEq partitions the two signals such that the partitioning are identical+-- in both result signals, but only up to the duration of the shorter of the +-- two signals:+cutEq :: (Num a, Num b) =>+         Signal (SubsigCT a) -> Signal (SubsigCT b) +      -> (Signal (SubsigCT a), Signal (SubsigCT b))+cutEq NullS s2 = (NullS, s2) +cutEq s1 NullS = (s1, NullS) +cutEq s1 s2 = unzipCT (cutEq' s1 s2)+    where +    cutEq' :: (Num a, Num b) =>+              Signal (SubsigCT a) -> Signal  (SubsigCT b) +	   -> Signal ((SubsigCT a), (SubsigCT b))+    cutEq' NullS _    = NullS+    cutEq' _ NullS    = NullS+    cutEq' (ss1:-s1) (ss2:-s2) +	| dur1 == dur2 = (ss1,ss2) :- (cutEq' s1 s2)+	| dur1 <  dur2 = (ss1, takeSubSig dur1 ss2) +			 :- (cutEq' s1 ((dropSubSig dur1 ss2) :- s2))+	| dur1 >  dur2 = (takeSubSig dur2 ss1, ss2) +			 :- (cutEq' ((dropSubSig dur2 ss1) :- s1) s2)+        | otherwise = error ("cutEq' pattern match error: dur1="++(show dur1)+                             ++ ", dur2="++ (show dur2)++";")+	where dur1 = durationSS ss1+	      dur2 = durationSS ss2+    unzipCT :: Num a =>+               Signal ((SubsigCT a), (SubsigCT b)) +	    -> (Signal (SubsigCT a), Signal (SubsigCT b))+    unzipCT NullS = (NullS, NullS)+    unzipCT ((ss1,ss2) :- s) = (ss1:-s1, ss2:-s2)+	where (s1,s2) = unzipCT s++-- The take and drop functions on CT signals:+takeCT :: (Num a) => +          Rational -> Signal (SubsigCT a) -> Signal (SubsigCT a)+takeCT _ NullS = NullS+takeCT 0 _     = NullS+takeCT c (ss:-s) | (durationSS ss) >= c = (takeSubSig c ss) :- NullS+		 | otherwise        = ss :- (takeCT (c - (durationSS ss)) s)++dropCT :: (Num a) =>+          Rational -> Signal (SubsigCT a) -> Signal (SubsigCT a)+dropCT _ NullS   = NullS+dropCT 0 s       = s+dropCT c (ss:-s) | (durationSS ss > c) = dropSubSig c ss :- s+		 | otherwise           = dropCT (c - (durationSS ss)) s++-- The interval length of a signal:+duration :: (Num a) => Signal (SubsigCT a) -> Rational+duration NullS = 0+duration (ss:- s) = (durationSS ss) + (duration s)++-- The interval length of a sub-signal:+durationSS :: (Num a) => (SubsigCT a) -> Rational+durationSS (SubsigCT (_, (a,b))) = b-a++-- The start time of a signal:+startTime :: (Num a) => Signal (SubsigCT a) -> Rational+startTime NullS = 0+startTime (SubsigCT (_,(a,_)) :- _) = a++-- The take and drop functions for sub-signals:+takeSubSig :: (Num a) => Rational -> (SubsigCT a) -> (SubsigCT a)+takeSubSig c (SubsigCT (f,(a,b))) | c >= (b-a) = SubsigCT (f,(a,b))+                                  | otherwise  = SubsigCT (f,(a,a+c))+++dropSubSig :: (Num a) => Rational -> (SubsigCT a) -> (SubsigCT a)+dropSubSig c (SubsigCT (f,(a,b))) | c > (b-a) = SubsigCT (f,(b,b))+                                  | otherwise = SubsigCT (f,(a+c,b))++-----------------------------------------------------------------------+-- Functions to display and plot signals:+-----------------------------------------------------------------------+{- $plotdoc+   Several functions are available to display a signal in textual or +   graphics form. All displaying of signals is based on sampling and +   evaluation the signal at regular sampling points. ++   The function 'sample' evaluates the signal and returns a list of +   (time,value) pairs, which can be displayed as text or used in any other way.+   +   'showParts' does not evaluate the signal; it only shows how it is +   partitioned. Hence, it returns a sequence of intervals.+  +   'plot', 'plotCT' and 'plotCT'' can plot a signal or a list of signals +   in a graph. They use @gnuplot@ for doing the actual work.+   They are in the IO monad because they write to the file system.+  +   'plot' is defined in terms of 'plotCT' but it uses the default sampling +   period 'timeStep' and it can plot only one signal in a plot.+  +   'plotCT' can plot a list of signals in the same plot.+   'plotCT' is defined in terms of 'plotCT'' but uses +   default label names for the plot.++   'vcdGen' writes the values of signals in Value Change Dump (VCD) format to +   a file. There are public domain wave viewers which understand this format +   and can display the signals.+-}++-- |'sample' computes the values of a signal with a given step size. +-- It returns a list with (x, (f x)) pairs of type [(Rational,Rational)].+sample :: (Num a) =>+          Rational            -- ^ The sampling period+       -> Signal (SubsigCT a) -- ^The signal to be sampled+       -> [(Rational,a)]      -- ^The list of (time,value) pairs of the +                              -- evaluated signal+sample _ NullS = []+sample step (ss :- s) = sampleSubsig step ss ++ (sample step s)++-- sampleSubsig samples a Subsig signal:+sampleSubsig :: (Num a) => Rational -> (SubsigCT  a) -> [(Rational,a)]+sampleSubsig step (SubsigCT (f,(a,b)))+    | b>a = (a,(f a)) : (sampleSubsig step (SubsigCT (f,(a+step,b))))+    | otherwise = []++-- |'showParts' allows to see how a signal is partitioned into sub-signals.+-- It returns the sequence of intervals.+showParts :: (Num a) =>+             Signal (SubsigCT a)   -- ^The partitioned signal+          -> [(Double,Double)] -- ^The sequence of intervals+showParts NullS = []+showParts (SubsigCT (_,(a,b)):-s) = (fromRational a,fromRational b) +                                     : (showParts s)++-----------------------------------------------------------------------------+-- |'plot' plots one signal in a graph with the default sampling period +-- of 1\/200 of the duration of the signal.+plot :: (Num a) =>+        Signal (SubsigCT a) -- ^The signal to be plotted.+     -> IO String          -- ^A reporting message.+plot s = plotCT step [s]+    where step = (duration s) / 200.0++-- |'plotCT' plots a list of signals in the same graph. The sampling period +-- has to be given as argument. In the graph default label names are used+-- to identify the signals.+plotCT :: (Num a) =>+          Rational              -- ^The sampling period+       -> [Signal (SubsigCT a)] -- ^The list of signals to be ploted +                                -- in the same graph+       -> IO String             -- ^A messeage reporting what has been done.+plotCT step sigs = plotCT' step (map (\ s -> (s,"")) sigs)++{- |+   'plotCT'' is the work horse for plotting and the functions 'plot' and +   'plotCT' use it with specialising arguments.++   'plotCT'' plots all the signals in the list in one graph. If a label is+   given for a signal, this label appears in the graph. If the label string is +   \"\", a default label like \"sig-1\"  is used.++   In addition to displaying the graph on the screen, the following files+   are created in directory .\/fig:++   [ct-moc-graph.eps]          an eps file of the complete graph++   [ct-moc-graph.pdf]          A pdf file of the complete graph+ +   [ct-moc-graph-latex.eps]    included by ct-moc-graph-latex.tex++   [ct-moc-graph-latex.tex]    This is the tex file that should be included+                               by your latex document. It in turn includes+ 			       the file ct-moc-graph-latex.eps.+			       These two files have to be used together;+ 			       the .eps file contains only the graphics,+			       while the .tex file contains the labels and +                               text.+-}+plotCT' :: (Num a) =>+           Rational             -- ^Sampling period+        -> [(Signal (SubsigCT a), String)]+           -- ^A list of (signal,label) pairs. The signals are plotted and+           -- denoted by the corresponding labels in the plot.+        -> IO String             -- ^A simple message to report completion+plotCT' _ [] = return []+plotCT' 0 _        = error "plotCT: Cannot compute signal with step=0.\n"+plotCT' step sigs = plotSig (expandSig 1 sigs)+    where +      expandSig :: (Num a ) => +                   Int -> [(Signal (SubsigCT a),String)] +                       -> [(Int,String,[(Rational,a)])]+      expandSig _ [] = []+      expandSig i ((sig,label):sigs) +          = (i, label, (sample step sig)) : (expandSig (i+1) sigs)+      plotSig :: (Num a) => [(Int,String,[(Rational,a)])] -> IO String+      plotSig sigs +          = do mkDir "./fig"+               writeDatFiles sigs+               -- We write the gnuplot script to a file;+               -- But we try several times with a different name because +               -- with ghc on cygwin we cannot write to a script file while+               -- gnuplot is still running with the old script file:+               fname <- tryNTimes 10 +                        (\ file -> (writeFile file+                                    (mkPlotScript (map mkDatFileName sigs))))+               -- We fire up gnuplot:+               system ("gnuplot -persist " ++ fname)+               -- We return some reporting string:+               return ("Signal(s) " ++(mkAllLabels sigs) ++ " plotted.")+      writeDatFiles [] = return ()+      writeDatFiles (s@(_, _, sig): sigs) +          = do writeFile (fst (mkDatFileName s)) (dumpSig sig)+               writeDatFiles sigs+      mkDatFileName :: (Int,String,a) -> (String,String)+      mkDatFileName (sigid,label,_) = ("./fig/ct-moc-" ++ (replChar ">" label) +                                       ++(show sigid)++".dat", +                                             (mkLabel label sigid))+      mkLabel :: String -> Int -> String+      mkLabel "" n = "sig-" ++ show n +      mkLabel l _  = l+      mkAllLabels :: (Num a) => [(Int,String,[(Rational,a)])] -> String+      mkAllLabels sigs = drop 2 (foldl f "" sigs)+          where f labelString (n,label,_) +                    = labelString ++ ", " ++ (mkLabel label n)+      replChar :: String -- all characters given in this set are replaced by '_'+               -> String -- the string where characters are replaced+               -> String -- the result string with all characters replaced+      replChar [] s = s+      replChar _ [] = []+      replChar replSet (c:s) | elem c replSet = '_' : (replChar replSet s)+                             | otherwise      = c   : (replChar replSet s)+      dumpSig :: (Num a) => [(Rational,a)] -> String+      dumpSig points = concatMap f points+        where f (x,y) = show ((fromRational x) :: Float) ++ "    " +                        ++ show (y) ++ "\n"++      mkPlotScript :: [(String  -- the file name of the dat file+                       ,String  -- the label for the signal to be drawn+                       )] -> String  -- the gnuplot script+      mkPlotScript ns = "set xlabel \"seconds\" \n"+                        ++ "plot " ++ (f1 ns) ++ "\n"+                        ++ "set terminal postscript eps color\n"+                        ++ "set output \"" ++ plotFileName++".eps\"\n"+                        ++ "replot \n"+                        ++ "set terminal epslatex color\n"+                        ++ "set output \"" ++ plotFileName++"-latex.eps\"\n"+                        ++ "replot\n"+                            -- ++ "set terminal pdf\n"+                            -- ++ "set output \"fig/ct-moc-graph.pdf\"\n"+                            -- ++ "replot\n"+          where f1 :: [(String,String)] -> String+                f1 ((datfilename,label):(n:ns)) +                    = "\t\"" ++ datfilename+                      ++ "\" with linespoints title \""++label++"\",\\\n"+                       ++ "    " ++ (f1 (n:ns))+                f1 ((datfilename,label):[]) +                    = "\"" ++ datfilename +                       ++ "\" with linespoints title \""++label++"\"\n"+                f1 [] = ""+                plotFileName = "fig/ct-moc-graph-" ++ (f2 ns)+                f2 :: [(String,String)] -> String -- f2 generates part of the +                                                  -- filename for the eps and +                                                  -- latex files, which is +                                                  -- determined by the signal+                                                  -- labels.+                f2 [] = ""+                f2 ((_,label):[]) = label+                f2 ((_,label):_) = label ++ "_"+      -- tryNTimes applies a given actions at most n times. Everytime+      -- the action is applied and an error occurrs, it tries again but +      -- with a decremented first argument. It also changes the file name+      -- because the file name uses the n as part of the name.+      -- The idea is that the action tries different files to operate on.+      -- The problem was that when gnuplot was called on a gnuplot script+      -- file, it was not possible to write a new script file with the same+      -- name and start a new gnuplot process (at least not with ghc or ghci on +      -- cygwin; it worked fine with hugs on cygwin). +      -- So we go around the problem here by trying different file names until+      -- we succeed or until the maximum number of attempts have been performed.+      tryNTimes :: Int -> (String -> IO ()) -> IO String+      tryNTimes n a | n <= 0 = error "tryNTimes: not succedded"+                    | n > 0 = +                        do catch (action fname a) (handler a)+          where handler :: (String -> IO()) -> IOError -> IO String+                handler a _ = tryNTimes (n-1) a+                fname = "./fig/ct-moc-" ++ (show n) ++ ".gnuplot"+                action :: String -> (String -> IO ()) -> IO String+                action fname a = do (a fname)+                                    return fname+      tryNTimes _ _ = error "tryNTimes: Unexpected pattern."++----------------------------------------------------------------------------+{- |+vcdGen dumps the values of a list of signal in VCD (Value Change Dump) format +(IEEE Std 1364-2001), which is part of the Verilog standard +(<http://en.wikipedia.org/wiki/Value_change_dump>).+There are public domain tools to view VCD files. For instance, +GTKWave (<http://home.nc.rr.com/gtkwave/>) is a popular viewer available for+Windows and Linux.++The values are written to the file ./fig/ct-moc.vcd. If the file exists, it+is overwritten. If the directory does not exist, it is created.++-}+vcdGen :: (Num a) +          => Rational             -- ^Sampling period; defines for what+                                  -- time stamps the values are written.+              -> [(Signal (SubsigCT a), String)]+              -- ^A list of (signal,label) pairs. The signal values written and+              -- denoted by the corresponding labels.+              -> IO String        -- ^A simple message to report completion+vcdGen _ [] = return []+vcdGen 0    _  = error "vcdgen: Cannot compute signals with step=0.\n"+vcdGen step sigs = +    do +      -- putStr (show (distLabels (expandSig 1 sigs)))+      plotSig (expandSig 1 sigs)+    where +      expandSig :: (Num a ) => +                   Int -> [(Signal (SubsigCT a),String)] +                       -> [(Int,String,[(Rational,a)])]+      expandSig _ [] = []+      expandSig i ((sig,label):sigs) +          = (i, label, (sample step sig)) : (expandSig (i+1) sigs)+      plotSig :: (Num a) => [(Int,String,[(Rational,a)])] -> IO String+      plotSig sigs +          = do writeVCDFile sigs+               -- We return some reporting string:+               return ("Signal(s) " ++(mkAllLabels sigs) ++ " dumped.")+      mkLabel :: String -> Int -> String+      mkLabel "" n = "sig-" ++ show n +      mkLabel l _  = l+      mkAllLabels sigs = drop 2 (foldl f "" sigs)+          where f labelString (n,label,_) +                    = labelString ++ ", " ++ (mkLabel label n)+      writeVCDFile :: (Show a) => [(Int,String,[(Rational,a)])] -> IO()+      writeVCDFile sigs+          = do +               mkDir "./fig"+               clocktime <- getClockTime+               let {date = calendarTimeToString (toUTCTime clocktime);+                    labels = getLabels sigs;+                    timescale = findTimescale sigs;}+                   in writeFile mkVCDFileName+                          ((vcdHeader timescale labels date)+                           ++ (valueDump timescale (prepSigValues sigs)))+      mkVCDFileName :: String+      mkVCDFileName = ("./fig/ct-moc.vcd")++mkDir :: String -> IO()+mkDir dir = do dirExists <- doesDirectoryExist dir+               if (not dirExists) +                  then (createDirectory dir) +                  else return ()++-- prepSigValues rearranges the [(label,[(time,value)])] lists such +-- that we get a list of time time stamps and for each time stamp +-- we have a list of (label,value) pairs to be dumped:+prepSigValues :: (Show a) => [(Int,String,[(Rational,a)])]+              -> [(Rational,[(String,a)])]+prepSigValues sigs = f2 (distLabels sigs)+    where +      -- f2 transforms a [[(label,time,value)]] +      -- into a [(time, [label,value])] structure:+      f2 :: (Show a) +            => [[(String,Rational,a)]] -> [(Rational,[(String,a)])]+      f2 [] = []+      f2 ([]:_) = []  +      f2 xs = f3 hdxs : f2 tailxs+          where +            -- here we take all first elements of the lists in xs+            -- and the tail of the lists in xs:+            (hdxs,tailxs) = (map g1 xs,+                             map (\ (_:ys)-> ys) xs)+            g1 [] = error ("prepSig.f2.g1: first element of xs is empty:"+                           ++ "xs="++show xs)+            g1 (y:_) = y+            f3 :: (Show a) +                  => [(String,Rational,a)] -> (Rational,[(String,a)])+            f3 (valList@((_, time, _):_)) = (time, f4 time valList)+            f3 [] = error ("prepSigValues.f2.f3: "+                           ++ "empty (label,time,value)-list")+            f4 :: (Show a) +                  => Rational -> [(String,Rational,a)] -> [(String,a)]+            f4 _ [] = []+            f4 time ((label,time1,value):valList) +               | time == time1 = (label,value) : f4 time valList+               | otherwise +                   = error ("prepSigValues: Time stamps in different"+                            ++ " signals do not match: time="+                            ++(show time)++", time1="++(show time1)+                            ++", label="++label++", value="++(show value)+                            ++"!")+-- distLabels inserts the labels into its corresponding +-- (time,value) pair list to get a (label,time,value) triple:+distLabels :: [(Int,String,[(Rational,a)])] +           -> [[(String,Rational,a)]]+distLabels [] = []+distLabels ((_,label,valList):sigs) +    = (map (\ (t,v) -> (label,t,v)) valList) : (distLabels sigs)+getLabels :: [(Int,String,[(Rational,a)])] -> [String]+getLabels = map (\(_,label,_)-> label)+vcdHeader :: Rational -> [String] -> String -> String+vcdHeader timescale labels date = "$date\n"+                       ++ date ++ "\n"+                       ++ "$end\n"+                       ++ "$version\n"+                       ++ "ForSyDe CTLib " ++ revision ++ "\n"+                       ++ "$end\n"+                       ++ "$timescale 1 " ++ (timeunit timescale) ++ " $end\n"+                       ++ "$scope module top $end\n"+                       ++ (concatMap (\ label -> ("$var real 64 "++label+                                                  ++ " " ++ label +                                                  ++ " $end\n")) labels)+                       ++ "$upscope $end\n"+                       ++ "$enddefinitions $end\n"+                       ++ "#0\n"+                       ++ "$dumpvars\n"+                       ++ (concatMap (\ label -> "r0.0 "++label++ "\n") +                                     labels)+                       ++ "\n"+valueDump :: (Show a) => Rational -> [(Rational,[(String,a)])] -> String+valueDump _ [] = ""+valueDump timescale ((t,values):valList) +    = "#"++(show (g (t/timescale)))++"\n" +      ++ (f values) ++ (valueDump timescale valList)+    where +      f :: (Show a) => [(String,a)] -> String+      f [] = ""+      f ((l,v):values) = "r"++(show v)++" "++l++"\n" ++ (f values)+      g :: Rational -> Integer+      -- Since the VCD format expects integers for the timestamp, we make+      -- sure that only an integer is printed in decimal format (no exponent):+      g t = round t+++timeunit :: Rational -> String+timeunit timescale | timescale == 1 % 1    = "s"+                   | timescale == 1 % 1000 = "ms"+                   | timescale == 1 % 1000000 = "us"+                   | timescale == 1 % 1000000000 = "ns"+                   | timescale == 1 % 1000000000000 = "ps"+                   | timescale == 1 % 1000000000000000 = "fs"+                   | otherwise = error ("timeunit: unexpected timescale: "+                                        ++ (show timescale))++findTimescale :: [(Int,String,[(Rational,a)])] -> Rational+findTimescale sigs +    = f 1 (concatMap (\ (_,_,valList) -> (fst (unzip valList))) sigs)+      where +        f :: Rational -> [Rational] -> Rational+        f scale [] = scale+        f scale (x:xs) | r == 0    = f scale xs+                       | otherwise = f (scale/1000) xs+                       where (_,r) = (properFraction (abs (x / scale))) +                                      :: (Int,Rational)++-------------------------------------------------------------------------+-----------------------------------------------------------+-- Testing the CT signals and process constructors:++{--+main = testAll+testAll = +    do +      testScaleCT +      testAddCT +      testMultCT +      testAbsCT +      testDelayCT+      testConverters+      testFeedback+-- test scaleCT:+testScaleCT = plotCT' 1E-4 [(toneA, "Tone A"), +                            ((scaleCT 1.5 toneA), "Tone A x 1.5"),+                            ((scaleCT 2.0 toneA), "Tone A x 2.0")]++-- test addCT:+testAddCT = plotCT' 1e-4 [(toneA, "Tone A"),+                          (toneE, "Tone E"), +                          ((addCT toneA toneE), "Tones A+E")]++-- test multCT:+testMultCT = plotCT' 1e-4 [(toneA, "Tone A"),+                          (toneE, "Tone E"), +                          ((multCT toneA toneE), "Tones A x E")]++-- test absCT:+testAbsCT = plotCT' 1E-4 [(toneA, "Tone A"), +                          ((absCT toneA), "abs (Tone A)")]++-- test delayCT:+testDelayCT = plotCT' 1E-4 +              [(toneA, "Tone A"), +               (takeCT 0.02 ((delayCT 0.0025 toneA)), +                           "Tone A delayed by 2.5ms"),+               (takeCT 0.02 ((shiftCT 0.003 toneA)), "Tone A shifted by 3ms")]++-- test a2dConverter:+testConverters = +    do (plotCT' 1e-4+        [(toneA, "Tone A"),+         (d2aConverter DAlinear 1e-3 (a2dConverter 1e-3 toneA),+          "Tone A (A->D->A) converted with linear mode, 1ms sampling period")])+       (plotCT' 1e-4+        [(toneA, "Tone A"),+         (d2aConverter DAhold 1e-3 (a2dConverter 1e-3 toneA),+          "Tone A (A->D->A) converted with hold mode, 1ms sampling period")])++-- test a feed back loop:+block sin = [sin,s1,s2,sout]+    where sout = p2 s1+          s1 = p1 sin s2+          s2 = p3 sout+          -- The individual processes:+          p1 :: Signal (SubsigCT Double) -> Signal (SubsigCT Double)+             -> Signal (SubsigCT Double)+          p2,p3 :: Signal (SubsigCT Double) -> Signal (SubsigCT Double)+          p1 = addCT+          p2 = scaleCT 0.5+          p3 = initCT (zeroCT 0.0005)+testFeedback = plotCT' 0.0001 ss+    where ss = [(sin, "sin"), (s1, "s1"), (s2, "s2"), (sout, "sout")]+          [sin,s1,s2,sout] = block (takeCT 0.005 toneA)++++toneA = sineWave (440.0) (0, 0.02)+toneE = sineWave 520.0 (0, 0.02)+-}++{- Some performance tests on my laptop under cygwin:++***********************************************************************+With ghc:++with +toneA = sineWave (440.0) (0, 2.0)+toneE = sineWave 520.0 (0, 2.0)++****+we make testAll with Double data types on++ghc --make CTLib.hs -O3 -o ttt.exe+time ttt+   +real    0m33.749s+user    0m0.010s+sys     0m0.010s++****+we make testAll with Rational data types on++ghc --make CTLib.hs -O3 -o ttt.exe+time ttt+   +real    0m53.687s+user    0m0.010s+sys     0m0.010s++****+hence the performance penalty when using Rational instead of Double is+1.59 (60%) longer delay.+++************************************************************************+On hugs: (when using 0.2 second long waves, hugs aborted with an out of memory +message both with Double and Rational; but with Double it aborted much faster;)++toneA = sineWave (440.0) (0, 0.02)+toneE = sineWave 520.0 (0, 0.02)++****************+**** with Double:+time runhugs.exe -h500k CTLib.hs++real    0m1.702s+user    0m0.020s+sys     0m0.010s++******************+**** with Rational:++time runhugs.exe -h500k CTLib.hs++real    0m21.501s+user    0m0.010s+sys     0m0.020s++****************+hence we have a factor of 12.5 longer delay with Rational compared to Double.+++-}
+ src/ForSyDe/Shallow/CoreLib.hs view
@@ -0,0 +1,37 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde@kth.se+-- Stability   :  experimental+-- Portability :  portable +-- +-- The CoreLib is the base for all MoC libraries and is a container+-- that includes the following libraries:+-- +-- * "ForSyDe.Shallow.Signal"+-- +-- * "ForSyDe.Shallow.Vector"+-- +-- * "ForSyDe.Shallow.AbsentExt" +-----------------------------------------------------------------------------++module ForSyDe.Shallow.CoreLib(  +			module ForSyDe.Shallow.Signal,+			module ForSyDe.Shallow.Vector,+			module ForSyDe.Shallow.AbsentExt+		    ) where++import ForSyDe.Shallow.Vector+import ForSyDe.Shallow.Signal+import ForSyDe.Shallow.AbsentExt++++++++
+ src/ForSyDe/Shallow/DFT.hs view
@@ -0,0 +1,71 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.DFT+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module includes the standard Discrete Fourier Transform (DFT)+-- function, and a fast Fourier transform (FFT) algorithm, for+-- computing the DFT, when the input vectors' length is a power of 2.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.DFT(dft, fft) where++import ForSyDe.Shallow.Vector+import Data.Complex++-- | The function 'dft' performs a standard Discrete Fourier Transformation+dft :: Int -> Vector (Complex Double) -> Vector (Complex Double)+dft bigN x | bigN == (lengthV x) = mapV (bigX_k bigN x) (nVector x)+	   | otherwise = error "DFT: Vector has not the right size!"   +   where+     nVector x'       = iterateV (lengthV x') (+1) 0+     bigX_k bigN' x' k = sumV (zipWithV (*) x' (bigW' k bigN'))+     bigW' k' bigN'     = mapV (** k') (mapV cis (fullcircle bigN'))+     sumV            = foldlV (+) (0:+ 0)++fullcircle :: Int -> Vector Double +fullcircle n = fullcircle1 0 (fromIntegral n) n+	  where+	     fullcircle1 l m n' +		| l == m    = NullV+		| otherwise = -2*pi*l/(fromIntegral n') +			      :> fullcircle1 (l+1) m n' ++-- | The function 'fft' implements a fast Fourier transform (FFT) algorithm, for computing the DFT, when the size N is a power of 2.+fft :: Int -> Vector (Complex Double) -> Vector (Complex Double)+fft bigN xv | bigN == (lengthV xv) = mapV (bigX xv) (kVector bigN)+	    | otherwise = error "FFT: Vector has not the right size!"++kVector :: (Num b, Num a) => a -> Vector b      +kVector bigN = iterateV bigN (+1) 0 +++bigX :: Vector (Complex Double) -> Int -> Complex Double+bigX (x0:>x1:>NullV) k | even k = x0 + x1 * bigW 2 0+		       | odd k  = x0 - x1 * bigW 2 0+bigX xv k = bigF_even k + bigF_odd k * bigW bigN (fromIntegral k)+     where bigF_even k' = bigX (evens xv) k'+	   bigF_odd k' = bigX (odds xv) k'+	   bigN = lengthV xv++bigW :: Int -> Int -> Complex Double+bigW bigN k = cis (-2 * pi * (fromIntegral k) / (fromIntegral bigN))++evens :: Vector a -> Vector a+evens NullV       = NullV+evens (v1:>NullV) = v1 :> NullV+evens (v1:>_:>v)  = v1 :> evens v++odds :: Vector a -> Vector a+odds NullV        = NullV+odds (_:>NullV)   = NullV+odds (_:>v2:>v)   = v2 :> odds v+++++
+ src/ForSyDe/Shallow/DomainInterfaces.hs view
@@ -0,0 +1,130 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.DomainInterfaces+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module defines domain interface constructors for the multi-rate computational +-- model.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.DomainInterfaces(downDI, upDI, par2serxDI, ser2parxDI, +			par2ser2DI, par2ser3DI, par2ser4DI, +			ser2par2DI, ser2par3DI, ser2par4DI) where++import ForSyDe.Shallow.CoreLib+import ForSyDe.Shallow.SynchronousLib+++-- | The domain interface constructor 'downDI' takes a parameter 'k' and downsamples an input signal.+downDI     :: Num a => a -> Signal b -> Signal b++-- | The domain interface constructors 'upDI' takes a parameter 'k' and upsamples an input signal.+upDI       :: Num a => a -> Signal b -> Signal (AbstExt b)++-- | The domain interface constructor 'par2ser2DI' converts two parallel signals into one signal.+par2ser2DI :: Signal a -> Signal a -> Signal a++-- | The domain interface constructor 'par2ser3DI' converts three parallel signals into one signal+par2ser3DI :: Signal a -> Signal a -> Signal a -> Signal a++-- | The domain interface constructor 'par2ser4DI' converts four parallel signals into one signal+par2ser4DI :: Signal a -> Signal a -> Signal a -> Signal a +	   -> Signal a+++-- | The domain interface constructor 'par2serxDI' converts n parallel signals into one signal.+par2serxDI :: Vector (Signal a) -> Signal a++-- | The domain interface constructor 'ser2par2DI' converts one signal into two parallel signals.+ser2par2DI :: Signal a -> (Signal (AbstExt a), Signal (AbstExt a))++-- | The domain interface constructor 'ser2par3DI' converts one signal into three parallel signals.+ser2par3DI :: Signal a -> (Signal (AbstExt a), Signal (AbstExt a), Signal (AbstExt a))++-- | The domain interface constructor 'ser2par4DI' converts one signal into four parallel signals.+ser2par4DI :: Signal a +	   -> (Signal (AbstExt a), Signal (AbstExt a), +               Signal (AbstExt a), Signal (AbstExt a))++-- | The domain interface constructors 'ser2parxDI' converts one signal into n parallel signals.+ser2parxDI :: (Num a, Ord a) => a -> Signal (AbstExt b) +				  -> Vector (Signal (AbstExt b))++-- Implementation++downDI n xs     = down1 n 1 xs +  where down1 _ _ NullS   = NullS+	down1 1 1 (x:-xs) = x :- down1 1 1 xs+	down1 n 1 (x:-xs) = x :- down1 n 2 xs+	down1 n m (_:-xs) = if m == n then+			       down1 n 1 xs+			    else+			       down1 n (m+1) xs ++upDI _ NullS   = NullS+upDI n (x:-xs) = (Prst x) :- ((copyS (n-1) Abst) +-+ upDI n xs)++par2ser2DI xs ys  = par2ser2DI' (zipSY xs ys)+  where par2ser2DI' NullS = NullS+	par2ser2DI' ((x,y):-xys) = x:-y:-par2ser2DI' xys++par2ser3DI xs ys zs = par2ser3DI' (zip3SY xs ys zs)+  where par2ser3DI' NullS = NullS+	par2ser3DI' ((x,y,z):-xyzs) = x:- y :-z :- par2ser3DI' xyzs++par2ser4DI ws xs ys zs = par2ser4DI' (zip4SY ws xs ys zs)+  where par2ser4DI' NullS = NullS+        par2ser4DI' ((w,x,y,z):-wxyzs) +            = w:-x:-y:-z:- par2ser4DI' wxyzs++ser2par2DI = unzipSY . group2SY . delaynSY Abst 2 . mapSY abstExt++ser2par3DI = unzip3SY . group3SY . delaynSY Abst 3 . mapSY abstExt++ser2par4DI = unzip4SY . group4SY . delaynSY Abst 4 . mapSY abstExt+++par2serxDI = par2serxDI' . zipxSY +  where par2serxDI' NullS    = NullS+	par2serxDI' (xv:-xs) = (signal . fromVector) xv +			          +-+ par2serxDI' xs ++ser2parxDI n = unzipxSY . delaySY (copyV n Abst) +			. filterAbstDI . group n++group2SY :: Signal t -> Signal (t, t)+group2SY NullS = NullS+group2SY (_:-NullS) = NullS+group2SY (x:-y:-xys) = (x, y) :- group2SY xys++group3SY :: Signal t -> Signal (t, t, t)+group3SY NullS = NullS+group3SY (_:-NullS) = NullS+group3SY (_:-_:-NullS) = NullS+group3SY (x:-y:-z:-xyzs) = (x, y, z) :- group3SY xyzs++group4SY :: Signal t -> Signal (t, t, t, t)+group4SY NullS = NullS+group4SY (_:-NullS) = NullS+group4SY (_:-_:-NullS) = NullS+group4SY (_:-_:-_:-NullS) = NullS+group4SY (w:-x:-y:-z:-wxyzs) = (w, x, y, z) :- group4SY wxyzs +++filterAbstDI :: Signal (AbstExt a) -> Signal a+filterAbstDI NullS          = NullS+filterAbstDI (Abst:-xs)     = filterAbstDI xs+filterAbstDI ((Prst x):-xs) = x :- filterAbstDI xs++group :: (Ord a, Num a) => a -> Signal a1 -> Signal (AbstExt (Vector a1))+group n xs = mapSY (output n) (scanlSY (addElement n)  (NullV, 0) xs)+	       where addElement m (vs, n) x | n < m  = (vs <: x, n+1)+      				            | n == m = (unitV x, 1)+                                            | otherwise = error "Vector of wrong size"+ 		     output m (vs, n) | m == n = Prst vs+				      | otherwise = Abst+
+ src/ForSyDe/Shallow/FIR.hs view
@@ -0,0 +1,36 @@+----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.FIR+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module implements a FIR filters for the synchronous computational model.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.FIR (firSY) where++import ForSyDe.Shallow.SynchronousLib+import ForSyDe.Shallow.CoreLib++-- | The function firSY implements a FIR-filter for the synchronous computational model. All kinds of FIR-filters can now be modeled by means of 'firSY'. The only argument needed is the list of coefficients, which is given as a vector of any size. To illustrate this, an 8-th order band pass filter is modeled as follows. +--+-- > bp = firSY (vector [0.06318761339784, 0.08131651217682, 0.09562326700432, +-- >                     0.10478344432968, 0.10793629404886, 0.10478344432968, +-- >                     0.09562326700432, 0.08131651217682, 0.06318761339784 ])+-- +firSY :: Fractional a => Vector a -> Signal a -> Signal a+firSY h = innerProdSY h . sipoSY k 0.0+    where k = lengthV h++sipoSY :: Int -> b -> Signal b -> Vector (Signal b) +sipoSY n s0 = unzipxSY . scanldSY shiftrV initState+    where initState = copyV n s0++innerProdSY :: (Num a) => Vector a -> Vector (Signal a) -> Signal a+innerProdSY coeffs = zipWithxSY (ipV coeffs)+   where ipV NullV   NullV   = 0+	 ipV (h:>hv) (x:>xv) = h*x + ipV hv xv+         ipV _       _       = error "Vector of different length"
+ src/ForSyDe/Shallow/FilterLib.hs view
@@ -0,0 +1,314 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.FilterLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This is the filter library for ForSyDe heterogeneous MoCs - CT-MoC, SR-MoC,+-- and Untimed-MoC.+--+-- The filters at CT-MoC are based on the filters implemented at SR-MoC and Untimed-MoC, +-- which means a signal in CT-MoC is always digitalized by a A\/D converter, processed by +-- digital filters at SR or Untimed domain, and converted back into a CT domain signal by +-- a D\/A converter. A CT-filter is composed of one A\/D converter, one digital filter, and +-- one D\/A converter.+--+-- The implementation of the filters at untimed and synchronous domains follows the+-- way in a paper /An introduction to Haskell with applications to digital signal processing, +-- David M. Goblirsch, in Proceedings of the 1994 ACM symposium on Applied computing./,+-- where the details of the FIR\/IIR, AR, and ARMA filters are introduced. The ARMA filter+-- is the kernel part of our general linear filter 'zLinearFilter' in Z-domain at SR\/Untimed+-- MoC, and is also the kernel digital filter for the linear filter 'sLinearFilter' in +-- S-domain at CT-MoC.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.FilterLib (+              -- *FIR filter+              firFilter,+              -- *AR and ARMA filter trim+              arFilterTrim, armaFilterTrim,+              -- *The solver mode+              SolverMode(..),+              -- *The general linear filter in S-domain+              sLinearFilter,+              -- *The general linear filter in Z-domain+              zLinearFilter,+              -- *s2z domain coefficient tranformation+              s2zCoef,+              -- *The Z-domain to ARMA coefficient tranformation+              h2ARMACoef+             )+    where ++import ForSyDe.Shallow.MoCLib+--import ForSyDe.Shallow.CTLib+import ForSyDe.Shallow.CoreLib+import ForSyDe.Shallow.PolyArith+import Data.List (zipWith5)+import Control.Monad.Instances () -- Monad instance for (-> r)++-- |The FIR filter. Let '[x_n]' denote the input signal, '[y_n]' denote the ouput+-- signal, and '[h_n]' the impulse response of the filter. Suppose the length of+-- the impulse responses is M samples. The formula for '[y_n]' is +-- $sum_{k=0}^{M-1} h_k*x_{n-k}$.+firFilter :: (Num a) => [a]      -- ^Coefficients of the FIR filter+                     -> Signal a -- ^Input signal+                     -> Signal a -- ^Output signal+firFilter hs xs = mealySY stateF (outF hs) (repeatN (length hs) 0) xs+  where+    stateF xs0 x = fixedList xs0 x+    outF hs xs0 x = iprod hs $ fixedList xs0 x++-- |The autoregressive filter is the simplest IIR filter. It is characterized +-- by a list of numbers '[a_1,a_2,...,a_M]' called the autoregression +-- coefficients and a single number 'b' called the gain. 'M' is the order of +-- the filter. Let '[x_n]' denote the input signal, '[y_n]' denote the ouput+-- signal. The formula for '[y_n]' is  $\sum_{k=1}^M {a_k*y_{n-k}+b*x_n}$. +-- Although it is an IIR filter, here we only get the same length of ouput +-- signal as the input signal.+arFilterTrim :: (Num a, Fractional a) => +                           [a]       -- ^Coefficients of the AR filter.+                         -> a        -- ^The gain+                         -> Signal a -- ^Input signal+                         -> Signal a -- ^Output signal+arFilterTrim as b xs = +    mealySY (stateF as b) (outF as b) (repeatN (length as) 0) xs+  where+    stateF as b xs0 x = fixedList xs0 $ outF as b xs0 x +    outF as b xs0 x = b*x + (iprod as xs0)++-- |The ARMA filter combines the FIR and AR filters. Let '[x_n]' denote the +-- input signal, '[y_n]' denote the ouput signal. The formula for '[y_n]' is+--  $\sum_{k=1}^M {a_k*y_{n-k}+b*x_n} + sum_{i=0}^{N-1} b_i*x_{n-i}$. The ARMA+-- filter can be defined as the composition of an FIR filter having the impulse+-- reponse '[b_0,b_1,...,b_N-1]' and an AR filter having the regression +-- coefficients '[a_1,a_2,...,a_M]' and a gain of '1'. Although it is an IIR +-- filter, here we only get the same length of ouput signal as the input signal.+armaFilterTrim :: (Num a, Fractional a) => +                             [a]      -- ^Coefficients of the FIR filter+                          -> [a]      -- ^Coefficients of the AR filter.+                          -> Signal a -- ^Input signal+                          -> Signal a -- ^Output signal+armaFilterTrim bs as = arFilterTrim as 1 . firFilter bs+++-- |The solver mode.+data SolverMode = S2Z   -- ^Tustin tranfer from s-domain to z-domain+                | RK4   -- ^Runge Kutta 4 with fixed simulation steps+  deriving (Show, Eq)++-- |The general linear filter in S-domain at CT-MoC. As the kernel+-- implementation is in Z-domain, the smapling rate should be specified. +-- It is used on the S-transformation with the following forms, with +-- coefficients for the descending powers of 's' and m < n.+--+-- >        b_0*s^m + b_1*s^m-1 + ... + b_m-1*s^1 + b_m*s^0+-- >H(s) = ------------------------------------------------         (Eq 1)+-- >        a_0*s^n + a_1*s^n-1 + ... + a_n-1*s^1 + a_n*s^0+--+-- If we multiply both the numerator and the denominator with s^-n, we get +-- another equivelent canonical form+--+-- >        b_0*s^m-n + b_1*s^m-n-1 + ... + b_m-1*s^1-n + b_m*s^-n+-- >H(s) = -----------------------------------------------------    (Eq 2)+-- >        a_0*s^0 + a_1*s^-1 + ... + a_n-1*s^1-n + a_n*s^-n+--+-- To instantiate a filter, with sampling interval 'T ', we use+--+-- > filter1 = sLinearFilter T [1] [2,1]+-- +-- to get a filter  with the transfer function+-- +-- >          1+-- >H(s) = --------+-- >       2*s + 1+-- +-- and+--+-- > filter2 = sLinearFilter T [2,1] [1,2,2]+--+-- to get another filter with the transfer function+-- +-- >           2*s +1+-- >H(s) = ----------------+-- >        s^2 + 2*s + 2+--+-- There are two solver modes, 'S2Z' and 'RK4'.+-- Caused by the precision problem, the time interval in CT uses Rational data+-- type and the digital data types in all the domains are Double.+sLinearFilter :: (Num a, Fractional a) =>+        SolverMode   -- ^Specify the solver mode+    ->  Rational     -- ^Fixed simulation interval+    -> [a]  -- ^Coefficients of the polynomial numerator in s-domain+    -> [a]  -- ^Coefficients of the polynomial denominator in s-domain+    -> Signal (SubsigCT a)-- ^Input CT-signal+    -> Signal (SubsigCT a)-- ^Output CT-signal+sLinearFilter filterMode step bs as inS =  outS +  where+    -- A2D conversion+    inSDigital = a2dConverter step inS+    -- D2A conversion+    outS =  d2aConverter DAhold step outSDigital+    -- Digital filter+    outSDigital | filterMode == S2Z = armaFilterTrim bs' as' inSDigital+                | otherwise =  rk4FilterDigital step as bs inSDigital+                      where (bs',as') = h2ARMACoef $ s2zCoef step bs as++-- |Digital filter using Runge Kutta 4 solver.+rk4FilterDigital :: Fractional a => +                    Rational -> [a] -> [a] -> Signal a -> Signal a+rk4FilterDigital step as bs inSDigital = outSDigital+  where+    -- Below are the skeletons of the RK-4 solver, with+    -- input signal 'inSDigital' and output signal 'outSDigital'+    -- Coefficients handling+    as'' = dropWhile (\x -> x==0.0) as+    a0 = head as''+    -- Normalized the coefficients+    as' = reverse $ tail $ map (\x -> -x/a0) as''+    bs' = reverse $ map (\x -> x/a0) bs+    -- Order of the filter+    orderFilter = length as'+    -- The last state function, '0' is for the time +    fXn = iprod (0:as')+    -- The functions for the observalbe state matrix 'A'+    stateFunctions = ffn' orderFilter ++ [fXn]+    -- Initial states+    initialStates = repeatN orderFilter 0.0+    inputSteps = signal $ repeat step'+    -- The states signal+    statesSignal = rks4InSY 0.0 initialStates stateFunctions +                             inputSteps inSDigital --xs+    -- The ouput digital signal +    outSDigital = mapSY (iprod bs') statesSignal+    -- The fixed simulation step+    step' = fromRational step++-- The length of the function list is 'n-1' for nth order filter+ffn' :: (Num t, Num t1) => t -> [[t1] -> t1]+ffn' n = ffn 0 n++-- Construct the functions for the diagonal '1'+ffn :: (Num t1, Num t) => Int -> t -> [[t1] -> t1]+ffn _ 1 = []+ffn m n = ff1 m : ffn (m+1) (n-1) ++ff1 :: Num t => Int -> [t] -> t+ff1 m = iprod ([0,0] ++ (repeatN m 0) ++ [1] ++ (repeat 0) )++-- |RK-4 to solve the 1st-order ODEs, with input signal.+rks4InSY :: (Num a, Fractional a) =>+          a     -- ^The initial time+      -> [a]               -- ^The initial state values+      -> [([a] -> a)] -- ^List of the functions of the ODEs.+      ->  Signal  a  -- ^Input signal of steps+      ->  Signal  a  -- ^Input signal+      ->  Signal [a] -- ^Next state signal+rks4InSY x0 ys0 fFs hs us = scanl3SY stateF ys0 xs hs us+  where+    stateF ysn xn h ut = zipWith (+) (repeatN orderODE' 0.0 ++ [ut*h]) $ --Input value+                                      rks4 h xn fFs ysn +    xs = scanldSY (+) x0 hs+    -- Order -1 of the ODEs+    orderODE' = length ys0 - 1++-- |One step RK-4 for the 1st-order ordinary differential equations (ODEs).+rks4 ::  (Num a, Fractional a) =>+         a    -- ^The step+     ->  a    -- ^Initial value of time+     -> [[a] -> a] -- ^List of the funcitons of the ODEs.+     -> [a]   -- ^List of the value at the current state+     -> [a]   -- ^List of the value at the next state+rks4 h x0 fFs ys0 = ys1+  where+    h_2 = h/2.0+    ks1 = map (h*) $ map' (x0:ys0) fFs  --    -- map (h *) $ applyFt x0 fFs ys0+    ks2 = map (h*) $ map' (x0+h_2:zipWith (\y k-> y+k/2.0) ys0 ks1) fFs +    ks3 = map (h*) $ map' (x0+h_2:zipWith (\y k-> y+k/2.0) ys0 ks2) fFs +    ks4 = map (h*) $ map' (x0+h:zipWith (\y k-> y+k) ys0 ks3) fFs +    ys1 = zipWith5 (\y0 k1 k2 k3 k4 -> y0 + k1/6 + k2/3 + k3/3 + k4/6)+                    ys0 ks1 ks2 ks3 ks4++-- |The general linear filter in Z-domain.+zLinearFilter :: Fractional a => [a] -> [a] -> Signal a -> Signal a+zLinearFilter bs as = armaFilterTrim bs' as'+  where+    bs' = map ((\x y-> y/x ) (head as)) bs+    as' = map ((\x y-> -y/x ) (head as)) $ tail as++-- |s2z domain coefficient tranformation with a specified sampling rate.+-- The Tustin transformation is used for the transfer, with+--+-- >      2(z - 1)  +-- > s = ----------                                                 (Eq 3)+-- >      T(z + 1)+--+-- in which, 'T' is the sampling interval.+s2zCoef :: (Num a, Fractional a) =>+            Rational   -- ^Sampling rate in Z-domain+        -> [a] -- ^Coefficients of the polynomial numerator in s-domain+        -> [a] -- ^Coefficients of the polynomial denominator in s-domain+        -> ([a], [a]) -- ^Tuple of the numerator and denominator +                      --  coefficients in Z-domain+s2zCoef sampleT bs as = (reverse bs', reverse as')+  where+    (bs',as') = getCoef hZ    +    bsInv = reverse bs+    asInv = reverse as+    numerator' = foldl (\x y -> addPoly x $ scalePoly (fst y) (snd y)) +       (Poly [0]) $ zip bsInv sList+    denominator' = foldl (\x y -> addPoly x $ scalePoly (fst y) (snd y)) +       (Poly [0]) $ zip asInv sList+    hZ = divPoly numerator' denominator'+    -- Tustin transform+    s = PolyPair (Poly [-2,2],Poly [fromRational sampleT,fromRational sampleT])+    sList = map (powerPoly s) [0..]++-- |The Z-domain to ARMA coefficient tranformation. It is used on the +-- Z-transfer function+--+-- >        b_0*z^m-n + b_1*z^m-n-1 + ... + b_m-1*z^1-n + b_m*z^-n+-- >H(z) = -----------------------------------------------------    (Eq 4)+-- >        a_0*z^0 + a_1*z^-1 + ... + a_n-1*z^1-n + a_n*z^-n+--+-- which is normalized as+--+-- >        b_0/a_0*z^m-n + b_1/a_0*z^m-n-1 + ... + b_m/a_0*z^-n+-- >H(z) = -------------------------------------------------------  (Eq 5)+-- >        1 + a_1/a_0*z^-1 + ... + a_n-1/a_0*z^1-n + a_n/a_0*z^-n+--+-- The implementation coudl be+--+-- >y(k) = b_0/a_0*x_k+m-n + b_1/a_0*x_k+m-n-1 + ... + b_m/a_0*x_k-n+-- >                                                                (Eq 6)+-- >                       - a_1/a_0*y_k-1 - ... - a_n/a_0*y_k-n+--+-- Then, we could get the coefficients of the ARMA filter.+h2ARMACoef :: (Num a, Fractional a) =>+               ([a], [a]) -- ^Coefficients in Z-domain+            -> ([a], [a]) -- ^Coefficients of the ARMA filter+h2ARMACoef (bs,as) = (scalePolyCoef a0_1 bs, +                      scalePolyCoef (0-a0_1) $ tail as)+  where+    a0_1 = 1.0/ head as++-- Helper functions++map' :: a -> [a->b] -> [b]+map' = flip $ sequence +++-- |Computes the inner product.+iprod :: Num b => [b] -> [b] -> b+iprod xs ys = sum [x*y | (x, y) <- zip xs ys]++-- |Repeat an element for a given times.+repeatN :: Int -> a -> [a]+repeatN n = take n . repeat++-- |Maintain a fixed length of list like Fifo, except the outputs are ignored.+fixedList :: [a] -> a -> [a]+fixedList xs y = take (length xs) $ y:xs
+ src/ForSyDe/Shallow/Gaussian.hs view
@@ -0,0 +1,68 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.Gaussian+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- We follow the Box-Muller method to generate white gaussian noise, +-- described at: <http://www.dspguru.com/howto/tech/wgn.htm>+-----------------------------------------------------------------------------+module ForSyDe.Shallow.Gaussian (+          pGaussianNoise+    )+where++import ForSyDe.Shallow.UntimedLib+import ForSyDe.Shallow.Signal++import System.Random++-- |To generate an infinite Signal of Gaussian values+pGaussianNoise:: Double -- Mean value of the Gaussian noise+            -> Double   -- Variance of the Gaussian noise+            -> Int      -- The seed+            -> Signal Double -- Output gaussian noise signal+pGaussianNoise mean variance = mapU 2 gaussianXY . pUnitNormXY+  where+    gaussianXY [x, y] = [mean + sqrt(variance) * x,+                         mean + sqrt(variance) * y]+    gaussianXY _      = error "gaussianXY: unexpected pattern."++-- |To get a uniform random variable in the range [0, 1]+uniform :: (Fractional a, RandomGen g, Random a) => +  g -> (a, g)+uniform rGen = randomR (0.0,1.0) rGen++-- |To generate an infinite signal of unit normal random variables,+-- with the specified seed+pUnitNormXY :: Int         -- The seed+         -> Signal Double  -- The infinite ouput signal+pUnitNormXY = mapU 3 unitNormXY . signal . svGenerator . mkStdGen+  where+    unitNormXY [s, v1, v2] = [sqrt(-2 * log(s) / s) * v1,+                              sqrt(-2 * log(s) / s) * v2]+    unitNormXY _ = error "pUnitNormXY: Unexpected pattern."+++-- |To generate the s, v1, v2 value+svGenerator :: StdGen -> [Double]+svGenerator s+    | sVal >=1 = []++ svGenerator newStdG+    | otherwise = svVal ++ svGenerator newStdG+  where+    svGen1 = svHelper  s+    svVal = fst svGen1+    sVal = head svVal+    newStdG = snd svGen1+    svHelper :: StdGen -> ([Double], StdGen)+    svHelper stdG = ([s, v1, v2], sNew2)+      where+        (u1, sNew1) = uniform stdG+        (u2, sNew2) = uniform sNew1+        v1=2 * u1 -1+        v2=2 * u2 -1+        s = v1*v1 + v2*v2
+ src/ForSyDe/Shallow/Memory.hs view
@@ -0,0 +1,64 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.Model+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module contains the data structure and access+-- functions for the memory model.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.Memory (+                Memory (..), Access (..), +                MemSize, Adr, newMem, memState, memOutput+              ) where++import ForSyDe.Shallow.Vector+import ForSyDe.Shallow.AbsentExt++type Adr		      =  Int+type MemSize                  =  Int++-- | The data type 'Memory' is modeled as a vector. +data Memory a                 =  Mem Adr (Vector (AbstExt a)) +                                    deriving (Eq, Show)++-- | The data type 'Access' defines two access patterns.+data Access a                 =  Read Adr     -- ^ 'Read adr' reads an address from the memory.+                              |  Write Adr a  -- ^ 'Write Adr a' writes a value into an address.+                                    deriving (Eq, Show)++-- | The function 'newMem' creates a new memory, where the number of entries is given by a parameter.+newMem                        :: MemSize -> Memory a++-- | The function 'memState' gives the new state of the memory, after an access to a memory. A 'Read' operation leaves the memory unchanged.+memState                      :: Memory a -> Access a -> Memory a+++-- | The function 'memOutput' gives the output of the memory after an access to the memory. A 'Write' operation gives an absent value as output.+memOutput                     :: Memory a -> Access a -> AbstExt a++-- Implementation++newMem size                   =  Mem size (copyV size Abst)++writeMem                      :: Memory a -> (Int, a) -> Memory a+writeMem (Mem size vs) (i, x) +   | i < size && i >= 0       =  Mem size (replaceV vs i (abstExt x))+   | otherwise                =  Mem size vs++readMem                       :: Memory a -> Int -> (AbstExt a)+readMem (Mem size vs) i       +   | i < size && i >= 0       =  vs `atV` i+   | otherwise                =  Abst++memState mem (Read _)         =  mem+memState mem (Write i x)      =  writeMem mem (i, x)++memOutput mem (Read i)        =  readMem mem i+memOutput _   (Write _ _)     =  Abst++
+ src/ForSyDe/Shallow/MoCLib.hs view
@@ -0,0 +1,38 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.MoCLib+-- Copyright   :  (c) SAM/KTH 2007+-- License     :  BSD-style (see the file LICENSE)+--+-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable +-- +-- The ForSyDeMoCLib is a container including all MoC libraries and+-- their domain interfaces. It consists of the following libraries:+--+-- * The library for the synchronous MoC: "SynchronousLib". In this+--   version the synchronous library is divided into three libraries:+--   SynchronousLib, SynchronousProcessLib and StochasticLib.+-- +-- * The library for the untimed MoC: "ForSyDe.Shallow.UntimedLib"+--  +-- * The library for the continuous time MoC: "ForSyDe.Shallow.CTLib"+--+-- * The library for the domain interfaces: "ForSyDe.Shallow.DomainInterfaces"+-----------------------------------------------------------------------------+module ForSyDe.Shallow.MoCLib(  +	              module ForSyDe.Shallow.SynchronousLib,+                      module ForSyDe.Shallow.SynchronousProcessLib,+                      module ForSyDe.Shallow.StochasticLib,+                      module ForSyDe.Shallow.CTLib,+		      module ForSyDe.Shallow.UntimedLib,+                      module ForSyDe.Shallow.DomainInterfaces+		    ) where++import ForSyDe.Shallow.StochasticLib+import ForSyDe.Shallow.SynchronousLib+import ForSyDe.Shallow.CTLib+import ForSyDe.Shallow.UntimedLib+import ForSyDe.Shallow.DomainInterfaces+import ForSyDe.Shallow.SynchronousProcessLib
+ src/ForSyDe/Shallow/PolyArith.hs view
@@ -0,0 +1,106 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.PolyArith+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This is the polynomial arithematic library. The arithematic operations include +-- addition, multiplication, division and power. However, the computation time is +-- not optimized for multiplication and is O(n2), which could be considered to be +-- optimized by FFT algorithms later on.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.PolyArith(+              -- *Polynomial data type+              Poly(..),+              -- *Addition, DmMultiplication, division and power operations+              addPoly, mulPoly, divPoly, powerPoly,+              -- *Some helper functions+              getCoef, scalePoly, addPolyCoef, subPolyCoef, scalePolyCoef+    )+    where ++-- |Polynomial data type.+data Num a => Poly a = Poly [a]+                     | PolyPair (Poly a, Poly a) deriving (Eq)+++-- |Multiplication operation of polynomials.+mulPoly :: Num a => Poly a -> Poly a -> Poly a+mulPoly (Poly []) _ = Poly []+mulPoly _ (Poly []) = Poly []+-- Here is the O(n^2) version of polynomial multiplication+mulPoly (Poly xs) (Poly ys) = Poly $ foldr (\y zs ->+  let (v:vs) = scalePolyCoef y xs in v :addPolyCoef vs zs) [] ys+mulPoly (PolyPair (a, b)) (PolyPair (c, d)) =+  PolyPair (mulPoly a c, mulPoly b d)+mulPoly (PolyPair (a, b)) (Poly c) =+  PolyPair (mulPoly a (Poly c), b)+mulPoly (Poly c) (PolyPair (a, b)) =+  mulPoly (PolyPair (a, b)) (Poly c)++-- |Division operation of polynomials.+divPoly :: Num a => Poly a -> Poly a -> Poly a+divPoly (Poly a) (Poly b) = PolyPair (Poly a,Poly b)+divPoly (PolyPair (a, b)) (PolyPair (c, d)) =+  mulPoly (PolyPair (a, b)) (PolyPair (d, c))+divPoly (PolyPair (a, b)) (Poly c) =+  PolyPair (a, mulPoly b (Poly c))+divPoly (Poly c) (PolyPair (a, b)) =+  PolyPair (mulPoly b (Poly c), a)++-- |Addition operations of polynomials.+addPoly :: Num a => Poly a -> Poly a -> Poly a+addPoly (Poly a) (Poly b) = Poly $ addPolyCoef a b+addPoly (PolyPair (a, b)) (PolyPair (c, d)) =+    if b==d then  -- simplifyPolyPair $+          PolyPair (addPoly a c, d)+    else  -- simplifyPolyPair $+          PolyPair (dividedPoly, divisorPoly)+  where+    divisorPoly = if b ==d then b else mulPoly b d+    dividedPoly = if b == d then addPoly a c+                  else addPoly (mulPoly a d) (mulPoly b c)+addPoly (Poly a) (PolyPair (c, d) ) =+    addPoly (PolyPair (multiPolyHelper, d)) (PolyPair (c,d) )+  where+    multiPolyHelper = mulPoly (Poly a) d+addPoly  abPoly@(PolyPair _) cPoly@(Poly _) = addPoly cPoly abPoly+ +-- |Power operation of polynomials.+powerPoly :: Num a => Poly a -> Int -> Poly a+powerPoly p n = powerX' (Poly [1]) p n+  where+    powerX' :: Num a => Poly a -> Poly a -> Int -> Poly a+    powerX' p' _ 0 = p'+    powerX' p' p n = powerX' (mulPoly p' p) p (n-1)++-- |Some helper functions below.++-- |To get the coefficients of the polynomial.+getCoef :: Num a => Poly a -> ([a],[a])+getCoef (Poly xs) = (xs,[1])+getCoef (PolyPair (Poly xs,Poly ys)) = (xs,ys)+getCoef _ = error "getCoef: Nested fractions found"++scalePoly :: (Num a) => a -> Poly a -> Poly a+scalePoly s p = mulPoly (Poly [s]) p++addPolyCoef :: Num a => [a] -> [a] -> [a]+addPolyCoef = zipWithExt (0,0) (+)+subPolyCoef :: RealFloat a => [a] -> [a] -> [a]+subPolyCoef = zipWithExt (0,0) (-)++scalePolyCoef :: (Num a) => a -> [a] -> [a]+scalePolyCoef s p = map (s*) p++-- |Extended version of 'zipWith', which will add zeros to the shorter list.+zipWithExt :: (a,b) -> (a -> b -> c) -> [a] -> [b] -> [c]+zipWithExt _ _ [] [] = []+zipWithExt (x0,y0) f (x:xs) [] = f x y0 : (zipWithExt (x0,y0) f xs [])+zipWithExt (x0,y0) f [] (y:ys)  = f x0 y : (zipWithExt (x0,y0) f [] ys)+zipWithExt (x0,y0) f (x:xs) (y:ys)  = f x y : (zipWithExt (x0,y0) f xs ys)+
+ src/ForSyDe/Shallow/Queue.hs view
@@ -0,0 +1,98 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.Queue+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+--+-- This provides two data types, that can be used to model queue+-- structures, such as FIFOs. There is a data type for an queue of+-- infinite size 'Queue' and one for finite size 'FiniteQueue'.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.Queue where++import ForSyDe.Shallow.AbsentExt ++-- | A queue is modeled as a list. The data type 'Queue' modelles an queue of infinite size.+data Queue a        =  Q [a] deriving (Eq, Show)++-- | The data type 'FiniteQueue' has an additional parameter, that determines the size of the queue.+data FiniteQueue a  =  FQ Int [a] deriving (Eq, Show)++{-+Table \ref{tab:QueueFunctions} shows the functions an the data types \haskell{Queue} and \haskell{FiniteQueue}.+%+\begin{table}+\label{tab:QueueFunctions}+\begin{tabular}{lll}+\hline+infinite & finite & description \\+\hline+\hline+\haskell{pushQ} & \haskell{pushFQ} & pushes one element on the queue \\+\haskell{pushListQ} & \haskell{pushListFQ} & pushes a list of elements on the queue \\+\haskell{popQ} & \haskell{popFQ} & pops one element from the queue \\+\haskell{queue} & \haskell{finiteQueue} & transforms a list into a queue \\+\hline+\end{tabular}+\caption{Functions on the data types \haskell{Queue} and \haskell{FiniteQueue}}+\end{table}+-}++-- | 'pushQ' pushes one element into an infinite queue.+pushQ                         :: Queue a -> a -> Queue a++-- | 'pushListQ' pushes a list of elements into an infinite queue.+pushListQ                     :: Queue a -> [a] -> Queue a++-- | 'popQ' pops one element from an infinite queue.+popQ                          :: Queue a -> (Queue a, AbstExt a)++-- | 'queue' transforms a list into an infinite queue.+queue                         :: [a] -> Queue a++-- | 'pushFQ' pushes one element into a finite queue.+pushFQ                        :: FiniteQueue a -> a -> FiniteQueue a++-- | 'pushListFQ' pushes a list of elements into a finite queue.+pushListFQ                    :: FiniteQueue a -> [a] -> FiniteQueue a++-- | 'popFQ' pops one element from a finite queue.+popFQ                         :: FiniteQueue a +			      -> (FiniteQueue a, AbstExt a)++-- | 'finiteQueue' transforms a list into an infinite queue.+finiteQueue		      :: Int -> [a] -> FiniteQueue a+++-- Implementation++pushQ (Q q) x                 =  Q (q ++ [x])++pushListQ (Q q) xs            =  Q (q ++ xs)++popQ (Q [])                   =  (Q [], Abst)+popQ (Q (x:xs))               =  (Q xs, Prst x)++queue xs                      =  Q xs++pushFQ (FQ n q) x             =  if length q < n then+                                    (FQ n (q ++ [x]))+                                 else +                                    (FQ n q)++pushListFQ (FQ n q) xs        =  FQ n (take n (q ++ xs))++popFQ (FQ n [])               =  (FQ n [], Abst)+popFQ (FQ n (q:qs))           =  (FQ n qs, Prst q)+                                             +finiteQueue n xs	      =  FQ n (take n xs)+++++
+ src/ForSyDe/Shallow/Signal.hs view
@@ -0,0 +1,224 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.Signal+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module defines the shallow-embedded 'Signal' datatype and+-- functions operating on it.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.Signal( Signal (NullS, (:-)), (-:), (+-+), (!-), +	       signal, fromSignal,+	       unitS, nullS, headS, tailS, atS, takeS, dropS,+	       lengthS, infiniteS, copyS, selectS, writeS, readS, fanS+	     ) where++infixr 5	:-+infixr 5	-:+infixr 5	+-++infixr 5	!-+++-- | A signal is defined as a list of events. An event has a tag and a value. The tag of an event is defined by the position in the list. A signal is defined as an instance of the classes 'Read' and 'Show'. The signal 1 :- 2 :- NullS is represented as \{1,2\}.+data Signal a = NullS+	      | a :- Signal a deriving (Eq)++-- | The function 'signal' converts a list into a signal.+signal		   :: [a] -> Signal a ++-- | The function 'fromSignal' converts a signal into a list.+fromSignal	   :: Signal a -> [a]++-- | The function 'unitS' creates a signal with one value.+unitS		   :: a -> Signal a++-- | The function 'nullS' checks if a signal is empty.+nullS		   :: Signal a -> Bool++-- | The function 'headS' gives the first value - the head -  of a signal.+headS		   :: Signal a -> a++-- | The function 'tailS' gives the rest of the signal - the tail.+tailS		   :: Signal a -> Signal a++-- | The function 'atS'  returns the n-th event in a signal. The numbering of events in a signal starts with 0. There is also an operator version of this function, '(!-)'.+atS		   :: Int -> Signal a -> a++-- | The function 'takeS' returns the first n values of a signal.+takeS		   :: Int -> Signal a -> Signal a++-- | The function 'dropS' drops the first $n$ values from a signal.+dropS		   :: Int -> Signal a -> Signal a++-- | The function 'selectS' takes three parameters, an offset, a stepsize and a signal and returns some elements of the signal such as in the following example:+--+-- @+-- Signal> selectS 2 3 (signal[1,2,3,4,5,6,7,8,9,10])+-- {3,6,9} :: Signal Integer+-- @+selectS		   :: Int -> Int -> Signal a -> Signal a++-- | The function 'lengthS' returns the length of a 'finite' signal.+lengthS		   :: Signal b -> Int++-- | The function 'infiniteS' creates an infinite signal. The first argument 'f' is a function that is applied on the current value. The second argument 'x' gives the first value of the signal.+--+-- > Signal> takeS 5 (infiniteS (*3) 1)+-- > {1,3,9,27,81} :: Signal Integer+--+infiniteS	   :: (a -> a) -> a -> Signal a++-- | The function 'writeS' transforms a signal into a string of the following format:+--+-- @ +-- Signal> writeS (signal[1,2,3,4,5])+-- "1\n2\n3\n4\n5\n" :: [Char]+-- @+writeS		   :: Show a => Signal a -> [Char]++-- | The function 'readS' transforms a formatted string into a signal.+--+-- @+-- Signal> readS "1\n2\n3\n4\n5\n" :: Signal Int+-- {1,2,3,4,5} :: Signal Int+-- @+readS		   :: Read a => [Char] -> Signal a++-- | The operator '-:' adds at an element to a signal at the tail.+(-:)		   :: Signal a -> a -> Signal a++-- | The operator '+-+' concatinates two signals into one signal.  +(+-+)		   :: Signal a -> Signal a -> Signal a +++-- | The function 'copyS' creates a signal with n values 'x'.+copyS :: Num a => a -> b -> Signal b+++-- | The combinator 'fanS' takes two processes 'p1' and 'p2' and and generates a process network, where a signal is split and processed by the processes 'p1' and 'p2'.+fanS :: (Signal a -> Signal b) -> (Signal a -> Signal c) +          -> Signal a -> (Signal b, Signal c)++-- Implementation++instance (Show a) => Show (Signal a) where+	 showsPrec p NullS = showParen (p > 9) (+	 		       showString "{}")+	 showsPrec p xs	   = showParen (p > 9) (+			       showChar '{' . showSignal1 xs)+			     where+				showSignal1 NullS+			           = showChar '}'+			        showSignal1 (y:-NullS) +			           = shows y . showChar '}'+				showSignal1 (y:-ys)    +		                   = shows y . showChar ',' +				     . showSignal1 ys++instance Read a => Read (Signal a) where+	 readsPrec _ s = readsSignal s++readsSignal	       :: (Read a) => ReadS (Signal a)+readsSignal s	       =  [((x:-NullS), rest) +			    | ("{", r2)   <- lex s,+			      (x, r3)     <- reads r2,+			      ("}", rest) <- lex r3]+		          ++ [(NullS, r4)	    +			    | ("{", r5) <- lex s,+			      ("}", r4) <- lex r5]+		          ++ [((x:-xs), r6)	    +			    | ("{", r7) <- lex s,+			      (x, r8)	<- reads r7,+			      (",", r9) <- lex r8,+			      (xs, r6)	<- readsValues r9]++readsValues	       :: (Read a) => ReadS (Signal a)+readsValues s	       =  [((x:-NullS), r1) +		            | (x, r2)   <- reads s,+			      ("}", r1) <- lex r2]+		          ++ [((x:-xs), r3)    +	   		    | (x, r4)   <- reads s,+			      (",", r5) <- lex r4,+			      (xs, r3)  <- readsValues r5]++signal []			=  NullS+signal (x:xs)			=  x :- signal xs ++fromSignal NullS		=  []+fromSignal (x:-xs)		=  x : fromSignal xs++unitS x				=  x :- NullS++nullS NullS			=  True+nullS _				=  False++headS NullS			=  error "headS : Signal is empty"+headS (x:-_)			=  x++tailS NullS			=  error "tailS : Signal is empty"+tailS (_:-xs)			=  xs++atS _ NullS			+      =  error "atS: Signal has not enough elements"+atS 0 (x:-_)			=  x+atS n (_:-xs)			=  atS (n-1) xs++(!-) :: Signal a -> Int -> a+(!-) xs n			= atS n xs++takeS 0 _			= NullS+takeS _ NullS			= NullS+takeS n (x:-xs) | n <= 0	= NullS+		| otherwise	= x :- takeS (n-1) xs++dropS 0 NullS			= NullS+dropS _ NullS			= NullS +dropS n (x:-xs) | n <= 0	= x:-xs+       	  | otherwise		= dropS (n-1) xs+++selectS offset step xs = select1S step (dropS offset xs) +  where+   select1S _  NullS   = NullS+   select1S st (y:-ys) = y :- select1S st (dropS (st-1) ys) ++(-:) xs x			= xs +-+ (x :- NullS)++(+-+) NullS   ys		= ys+(+-+) (x:-xs) ys		= x :- (xs +-+ ys)++lengthS NullS			= 0+lengthS (_:-xs)			= 1 + lengthS xs++infiniteS f x			= x :- infiniteS f (f x)++copyS 0 _			= NullS+copyS n x			= x :- copyS (n-1) x++fanS p1 p2 xs			= (p1 xs, p2 xs)++writeS NullS   = []+writeS (x:-xs) = show x ++ "\n" ++ writeS xs++readS xs       = readS' (words xs)+  where+    readS' []        = NullS+    readS' ("\n":ys) = readS' ys+    readS' (y:ys)	 = read y :- readS' ys+++++++++++++
+ src/ForSyDe/Shallow/StochasticLib.hs view
@@ -0,0 +1,255 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.StochasticLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The stochastic library provides a few stochastic skeletons, which are+-- relatives to the skeletons of the synchronous library. These skeletons are+-- based on two elementary functions, 'sigmaUn' and 'sigmaGe'+-- which provide stochastic signals. The background and motivation for this+-- approach is described in the paper +--+-- Axel Jantsch, Ingo Sander, and Wenbiao Wu,+-- \"The usage of stochastic processes in embedded system specifications\",+-- In /Proceedings of the Ninth International Symposium on Hardware and Software Codesign/, +-- April 2001 (<http://web.it.kth.se/~axel/papers/2001/codes-2001.pdf>). +--+-- Unfortunately, not all of the suggested skeletons are+-- implemented. In particular, consolidation-based process+-- constructors and all constructors for the untimed and the discrete+-- timed MoCs are missing.+-----------------------------------------------------------------------------++module ForSyDe.Shallow.StochasticLib(+                     -- * Select based synchronous process constructors+                     selMapSY, selScanlSY, selMealySY, selMooreSY+                     -- * Elementary stochastic processes+                    , sigmaUn, sigmaGe) where++import ForSyDe.Shallow.SynchronousLib+import ForSyDe.Shallow.Signal+import System.Random++-- | The skeleton 'selMapSY' is a stochastic variant of+-- 'mapSY'. It has an internal stochastic process and selects one+-- out of two combinatorial functions depending on the output of the+-- stochastic process.+selMapSY   :: Int      -- ^The seed for the stochastic process+           -> (a -> b) -- ^The first alternative function+           -> (a -> b) -- ^The second alternative function+           -> Signal a -- ^The input signal+           -> Signal b -- ^The output signal of the process+selMapSY _    _  _  NullS = NullS+selMapSY seed f0 f1 xs = selmap1 f0 f1 (sigmaUn seed (0,1)) xs+        where selmap1 :: (a->b)->(a->b)->(Signal Int) -> Signal a -> Signal b+              selmap1 _  _  _       NullS = NullS+              selmap1 f0 f1 (s:-ss) (x:-xs) +                 = (select1 s f0 f1 x) :- (selmap1 f0 f1 ss xs)+              selmap1 _  _  NullS _ = error "selMapSY: empty seed signal."++-- | The skeleton 'selScanlSY' is a stochastic variant of 'scanlSY'.+selScanlSY :: Int           -- ^The seed+           -> (a -> b -> a) -- ^The first alternative next-state function+           -> (a -> b -> a) -- ^The second alternative function+           -> a             -- ^The initial state+           -> Signal b      -- ^The input signal+           -> Signal a      -- ^The output signal+selScanlSY _    _  _  _   NullS   = NullS+selScanlSY seed f0 f1 mem xs      = selscan1 f0 f1 mem (sigmaUn seed (0,1)) xs+          where selscan1 :: (a -> b -> a) -> (a -> b -> a) -> a +                            -> Signal Int -> Signal b -> Signal a+                selscan1 _  _  _   _       NullS = NullS+                selscan1 f0 f1 mem (s:-ss) (x:-xs)+                         = newmem :- (selscan1 f0 f1 newmem ss xs)+                         where newmem = (select2 s f0 f1 mem x) +                selscan1 _  _  _   NullS _ +                    = error "selScanlSY: empty seed signal"++select1		  :: Int -> (a -> b) -> (a->b) -> a -> b+select1 0 f0 _  x =  f0 x+select1 1 _  f1 x =  f1 x+select1 s _  _  _ =  error ("select1: seed value neither 0 nor 1: " +                            ++ (show s))++select2		    :: Int -> (a -> b -> c) -> (a->b->c) +		       -> a -> b -> c+select2 0 f0 _  x y =  f0 x y+select2 1 _  f1 x y =  f1 x y+select2 s _  _  _ _ =  error ("select2: seed value neither 0 nor 1: " +                              ++ (show s))++-- | 'selMooreSY' is the stochastic variant of mooreSY. Both the +--   next-state and the output function is randomly selected based on a +--   uniform distribution.+selMooreSY :: Int           -- ^The seed for the next-state function+           -> Int           -- ^The seed for the output function+           -> (a -> b -> a) -- ^First alternative for the next-state function+           -> (a -> b -> a) -- ^Second alternative for the next-state function+           -> (a -> c)      -- ^First alternative for the output function+           -> (a -> c)      -- ^Second alternative for the output function+           -> a             -- ^The initial state+           -> Signal b      -- ^The input signal+           -> Signal c      -- ^The output signal+selMooreSY _ _ _ _ _ _ _ NullS = NullS+selMooreSY seedg seedf g0 g1 f0 f1 w0 s+    = ((selMapSY seedf f0 f1 ) . (selScanlSY seedg g0 g1 w0)) s++-- | 'selMealySY' is the stochastic variant of mealySY. Both the +--   next-state and the output function is randomly selected based on a +--   uniform distribution.+selMealySY :: Int           -- ^The seed for the next-state function+           -> Int           -- ^The seed for the output function+           -> (a -> b -> a) -- ^First alternative for the next-state function+           -> (a -> b -> a) -- ^Second alternative for the next-state function+           -> (a -> b -> c) -- ^First alternative for the output function+           -> (a -> b -> c) -- ^Second alternative for the output function+           -> a             -- ^The initial state+           -> Signal b      -- ^The input signal+           -> Signal c      -- ^The output signal+selMealySY _ _ _ _ _ _ _ NullS = NullS+selMealySY seedg seedf g0 g1 f0 f1 w0 s+    = ((selMapSY seedf f0' f1' ) . (zipSY s) . (selScanlSY seedg g0 g1 w0)) s+      where f0' (b, a) = f0 a b+            f1' (b, a) = f1 a b+-- |'sigmaUn' generates a signal list of uniformly distributed Int within+-- the given range and with a given seed. +sigmaUn :: Int        -- ^The seed+        -> (Int, Int) -- ^The interval from which the stochastic values are +                      --  taken+        -> Signal Int -- ^The sequence of stochastic values+sigmaUn seed range = signal (stoch range (mkStdGen seed))+        where stoch :: (Int, Int) -> StdGen -> [Int]+	      stoch range g = newNum `seq` +                              (newNum : (stoch range newGen))+                  where newNum = (fst (randomR range g)) +                        newGen = snd (next g)++-- |'sigmaGe' is a more general stochastic process. The first argument is a+-- function f which describes the distribution. For each value v in the+-- given range (r1,r2), f(v) is the probability that v is generated.  +--+-- Note, that the user has to make sure that sum(f(v))=1 for v in (r1,r2).+--+-- For illustration consider the following example.+--+-- > pdist :: Float -> Float+-- > pdist d = 1\/\(2**d\)+-- > pdistsum 1 = pdist 1+-- > pdistsum d = \(pdist d\) + \(pdistsum \(d-1\)\)+--+-- > pdistnorm :: Float -> Float -> Float+-- > pdistnorm dmax d = 1\/((pdistsum dmax) * (2**d))+--+-- @pdistnorm dmax d@ gives the probability of a value <= d;+--+-- @pdistnorm dmax dmax@ is always 1.0+--+-- Hence, using pdistnorm as a function in 'sigmaGe' gives an exponantial+-- distribution for values in the range \[0, dmax\].+sigmaGe :: (Float -> Float) -- ^The stochastic distribution+        -> Int              -- ^The seed+        -> (Int, Int)       -- ^The range+        -> Signal Int       -- ^The sequence of stochastic values+sigmaGe f seed (r1,r2) = sigma2 (checkSum f (fromIntegral r1) +                                           (fromIntegral r2)) f seed (r1,r2)+      where sigma2 s f seed (r1,r2) +                    | s > 0.999 = signal (sigma1 (mkStdGen seed) +                                           (mkdlist f (fromIntegral (r2-r1))))+                   | otherwise = error +                                  ("sigmaGe: sum of probabilitites is "+                                  ++ (show s) ++ ". It must be 1.")+            checkSum :: (Float -> Float) -> Float -> Float -> Float+            checkSum f c max | c == max = f c+                             | otherwise = f(c) + (checkSum f (c+1) max)++            sigma1 :: StdGen -> [Float] -> [Int]+            sigma1 g fl = (findk (fst (randomR (0.0,1.0) g)) fl)+                          : (sigma1 (snd (next g)) fl)++            findk :: Float -> [Float] -> Int+            findk r fs = findk1 0 r fs++            findk1 k r (f:fs) | r < f = k+                              | otherwise = findk1 (k+1) r fs+            findk1 k _ []  = k++            mkdlist :: (Float -> Float) -> Float  -> [Float]+            mkdlist f d = scanl (sumf f) 0.0 [1..d]++            sumf :: (Float -> Float) -> Float -> Float -> Float+            sumf g x y = x + (g y)++--pdist :: Float -> Float+--pdist d = 1/(2**d)++--pdistsum 1 = pdist 1+--pdistsum d = (pdist d) + (pdistsum (d-1))++-- The function pdistnorm can be used as a function in sigmaGe for an+-- exponantial distribution of values in the range [0, dmax]:+--pdistnorm :: Float -> Float -> Float+--pdistnorm dmax d = 1/((pdistsum dmax) * (2**d))++--pdnormsum dmax 1 = pdistnorm dmax 1+--pdnormsum dmax d = (pdistnorm dmax d) + (pdnormsum dmax (d-1))+++-----------------------------------------------------------------------------+-- Test section:+--+-- These tests are commented to avoid warnings about not-used functions.+-- But the test functions work and are useful.+-- testAll = "test selMapSY: " ++ testSelMap +--           ++ ", test selMooreSY: " ++ testSelMoore+--           ++ ", test selMealySY: " ++ testSelMealy++-- testSelMap = show so ++ " -> " ++ (cmpSig so (signal [0,3,4,5,4,5,8,9,8,11]))+--     where f0 x = x + 1+--           f1 x = x - 1+--           so = takeS 10 (selMapSY 876876 f0 f1 (signal [1,2..]))++-- testSelMoore = show so ++ " -> " +--                ++ (cmpSig so (signal [10,2,3,-40,-5,0,7,-80,0,-100]))+--     where so = takeS 10 (selMooreSY 7667567 123234 g0 g1 f0 f1 w0 +--                                         (signal [1,2..]))+--           g0 (0,y) x | even x         = (0,x)+--                      | otherwise      = (1,x)+--           g0 (1,y) x | x `mod` 3 == 0 = (0,x)+--                      | otherwise      = (1,x)+--           g1 (0,y) x | even x         = (1,x)+--                      | otherwise      = (0, x)+--           g1 (1,y) x | x `mod` 3 == 0 = (0,0)+--                      | otherwise      = (1,x)+--           f0 (0,y) = y+--           f0 (1,y) = -1 * y+--           f1 (0,y) = 10 * y+--           f1 (1,y) = -10 * y+--           w0 = (0,0)++-- testSelMealy = show so ++ " -> " +--                ++ (cmpSig so (signal [10,2,3,-40,-5,0,7,-80,0,-100]))+--     where so = takeS 10 (selMealySY 7667567 123234 g0 g1 f0 f1 w0 +--                                         (signal [1,2..]))+--           g0 (0,y) x | even x         = (0,x)+--                      | otherwise      = (1,x)+--           g0 (1,y) x | x `mod` 3 == 0 = (0,x)+--                      | otherwise      = (1,x)+--           g1 (0,y) x | even x         = (1,x)+--                      | otherwise      = (0, x)+--           g1 (1,y) x | x `mod` 3 == 0 = (0,0)+--                      | otherwise      = (1,x)+--           f0 (0,y) x = y+--           f0 (1,y) x = -1 * y+--           f1 (0,y) x = 10 * y+--           f1 (1,y) x = -10 * y+--           w0 = (0,0)+--+--+-- cmpSig :: Eq a => Signal a -> Signal a -> String+-- cmpSig s1 s2 | s1 == s2 = "OK"+--              | otherwise = "Not OK"
+ src/ForSyDe/Shallow/SynchronousLib.hs view
@@ -0,0 +1,349 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.SynchronousLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The synchronuous library defines process constructors and processes+-- for the synchronous computational model. A process constructor is a+-- higher order function which together with combinational function(s)+-- and values as arguments constructs a process.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.SynchronousLib(+			-- * Combinational process constructors+			-- | Combinational process constructors are used for processes that do not have a state.+			mapSY, zipWithSY, zipWith3SY, +			zipWith4SY, zipWithxSY, +			-- * Sequential process constructors+			-- | Sequential process constructors are used for processes that have a state. One of the input parameters is the initial state.+			delaySY, delaynSY,+			scanlSY, scanl2SY, scanl3SY, scanldSY, scanld2SY,+			scanld3SY, mooreSY, moore2SY, moore3SY, mealySY,+			mealy2SY, mealy3SY, sourceSY, +			filterSY, fillSY, holdSY,+			-- * Synchronous Processes+			-- | The library contains a few simple processes that are applicable to many cases.+			whenSY, zipSY, zip3SY, zip4SY, zip5SY, zip6SY, +                        unzipSY, unzip3SY, unzip4SY, unzip5SY, unzip6SY,+                        zipxSY, unzipxSY, mapxSY, +			fstSY, sndSY+        	     ) where++import ForSyDe.Shallow.CoreLib++----------------------------------------+--                                    --+-- COMBINATIONAL PROCESS CONSTRUCTORS --+--                                    --+----------------------------------------++-- | The process constructor 'mapSY' takes a combinational function as argument and returns a process with one input signal and one output signal.+mapSY		:: (a -> b) -> Signal a	-> Signal b+mapSY _ NullS	= NullS+mapSY f (x:-xs)	= f x :- (mapSY f xs)++-- | The process constructor 'zipWithSY' takes a combinational function as argument and returns a process with two input signals and one output signal.+zipWithSY	:: (a -> b -> c) -> Signal a -> Signal b -> Signal c+zipWithSY _ NullS   _       = NullS+zipWithSY _ _       NullS   = NullS+zipWithSY f (x:-xs) (y:-ys) = f x y :- (zipWithSY f xs ys)++-- | The process constructor 'zipWith3SY' takes a combinational function as argument and returns a process with three input signals and one output signal.+zipWith3SY	:: (a -> b -> c -> d) -> Signal a -> Signal b -> Signal c -> Signal d+zipWith3SY _ NullS   _       _       = NullS+zipWith3SY _ _       NullS   _       = NullS+zipWith3SY _ _       _       NullS   = NullS+zipWith3SY f (x:-xs) (y:-ys) (z:-zs) = f x y z +				       :- (zipWith3SY f xs ys zs)++-- | The process constructor 'zipWith4SY' takes a combinational function as argument and returns a process with four input signals and one output signal.+zipWith4SY	:: (a -> b -> c -> d -> e) -> Signal a -> Signal b +		-> Signal c -> Signal d	-> Signal e+zipWith4SY _ NullS   _       _       _      = NullS+zipWith4SY _ _       NullS   _       _      = NullS+zipWith4SY _ _       _       NullS   _      = NullS+zipWith4SY _ _       _       _       NullS  = NullS+zipWith4SY f (w:-ws) (x:-xs) (y:-ys) (z:-zs) +				      = f w x y z +				        :- (zipWith4SY f ws xs ys zs)++-- | The process constructor 'mapxSY' creates a process network that maps a function onto all signals in a vector of signals.+mapxSY		:: (a -> b) -> Vector (Signal a) -> Vector (Signal b)+mapxSY f = mapV (mapSY f)++-- | The process constructor 'zipWithxSY' works as 'zipWithSY', but takes a vector of signals as input.+zipWithxSY	:: (Vector a -> b) -> Vector (Signal a)	-> Signal b+zipWithxSY f = mapSY f . zipxSY++++-------------------------------------+--                                 --+-- SEQUENTIAL PROCESS CONSTRUCTORS --+--                                 --+-------------------------------------++-- | The process constructor 'delaySY' delays the signal one event cycle +--   by introducing an initial value at the beginning of the output signal. +--   Note, that this implies that there is one event (the first) at the +--   output signal that has no corresponding event at the input signal. +--   One could argue that input and output signals are not fully synchronized,+--   even though all input events are synchronous with a corresponding output +--   event. However, this is necessary to initialize feed-back loops.+delaySY	       :: a -- ^Initial state +	       -> Signal a -- ^Input signal+	       -> Signal a -- ^Output signal+delaySY e es = e:-es++-- | The process constructor 'delaynSY' delays the signal n events by introducing n identical default values.   +delaynSY       :: a -- ^Initial state+	       -> Int -- ^ Delay cycles +	       -> Signal a -- ^Input signal+	       -> Signal a -- ^Output signal+delaynSY e n xs | n <= 0    = xs+                | otherwise = e :- delaynSY e (n-1) xs ++-- | The process constructor 'scanlSY' is used to construct a finite state machine process without output decoder. It takes an initial value and a function for the next state decoder. The process constructor behaves similar to the Haskell prelude function 'scanlSY' and has the value of the new state as its output value as illustrated by the following example.  +--+-- > SynchronousLib> scanldSY (+) 0 (signal [1,2,3,4])+--+-- > {1,3,6,10} :: Signal Integer+-- +-- This is in contrast to the function 'scanldSY', which has its current state as its output value. +scanlSY	       :: (a -> b -> a) -- ^Combinational function for next state decoder+	       -> a -- ^Initial state+	       -> Signal b -- ^ Input signal +	       -> Signal a -- ^ Output signal+scanlSY f mem xs = s'+    where s' = zipWithSY f (delaySY mem s') xs ++-- | The process constructor 'scanl2SY' behaves like 'scanlSY', but has two input signals.+scanl2SY       :: (a -> b -> c -> a) -> a -> Signal b -> Signal c -> Signal a+scanl2SY f mem xs ys = s'+    where s' = zipWith3SY f (delaySY mem s') xs ys++-- | The process constructor 'scanl3SY' behaves like 'scanlSY', but has three input signals.+scanl3SY       :: (a -> b -> c -> d -> a) -> a -> Signal b +	           -> Signal c -> Signal d -> Signal a+scanl3SY f mem xs ys zs = s'+    where s' = zipWith4SY f (delaySY mem s') xs ys zs++-- | The process constructor 'scanldSY' is used to construct a finite state machine process without output decoder. It takes an initial value and a function for the next state decoder. The process constructor behaves similar to the Haskell prelude function 'scanlSY'. In contrast to the process constructor 'scanlSY' here the output value is the current state and not the one of the next state.+--+-- > SynchronousLib> scanlSY (+) 0 (signal [1,2,3,4])+--+-- > {0,1,3,6} :: Signal Integer+scanldSY       :: (a -> b -> a) -- ^Combinational function for next state decoder+	       -> a -- ^Initial state+	       -> Signal b -- ^ Input signal +	       -> Signal a -- ^ Output signal+scanldSY f mem xs = s'+    where s' = delaySY mem $ zipWithSY f s' xs +++-- | The process constructor 'scanld2SY' behaves like 'scanldSY', but has two input signals.+scanld2SY      :: (a -> b -> c -> a) -> a -> Signal b -> Signal c +		   -> Signal a+scanld2SY f mem xs ys = s'+    where s' = delaySY mem $ zipWith3SY f s' xs ys++-- | The process constructor 'scanld3SY' behaves like 'scanldSY', but has three input signals.+scanld3SY      :: (a -> b -> c -> d -> a) -> a -> Signal b +		   -> Signal c -> Signal d -> Signal a+scanld3SY f mem xs ys zs = s'+    where s' = delaySY mem $ zipWith4SY f s' xs ys zs++-- | The process constructor 'mooreSY' is used to model state machines of \"Moore\" type, where the output only depends on the current state. The process constructor is based on the process constructor 'scanldSY', since it is natural for state machines in hardware, that the output operates on the current state and not on the next state. The process constructors takes a function to calculate the next state, another function to calculate the output and a value for the initial state. +--+-- In contrast the output of a process created by the process constructor 'mealySY' depends not only on the state, but also on the input values.+mooreSY	       :: (a -> b -> a) -- ^Combinational function for next state decoder +	       -> (a -> c) -- ^Combinational function for output decoder+	       -> a -- ^Initial state+	       -> Signal b -- ^Input signal+	       -> Signal c -- ^Output signal+mooreSY nextState output initial +        = mapSY output . (scanldSY nextState initial)++-- | The process constructor 'moore2SY' behaves like 'mooreSY', but has two input signals.+moore2SY       :: (a -> b -> c -> a) -> (a -> d) -> a -> Signal b +	           -> Signal c -> Signal d+moore2SY nextState output initial inp1 inp2 =+ 	 mapSY output (scanld2SY nextState initial inp1 inp2)++-- | The process constructor 'moore3SY' behaves like 'mooreSY', but has three input signals.+moore3SY       :: (a -> b -> c -> d -> a) -> (a -> e) -> a -> Signal b +		   -> Signal c -> Signal d -> Signal e+moore3SY nextState output initial inp1 inp2 inp3 =+ 	 mapSY output (scanld3SY nextState initial inp1 inp2 inp3)++-- | The process constructor 'melaySY' is used to model state machines of \"Mealy\" type, where the output only depends on the current state and the input values. The process constructor is based on the process constructor 'scanldSY', since it is natural for state machines in hardware, that the output operates on the current state and not on the next state. The process constructors takes a function to calculate the next state, another function to calculate the output and a value for the initial state. +--+-- In contrast the output of a process created by the process constructor 'mooreSY' depends only on the state, but not on the input values.+mealySY	       :: (a -> b -> a) -- ^Combinational function for next state decoder  +	       -> (a -> b -> c) -- ^Combinational function for output decoder+	       -> a -- ^Initial state+	       -> Signal b -- ^Input signal +	       -> Signal c -- ^Output signal+mealySY nextState output initial sig =+        zipWithSY output state sig+        where state = scanldSY nextState initial sig++-- | The process constructor 'mealy2SY' behaves like 'mealySY', but has two input signals.+mealy2SY       :: (a -> b -> c -> a) -> (a -> b -> c -> d) -> a +	           -> Signal b -> Signal c -> Signal d+mealy2SY nextState output initial inp1 inp2 =+ 	zipWith3SY output (scanld2SY nextState initial inp1 inp2)+	                  inp1 inp2      ++-- | The process constructor 'mealy3SY' behaves like 'mealySY', but has three input signals.+mealy3SY       :: (a -> b -> c -> d -> a) -> (a -> b -> c -> d -> e) -> a +	           -> Signal b -> Signal c -> Signal d -> Signal e+mealy3SY nextState output initial inp1 inp2 inp3 =+        zipWith4SY output (scanld3SY nextState initial inp1 inp2 inp3)+		         inp1 inp2 inp3 ++-- | The process constructor 'filterSY' discards the values who do not fulfill a predicate given by a predicate function and replaces them with absent events.+filterSY       :: (a -> Bool) -- Predicate function+		  -> Signal a -- Input signal+		  -> Signal (AbstExt a) -- Output signal+filterSY _ NullS	= NullS+filterSY p (x:-xs)	= if (p x == True) then+			     Prst x :- filterSY p xs+			  else+			     Abst :- filterSY p xs	++-- | The process 'sourceSY' takes a function and an initial state and generates an infinite signal starting with the initial state as first output followed by the recursive application of the function on the current state. The state also serves as output value. +--+-- The process that has the infinite signal of natural numbers as output is constructed by +--+-- > SynchronousLib> takeS 5 (sourceSY (+1) 0)+--+-- > {0,1,2,3,4} :: Signal Integer+sourceSY       :: (a -> a) -> a -> Signal a+sourceSY f s0		= o+  where +    o			= delaySY s0 s+    s			= mapSY f o++-- | The process constructor 'fillSY' creates a process that 'fills' a signal with present values by replacing absent values with a given value. The output signal is not any more of the type 'AbstExt'.+fillSY	     :: a -- ^Default value  +	     -> Signal (AbstExt a) -- ^Absent extended input signal +	     -> Signal a -- ^Output signal+fillSY a xs = mapSY (replaceAbst a) xs+              where replaceAbst a' Abst     = a'+                    replaceAbst _  (Prst x) = x++-- | The process constructor 'holdSY' creates a process that 'fills' a signal with values by replacing absent values by the preceding present value. Only in cases, where no preceding value exists, the absent value is replaced by a default value. The output signal is not any more of the type 'AbstExt'.+holdSY       :: a -- ^Default value +	     -> Signal (AbstExt a) -- ^Absent extended input signal +	     -> Signal a -- ^Output signal+holdSY a xs = scanlSY hold a xs+   	      where hold a' Abst     = a'+ 		    hold _  (Prst x) = x++++---------------------------+--                       --+-- SYNCHRONOUS PROCESSES --+--                       --+---------------------------++-- | The process constructor 'whenSY' creates a process that synchronizes a signal of absent extended values with another signal of absent extended values. The output signal has the value of the first signal whenever an event has a present value and 'Abst' when the event has an absent value.+whenSY	     :: Signal (AbstExt a) -> Signal (AbstExt b) +		-> Signal (AbstExt a)+whenSY NullS   _            = NullS+whenSY _       NullS        = NullS+whenSY (_:-xs) (Abst:-ys)   = Abst :- (whenSY xs ys)+whenSY (x:-xs) (_:-ys)      = x    :- (whenSY xs ys)++-- | The process 'zipSY' \"zips\" two incoming signals into one signal of tuples.+zipSY        :: Signal a -> Signal b -> Signal (a,b)+zipSY (x:-xs) (y:-ys) = (x, y) :- zipSY xs ys+zipSY _	     _	     = NullS++-- | The process 'zip3SY' works as 'zipSY', but takes three input signals.+zip3SY       :: Signal a -> Signal b -> Signal c -> Signal (a,b,c)+zip3SY (x:-xs) (y:-ys) (z:-zs) = (x, y, z) :- zip3SY xs ys zs+zip3SY _	     _	_      = NullS++-- | The process 'zip4SY' works as 'zipSY', but takes four input signals.+zip4SY	     :: Signal a -> Signal b -> Signal c -> Signal d +		-> Signal (a,b,c,d)+zip4SY (w:-ws) (x:-xs) (y:-ys) (z:-zs) = (w, x, y, z) +					 :- zip4SY ws xs ys zs+zip4SY _	_      _	_      = NullS++-- | The process 'zip5SY' works as 'zipSY', but takes four input signals.+zip5SY	     :: Signal a -> Signal b -> Signal c -> Signal d -> Signal e+		-> Signal (a,b,c,d,e)+zip5SY (x1:-x1s) (x2:-x2s) (x3:-x3s) (x4:-x4s) (x5:-x5s) +    = (x1,x2,x3,x4,x5) :- zip5SY x1s x2s x3s x4s x5s+zip5SY _	 _         _	     _         _ = NullS++-- | The process 'zip6SY' works as 'zipSY', but takes four input signals.+zip6SY	     :: Signal a -> Signal b -> Signal c -> Signal d -> Signal e+             -> Signal f -> Signal (a,b,c,d,e,f)+zip6SY (x1:-x1s) (x2:-x2s) (x3:-x3s) (x4:-x4s) (x5:-x5s)  (x6:-x6s) +    = (x1,x2,x3,x4,x5,x6) :- zip6SY x1s x2s x3s x4s x5s x6s+zip6SY _	 _         _	     _         _          _ = NullS++-- | The process 'unzipSY' \"unzips\" a signal of tuples into two signals.+unzipSY      :: Signal (a,b) -> (Signal a,Signal b)+unzipSY NullS	     = (NullS, NullS)+unzipSY ((x, y):-xys) = (x:-xs, y:-ys) where (xs, ys) = unzipSY xys++-- | The process 'unzip3SY' works as 'unzipSY', but has three output signals.+unzip3SY     :: Signal (a, b, c) -> (Signal a, Signal b, Signal c)+unzip3SY NullS             = (NullS, NullS, NullS)+unzip3SY ((x, y, z):-xyzs) = (x:-xs, y:-ys, z:-zs) where+  			     (xs, ys, zs) = unzip3SY xyzs++-- | The process 'unzip4SY' works as 'unzipSY', but has four output signals.+unzip4SY     :: Signal (a,b,c,d) +		-> (Signal a,Signal b,Signal c,Signal d)+unzip4SY NullS              = (NullS, NullS, NullS, NullS)+unzip4SY ((w,x,y,z):-wxyzs) = (w:-ws, x:-xs, y:-ys, z:-zs) where+  			      (ws, xs, ys, zs) = unzip4SY wxyzs++-- | The process 'unzip5SY' works as 'unzipSY', but has four output signals.+unzip5SY     :: Signal (a,b,c,d,e) +		-> (Signal a,Signal b,Signal c,Signal d,Signal e)+unzip5SY NullS              = (NullS, NullS, NullS, NullS,NullS)+unzip5SY ((x1,x2,x3,x4,x5):-xs) = (x1:-x1s, x2:-x2s, x3:-x3s, x4:-x4s, x5:-x5s)+    where (x1s, x2s, x3s, x4s,x5s) = unzip5SY xs++-- | The process 'unzip6SY' works as 'unzipSY', but has four output signals.+unzip6SY     :: Signal (a,b,c,d,e,f) +		-> (Signal a,Signal b,Signal c,Signal d,Signal e,Signal f)+unzip6SY NullS              = (NullS, NullS, NullS, NullS,NullS,NullS)+unzip6SY ((x1,x2,x3,x4,x5,x6):-xs) +    = (x1:-x1s, x2:-x2s, x3:-x3s, x4:-x4s, x5:-x5s, x6:-x6s)+    where (x1s, x2s, x3s, x4s, x5s, x6s) = unzip6SY xs++-- | The process 'zipxSY' \"zips\" a signal of vectors into a vector of signals.+zipxSY       :: Vector (Signal a) -> Signal (Vector a)+zipxSY NullV            = NullS+zipxSY (NullS   :> xss) = zipxSY xss+zipxSY ((x:-xs) :> xss) = (x :> (mapV headS xss)) + 			     :- (zipxSY (xs :> (mapV tailS xss)))++-- | The process 'unzipxSY' \"unzips\" a vector of signals into a signal of vectors.+unzipxSY     :: Signal (Vector a) -> Vector (Signal a)+unzipxSY NullS            = NullV+unzipxSY (NullV   :- vss) = unzipxSY vss+unzipxSY ((v:>vs) :- vss) = (v :- (mapSY headV vss)) + 			    :> (unzipxSY (vs :- (mapSY tailV vss)))++-- | The process 'fstSY' selects always the first value from a signal of pairs.+fstSY        :: Signal (a,b) -> Signal a+fstSY = mapSY fst		  ++-- | The process 'sndSY' selects always the second value from a signal of pairs.+sndSY        :: Signal (a,b) -> Signal b+sndSY = mapSY snd+
+ src/ForSyDe/Shallow/SynchronousProcessLib.hs view
@@ -0,0 +1,115 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.SynchronousProcessLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The synchronous process library defines processes for the+-- synchronous computational model. It is based on the synchronous+-- library "ForSyDe.Shallow.SynchronousLib".+-----------------------------------------------------------------------------+module ForSyDe.Shallow.SynchronousProcessLib(+			       fifoDelaySY, finiteFifoDelaySY,+			       memorySY, mergeSY, groupSY, counterSY+			     ) where++import ForSyDe.Shallow.SynchronousLib+import ForSyDe.Shallow.CoreLib+import ForSyDe.Shallow.Queue+import ForSyDe.Shallow.Memory++-- | The process 'fifoDelaySY' implements a synchronous model of a+-- FIFO with infinite size. The FIFOs take a list of values at each+-- event cycle and output one value. There is a delay of one cycle.+fifoDelaySY		:: Signal [a] -> Signal (AbstExt a)++-- | The process 'finiteFifoDelaySY' implements a FIFO with finite+-- size. The FIFOs take a list of values at each event cycle and+-- output one value. There is a delay of one cycle.+finiteFifoDelaySY	:: Int -> Signal [a] -> Signal (AbstExt a)++-- | The process 'memorySY' implements a synchronous memory. It uses+-- access functions of the type 'Read adr' and 'Write adr value'.+memorySY		:: Int -> Signal (Access a) -> Signal (AbstExt a) ++-- | The process 'mergeSY' merges two input signals into a single+-- signal. The process has an internal buffer in order to prevent loss+-- of data. The process is deterministic and outputs events according+-- to their time tag. If there are two valid values at on both+-- signals. The value of the first signal is output first.+mergeSY			:: Signal (AbstExt a) -> Signal (AbstExt a) +			   -> Signal (AbstExt a)++-- | The process 'counterSY' implements a counter, that counts from+--   min to max. The process 'counterSY' has no input and its output is+--   an infinite signal.+counterSY		:: (Enum a, Ord a) => a -> a -> Signal a++-- | The function 'groupSY' groups values into a vector of size n,+-- which takes n cycles. While the grouping takes place the output+-- from this process consists of absent values.+groupSY :: Int -> Signal a -> Signal (AbstExt (Vector a))++fifoDelaySY xs		=  mooreSY fifoState fifoOutput (queue []) xs++fifoState		:: Queue a -> [a] -> Queue a+fifoState (Q []) xs	=  (Q xs)+fifoState q xs		=  fst (popQ (pushListQ q xs))++fifoOutput		:: Queue a -> AbstExt a+fifoOutput (Q [])	=  Abst+fifoOutput (Q (x:_))	=  Prst x++finiteFifoDelaySY n xs	+   = mooreSY fifoStateFQ fifoOutputFQ (finiteQueue n []) xs++fifoStateFQ :: FiniteQueue a -> [a] -> FiniteQueue a+fifoStateFQ (FQ n []) xs =  (FQ n xs)+fifoStateFQ q xs	 =  fst (popFQ (pushListFQ q xs))++fifoOutputFQ :: FiniteQueue a -> AbstExt a+fifoOutputFQ (FQ _ [])	  =  Abst+fifoOutputFQ (FQ _ (x:_)) =  Prst x++memorySY size xs	=  mealySY ns o (newMem size) xs+  where +     ns mem (Read x)	=  memState mem (Read x)+     ns mem (Write x v)	=  memState mem (Write x v)+     o mem (Read x)	=  memOutput mem (Read x)+     o mem (Write x v)	=  memOutput mem (Write x v)+++mergeSY xs ys		=  moore2SY mergeState mergeOutput [] xs ys+   where +	 mergeState []      Abst     Abst    = []+         mergeState []	    Abst    (Prst y) = [y]+         mergeState []     (Prst x)  Abst    = [x]+         mergeState []     (Prst x) (Prst y) = [x, y]+         mergeState (_:us)  Abst     Abst    = us+	 mergeState (_:us)  Abst    (Prst y) = us ++ [y]+	 mergeState (_:us) (Prst x)  Abst    = us ++ [x]+         mergeState (_:us) (Prst x) (Prst y) = us ++ [x, y]++	 mergeOutput []	    = Abst+         mergeOutput (u:_) = Prst u	++groupSY k = mealySY f g s0 +  where+    s0 = NullV+    f v x | (lengthV v) == 0 = unitV x+	  | (lengthV v) == k = unitV x +	  | otherwise        = v <: x+    g v _ | (lengthV v) == 0   = Abst+    g v x | (lengthV v) == k-1 = Prst (v<:x)+    g _ _ | otherwise          = Abst+      +counterSY m n = sourceSY f m+  where +    f x | x >= n    = m+	| otherwise = succ x++
+ src/ForSyDe/Shallow/UntimedLib.hs view
@@ -0,0 +1,200 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.UntimedLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The untimed library defines process constructors and processes for+-- the untimed computational model. A process constructor is a higher+-- order function which together with combinational function(s) and+-- values as arguments constructs a process.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.UntimedLib(  +                    -- * Combinational process constructors+		    -- | Combinational process constructors are used for processes that do not have a state.+                    combU, comb2U, comb2UC,+		    mapU,+           	    -- * Sequential process constructors+		    -- | Sequential process constructors are used for processes that have a state. One of the input parameters is the initial state.+                    scanU, mealyU, mooreU, sourceU, sinkU, initU,+		    -- * Zipping and unzipping signals+		    zipU, zipUs,+		    zipWithU, zipWith3U, zipWith4U,+		    unzipU+                  )+where++import ForSyDe.Shallow.CoreLib++----------------------------------------+--                                    --+-- COMBINATIONAL PROCESS CONSTRUCTORS --+--                                    --+----------------------------------------++combU :: Int -> ([a] -> [b]) -> Signal a -> Signal b+combU = mapU++comb2U :: Int -> Int -> ([a]->[b]->[c]) -> Signal a -> Signal b -> Signal c+comb2U = zipWithU++comb2UC :: Int -> (a->[b]->[c]) -> Signal a -> Signal b -> Signal c+comb2UC = zipWithUC++-- | The first parameter of 'mapU' is a constant integer defining the number of tokens consumed in every evaluation cycle. The second argument is a function on lists of the input type and returning a list of the output type. For instance,+--+-- > r2 = mapU 1 f+-- >   where f :: [Int] -> [Int]+-- >         f [x] = [2*x]+--+-- defines a process r2 which consumes one token in each evaluation cycle and multiplies it by two.+mapU :: Int -> ([a] -> [b]) -> Signal a -> Signal b+mapU _ _ NullS = NullS+mapU c f xs | lengthS (takeS c xs) < c = NullS+            | otherwise+	      = signal (f (takeL c xs)) +-+ (mapU c f (dropS c xs))+	      +--mapUC :: Int -> ([a] -> b) -> Signal a -> Signal b+--mapUC _ _ NullS = NullS+--mapUC c f xs | lengthS (takeS c xs) < c = NullS+--             | otherwise +--	       =  signal [(f (takeL c xs))] +-+ (mapUC c f (dropS c xs))++---------------------------+--                       --+-- SYNCHRONOUS PROCESSES --+--                       --+---------------------------++-- | 'scanU' has an internal state which is visible at the output. The first argument is a function \'gamma\' which, given the state returns the number of tokens consumed next. The second argument is the next state function and the third is the initial state.+scanU :: (b->Int) -> (b->[a]->b) -> b -> Signal a -> Signal b+scanU _     _ _     NullS = NullS+scanU gamma g state xs +    | length as == c = newstate :- scanU gamma g newstate (dropS c xs)+    | otherwise       = NullS+    where c        = gamma state+	  as       = takeL c xs+	  newstate = g state as++++-- | The process constructor 'mooreU' creates a state machine of Moore type. In addition to the next state function they also have an output encoding function. The output depends directly on the internal state.+mooreU :: (b->Int) -> (b->[a]->b) -> (b -> [c]) -> b -> Signal a -> Signal c+mooreU _ _ _ _ NullS = NullS+mooreU gamma g f state xs+    | length as == c = (signal bs) +-+ mooreU gamma g f newstate (dropS c xs)+    | otherwise      = NullS+    where c        = gamma state+	  as       = takeL c xs+	  newstate = g state as +	  bs       = f state++-- | The process constructor 'mealyU' creates a state machine of Moore type. In addition to the next state function they also have an output encoding function. The output depends directly on the internal state.+mealyU :: (b->Int) -> (b->[a]->b) -> (b -> [a] -> [c]) -> b +       -> Signal a -> Signal c+mealyU _ _ _ _ NullS = NullS+mealyU gamma g f state xs+    | length as == c = (signal bs) +		       +-+ mealyU gamma g f newstate (dropS c xs)+    | otherwise      = NullS+    where c        = gamma state+	  as       = takeL c xs+	  newstate = g state as+	  bs       = f state as+++zipU  :: Signal (Int,Int) -> Signal a -> Signal b -> Signal ([a],[b])+zipU NullS _ _ = NullS+zipU _ NullS _ = NullS+zipU _ _ NullS = NullS+zipU ((c1,c2):-cs) xs ys+     | lengthS (takeS c1 xs) == c1 && lengthS (takeS c2 ys) == c2+       = (takeL c1 xs,takeL c2 ys) :- zipU cs (dropS c1 xs) (dropS c2 ys)+     | otherwise = NullS++zipUs :: Int -> Int ->       Signal a -> Signal b -> Signal ([a],[b])+zipUs _ _ NullS _ = NullS +zipUs _ _ _ NullS = NullS +zipUs c1 c2 xs ys +      | lengthS (takeS c1 xs) == c1 && lengthS (takeS c2 ys) == c2+        = (takeL c1 xs,takeL c2 ys) +	  :- zipUs c1 c2 (dropS c1 xs) (dropS c2 ys)+      | otherwise = NullS++zipWithU :: Int -> Int -> ([a]->[b]->[c]) -> Signal a -> Signal b -> Signal c+zipWithU _ _ _ NullS _     = NullS+zipWithU _ _ _ _     NullS = NullS+zipWithU c1 c2 f xs ys +	 | lengthS (takeS c1 xs) == c1 && lengthS (takeS c2 ys) == c2+	   = signal (f (takeL c1 xs) (takeL c2 ys))+	     +-+ zipWithU c1 c2 f (dropS c1 xs) (dropS c2 ys)+         | otherwise = NullS++zipWithUC :: Int -> (a->[b]->[c]) -> Signal a -> Signal b -> Signal c+zipWithUC _ _ NullS _ = NullS+zipWithUC _ _ _ NullS = NullS+zipWithUC c1 f xs ys+	 | lengthS (takeS 1 xs) == 1 && lengthS (takeS c1 ys) == c1+	   = signal (f (headS xs) (takeL c1 ys))+	     +-+ zipWithUC c1 f (tailS xs) (dropS c1 ys)+         | otherwise = NullS++zipWith3U :: Int -> Int -> Int -> ([a]->[b]->[c]->[d]) -> Signal a -> Signal b -> Signal c -> Signal d+zipWith3U _ _ _ _ NullS _ _ = NullS+zipWith3U _ _ _ _ _ NullS _ = NullS+zipWith3U _ _ _ _ _ _ NullS = NullS+zipWith3U c1 c2 c3 f xs ys zs+	 | lengthS (takeS c1 xs) == c1 && lengthS (takeS c2 ys) == c2 && lengthS (takeS c3 zs) == c3+	   = signal (f (takeL c1 xs) (takeL c2 ys) (takeL c3 zs))+	     +-+ zipWith3U c1 c2 c3 f (dropS c1 xs) (dropS c2 ys) (dropS c3 zs)+         | otherwise = NullS+         +zipWith4U :: Int -> Int -> Int -> Int -> ([a]->[b]->[c]->[d]->[e]) ->+               Signal a -> Signal b -> Signal c -> Signal d -> Signal e+zipWith4U _ _ _ _ _ NullS _ _ _= NullS+zipWith4U _ _ _ _ _ _ NullS _ _ = NullS+zipWith4U _ _ _ _ _ _ _ NullS _ = NullS+zipWith4U _ _ _ _ _ _ _ _ NullS = NullS+zipWith4U c1 c2 c3 c4 f xs ys zs as+	 | lengthS (takeS c1 xs) == c1 && lengthS (takeS c2 ys) == c2 +           && lengthS (takeS c3 zs) == c3 && lengthS (takeS c4 as) == c4+	   = signal (f (takeL c1 xs) (takeL c2 ys) (takeL c3 zs) (takeL c4 as))+	     +-+ zipWith4U c1 c2 c3 c4 f (dropS c1 xs) (dropS c2 ys) (dropS c3 zs) (dropS c4 as)+         | otherwise = NullS++unzipU :: Signal ([a],[b]) -> (Signal a,Signal b)+unzipU NullS = (NullS,NullS)+unzipU ((as,bs):-xs) = (signal as +-+ ass, +		        signal bs +-+ bss)+		     where (ass,bss) = unzipU xs++sourceU :: (a->a) -> a -> Signal a+sourceU g state = newstate :- sourceU g newstate+		where newstate = g state++sinkU :: (a->Int) -> (a->a) -> a -> Signal b -> Signal b+sinkU _ _ _ NullS = NullS+sinkU gamma g state xs +      |  length as == c = sinkU gamma g newstate (dropS c xs)+      | otherwise      = NullS+      where as       = takeL c xs+	    c        = gamma state+	    newstate = g state+++-- | 'initU' is used to initialise a signal. Its first argument is prepended to its second argument, a signal.+initU ::  [a] -> Signal a -> Signal a+initU initial s = (signal initial) +-+ s++takeL :: Int -> Signal a -> [a]+takeL c = fromSignal . (takeS c)++++++
+ src/ForSyDe/Shallow/UtilityLib.hs view
@@ -0,0 +1,54 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.UtilityLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- The ForSyDeUtilityLib is a container including all libraries that+-- are related to the ForSyDe shallow-embedded implementation and+-- either extend the ForSyDe MoC libraries or add additional+-- functionality to ForSyDe.+-- +-- * "ForSyDe.Shallow.DFT"+-- +-- * "ForSyDe.Shallow.Memory"+-- +-- * "ForSyDe.Shallow.Queue"+-- +-- * "ForSyDe.Shallow.BitVector"+--+-- * "ForSyDe.Shallow.FilterLib"+-- +-- * "ForSyDe.Shallow.Gaussian"		+-- +-- * "ForSyDe.Shallow.PolyArith"		+--+-- * "ForSyDe.Shallow.StochasticLib"+-----------------------------------------------------------------------------+module ForSyDe.Shallow.UtilityLib(  +                      module ForSyDe.Shallow.DFT,            +                      module ForSyDe.Shallow.Memory,+                      module ForSyDe.Shallow.Queue+                      --module ForSyDe.Shallow.Combinators    +	              --module ForSyDe.Shallow.BitVector+                      --module ForSyDe.Shallow.FilterLib,+		      --module ForSyDe.Shallow.Gaussian,+		      --module ForSyDe.Shallow.PolyArith,+		      --module ForSyDe.Shallow.StochasticLib+		    ) where++import ForSyDe.Shallow.DFT          +import ForSyDe.Shallow.Memory+import ForSyDe.Shallow.Queue+--import ForSyDe.Shallow.Combinators+--import ForSyDe.Shallow.BitVector+--import ForSyDe.Shallow.FilterLib+--import ForSyDe.Shallow.Gaussian+--import ForSyDe.Shallow.PolyArith+--import ForSyDe.Shallow.StochasticLib++
+ src/ForSyDe/Shallow/Vector.hs view
@@ -0,0 +1,398 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Shallow.Vector+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module defines the data type 'Vector' and the+-- corresponding functions. It is a development of the module+-- defined by Reekie.  Though the vector is modeled as a list, it+-- should be viewed as an array, i.e. a vector has a fixed+-- size. Unfortunately, it is not possible to have the size of the+-- vector as a parameter of the vector data type, due to restrictions+-- in Haskells type system. Still most operations are defined for+-- vectors with the same size.+-----------------------------------------------------------------------------+module ForSyDe.Shallow.Vector ( +              Vector (..), vector, fromVector, unitV, nullV, lengthV,+              atV, replaceV, headV, tailV, lastV, initV, takeV, dropV, +	      selectV, groupV, (<+>), (<:), mapV, foldlV, foldrV, +	      -- scanlV, scanrV, meshlV, meshrV, +	      zipWithV, filterV, zipV, unzipV, +	      concatV, reverseV, shiftlV, shiftrV, rotrV, rotlV, +	      generateV, iterateV, copyV --, serialV, parallelV +	      )+       where++infixr 5 :>+infixl 5 <:+infixr 5 <+>++-- | The data type 'Vector' is modeled similar to a list. It has two data type constructors. 'NullV' constructs the empty vector, while ':>' constructsa vector by adding an value to an existing vector. Using the inheritance mechanism of Haskell we have declared 'Vector' as an instance of the classes 'Read' and 'Show'.+--+-- | This means that the vector 1:>2:>3:>NullV is shown as <1,2,3>.+data Vector a = NullV+              | a :> (Vector a) deriving (Eq)++-- | The function 'vector' converts a list into a vector.+vector     :: [a] -> Vector a++-- | The function 'fromVector' converts a vector into a list.+fromVector :: Vector a -> [a]++-- | The function 'unitV' creates a vector with one element. +unitV    :: a -> Vector a++-- | The function 'nullV' returns 'True' if a vector is empty. +nullV    :: Vector a -> Bool++-- | The function 'lengthV' returns the number of elements in a value. +lengthV  :: Vector a -> Int++-- | The function 'atV' returns the n-th element in a vector, starting from zero.+atV      :: Num a => Vector b -> a -> b++-- |  The function 'replaceV' replaces an element in a vector.+replaceV :: Vector a -> Int -> a -> Vector a++-- | The functions 'headV' returns the first element of a vector.+headV :: Vector a -> a++-- | The function 'lastV' returns the last element of a vector.+lastV :: Vector a -> a++-- | The functions 'tailV' returns all, but the first element of a vector.+tailV :: Vector a -> Vector a ++-- | The function 'initV' returns all but the last elements of a vector.+initV :: Vector a -> Vector a ++-- | The function 'takeV' returns the first n elements of a vector.+takeV :: (Num a, Ord a) => a -> Vector b -> Vector b++-- | The function 'dropV' drops the first n elements of a vector.+dropV :: (Num a, Ord a) => a -> Vector b -> Vector b++++-- | The function 'selectV' selects elements in the vector. The first argument gives the initial element, starting from zero, the second argument gives the stepsize between elements and the last argument gives the number of elements. +selectV :: Int -> Int -> Int -> Vector a -> Vector a+++-- | The function 'groupV' groups a vector into a vector of vectors of size n.+groupV :: Int -> Vector a -> Vector (Vector a)++-- | The operator '(<:)' adds an element at the end of a vector.+(<:)  :: Vector a -> a -> Vector a++-- | The operator '(<+>)' concatinates two vectors.+(<+>) :: Vector a -> Vector a -> Vector a+++++-- | The higher-order function 'mapV' applies a function on all elements of a vector.+mapV :: (a -> b) -> Vector a -> Vector b    +++-- | The higher-order function 'zipWithV' applies a function pairwise on to vectors.+zipWithV :: (a -> b -> c) -> Vector a -> Vector b -> Vector c+++-- | The higher-order functions 'foldlV' folds a function from the right to the left  over a vector using an initial value.+foldlV :: (a -> b -> a) -> a -> Vector b -> a ++-- | The higher-order functions 'foldrV' folds a function from the left to the right over a vector using an initial value.+foldrV :: (b -> a -> a) -> a -> Vector b -> a++-- | The higher-function 'filterV' takes a predicate function and a vector and creates a new vector with the elements for which the predicate is true. +filterV :: (a -> Bool) -> Vector a -> Vector a++-- | The function 'zipV' zips two vectors into a vector of tuples.+zipV   :: Vector a -> Vector b -> Vector (a, b)++-- | The function 'unzipV' unzips a vector of tuples into two vectors.+unzipV :: Vector (a, b) -> (Vector a, Vector b)++++-- | The function 'shiftlV' shifts a value from the left into a vector. +shiftlV :: Vector a -> a-> Vector a ++-- | The function 'shiftrV' shifts a value from the right into a vector. +shiftrV :: Vector a -> a -> Vector a++-- | The function 'rotlV' rotates a vector to the left. Note that this fuctions does not change the size of a vector.+rotlV   :: Vector a -> Vector a++-- | The function 'rotrV' rotates a vector to the right. Note that this fuction does not change the size of a vector.+rotrV   :: Vector a -> Vector a+++-- | The function 'concatV' transforms a vector of vectors to a single vector. +concatV   :: Vector (Vector a) -> Vector a++-- | The function 'reverseV' reverses the order of elements in a vector. +reverseV  :: Vector a -> Vector a+++-- | The function 'iterateV' generates a vector with a given number of elements starting from an initial element using a supplied function for the generation of elements. +--+-- > Vector> iterateV 5 (+1) 1+--+-- > <1,2,3,4,5> :: Vector Integer+iterateV :: Num a => a -> (b -> b) -> b -> Vector b++-- | The function 'generateV' behaves in the same way, but starts with the application of the supplied function to the supplied value. +--+-- > Vector> generateV 5 (+1) 1+-- +-- > <2,3,4,5,6> :: Vector Integer+generateV :: Num a => a -> (b -> b) -> b -> Vector b++-- | The function 'copyV' generates a vector with a given number of copies of the same element. +--+-- > Vector> copyV 7 5 +-- +-- > <5,5,5,5,5,5,5> :: Vector Integer+copyV     :: Num a => a -> b -> Vector b+++{-+-- | The function 'serialV' can be used to construct a serial network of processes.++--|The function \haskell{serialV} and \haskell{parallelV} can be used to construct serial and parallel networks of processes.+\begin{code}+serialV		:: Vector (a -> a) -> a -> a+parallelV	:: Vector (a -> b) -> Vector a -> Vector b+\end{code}++The functions \haskell{scanlV} and \haskell{scanrV} "scan" a function through a vector. The functions take an initial element apply a functions recursively first on the element and then on the result of the function application.+%+\begin{code}+scanlV    :: (a -> b -> a) -> a -> Vector b -> Vector a +scanrV    :: (b -> a -> a) -> a -> Vector b -> Vector a+\end{code}++\index{scanlV@\haskell{scanlV}}+\index{scanrV@\haskell{scanrV}}++Reekie also proposed the \haskell{meshlV} and \haskell{meshrV} iterators. They are like a combination of \haskell{mapV} and \haskell{scanlV} or \haskell{scanrV}. The argument function supplies a pair of values: the first is input into the next application of this function, and the second is the output value. As an example consider the expression:+%+\begin{code}+f x y = (x+y, x+y)++s1 = vector [1,2,3,4,5]+\end{code}+%+Here \haskell{meshlV} can be used to calculate the running sum. +%+\begin{verbatim}+Vector> meshlV f 0 s1+(15,<1,3,6,10,15>)+\end{verbatim}++\begin{code}+meshlV    :: (a -> b -> (a, c)) -> a -> Vector b -> (a, Vector c)+meshrV    :: (a -> b -> (c, b)) -> b -> Vector a -> (Vector c, b)+\end{code}++\index{meshlV@\haskell{meshlV}}+\index{meshrV@\haskell{meshrV}}+-}++instance (Show a) => Show (Vector a) where+       showsPrec p NullV = showParen (p > 9) (+                             showString "<>")+       showsPrec p xs    = showParen (p > 9) (+                             showChar '<' . showVector1 xs)+                           where+                              showVector1 NullV+                                 = showChar '>'                            +                              showVector1 (y:>NullV) +                                 = shows y . showChar '>'+                              showVector1 (y:>ys)    +                                 = shows y . showChar ',' +					   . showVector1 ys+++instance Read a => Read (Vector a) where+       readsPrec _ s = readsVector s++readsVector :: (Read a) => ReadS (Vector a)+readsVector s = [((x:>NullV), rest) | ("<", r2) <- lex s,+                                    (x, r3)   <- reads r2,+                                    (">", rest) <- lex r3]+               +++              [(NullV, r4)        | ("<", r5) <- lex s,+                                    (">", r4) <- lex r5]+               +++              [((x:>xs), r6)      | ("<", r7) <- lex s,+                                    (x, r8)   <- reads r7,+                                    (",", r9) <- lex r8,+                                    (xs, r6) <- readsValues r9]++readsValues :: (Read a) => ReadS (Vector a)+readsValues s = [((x:>NullV), r1) | (x, r2)   <- reads s,+                                  (">", r1) <- lex r2]+              +++              [((x:>xs), r3)    | (x, r4)   <- reads s,+                                  (",", r5) <- lex r4,+                                  (xs, r3)  <- readsValues r5]++vector []     = NullV+vector (x:xs) = x :> (vector xs)++fromVector NullV   = []+fromVector (x:>xs) = x : fromVector xs++unitV x = x :> NullV++nullV NullV   = True+nullV _             = False++lengthV NullV   = 0+lengthV (_:>xs) = 1 + lengthV xs++replaceV vs n x +    | n <= lengthV vs && n >= 0 = takeV n vs <+> unitV x +					     <+> dropV (n+1) vs+    | otherwise                 =  vs++NullV   `atV` _ = error "atV: Vector has not enough elements"+(x:>_)  `atV` 0 = x+(_:>xs) `atV` n = xs `atV` (n-1)++headV NullV   = error "headV: Vector is empty"+headV (v:>_) = v++tailV NullV   = error "tailV: Vector is empty"+tailV (_:>vs) = vs++lastV NullV      = error "lastV: Vector is empty"+lastV (v:>NullV) = v+lastV (_:>vs)    = lastV vs++initV NullV      = error "initV: Vector is empty"+initV (_:>NullV) = NullV+initV (v:>vs)    = v :> initV vs++takeV 0 _                   = NullV+takeV _ NullV               = NullV+takeV n (v:>vs) | n <= 0    = NullV+                | otherwise = v :> takeV (n-1) vs++dropV 0 vs                  = vs+dropV _ NullV               = NullV+dropV n (v:>vs) | n <= 0    = v :> vs+                | otherwise = dropV (n-1) vs++selectV f s n vs | n <= 0               +                     = NullV+                 | (f+s*n-1) > lengthV vs +                    = error "selectV: Vector has not enough elements"+                 | otherwise            +                    = atV vs f :> selectV (f+s) s (n-1) vs++groupV n v +      | lengthV v < n = NullV+      | otherwise     = selectV 0 1 n v +			:> groupV n (selectV n 1 (lengthV v-n) v)++NullV <+> ys   = ys+(x:>xs) <+> ys = x :> (xs <+> ys) ++xs <: x = xs <+> unitV x         ++mapV _ NullV   = NullV+mapV f (x:>xs) = f x :> mapV f xs++zipWithV f (x:>xs) (y:>ys) = f x y :> (zipWithV f xs ys)+zipWithV _ _       _       = NullV++foldlV _ a NullV   = a+foldlV f a (x:>xs) = foldlV f (f a x) xs++foldrV _ a NullV   = a +foldrV f a (x:>xs) = f x (foldrV f a xs)++filterV _ NullV   = NullV+filterV p (v:>vs) = if (p v) then+                     v :> filterV p vs+                  else +                     filterV p vs++zipV (x:>xs) (y:>ys) = (x, y) :> zipV xs ys+zipV _       _       = NullV++unzipV NullV           = (NullV, NullV)+unzipV ((x, y) :> xys) = (x:>xs, y:>ys) +			 where (xs, ys) = unzipV xys++shiftlV vs v = v :> initV vs++shiftrV vs v = tailV vs <: v++rotrV NullV = NullV+rotrV vs    = tailV vs <: headV vs++rotlV NullV = NullV+rotlV vs    = lastV vs :> initV vs++concatV = foldrV (<+>) NullV++reverseV NullV   = NullV+reverseV (v:>vs) = reverseV vs <: v++generateV 0 _ _ = NullV+generateV n f a = x :> generateV (n-1) f x +                where x = f a++iterateV 0 _ _ = NullV+iterateV n f a = a :> iterateV (n-1) f (f a)++copyV k x = iterateV k id x ++{-+serialV  fs      x = serialV' (reverseV fs ) x+  where+    serialV' NullV   x = x+    serialV' (f:>fs) x = serialV fs (f x)+++parallelV NullV   NullV   = NullV+parallelV _	  NullV   +   = error "parallelV: Vectors have not the same size!"+parallelV NullV	  _       +   = error "parallelV: Vectors have not the same size!"+parallelV (f:>fs) (x:>xs) = f x :> parallelV fs xs++scanlV _ _ NullV   = NullV+scanlV f a (x:>xs) = q :> scanlV f q xs +                   where q = f a x++scanrV _ _ NullV      = NullV+scanrV f a (x:>NullV) = f x a :> NullV+scanrV f a (x:>xs)    = f x y :> ys +                      where ys@(y:>_) = scanrV f a xs++meshlV _ a NullV   = (a, NullV)+meshlV f a (x:>xs) = (a'', y:>ys) +                   where (a', y)   = f a x+                         (a'', ys) = meshlV f a' xs++meshrV _ a NullV    = (NullV, a)+meshrV f a (x:>xs)  = (y:>ys, a'') +                    where (y, a'') = f x a'+                          (ys, a') = meshrV f a xs+-}++++++
+ src/ForSyDe/Signal.hs view
@@ -0,0 +1,30 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.Signal+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+--  +-- This module provides the fundamental data structure for deep-embedded +-- ForSyDe models: 'Signal'.+--+-----------------------------------------------------------------------------+++-- This module is simply used to export Signal to the end user hiding its internal +-- representation+module ForSyDe.Signal (Signal)  where+++import ForSyDe.Netlist (Signal)++++           +++
+ src/ForSyDe/System.hs view
@@ -0,0 +1,24 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides publicly usable functions to build a system definition+-- and instantiate it.+-- +-----------------------------------------------------------------------------+module ForSyDe.System  +(SysDef, newSysDef, newSysDefTH, newSysDefTHName,+ SysFun, SysFunToSimFun, SysFunToIOSimFun,+ instantiate)+where++import ForSyDe.System.SysDef (SysDef, newSysDef, newSysDefTH, newSysDefTHName)+import ForSyDe.System.SysFun (SysFun, SysFunToSimFun, SysFunToIOSimFun)+import ForSyDe.System.SysFun.Instances ()+import ForSyDe.System.Instantiate (instantiate)
+ src/ForSyDe/System/Instantiate.hs view
@@ -0,0 +1,44 @@+{-# LANGUAGE TemplateHaskell #-} +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System.Instantiate+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides instantiation capabilities to System Definitions+-- ('SysDef's).through a  Template-Haskell-based function: 'instantiate'.+--+-- Thanks to 'instantiate' ForSyDe models have hierarchy capabilities.+--+-----------------------------------------------------------------------------+module ForSyDe.System.Instantiate (instantiate) where++import ForSyDe.Ids (ProcId)+import ForSyDe.OSharing (readURef)+import ForSyDe.Netlist+import ForSyDe.System.SysDef (SysDef)+import ForSyDe.System.SysFun (SysFun(fromListSysFun))+++++-- | Generates an instance of a 'SysDef' in the form of  +--   function out of the name of a 'SysDef' with the same type as its +--   system function. The resulting function can then be used to plug the +--   instance to the rest of the system.+instantiate :: SysFun f => ProcId -> SysDef f -> f+instantiate id sysDef = fromListSysFun (instantiateList id sysDef) []+++-------------------+-- Helper Functions+-------------------++instantiateList :: ProcId -> SysDef a -> [NlSignal] -> [NlSignal]+instantiateList id sysDef inSigs = map (\t -> newNodeOutSig instanceSig t) tags +   where instanceSig = newSysIns id sysDef inSigs +         tags = outTags $ readURef instanceSig
+ src/ForSyDe/System/SysDef.hs view
@@ -0,0 +1,405 @@+{-# LANGUAGE TemplateHaskell #-} +-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System.SysDef+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides the System Definition type ('SysDef') together with+-- a Template Haskell constructor to build it. +--+-----------------------------------------------------------------------------+module ForSyDe.System.SysDef +  (SysDef(..),+   PrimSysDef(..),+   SysDefVal(..), +   SysLogic(..),+   newSysDef,+   newSysDefTH,+   newSysDefTHName,+   Iface) where++import ForSyDe.Ids+import ForSyDe.Netlist +import ForSyDe.Netlist.Traverse+import ForSyDe.OSharing+import ForSyDe.ForSyDeErr+import ForSyDe.System.SysFun (checkSysFType, SysFun(..))++import Data.Maybe (isJust, fromJust)+import Control.Monad.Error+import Control.Monad.ST+import Control.Monad.State+import Data.Typeable+import Language.Haskell.TH+import Language.Haskell.TH.LiftInstances ()++++++-- | Interface, describes the input or output ports of the system.+--   Each entry contains the name of the port and its type.+type Iface = [(PortId, TypeRep)]+++-- | We add a phantom parameter to indicate the type of the system +newtype SysDef a = SysDef {unSysDef :: PrimSysDef}++-- | The Primitive System Definition.+--   Instead of just providing the value, a reference is provided+--   to allow sharing between instances.+newtype PrimSysDef = PrimSysDef {unPrimSysDef :: URef SysDefVal}++++-- | Indicates wether a system is combinational or sequential+--   In practice, a system is sequential if if contains a delay process or+--   a sequential system instance, otherwise its combinational.+data SysLogic = Combinational | Sequential+ deriving (Eq, Show)+++-- | The System Definition value+data SysDefVal = SysDefVal +     {sid     :: SysId,        -- ^ Identifier of the System +      netlist :: Netlist [],   -- ^ System netlist+      subSys  :: [PrimSysDef], -- ^ List of all unique nested subsystems+                               --   (i.e. flattened tree, without duplicates,+                               --    of all the systems in lower levels of the +                               --    hierarchy)+      logic   :: SysLogic,     -- ^ 'SysLogic' of the system +                                          +      iIface  :: Iface,        -- ^ Input  interface+      oIface  :: Iface,        -- ^ Output interface +      loc     :: Maybe Loc}    -- ^ Location of the call to newSysDef+                               --   which created this System definition+                               --   (used for later error reporting)+                               --   It will initialized or not depending+                               --   on the newSysDef* function used++++-- | 'SysDef' constructor+--+--   Builds a system definition out of a system function describing the system +--   and its port identifers.   +newSysDef :: SysFun f => f -- ^ system function +                      -> SysId    -- ^ System identifier +                      -> [PortId] -- ^ Input interface port identifiers +                      -> [PortId] -- ^ Output interface port identifiers +                      -> SysDef f+newSysDef f sysId inIds outIds = either currError id eProneResult+ where currError = uError "newSysDef"+       eProneResult = newSysDefEProne f Nothing sysId inIds outIds++-- | CURRENTLY BROKEN, do not use!+--+--  'SysDef' constructor, Template Haskell version+--+--   Builds a system definition out of a system function, a system identifiers +--   and its port identifers.+--+--  For example @$(newSysDefTH mySysFun \"mysys\" [\"in1\"] [\"out1\"])@ creates a+--  system definition from system funcion @mySysFun@ which should have +--  one input and output signals.+--+--  The advantage of 'newSysDefTH' over 'newSysDef' is that it +--  reports errors (e.g duplicated port and process identifiers) earlier, +--  at host-language (Haskell) compile-time. +--+--  In addition, due to the use of Template Haskell, 'newSysDefTH' is+--  aware of the source location at which it was called, making+--  further error reports friendlier to the user.+newSysDefTH :: SysFun f => f -- ^ system function +                        -> SysId    -- ^ System identifier +                        -> [PortId] -- ^ Input interface port identifiers +                        -> [PortId] -- ^ Output interface port identifiers +                        -> ExpQ+newSysDefTH f sysId inIds outIds = + case eProneResult of+   Left err -> currError err+   -- unfortunately SysDef can't easily be an instance of Lift +   -- due to the unsafe, unmutable references used in observable sharing +   -- Right sysDef -> [| sysDef |]+   Right _ -> intError "newSysDefTH" (Other "Unimplemented")+-- FIXME: Fix this function or remove (updating the documentation of+--        newSysDef* in the latter case).+{-+   Right _ -> do+    loc <- currentModule+    [| let iIds = inIds+           oIds = outIds+           (nlist, inTypes, outTypes) = applySysFun f iIds+       in SysDef $ PrimSysDef $ newURef $ SysDefVal sysId+                                          (Netlist nlist)+                                          (zip iIds inTypes)+                                          (zip oIds outTypes)+                                          (Just loc) |]+-}+ where currError = qError "newSysDefTH"+       eProneResult = newSysDefEProne f Nothing sysId inIds outIds+++-- | 'SysDef' constructor, Template Haskell 'Name' version+--+--   Builds a 'SysDef' out of the name of a system function+--   and its port identifers.+--+--   The system will later be identified by the basename +--   (i.e. unqualified name) of the function.+--+--  For example @$(newSysDefTHName \'mySysFun [\"in1\"] [\"out1\"])@ creates a+--  system definition from system funcion @mySysFun@ which has one input and+--  output signals.+-- +--   The advantage of 'newSysDefTHName' over 'newSysDefTH' is that it +--   doesn't suffer from the Template Haskell bug <http://hackage.haskell.org/trac/ghc/ticket/1800>, or in other words, it allows to declare the system +--   defintion and system function in the same module.+--+--   However, since it doesn't have acces to the system function itself,+--   it can only give early error reports related to incorrect port identifiers+--   (process identifier duplicate errors will be reported at runtime).+newSysDefTHName :: Name     -- ^ Name of the system function +         -> [PortId] -- ^ Input interface port identifiers +         -> [PortId] -- ^ Output interface port identifiers+         -> ExpQ +newSysDefTHName sysFName inIds outIds =  do+           sysFInfo <- reify sysFName+           -- Check that a function name was provided+           sysFType <- case sysFInfo of+                        VarI _ t _  _ -> return t+                        _             -> currError  (NonVarName sysFName)+           -- Check that the function complies with the expected type+           -- and extract the port types+           ((inTypes,inN),(outTypes, outN)) <- recover+                          (currError $ IncomSysF sysFName sysFType)+                          (checkSysFType sysFType)+           -- Check the ports+           let portCheck = checkSysDefPorts (show sysFName)+                                            (inIds, inN) +                                            (outIds, outN)+           when (isJust portCheck) (currError (fromJust portCheck))+           -- Build the system definition+           errInfo <- currentModule+           let+            -- Input arguments passed to the  system function+            -- in order to get the netlist+            inArgs = [ [| Signal $ newInPort $(litE $ stringL id) |] +                       | id <- inIds ]+            -- The system definition without type signature for the+            -- phantom parameter +            untypedSysDef =+            -- The huge let part of this quasiquote is not+            -- really necesary but generates clearer code+             [|let +               -- Generate the system netlist+               toList = $(signalTup2List outN)+               outNlSignals = toList $ $(appsE $ varE sysFName : inArgs)+               -- Rest of the system defintion+               inIface   = $(genIface inIds inTypes)+               outIface  = $(genIface outIds outTypes)+               errorInfo = errInfo+               nlist = Netlist outNlSignals+               (subSys,logic) = either (intError currFun) id+                                (checkSysDef nlist) +               in  SysDef $ PrimSysDef $ newURef $ +                         SysDefVal (nameBase sysFName)+                                   nlist+                                   subSys+                                   logic+                                   inIface +                                   outIface  +                                   (Just errorInfo) |] +           -- We are done, we simply specify the concrete type of the SysDef+           sigE untypedSysDef (return $ ConT ''SysDef `AppT` sysFType)+ where currError  = qError currFun+       currFun = "newSysDef"+++        ++----------------------------+-- Internal Helper Functions+----------------------------++-- | Error prone version of 'newSysDef'+newSysDefEProne :: SysFun f => f -- ^ system function +                -> Maybe Loc -- ^ Location where the originating +                             -- call took place (if available)+                -> SysId     -- ^ System function +                -> [PortId]  -- ^ Input interface port identifiers +                -> [PortId]  -- ^ Output interface port identifiers +                -> EProne (SysDef f)+newSysDefEProne f mLoc sysId inIds outIds +  -- check the ports for problems+  | isJust portCheck = throwError (fromJust portCheck)+  | otherwise = do+      let nl = Netlist nlist+      (subSys, logic) <- checkSysDef nl+      return (SysDef $ PrimSysDef $ newURef $ SysDefVal sysId+                                                        nl+                                                        subSys+                                                        logic+                                                        (zip inIds  inTypes)+                                                        (zip outIds outTypes)+                                                        mLoc)+ where (nlist, inTypes, outTypes) = applySysFun f inIds+       inN = length inIds+       outN = length outIds+       portCheck = checkSysDefPorts sysId (inIds, inN) (outIds, outN) ++-- | Check that the system definition ports match certain lengths and+--   don't containt duplicates+checkSysDefPorts :: SysId -- ^ System currently being checked+                 -> ([PortId], Int) -- ^ input ports and expected length+                 -> ([PortId], Int) -- ^ output ports and expected length+                 -> Maybe ForSyDeErr+checkSysDefPorts sysId (inIds, inN) (outIds, outN)  +  | inN  /= inIdsL = Just $ InIfaceLength (sysId, inN) (inIds, inIdsL)+  | outN /= outIdsL = Just $ OutIfaceLength (sysId, outN) (outIds, outIdsL)+  | isJust (maybeDup) = Just $ MultPortId  (fromJust maybeDup)+  | otherwise = Nothing+ where inIdsL  = length inIds+       outIdsL = length outIds+       maybeDup = findDup (inIds ++ outIds)+++-- | In order to check the system for identifier duplicates we keep track+--   of the process identifiers and of the accumulated subsytem definitions+data CheckState = CheckState {accumSubSys  :: [PrimSysDef],+                              accumProcIds :: [ProcId]    ,+                              accumLogic   :: SysLogic    }++-- Monad used to traverse the system in order to check that there are no +-- duplicates+type CheckSysM st a = TravSEST CheckState ForSyDeErr st a++-- | Check that the system netlist does not contain process identifier+--   duplicates (i.e. different processes with the same process+--   identifier) or instances of different systems with the same identifier.+--   In case there are no duplicates, the list of nested subsystems together+--   with the the logic is returned.+checkSysDef :: Netlist [] -> EProne ([PrimSysDef], SysLogic)+checkSysDef nl = do+  endSt <- runST (runErrorT +            (execStateT (traverseSEST newCheckSys defineCheckSys nl) initState))+  let finalSubSys = accumSubSys endSt+  -- we already checked all the delay processes of the system+  -- but the system can still be sequential if any of the subsystems is +  -- sequential+      finalLogic = +        if (accumLogic endSt == Sequential) ||+         (any (\s -> (logic.readURef.unPrimSysDef) s == Sequential) finalSubSys)+              then Sequential+              else Combinational+  return (finalSubSys, finalLogic)+ where initState = CheckState [] [] Combinational+       ++defineCheckSys :: [(NlNodeOut, ())] -> NlNode () -> CheckSysM st ()+defineCheckSys _ _= return ()+       +newCheckSys :: NlNode NlSignal -> CheckSysM st [(NlNodeOut, ())]+newCheckSys node = do+  st <- get+  let acIds = accumProcIds st+      acSys = accumSubSys st+      acLog = accumLogic st+  -- check the process Id of current node for duplicates+  acIds' <- case node of +            -- input ports don't count as process identifiers+              InPort _  -> return acIds +              Proc pid _ -> if pid `elem` acIds +                              then throwError $ MultProcId pid+                              else return (pid:acIds)+  -- If the node is a system instance, check that+  -- the system and all its subsytems are either:+  --  * already in the accumulated systems+  --  * not in the accumulated systems, but have a different system+  --    identifiers+  -- FIXME: in order to avoid making so many comparisons, it+  --        would probably be more efficient to also mark which+  --        subsystems belong to the first hierarchy level in+  --        SysVal (i.e.  creating a tree-structure as a reult).+  --        Then, if the system to compare (psys) matches a+  --        root in the accumulated subsystems there would be+  --        no need to continue comparing the childs of psys.+  acSys' <- case node of +             Proc _ (SysIns pSys _) -> +              liftEither $ +                 mergeSysIds (pSys:(subSys.readURef.unPrimSysDef) pSys) acSys+             _ -> return acSys+  let acLog' = case node of+                    Proc _ (DelaySY _ _) -> Sequential +                    _ -> acLog+  put $ CheckState acSys' acIds' acLog'+  -- return a phony value for each output of the node+  return $ map (\tag -> (tag,())) (outTags node)      ++ where mergeSysIds :: [PrimSysDef] -> [PrimSysDef] -> EProne [PrimSysDef]+       mergeSysIds xs  [] = return xs+       mergeSysIds [] xs  = return xs+       mergeSysIds (x:xs) ys = do +               shouldAdd <- addSysId x ys +               if shouldAdd then do rest <- mergeSysIds xs ys+                                    return (x:rest)+                            else mergeSysIds xs ys+        -- should we add the Id to the accumulated ones?+       addSysId :: PrimSysDef -> [PrimSysDef] -> EProne Bool+       addSysId _ [] = return True+       addSysId psdef (x:xs)  +                -- Both systems are equal+                | unx == unpsdef = return False+                -- Both systems are different, but their ids+                -- are equal+                | sdefid == sid xval = +                     throwError (SubSysIdClash sdefid (loc sdefval) (loc xval))+                | otherwise = addSysId psdef xs+          where unpsdef = unPrimSysDef psdef+                unx = unPrimSysDef x+                xval = readURef unx+                sdefval = readURef unpsdef+                sdefid = sid sdefval+++-- | Generate a lambda expression to transform a tuple of N 'Signal's into a +-- a list of 'NlSignal's+signalTup2List :: Int  -- ^ size of the tuple+              ->  ExpQ+signalTup2List n = do -- Generate N signal variable paterns and+                      -- variable expressions refering to the same names+                      names <- replicateM n (newName "i")+                      let tupPat  = tupP  [conP 'Signal [varP n] | n <- names]+                          listExp = listE [varE n                | n <- names]+                      lamE [tupPat] listExp+++-- | Find a duplicate in a list+findDup :: Eq a => [a] -> Maybe a+findDup []  = Nothing +findDup [_] = Nothing+findDup (x:xs)+ | elem x xs = Just x+ | otherwise = findDup xs+++-- | Generate a TypeRep expression given a Template Haskell Type+--   note that the use of typeOf cannot lead to errors since all the signal+--   types in a system function are guaranteed to be Typeable by construction+type2TypeRep :: Type -> ExpQ+type2TypeRep t = [| typeOf $(sigE [| undefined |] (return t) ) |]++-- | Generate an interface given its identifiers and Template Haskell Types+genIface :: [PortId] -> [Type] -> ExpQ+genIface [] _  = listE []+genIface _  [] = listE []+genIface (i:ix) (t:tx)  = do+ ListE rest <- genIface ix tx+ tupExp <- tupE [[| i |], type2TypeRep t]+ return (ListE (tupExp:rest)) +
+ src/ForSyDe/System/SysDef.hs-boot view
@@ -0,0 +1,19 @@+-- SysDef.hs-boot: GHC bootstrapping module for Netlist.hs+-- (it breaks the recursive import loop with Netlist.hs)+-- See "How to compile mutually recursive modules" in GHC's manual for details++module ForSyDe.System.SysDef where++import ForSyDe.OSharing+import ForSyDe.Ids+import Data.Typeable (TypeRep)++type Iface = [(PortId, TypeRep)]++newtype SysDef a = SysDef {unSysDef :: PrimSysDef}++newtype PrimSysDef = PrimSysDef {unPrimSysDef :: URef SysDefVal}++data SysDefVal ++oIface :: SysDefVal -> Iface
+ src/ForSyDe/System/SysFun.hs view
@@ -0,0 +1,312 @@+{-# LANGUAGE TemplateHaskell, ScopedTypeVariables, MultiParamTypeClasses,+             FunctionalDependencies #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System.SysFun+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides the 'SysFun' class and a Template Haskell +-- function to check whether a 'Type' complies with the expected +-- type of a system function not.+--+----------------------------------------------------------------------------- +module ForSyDe.System.SysFun + (SysFun(..),+  SysFunToSimFun(..), +  SysFunToIOSimFun(..),+  funOutInstances, +  checkSysFType) where++import ForSyDe.Ids(PortId)+import ForSyDe.Netlist (NlSignal, Signal(..))+import ForSyDe.ForSyDeErr+import ForSyDe.Process.ProcType (ProcType(..))++import Language.Haskell.TH.TypeLib++import Data.Dynamic+import Control.Monad (when, liftM3)+import Text.Regex.Posix ((=~))+import qualified Language.Haskell.TH as TH (Exp)+import Language.Haskell.TH+import Text.ParserCombinators.ReadP (readP_to_S)+++---------------+-- SysFun class+---------------++-- | Class used to describe a System function. It uses the same trick+--   as 'Text.Printf' to implement the variable number of arguments.+class SysFun f where+ -- | Gets the result of applying a system function to input port signals+ --   whose name is given in first argument.+ --   In case the input id list is not long enough, \"default\" will be used+ --   as the id of the remaining ports.+ applySysFun :: f +             -> [PortId] -- ^ ids used to build the input ports+             -> ([NlSignal], [TypeRep], [TypeRep])+               -- ^ (output signals returned by the system function,+               --    types of input ports, +               --    types of output ports)++ -- | Transforms a primitive-signal-list version of a system function+ --   into a standard system function.+ --   Note the length of input/output lists of the list version must match with + --   the argument number and return tuple size of the system function.+ fromListSysFun :: ([NlSignal] -> [NlSignal]) -- ^ primitive-signal-list sysfun+                -> [NlSignal] -- ^ accumulated primitive signals+                              --   (must be initialized to [])+                -> f+                   +++-----------------------+-- SysFunToSimFun class+-----------------------++-- | Multiparameter class to transform a System Function into a Simulation +--   Function, able to simulate a System using a list-based representation +--   of its signals.+class SysFun sysFun => +      SysFunToSimFun sysFun simFun | sysFun -> simFun, simFun -> sysFun where+ -- | Transforms a dynamic-list version of a simulation function+ --   into a standard simulation function.+ --   Note the length of input/output lists of the list version must match with + --   the argument number and return tuple size of the simulation function.+ fromDynSimFun :: ([[Dynamic]] -> [[Dynamic]]) -- ^ dynamic-list simfun+                -> [[Dynamic]] -- ^ accumulated dynamic values+                               --   (must be initialized to [])+                -> simFun++-------------------------+-- SysFunToIOSimFun class+-------------------------++-- | Multiparameter class to transform a System Function into an IO +--   Simulation Function, able to externally simulate a System using a +--   list-based representation of its signals.+class SysFun sysFun => +      SysFunToIOSimFun sysFun simFun | +      sysFun -> simFun, simFun -> sysFun where+ -- | Transforms a TH/String version of a simulation function into a+ --   standard simulation function.  + --   Again, the length of input/output lists of the list version must+ --   match with the argument number and return tuple size of the+ --   simulation function.+ fromTHStrSimFun :: ([[TH.Exp]] -> IO [[String]]) -- ^ TH/String-list simfun+                 -> [[TH.Exp]] -- ^ accumulated dynamic values+                               --   (must be initialized to [])+                 -> simFun++-- Function to automatically generate instances for the system and+-- simulate function outputs with Template Haskell. For example, in+-- the case of 2 outputs, the code generated would be:+--+-- @+--   NOTE: even if all ProcType constraints could be less restrictive (Typeable+--         would do), it makes more sense, and who nows, maybe we end up requiring+--         full ProcType functionality at some point. +--+--+-- instance (ProcType o1, ProcType o2) => SysFun (Signal o1, Signal o2) where+--  applyFun (o1, o2) _ = +--         ([unSignal o1, unSignal o2], [], [typeOf o1, typeOf o2]) +--  fromListSysFun f accum = (Signal o1, Signal o2)+--          where [o1, o2] = f (reverse accum) +--+-- instance (ProcType o1, ProcType o2) => +--          SysFun2SimFun (Signal o1, Signal o2) ([o1], [o2]) where+--  fromDynSimFun f accum = (map unsafeFromDyn o1, map unsafeFromDyn o2)+--          -- use pattern (o1:o2:_) and not not [o1,o2]+--          -- because the second one doesn't when o1 and o2 are infinite lists+--          where (o1:o2:_) = f (reverse accum) +--+-- instance (ProcType o1, ProcType o2) => +--          SysFun2SimFun (Signal o1, Signal o2) (IO ([o1], [o2])) where+--  fromTHStrSimFun f accum = do+--         [o1, o2] <- f (reverse accum)+--         return (map parseProcType o1, map parseProcType o2) +--+--+-- @+funOutInstances :: Int -- ^ number of outputs to generate+                -> Q (Dec, Dec, Dec)+funOutInstances n = do+ -- Generate N output names+ outNames <- replicateM n (newName "o")+ + -- 1) Generate applyFun+ --    Generate an input tuple pattern for applyFun+ --    (o1, o2, ..., on)+ let tupPatApply = tupP (map varP outNames)+ --     Generate the output primitive signal list expression for applyFun+ --    [unsignal o1, unsignal o2, ...., unsignal on]+     outPrimSignalsApply = +        listE $ map (\oName -> varE 'unSignal `appE` varE oName) outNames+ --    Generate the output signal types for ApplyFun+ --    [typeOf o1, typeOf o2, ...., typeOf on]+     outTypeRepsApply =+        listE $ map (\oName -> varE 'typeOf `appE` varE oName) outNames+ --    Generate the full output expression+     outEApply = [| ($outPrimSignalsApply, [], $outTypeRepsApply) |]+ --    Finally, the full declaration of applyFun +     applySysFunDec = +       funD 'applySysFun [clause [tupPatApply, wildP] (normalB outEApply) []]+ -- 2) Generate fromListSysFun+ --    Generate the parameter names+ fParFromSys <- newName "f"+ accumParFromSys <- newName "accum"+ --    Generate the parameter patterns+ let fPatFromSys = varP fParFromSys+     accumPatFromSys = varP accumParFromSys + --    Generate the list pattern: [o1, o2, .., on]+     listPatFromSys = listP $ map varP outNames+ --    Generate the rhs of the where declaration+     whereRHSFromSys = +         [| $(varE fParFromSys) (reverse $(varE accumParFromSys)) |]+ --    Generate the where clause declaration+     whereDecFromSys = valD listPatFromSys (normalB whereRHSFromSys) []+ --    Generate output expression: (Signal o1, Signal o2, ..., Signal on)+     outEFromSys = +          tupE $ map (\oName -> conE 'Signal `appE` varE oName) outNames+ --    Finally, the full declaration of fromListSysFun+     fromListSysFunDec = +          funD 'fromListSysFun [clause [fPatFromSys, accumPatFromSys] +                                       (normalB outEFromSys) +                                       [whereDecFromSys]             ]   + -- 3) Generate fromDynSimFun reusing parts of fromListSysFun+ --    Generate the list pattern: o1:o2: .. on:_+     listPatFromDynSim = foldr (\oName pat -> infixP (varP oName) '(:) pat) +                               wildP outNames+ --    Generate the rhs of the where declaration+     whereRHSFromDynSim = +         [| $(varE fParFromSys) (reverse $(varE accumParFromSys)) |]+ --    Generate the where clause declaration+     whereDecFromDynSim = valD listPatFromDynSim (normalB whereRHSFromSys) []+ --    Generate output expression: (Signal o1, Signal o2, ..., Signal on)+     outEFromDynSim = tupE $ map +            (\oName -> varE 'map `appE` varE 'unsafeFromDyn `appE` varE oName)+            outNames+ --    Finally, the full declaration of fromDynSimFun+     fromDynSimFunDec = +          funD 'fromDynSimFun [clause [fPatFromSys, accumPatFromSys] +                                       (normalB outEFromDynSim) +                                       [whereDecFromDynSim] ]   + -- 4) Generate fromTHStrSimFun reusing parts of fromListSysFun+     listPatFromTHStrSim = listP $ map varP outNames+ --    Generate the rhs of the where declaration+     doFromTHStrSim = doE $+       [bindS listPatFromDynSim  [| $(varE fParFromSys) +                                    (reverse $(varE accumParFromSys)) |],+        noBindS $ +           (varE 'return) `appE`+           (tupE $ map +            (\oName -> varE 'map `appE` varE 'parseProcType `appE` varE oName)+            outNames) ]+ --    Finally, the full declaration of fromThStrSimFun+     fromTHStrSimFunDec = +          funD 'fromTHStrSimFun [clause [fPatFromSys, accumPatFromSys] +                                       (normalB doFromTHStrSim) +                                       []          ]   + -- 5) Generate the SysFun instance+ --    We reuse the output signal names for the head type variables+ --    (Signal o1, Signal o2, ..., Signal on)+     signalTupT = if n == 1 then conT ''Signal `appT` varT (head outNames)+                            else foldl accumApp (tupleT n) outNames +       where accumApp accumT vName =  +                       accumT `appT` (conT ''Signal `appT` varT vName)+ --    Create the ProcType context+     procTypeCxt = map (\vName -> conT ''ProcType `appT` varT vName) outNames++ --    Finally return the instance declaration+     sysFunIns = instanceD (cxt procTypeCxt) +                           (conT ''SysFun `appT` signalTupT) +                           [applySysFunDec, fromListSysFunDec]+ -- 6) Generate the SysFun2SimFun instance +     listTupT = if n == 1 then listT `appT` varT (head outNames)+                          else foldl accumApp (tupleT n) outNames +       where accumApp accumT vName  =  +                       accumT `appT` (listT `appT` varT vName)+     simFunIns = instanceD (cxt procTypeCxt) +                    (conT ''SysFunToSimFun `appT` signalTupT `appT` listTupT) +                    [fromDynSimFunDec]+ -- 7) Generate the SysFun2IOSimFun instance+     ioSimFunIns = instanceD (cxt procTypeCxt)+                (conT ''SysFunToIOSimFun `appT` +                      signalTupT `appT` +                      (conT ''IO `appT` listTupT))+                [fromTHStrSimFunDec]+ -- Finally, return the declarations+ liftM3 (,,) sysFunIns simFunIns ioSimFunIns++---------------------------------------------------------------+-- Checking the type of a System Function with Template Haskell+---------------------------------------------------------------++-- | Given a function type expressed with Template Haskell, check+--   whether it complies with the expected type of a system function+--   and, in that case, provide the type and number of the system+--   inputs and outputs.+checkSysFType :: Type -> Q (([Type],Int),([Type],Int))+checkSysFType t = do let (inputTypes, retType, context) = unArrowT t+                         (outCons, outTypes,  _)        = unAppT retType     +                     -- Discard polymorphic system functions+                     -- FIXME: We could support polymorphic signals, but it+                     -- requires more work and we don't still know if it +                     -- will be necessary anyway.+                     when (isPoly context) (qGiveUp name)+                     -- Check that all inputs are signals+                     when (not $ all isSignalT inputTypes) (qGiveUp name)+                     -- Check the outputs+                     outInfo <- checkSysFOutputs (outCons, outTypes)+                     return ((inputTypes, length inputTypes), outInfo)+ where name = "ForSyDe.System.checkSysFType"+++-- | Check the output types of the system function given its+--   constructor and its type arguments+checkSysFOutputs :: (Type, [Type]) -> Q ([Type], Int)+-- The system function doesn't output any signals at all+checkSysFOutputs (ConT n, []) |  n == ''() = return ([],0)+-- The system function just returns a signal+checkSysFOutputs (ConT s, [arg]) | s == ''Signal  = + return ([ConT ''Signal  `AppT` arg ], 1)+-- The system function returns various signals in a tuple+-- NOTE: Unfortunatelly due to ghc's bug 1849 TupleT is never returned by reify+-- so we have to match the constructor with a regex+-- FIXME: Update this function whenever the bug is fixed +--        http://hackage.haskell.org/trac/ghc/ticket/1849+checkSysFOutputs (ConT name, outTypes) + | show name =~ "^Data\\.Tuple\\.\\(,+\\)$" =  do+     when (not $ all isSignalT outTypes) (qGiveUp checkSysFOutputsNm)+     return (outTypes, length outTypes)+-- Otherwise the function output type is incorrect+checkSysFOutputs _ = qGiveUp checkSysFOutputsNm++checkSysFOutputsNm :: String+checkSysFOutputsNm = "ForSyDe.System.SysFun.checkSysFOutputs"++-- | Check if a type corresponds to a signal+isSignalT :: Type -> Bool+isSignalT ((ConT name)  `AppT` _ ) | name == ''Signal = True+isSignalT _                                           = False++-- | Unsafely transform from a dynamic value+unsafeFromDyn :: forall a . Typeable a => Dynamic -> a+unsafeFromDyn dyn = fromDyn dyn err +  where err = intError "unsafeFromDyn" (DynMisMatch dyn targetType) +        targetType = typeOf (undefined :: a)++-- | Parse a proctype value+parseProcType :: forall a .ProcType a => String -> a+parseProcType s = +    case (readP_to_S readProcType) s of +        [(a,_)] -> a+        _ -> error ("parseProcType: error parsing element of type " +++                    show (typeOf (undefined :: a)) )
+ src/ForSyDe/System/SysFun/Instances.hs view
@@ -0,0 +1,81 @@+{-# LANGUAGE TemplateHaskell, FlexibleInstances, ScopedTypeVariables,+             MultiParamTypeClasses, UndecidableInstances #-}+-----------------------------------------------------------------------------+-- |+-- Module      :  ForSyDe.System.SysFun.Instances+-- Copyright   :  (c) The ForSyDe Team 2007+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  non-portable (Template Haskell)+--+-- This module provides the instances for 'SysFun', it cannot+-- be included in "ForSyDe.System.SysFun" directly due to a Template Haskell+-- bug which prevents Template Haskell from executing functions defined in the+-- same module: <http://hackage.haskell.org/trac/ghc/ticket/1800>+--+----------------------------------------------------------------------------- +module ForSyDe.System.SysFun.Instances () where++import Data.Dynamic+import Control.Monad (liftM)+import Language.Haskell.TH.Syntax (runIO, runQ, lift)+import System.IO.Unsafe (unsafePerformIO)++import ForSyDe.Config (maxTupleSize)+import ForSyDe.System.SysFun (+     SysFun(..), +     SysFunToSimFun(..), +     SysFunToIOSimFun(..), +     funOutInstances)+import ForSyDe.Netlist+-- This aparently unnecesary SysDef import is needed as a workaround for +-- http://hackage.haskell.org/trac/ghc/ticket/1012+import ForSyDe.System.SysDef()+import ForSyDe.Process.ProcType (ProcType(..))+++--   IMPORTANT NOTE: even if all ProcType constraints in SysFun and+--         SysFunToSimFun instances could be less restrictive+--         (Typeable would do), it makes more sense, and who nows,+--         maybe we end up requiring full ProcType functionality at+--         some point.+++-- This three instances are the ones in charge of providing the necessary +-- recursion step needed to support the variable number of arguments.+-- In each step, the system function is provided with a new input signal port+-- until the output signals are obtained.+instance (ProcType a, SysFun f) => SysFun (Signal a -> f) where+ applySysFun f ids = (outSignals, currInType : nextInTypeReps, outTypeReps)+  where (outSignals, nextInTypeReps, outTypeReps) = +          case ids of+            [] -> applySysFun (f (Signal (newInPort "default"))) []+            (i:is) -> applySysFun (f (Signal (newInPort i))) is +        currInType = typeOf (undefined :: Signal a)+ fromListSysFun f accum s = fromListSysFun f ((unSignal s):accum)++instance (ProcType a, SysFunToSimFun sysFun simFun) => +         SysFunToSimFun (Signal a -> sysFun) ([a] -> simFun) where+ fromDynSimFun f accum s = fromDynSimFun f ((map toDyn s):accum)++instance (ProcType a, SysFunToIOSimFun sysFun simFun) => +         SysFunToIOSimFun (Signal a -> sysFun) ([a] -> simFun) where+ fromTHStrSimFun f accum s = fromTHStrSimFun f ((map unsafeLift s):accum)+   -- FIXME: This won't be needed once the Data a => Lift a instance+   --        is created+   where unsafeLift = unsafePerformIO.runQ.lift++-- Generate instances for the system function outputs up to the maximum+-- tuple size+$(let concatMapM f xs = liftM concat (mapM f xs) +      listFunOutInstances = liftM (\(a,b,c) -> [a,b,c]) . funOutInstances+      msg = "Generating and compiling " ++ show maxTupleSize ++ +            " output instances of " +++            show ''SysFun ++ show ''SysFunToSimFun ++ +            " and " ++ show ''SysFunToIOSimFun ++ +            ", this might take some time ... \n"+  in runIO (putStrLn $ msg) >>+     concatMapM listFunOutInstances [0..maxTupleSize]+  )
+ src/Language/Haskell/TH/Lift.hs view
@@ -0,0 +1,101 @@+{-# LANGUAGE MagicHash, TemplateHaskell  #-}  +{-# OPTIONS_GHC -fno-warn-deprecations #-}+-- Due to the use of unboxed types, TH, and deprecated Packed Strings+-----------------------------------------------------------------------------+-- |+-- Module      :  Language.Haskell.TH.Lift+-- Copyright   :  (c) Ian Lynagh, 2006, (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- Automatically derive Template Haskell's 'Lift' class for datatypes+-- using Template Haskell splices.+-- +-- Based on Lynagh's th-lift package: <http://hackage.haskell.org/cgi-bin/hackage-scripts/package/th-lift>+-----------------------------------------------------------------------------+module Language.Haskell.TH.Lift (deriveLift1, deriveLift) where++import GHC.Exts+import Data.PackedString+import Language.Haskell.TH+import Language.Haskell.TH.Syntax+import Control.Monad (liftM)++modName :: String+modName = "Language.Haskell.TH.Lift"++-- | Automatically generate an instance of 'Lift' for one data type. For example:+-- +-- >{-# LANGUAGE TemplateHaskell #-}+-- >module Colour where+-- >import Language.Haskell.TH.Lift+-- >+-- >data RGB = Red | Green | Blue+-- >+-- >-- Generate the Lift instance of RGB+-- >$(deriveLift1 ''RGB)+deriveLift1 :: Name -> Q [Dec]+deriveLift1 = (liftM (\a -> [a])) . deriveLift ++-- | Version of 'deriveLif1' used to automatically generate instances+--   of Lift for multiple data types. For instance:+--+-- >{-# LANGUAGE TemplateHaskell #-}+-- >module Colour where+-- >import Language.Haskell.TH.Lift+-- >+-- >data RGB = Red | Green | Blue+-- >+-- >data Num a => Pixel a = Pixel a a a+-- >+-- >-- Generate Lift instances for RGB and Pixel+-- >$(mapM deriveLift [''RGB, ''Pixel])+deriveLift :: Name -> Q Dec+deriveLift n+ = do i <- reify n+      case i of+          TyConI (DataD dcxt _ vs cons _) ->+              let ctxt = liftM (++ dcxt) $ +                         cxt  [conT ''Lift `appT` varT v | v <- vs] +                  typ = foldl appT (conT n) $ map varT vs+                  fun = funD 'lift (map doCons cons)+              in instanceD ctxt (conT ''Lift `appT` typ) [fun]+          _ -> error (modName ++ ".deriveLift: unhandled: " ++ pprint i)++doCons :: Con -> Q Clause+doCons (NormalC c sts)+ = do let ns = zipWith (\_ i -> "x" ++ show i) sts [(0::Integer)..]+          con = [| conE c |]+          args = [ [| lift $(varE (mkName n)) |] | n <- ns ]+          e = foldl (\e1 e2 -> [| appE $e1 $e2 |]) con args+      clause [conP c (map (varP . mkName) ns)] (normalB e) []+doCons (InfixC st1 n st2) = doCons (NormalC n [st1,st2])+doCons (RecC n vsts)  + = let st (_, s, t) = (s, t)+   in doCons (NormalC n (map st vsts))+doCons c = error (modName ++ ".doCons: Unhandled constructor: " ++ pprint c)++instance Lift Name where+    lift (Name occName nameFlavour) = [| Name occName nameFlavour |]++instance Lift PackedString where+    lift ps = [| packString $(lift $ unpackPS ps) |]++instance Lift NameFlavour where+    lift NameS = [| NameS |]+    lift (NameQ modName) = [| NameQ modName |]+    lift (NameU i) = [| case $( lift (I# i) ) of+                            I# i' -> NameU i' |]+    lift (NameL i) = [| case $( lift (I# i) ) of+                            I# i' -> NameL i' |]+    lift (NameG nameSpace pkgName modName)+     = [| NameG nameSpace pkgName modName |]++instance Lift NameSpace where+    lift VarName = [| VarName |]+    lift DataName = [| DataName |]+    lift TcClsName = [| TcClsName |]+
+ src/Language/Haskell/TH/LiftInstances.hs view
@@ -0,0 +1,90 @@+{-# LANGUAGE TemplateHaskell #-}  +-----------------------------------------------------------------------------+-- |+-- Module      :  Language.Haskell.TH.LiftInstances+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides  'Lift' instances for all the AST-types defined+-- in "Language.Haskell.Syntax":+-- 'Guard' 'Strict', 'Callconv', 'Safety','Body', 'Con', 'FunDep', 'Foreign', +-- 'Lit', 'Pat', 'Match', 'Stmt', 'Range', 'Clause', 'Type', 'Dec', 'Exp'+--+-- Furthermore it provides a 'Lift' instance of 'Ratio', 'Int8', 'Int16',+-- 'Int32',  +-- (essential for some of the other instantiations) and a function (metaLift)+-- which lifts an expression twice, obtaing its meta AST (the AST of the AST)+-- +-----------------------------------------------------------------------------+module Language.Haskell.TH.LiftInstances (metaLift) where++import Language.Haskell.TH.Lift (deriveLift)++import Language.Haskell.TH.Syntax+ (Guard,+  Strict,+  Callconv,+  Safety,+  Body, +  Con, +  FunDep, +  Foreign, +  Lit(IntegerL), +  Pat, +  Match, +  Stmt, +  Range, +  Clause, +  Type, +  Dec, +  Exp(LitE),+  Q,+  Lift(..))++import Control.Monad (mapM)+import Data.Ratio (Ratio)+import Data.Int (Int8, Int16, Int32, Int64)++$(mapM deriveLift +      [''Ratio,+       ''Guard,+       ''Strict,+       ''Callconv,+       ''Safety,+       ''Body, +       ''Con, +       ''FunDep, +       ''Foreign, +       ''Lit, +       ''Pat, +       ''Match, +       ''Stmt, +       ''Range, +       ''Clause, +       ''Type, +       ''Dec, +       ''Exp])++instance Lift Int64 where+  lift x = return (LitE (IntegerL (fromIntegral x)))+++instance Lift Int32 where+  lift x = return (LitE (IntegerL (fromIntegral x)))++instance Lift Int16 where+  lift x = return (LitE (IntegerL (fromIntegral x)))++instance Lift Int8 where+  lift x = return (LitE (IntegerL (fromIntegral x)))+++-- | lift twice, getting the meta AST (the AST of the AST)+metaLift :: Lift a => a -> Q Exp+metaLift exp = do expAST <- lift exp+                  lift expAST+
+ src/Language/Haskell/TH/TypeLib.hs view
@@ -0,0 +1,203 @@+-----------------------------------------------------------------------------+-- |+-- Module      :  Language.Haskell.TH.TypeLib+-- Copyright   :  (c) SAM Group, KTH/ICT/ECS 2007-2008+-- License     :  BSD-style (see the file LICENSE)+-- +-- Maintainer  :  forsyde-dev@ict.kth.se+-- Stability   :  experimental+-- Portability :  portable+--+-- This module provides basic functions related to Template-Haskell's 'Type'.+-- +-----------------------------------------------------------------------------+module Language.Haskell.TH.TypeLib + (Context,+  mkContext,+  monoContext,+  isPoly,+  contextVarNames,+  contextConstraints,+  mkForallT, +  unArrowT, +  unAppT,+  (-->),+  reAppT,+  reArrowT,+  dynTHType,+  thTypeOf,+  typeRep2Type,+  tyCon2Type) + where++import Data.Dynamic+import Data.Typeable+import Language.Haskell.TH (Type(..), Cxt, Name, pprint, mkName)+import Text.Regex.Posix ((=~))++-----------+-- Context+-----------++-- | A 'Context' represents the forall part and constraints of a type+--   (see 'ForallT')+--  For instance, the context of the type+--  @+--  forall a b. (Show a, Show b) => (a,b)+--  @+--  is @forall a b. (Show a, Show b) =>@+--  where @a@ and @b@ are the the context variables and  +--  @(Show a, Show b)@ are the context constraints +data Context = Context +                   [Name] -- Variable names +                   Cxt    -- Constraints (the context itself)++instance Show Context where+-- FIXME: this is really ugly, refactor and improve its look+ showsPrec _ (Context n cxt) = +   showVars n . showConstraints cxt +   where showVars n = showForall (not (null n))  (showVars' n)+         showVars' (n:ns) = shows n . showChar ' ' . showVars' ns+         showVars' []   = id+         showConstraints c = (\s -> if not (null c) then ' ':s else s).+                             showParen (length c > 1) (showConstraints' c) .+                             (\s -> if not (null c) then s ++ " =>" else s)+         showConstraints' [c]    = shows c+         showConstraints' (c:cx) = showString (pprint c) . showString ", " . +                                   showConstraints' cx+         showConstraints' []    = id+         showForall b s = if b then showString "forall " . s . showChar '.' +                               else s++-- | 'Context' constructor+mkContext :: [Name] -> Cxt -> Context+mkContext n c = Context n c++-- | Empty context for monomorphic types+monoContext :: Context+monoContext = Context [] []+ +-- | Tells if the context corresponds to a polymorphic type+isPoly :: Context -> Bool+isPoly (Context [] _) = False+isPoly _              = True++-- | Returns the variable names related to a context+contextVarNames :: Context -> [Name]+contextVarNames (Context n _) = n++-- | Returns the context constraints+contextConstraints :: Context -> Cxt+contextConstraints (Context _ cxt) = cxt++-- | Builds a 'ForallT' type out of a context and a type+mkForallT :: Context -> Type -> Type+mkForallT (Context n cxt) t = ForallT n cxt t++--------------------------------+-- Functions to observe a 'Type'+--------------------------------++-- | Obtains the arguments and return type of a given 'Type' +--   (normally a function)+--   together with its 'Context' (non-empty if the type is polymorphic)+unArrowT :: Type                    -- ^ Type to observe  +        ->  ([Type], Type, Context) -- ^ (args 'Type', ret 'Type', 'Context')+unArrowT (ForallT names cxt t) = let (args,ret) = unArrowT' t +                                 in (args, ret, Context names cxt)+unArrowT t = let (args,ret) = unArrowT' t +             in (args, ret, Context [] [])++-- unArrowT for non-Forall Types+unArrowT' :: Type -> ([Type], Type)+unArrowT' ((ArrowT `AppT` first) `AppT` rest) = let (args, ret) = unArrowT' rest+                                                in  (first:args, ret)+unArrowT' t = ([],t)++-- | Obtains the type constructor of a 'Type' together with its+--   arguments and its 'Context' (non-empty if the type is polymorphic)+unAppT :: Type                    -- ^ Type to observe+       -> (Type, [Type], Context) -- ^ (Constructor, args 'Type', Context)+unAppT (ForallT names cxt t) = let (cons, args)  = unAppT' t+                               in (cons, args, Context names cxt)+unAppT t = let (cons, args)  = unAppT' t+           in (cons, args, Context [] [])++-- unAppT for non-Forall Types +unAppT' :: Type -> (Type, [Type])+unAppT' t = (first,rest)+  where first:rest = unAppT'ac [] t+        -- Since the constructor is a leaf of the Type tree representation,+        -- it is the last element to be gathered and thus, an accumulator+        -- is used to reverse the list to be returned+        unAppT'ac :: [Type] -> Type -> [Type]+        unAppT'ac acum (prefix `AppT` lastarg) = unAppT'ac (lastarg:acum) prefix+        unAppT'ac acum cons                   = cons:acum+------------------------------+-- Functions to build a 'Type'+------------------------------++-- | Form a function type out of two types+(-->) :: Type -- ^ Argument type+      -> Type -- ^ Return type+      -> Type -- ^ Resulting function+arg --> ret = (ArrowT `AppT` arg) `AppT` ret++-- | Rebuild a type out of a constructor, its argument types and its context+--   (inverse of 'unAppT')+reAppT :: (Type, [Type], Context)  -- ^ (Constructor, type arguments, context)+       -> Type                     -- ^ resulting 'Type'+-- Polymorphic types+reAppT (cons, args, cxt) | isPoly cxt = + mkForallT cxt (reAppT (cons, args, monoContext)) +-- Monomorphic types+reAppT (cons, args, _) = foldl1 AppT (cons:args)++-- | Rebuild a function type out of its argument types, return type+--   and context (inverse of 'ArrowT')+reArrowT :: ([Type], Type, Context)  -- ^ (Constructor, type arguments, context)+           -> Type                   -- ^ resulting 'Type'+-- Polymorphic types+reArrowT (args, ret, cxt) | isPoly cxt = + mkForallT cxt (reArrowT (args, ret, monoContext)) +-- Monomorphic types+reArrowT (args, ret, _) = foldr1 (-->) (args ++ [ret])++  ++-------------------------------------------------------------------+-- Transforming Data.Typeable.TypeRep into Language.Haskell.TH.Type+-------------------------------------------------------------------++dynTHType :: Dynamic -> Type+dynTHType = typeRep2Type . dynTypeRep++-- | Give the template haskell 'Type' of a Typeable object+thTypeOf :: Typeable a => a -> Type+thTypeOf = typeRep2Type . typeOf++-- | Translate a 'TypeRep' to a Template Haskell 'Type'+typeRep2Type :: TypeRep -> Type+typeRep2Type rep = let (con, reps) = splitTyConApp rep+  in reAppT (tyCon2Type con, map typeRep2Type reps, monoContext)+ +-- | Gives the corresponding Template Haskell 'Type' of a 'TyCon'+tyCon2Type :: TyCon -> Type+tyCon2Type = tyConStr2Type . tyConString+++----------------------------+-- Internal Helper Functions+----------------------------++tyConStr2Type :: String -> Type+-- NOTE: The tyCon strings of basic types are not qualified and buggy in +-- some cases.+-- See http://hackage.haskell.org/trac/ghc/ticket/1841+-- FIXME: update this function whenever the bug is fixed+-- FIXME FIXME: This code is incorrect:+-- mkName doesn't generate global names! ''Maybe /= mkName "Data.Maybe.Maybe"+tyConStr2Type "->" = ArrowT+tyConStr2Type  tupStr | tupStr =~ "^,+$" = + ConT (mkName $ "Data.Tuple.(" ++ tupStr ++ ")")   +tyConStr2Type str  = ConT $ mkName str
+ tests/Install.hs view
@@ -0,0 +1,47 @@+module Install (testInstall) where++import Distribution.Simple.SetupWrapper+import System.Process+import System.Directory+import System.FilePath+import System.Exit+import System.IO++-- Test if the ForSyDe project configures, builds, generates+-- the haddock documentation and installs without problems.+-- In order to avoid poisoning the haskell-package databases+-- and the file system, the package is configured with +-- the local prefix "testInstallation/" and registered+-- in a fresh local package database called "testInstallation.conf"+-- Note that this test will only work with ghc because the creation+-- of a new package database relies on ghc-pkg.+-- Also note that the current working directory must be the root of the project.+testInstall :: IO ()+testInstall = do+  cwd <- getCurrentDirectory+  putStrLn "Configuring ForSyDe ..." +  setupCWD ["configure","--user","--prefix=" ++ cwd </> "testInstallation",+            "-v0"]+  putStrLn "  done.\n"  +  putStrLn "Building ForSyDe ..." +  setupCWD ["build","-v0"]+  putStrLn "  done.\n"+  putStrLn "Testing the haddock markup of ForSyDe ... " +  setupCWD ["haddock", "-v0"]+  putStrLn "  done.\n"+  putStrLn "Copying ForSyDe under testInstallation/ ... "+  setupCWD ["copy", "-v0"]+  putStrLn "  done.\n"+  putStrLn ("Registering ForSyDe in fresh package database " +++            "(testInstallation.conf) ...")+  -- Cabal doesn't allow specifying an alternative package database:+  -- http://hackage.haskell.org/trac/hackage/ticket/307+  -- Thus, we register the package by hand using ghc-pkg+  setupCWD ["register", "--gen-pkg-config=ForSyDeconfig","-v0"]+  code <- waitForProcess =<< +          runCommand  "ghc-pkg -f testInstallation.conf register ForSyDeconfig"+  case code of+     ExitSuccess -> return ()+     e@(ExitFailure _) -> exitWith e+  putStrLn "done."+ where setupCWD command = setupWrapper command Nothing
+ tests/Main.hs view
@@ -0,0 +1,68 @@+-- Main test module, it must be run from the root directory of the project+module Main (main) where++import Install++import Distribution.System+import Control.Monad (liftM)+import System.IO+import System.Environment (getArgs, getEnv)+import System.Process (runCommand, waitForProcess)+import System.Exit+import System.FilePath (splitDirectories, normalise)+++main :: IO ()+main = do+ needed <- testNeeded+ if needed +   then +     do hSetBuffering stdout LineBuffering+        testInstall+        --  test the properties using the fresh installation+        -- due to many problems with runghc, I decided to compile it first+        putStrLn ("Compiling the unit testbench: " ++ compilePropertiesCmd)+        h1 <- runCommand  compilePropertiesCmd+        e1 <- waitForProcess h1+        case e1 of+          ExitSuccess -> do h2 <- runCommand properties+                            e2 <- waitForProcess h2+                            exitWith e2+          _ -> exitFailure++--        h <- runCommand runPropertiesCmd+--        e <- waitForProcess h+--        exitWith e++   else putStrLn "There is no need to run the test suite."+ where compilePropertiesCmd = +         "ghc --make -itests/properties -iexamples -package-conf testInstallation.conf " ++ +                 "tests/properties/Main.hs -o properties"+       properties = case os of+                     Windows _ -> "properties.exe"+                     _ -> "./properties"++-- Check if we need to do the tests, This will be true unless an+-- automatic test is done from darcs, in which case we only need+-- to perform the tests if the affected files are ForSyDe.cabal+-- Setup.hs or any file under src/, tests/ or lib/+testNeeded :: IO Bool+testNeeded = do+  mDARCS_FILES <- catch (liftM Just $ getEnv "DARCS_FILES")+                        (\_ -> return Nothing)+  case mDARCS_FILES of+    Nothing -> do putStrLn "DARCS_FILES wasn't set by darcs: forcing test."+                  return True+    Just multiLine -> (return.checkAffected) multiLine+  where checkAffected str = any affected (lines str) +        affected file = let nfile = normalise file in+                        nfile `elem` ["Setup.hs", "ForSyDe.cabal"] ||+                        firstDir nfile `elem` ["src", "tests", "lib"]         +          +        firstDir filePath = +               let sDirName = splitDirectories filePath+               in case sDirName of+                  [_]     -> ""+                  (x:xs)  -> x++
+ tests/properties/Main.hs view
@@ -0,0 +1,20 @@+-- Property-testing wrapper module+module Main (main) where+import Test.HUnit+import System.Exit+import System.IO+import VHDLBackend (vhdlBackendTest)+import Shallow (shallowTest)+++main :: IO ()+main = do+    hSetBuffering stdout LineBuffering+    putStrLn "Running ForSyDe's unit test suite"+    runTestCount $ test ["VHDL Backend Test" ~: vhdlBackendTest,+                         "Shallow Library Test" ~: shallowTest]+  where runTestCount t = do (c, _) <- myRunTestText t +                            if errors c /= 0 || failures c /= 0 +                               then exitFailure +                               else exitWith ExitSuccess+        myRunTestText = runTestText (PutText (\str _ _ -> putStrLn str) ())
+ tests/properties/Shallow.hs view
@@ -0,0 +1,7 @@+module Shallow (shallowTest) where++import Shallow.SynchronousMoC (synchronousMoCTest)+import Test.HUnit++shallowTest :: Test+shallowTest = test [synchronousMoCTest]
+ tests/properties/Shallow/SynchronousMoC.hs view
@@ -0,0 +1,14 @@+module Shallow.SynchronousMoC (synchronousMoCTest) where++import ForSyDe.Shallow+import Test.HUnit++synchronousMoCTest :: Test+synchronousMoCTest = test [mapSYTest]++mapSYTest :: Test+mapSYTest = "mapSYTest" ~: test $ do putStrLn "Test mapSY"+                                     expectedOutput @=? +                                        mapSY (+1) (signal [1,2,3])+   where expectedOutput :: Signal Int+         expectedOutput = signal [2,3,4]
+ tests/properties/VHDLBackend.hs view
@@ -0,0 +1,194 @@+{-# LANGUAGE TemplateHaskell #-}+-- VHDL-Backend property testing module+-- ALl the tests are based on asserting that the internal simulation of the system+-- equals the simulation of the generated vhdl code with modelsim+module VHDLBackend (vhdlBackendTest) where+-- import the example-modules+import ALU+import Counter+import ParAddFour+import Multiplexer+import Multiplexer_FSVector+import SeqAddFour+import ButtonEncoder        +import ZipTwist+import CarrySelectAdder     +import Null+import LFSR++import Control.Monad (liftM, replicateM)+import Data.List (transpose)+import Data.Param.FSVec (vectorTH, reallyUnsafeVector)+import System.Random+import Test.HUnit+import ForSyDe+import Data.Int++vhdlBackendTest :: Test+vhdlBackendTest = test [aluTest, +                        counterTest,+                        parAddFourTest,+                        muxTest,+                        muxFSVecTest,+                        seqAddFourTest,+                        buttonEncoderTest,+                        zipTwistTest,+                        nullTest,+                        lfsrTest]++-- systematic test for the ALU+aluTest :: Test+aluTest =  "aluTest" ~: outSim <~=?> outVHDL+ where and = $(vectorTH [H,H])+       or =  $(vectorTH [H,L])+       add = $(vectorTH [L,H])+       shiftl = $(vectorTH [L,L])+       fourBitCombs = map reallyUnsafeVector (combN 4 [L,H])+       [arg1,arg2] = parCombN 2 fourBitCombs+       l = length arg1+       select = replicate l and +++                replicate l or +++                replicate l add +++                replicate l shiftl+       op1 = arg1 ++ arg1 ++ arg1 ++ arg1+       op2 = arg2 ++ arg2 ++ arg2 ++ arg2+       outSim = simALU select op1 op2+       outVHDL = vhdlTest Nothing aluSys select op1 op2++counterTest :: Test+counterTest = "counterTest" ~: "first 400 outputs" ~: +                                   out400Sim <~=?>  out400VHDLSim+ where out400Sim = take 400 simCounter+       out400VHDLSim = vhdlTest (Just 400) counterSys++parAddFourTest :: Test+parAddFourTest = "parAddFourTest" ~: test doTest+ where -- testt the overflows, and 400 different pseudorandom numbers+       lastInt32 :: Num a => a+       lastInt32 = 2147483647+       firstInt32 :: Num a => a+       -- FIXME: this should be -2147483648, but due to bug http://code.google.com/p/forsyde-comp/issues/detail?id=22 it was set to -2147483647+       firstInt32 = -2147483647 +       gen400Int32 :: IO [Int32]+       gen400Int32 = do+          let randomInt32 :: IO Int32+              randomInt32 = do+                 let getInt32Range :: IO Integer+                     getInt32Range = getStdRandom (randomR (firstInt32, lastInt32))+                 liftM fromIntegral getInt32Range+          replicateM 400 randomInt32+       doTest :: IO ()+       doTest = do  arg1 <- gen400Int32  +                    arg2 <- gen400Int32+                    arg3 <- gen400Int32+                    arg4 <- gen400Int32 +                    arg5 <- gen400Int32  +                    let sim = simParAddFour (1:(-1):arg1) +                                            -- (firstInt32:lastInt32:arg2)+                                            -- (lastInt32:firstInt32:arg3)+                                            arg2+                                            arg3+                                            (-1:1:arg4)+                                            (0:1:arg5)+                        simVHDL = vhdlTest Nothing+                                           parAddFourSys+                                           (1:(-1):arg1) +                                           -- (firstInt32:lastInt32:arg2)+                                           -- (lastInt32:firstInt32:arg3)+                                           arg2+                                           arg3+                                           (-1:1:arg4)+                                           (0:1:arg5)+                    resVHDL <- simVHDL+                    sim @=? resVHDL                    +++muxTest :: Test+muxTest = "muxTest" ~:  Multiplexer.simMux sel input <~=?> +                        vhdlTest Nothing Multiplexer.muxSysDef sel input+ where sel = [(L,L),(L,H),(H,L),(H,H)]+       input = [(L,L,L,H),(L,L,H,L),(L,H,L,L),(H,L,L,L)]+        +++muxFSVecTest :: Test+muxFSVecTest = "muxTest" ~:  Multiplexer_FSVector.simMux sel input <~=?> +                        vhdlTest Nothing Multiplexer_FSVector.muxSysDef sel input+ where sel = [$(vectorTH [L,L]),$(vectorTH [L,H]),$(vectorTH [H,L]),$(vectorTH [H,H])]+       input = [$(vectorTH [L,L,L,H]), $(vectorTH [L,L,H,L]), $(vectorTH [L,H,L,L]),+                $(vectorTH [H,L,L,L])]++seqAddFourTest :: Test+seqAddFourTest = "seqAddFourTest" ~: simAddFour input <~=?>+                                     vhdlTest Nothing addFourSys input+ where input = [-100,-99..100] ++buttonEncoderTest :: Test+buttonEncoderTest = "buttonEncoderTest" ~: simButtonEncoder input <~=?>+                                           vhdlTest Nothing buttonEncoderSys input+ where input = [(H,L,L,L), (L,H,L,L), (L,L,H,L), (L,L,L,H), (L,L,L,L)]++zipTwistTest :: Test+zipTwistTest = "zipTwistTest" ~: +  simZipTwist input1 input2 input3 input4 input5 input6 <~=?> +  vhdlTest Nothing zipTwistSys input1 input2 input3 input4 input5 input6+ where input1 = [-100..0]+       input2 = [-10..90]+       input3 = [100..200]+       input4 = [350..450]+       input5 = [-400..(-300)]+       input6 = [-50..50]++nullTest :: Test+-- we don't test quartus here, because it complains about no logic+nullTest = "nullTest" ~: simNull <~=?>  writeAndModelsimVHDL Nothing nullSysDef +       +lfsrTest :: Test+lfsrTest = "lsfrTest" ~: outSim <~=?> outVHDL+ where take400Tup4 (i1,i2,i3,i4) = (take 400 i1, take 400 i2, take 400 i3,+                                    take 400 i4)+       outSim = take400Tup4 simlfsr+       outVHDL =  vhdlTest (Just 400) lfsrSys++-------------------+-- Helper functions+-------------------+++-- run a vhdl testbench with custom backend options+vhdlTest :: SysFunToIOSimFun sysF simF => Maybe Int -> SysDef sysF -> simF+vhdlTest = writeAndModelsimVHDLOps testVHDLOps++-- testing VHDL options+testVHDLOps :: VHDLOps+testVHDLOps = defaultVHDLOps{execQuartus=Just checkSynthesisQuartus}++-- Compare an IO test with a pure expected result+(<~=?>) :: (Eq a, Show a) => a -> IO a -> Test  +expected <~=?> actualM  = TestCase $ do a <- actualM+                                        expected @=? a+++-- | permutation a list+--   Each element of the input list indicates the posibilities of each+--   positional elements in the resulting lists+permut :: [[a]] -> [[a]]+permut [] = []+permut [xs] = map (\x -> [x]) xs+permut (xs:xss) = let res = permut xss+                  in concatMap (\e -> map (:e) xs) res++-- | Combinations of 2 elements from a set of values +comb2 :: [a] -> [(a,a)]+comb2 xs = concatMap (\i -> map (\j -> (i,j) ) xs) xs++-- | Parallel combination of N elements+parCombN :: Int -> [a] -> [[a]]+parCombN n xs = transpose $ combN n xs++-- | Combinations os N elements from a set of values+combN :: Int -> [a] -> [[a]]+combN n _ | n <= 0 = []+combN 1 xs = map (\x -> [x]) xs+combN n xs = let res = combN (n-1) xs+             in concatMap (\i -> map (\j -> j:i) xs) res